URL
https://opencores.org/ocsvn/wb4pb/wb4pb/trunk
Subversion Repositories wb4pb
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.v
131,8 → 131,11
); |
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// reset synchronisation |
always@(clk) |
rst <= ! dcm_locked; |
always@(negedge dcm_locked or posedge clk) |
if (! dcm_locked) |
rst <= 1'b1; |
else |
rst <= ! dcm_locked; |
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// module instances |
/////////////////// |
/wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.v
106,7 → 106,7
reg[23:0] timer; |
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// reset synchronisation |
always@(clk) |
always@(posedge clk) |
rst <= FPGA_RESET; |
assign clk = CLK_16MHZ; |
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/wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.vhd
204,9 → 204,13
); |
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-- reset synchronisation |
process(clk) |
process(dcm_locked, clk) |
begin |
rst <= not dcm_locked; |
if dcm_locked = '0' then |
rst <= '1'; |
elsif rising_edge(clk) then |
rst <= not dcm_locked; |
end if; |
end process; |
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-- module instances |
/wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.vhd
168,7 → 168,9
-- reset synchronisation |
process(clk) |
begin |
rst <= FPGA_RESET; |
if rising_edge(clk) then |
rst <= FPGA_RESET; |
end if; |
end process; |
clk <= CLK_16MHZ; |
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