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Rev 28 → Rev 29

/versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v
1,4 → 1,48
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module adr_gen ( cke, q, q_bin, rst, clk);
 
parameter length = 4;
input cke;
output reg [length:1] q;
5,9 → 49,12
output [length:1] q_bin;
input rst;
input clk;
 
 
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
 
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
14,6 → 61,7
else
if (cke)
qi <= q_next;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
20,8 → 68,15
else
if (cke)
q <= (q_next>>1) ^ q_next;
 
assign q_bin = qi;
 
endmodule
// true dual port RAM, sync
 
 
module vfifo_dual_port_ram_dc_dw
(
d_a,
47,7 → 102,7
input we_b;
input clk_a, clk_b;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
61,12 → 116,56
ram[adr_b] <= d_b;
end
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module dff_sr ( aclr, aset, clock, data, q);
 
input aclr;
input aset;
input clock;
input data;
output reg q;
 
always @ (posedge clock or posedge aclr or posedge aset)
if (aclr)
q <= 1'b0;
74,25 → 173,81
q <= 1'b1;
else
q <= data;
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
 
 
reg direction;
 
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
101,6 → 256,8
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
112,31 → 269,56
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
 
 
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
 
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule
 
endmodule // async_comp
module async_fifo_dw_simplex_top (
// a side
a_d, a_wr, a_fifo_full,
a_q, a_rd, a_fifo_empty,
a_clk, a_rst,
// b side
b_d, b_wr, b_fifo_full,
b_q, b_rd, b_fifo_empty,
b_clk, b_rst
);
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input [data_width-1:0] a_d;
input a_wr;
output a_fifo_full;
145,6 → 327,8
output a_fifo_empty;
input a_clk;
input a_rst;
 
// b side
input [data_width-1:0] b_d;
input b_wr;
output b_fifo_full;
153,31 → 337,44
output b_fifo_empty;
input b_clk;
input b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
adr_gen
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_rst));
 
adr_gen
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vfifo_dual_port_ram_dc_dw
# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
 
versatile_fifo_async_cmp
# (.ADDR_WIDTH(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
versatile_fifo_async_cmp
# (.ADDR_WIDTH(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
endmodule
/versatile_fifo/trunk/rtl/verilog/Makefile
1,34 → 1,34
dual_port_ram:
vppreproc +define+TYPE+"sc_sw" --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_sw.v
vppreproc +define+TYPE+"sc_dw" +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_dw.v
vppreproc +define+TYPE+"dc_sw" +define+DC --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_sw.v
vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
 
export: svn_export_versatile_counter
 
gray_counter:
excel2csv gray_counter.xls -S ,
./versatile_counter_generator.php gray_counter.csv > gray_counter.v
 
sd:
excel2csv sd_counter.xls -S ,
./versatile_counter_generator.php sd_counter.csv > sd_counter.v
 
adr_gen:
excel2csv adr_gen.xls -S ,
 
async_fifo_altera.v: adr_gen
./versatile_counter_generator.php adr_gen.csv > adr_gen.v
vppreproc +define+GENERATE_DIRECTION_AS_LATCH --simple ../../backend/altera/cycloneIV/dff_sr.v adr_gen.v versatile_fifo_dual_port_ram_dc_sw.v versatile_fifo_async_cmp.v async_fifo_top.v > async_fifo_altera.v
 
async_fifo_mq: gray_counter
vppreproc --simple gray_counter.v
 
async_fifo_dw_simplex_actel.v: adr_gen
vppreproc +define+GENERATE_DIRECTION_AS_LATCH +define+ACTEL --simple adr_gen.v versatile_fifo_dual_port_ram_dc_dw.v dff_sr.v versatile_fifo_async_cmp.v async_fifo_dw_simplex_top.v > async_fifo_dw_simplex_actel.v
 
svn_export_versatile_counter:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
 
all: export gray_counter gray_counter sd
dual_port_ram:
vppreproc +define+TYPE+"sc_sw" --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_sw.v
vppreproc +define+TYPE+"sc_dw" +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_dw.v
vppreproc +define+TYPE+"dc_sw" +define+DC --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_sw.v
vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
 
export: svn_export_versatile_counter
 
gray_counter:
excel2csv gray_counter.xls -S ,
./versatile_counter_generator.php gray_counter.csv > gray_counter.v
 
sd:
excel2csv sd_counter.xls -S ,
./versatile_counter_generator.php sd_counter.csv > sd_counter.v
 
adr_gen:
excel2csv adr_gen.xls -S ,
 
async_fifo_altera.v: adr_gen
./versatile_counter_generator.php adr_gen.csv > adr_gen.v
vppreproc +define+GENERATE_DIRECTION_AS_LATCH --simple ../../backend/altera/cycloneIV/dff_sr.v adr_gen.v versatile_fifo_dual_port_ram_dc_sw.v versatile_fifo_async_cmp.v async_fifo_top.v > async_fifo_altera.v
 
async_fifo_mq: gray_counter
vppreproc --simple gray_counter.v
 
async_fifo_dw_simplex_actel.v: adr_gen
vppreproc +define+GENERATE_DIRECTION_AS_LATCH +define+ACTEL --noline adr_gen.v versatile_fifo_dual_port_ram_dc_dw.v dff_sr.v versatile_fifo_async_cmp.v async_fifo_dw_simplex_top.v > async_fifo_dw_simplex_actel.v
 
svn_export_versatile_counter:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
 
all: export gray_counter gray_counter sd

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