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/bch_configurable/trunk/testbench/tb_encode.v
0,0 → 1,184
`timescale 1ns/100ps
module tb_encode
#(
parameter C_DWIDTH = 32,
parameter C_COEF_NUM = 2,
parameter C_PRIMPOLY_ORDER = 10,
parameter C_GENPOLY = 'h409,
parameter C_INPUT_NUM = 512,
parameter C_SEARCH_THREAD_NUM = 32,
parameter C_TOTALBIT_NUM = 100
)
(
input I_clk ,
input I_rst ,
input [C_DWIDTH-1:0] I_data ,
input I_data_v ,
input I_data_sof ,
input I_data_eof ,
input [C_DWIDTH-1:0] I_data_ori ,
input I_data_v_ori ,
input I_data_sof_ori ,
input I_data_eof_ori ,
output reg [1:0] O_result
);
wire [C_DWIDTH-1:0] S_data ;
wire [C_DWIDTH-1:0] S_data_d;
wire S_data_v ;
wire S_data_sof ;
wire S_data_eof ;
wire [C_PRIMPOLY_ORDER*C_COEF_NUM-1:0] S_syndrome;
wire S_syndrome_v;
wire [C_PRIMPOLY_ORDER*C_COEF_NUM-1+C_PRIMPOLY_ORDER:0] S_err_pos;
wire [C_SEARCH_THREAD_NUM-1:0] S_ecc;
wire S_ecc_v;
wire S_ecc_sof;
wire S_ecc_eof;
wire [C_DWIDTH-1:0] S_data_cor;
wire S_data_v_cor;
wire S_data_sof_cor;
wire S_data_eof_cor;
 
reg [C_DWIDTH-1:0] S_ram_ori [1023:0];
reg [9:0] S_ram_ori_waddr = 0;
reg [9:0] S_ram_ori_raddr = 0;
reg S_data_eof_cor_d = 0;
reg [C_DWIDTH-1:0] S_ram_ori_dout = 0;
reg S_data_v_cor_d = 0;
reg [C_DWIDTH-1:0] S_data_cor_d = 0;
reg S_data_eof_ori = 0;
 
always @(posedge I_clk)
begin
S_data_eof_ori <= I_data_eof_ori;
if(S_data_eof_ori)
S_ram_ori_waddr <= 'd0;
else if(I_data_v_ori)
S_ram_ori_waddr <= S_ram_ori_waddr + 'd1;
if(I_data_v_ori)
S_ram_ori[S_ram_ori_waddr] <= I_data_ori;
end
 
always @(posedge I_clk)
begin
S_data_eof_cor_d <= S_data_eof_cor;
if(S_data_eof_cor_d)
S_ram_ori_raddr <= 'd0;
else if(S_data_v_cor)
S_ram_ori_raddr <= S_ram_ori_raddr + 'd1;
S_ram_ori_dout <= S_ram_ori[S_ram_ori_raddr];
S_data_v_cor_d <= S_data_v_cor;
S_data_cor_d <= S_data_cor;
end
 
always @(posedge I_clk)
begin
if(S_data_sof_cor)
O_result[0] <= 1'b1;
else if(S_data_v_cor_d)
O_result[0] <= O_result[0] && (S_ram_ori_dout == S_data_cor_d);
O_result[1] <= S_data_eof_cor_d;
end
 
/*test_bch_encode
#(
.C_DWIDTH (C_DWIDTH ),
.C_COEF_NUM (C_COEF_NUM ),
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_PRIM_POLY (C_GENPOLY )
)
test_bch_encode_inst
(
.I_clk (I_clk ),
.I_rst (I_rst ),
.I_data (I_data ),
.I_data_v (I_data_v ),
.I_data_sof (I_data_sof ),
.I_data_eof (I_data_eof ),
.O_data (S_data ),
.O_data_v (S_data_v ),
.O_data_sof (S_data_sof ),
.O_data_eof (S_data_eof )
);*/
 
test_bch_syndrome
#(
.C_DWIDTH (C_DWIDTH),
.C_COEF_NUM (C_COEF_NUM),
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_PRIM_POLY (C_GENPOLY)
)
test_bch_syndrome_inst
(
.I_clk (I_clk),
.I_rst (I_rst),
.I_data (I_data ),
.I_data_v (I_data_v ),
.I_data_sof (I_data_sof),
.I_data_eof (I_data_eof),
.O_syndrome (S_syndrome),
.O_syndrome_v (S_syndrome_v)
);
 
test_bch_bm
#(
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_COEF_NUM (C_COEF_NUM),
.C_PRIMPOLY (C_GENPOLY)
)
test_bch_bm_inst
(
.I_clk (I_clk),
.I_rst (I_rst),
.I_syndrome (S_syndrome),
.I_syndrome_v (S_syndrome_v),
.O_err_pos (S_err_pos),
.O_err_pos_v (S_err_pos_v)
);
 
test_chian_search
#(
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_COEF_NUM (C_COEF_NUM),
.C_TOTALBIT_NUM (C_TOTALBIT_NUM),
.C_THREAD_NUM (C_SEARCH_THREAD_NUM),
.C_PRIMPOLY (C_GENPOLY)
)
test_chian_search_inst
(
.I_clk (I_clk),
.I_rst (I_rst),
.I_coef (S_err_pos),
.I_coef_v (S_err_pos_v),
.O_data (S_ecc ),
.O_data_v (S_ecc_v ),
.O_data_sof (S_ecc_sof),
.O_data_eof (S_ecc_eof)
);
 
test_correct
#(
.C_INPUT_NUM (C_INPUT_NUM),
.C_DWIDTH (C_DWIDTH ),
.C_ECCWIDTH (C_SEARCH_THREAD_NUM )
)
test_correct_inst
(
.I_clk (I_clk),
.I_rst (I_rst),
.I_data (I_data ),
.I_data_sof (I_data_sof ),
.I_data_eof (I_data_eof),
.I_data_v (I_data_v),
.I_ecc (S_ecc ),
.I_ecc_v (S_ecc_v ),
.I_ecc_sof (S_ecc_sof),
.I_ecc_eof (S_ecc_eof),
.O_data (S_data_cor ),
.O_data_v (S_data_v_cor ),
.O_data_sof (S_data_sof_cor),
.O_data_eof (S_data_eof_cor)
);
 
endmodule
/bch_configurable/trunk/testbench/sim.do
0,0 → 1,9
vlib work
vlog ../src/test_bch_encode.v
vlog ./tb_encode.v
vlog ./sim_top.v
vlog ../src/test_bch_syndrome.v
vlog ../src/test_bch_bm.v
vlog ../src/test_chian_search.v
vlog ../src/test_correct.v
vsim -novopt work.sim_top
/bch_configurable/trunk/testbench/sim_top.v
0,0 → 1,238
`timescale 1ns/100ps
module sim_top;
 
 
reg I_clk;
reg I_rst;
 
reg [31:0] S_data_random1 = 0;
reg [31:0] S_data_random2 = 0;
reg [31:0] S_data_random3 = 0;
reg [31:0] S_data_random4 = 0;
 
reg S_start_id = 0;
wire [127:0] S_data_random;
initial
begin
I_clk = 0;
forever #5 I_clk = !I_clk;
end
 
initial
begin
I_rst = 0;
#100
forever
begin
@(posedge I_clk);
T_random_gen;
end
end
 
initial
begin
S_start_id = 0;
#120
@(posedge I_clk);
S_start_id = 1;
@(posedge I_clk);
S_start_id = 0;
end
 
task T_random_gen;
begin
S_data_random1 = $random;
S_data_random2 = $random;
S_data_random3 = $random;
S_data_random4 = $random;
end
endtask
 
 
assign S_data_random = {S_data_random4,S_data_random3,S_data_random2,S_data_random1};
localparam C_FRAME_LEN = 64;
genvar S_i;
generate
for(S_i=0;S_i<1;S_i=S_i+1)
begin:test
 
localparam C_DWIDTH_THREAD = 2**(S_i+1);
localparam C_INPUT_NUM = C_DWIDTH_THREAD*C_FRAME_LEN;
localparam C_COEF_NUM = (S_i<3) ? 15 : 4*(S_i+4);
localparam C_TOTALBIT_NUM = C_INPUT_NUM + C_COEF_NUM*(S_i+8);
//localparam C_TOTALBIT_NUM = C_INPUT_NUM + C_COEF_NUM*(S_i+8) - 4; //primpoly8 is not all 8 in genpoly,one in the middle is 4
localparam C_PRIMPOLY_ORDER = S_i + 8;
localparam C_GENPOLY = (S_i == 0) ? 'h11d : ((S_i == 1) ? 'h211 : ((S_i == 2) ? 'h409 : ((S_i == 3) ? 'h805 : ((S_i == 4) ? 'h1053 : ((S_i == 5) ? 'h201b : 'h4443)))));
localparam C_SEARCH_THREAD_NUM = 2**S_i;
localparam C_BYTE_NUM = C_TOTALBIT_NUM/C_DWIDTH_THREAD;
localparam C_COEF_NUM2 = C_COEF_NUM;
 
wire [C_DWIDTH_THREAD-1:0] S_data;
reg [C_DWIDTH_THREAD-1:0] S_data_d;
wire S_data_v;
wire S_data_sof;
wire S_data_eof;
reg S_data_v_d;
reg S_data_sof_d;
reg S_data_eof_d;
wire [1:0] S_result;
reg I_data_v;
reg I_data_sof;
reg I_data_eof;
integer S_err_byte [C_COEF_NUM2-1 : 0];
reg [C_DWIDTH_THREAD-1:0] S_err_bit [C_COEF_NUM2-1 : 0] ;
integer S_err_num;
 
reg [7:0] S_encode_cnt = 0;
reg [7:0] S_cnt = 0;
reg S_data_v_2d = 0;
 
test_bch_encode
#(
.C_DWIDTH (C_DWIDTH_THREAD ),
.C_COEF_NUM (C_COEF_NUM ),
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_PRIM_POLY (C_GENPOLY )
)
test_bch_encode_inst
(
.I_clk (I_clk ),
.I_rst (I_rst ),
.I_data (S_data_random[C_DWIDTH_THREAD-1:0]),
.I_data_v (I_data_v ),
.I_data_sof (I_data_sof ),
.I_data_eof (I_data_eof ),
.O_data (S_data ),
.O_data_v (S_data_v ),
.O_data_sof (S_data_sof ),
.O_data_eof (S_data_eof )
);
 
always @(posedge I_clk)
begin
if(S_start_id || S_result[1] || S_cnt != 0)
begin
if(S_cnt == C_FRAME_LEN)
S_cnt <= 'd0;
else
S_cnt <= S_cnt + 'd1;
end
end
 
always @(posedge I_clk)
begin
I_data_v <= (S_cnt != 'd0);
I_data_sof <= S_cnt == 'd1;
I_data_eof <= S_cnt == C_FRAME_LEN;
end
 
integer ii;
 
initial
begin
forever
begin
wait(I_data_sof || S_result[1]);
S_err_num = {$random}%C_COEF_NUM;
for(ii=0;ii<C_COEF_NUM2;ii=ii+1)
begin
S_err_byte[ii] = {$random}%C_BYTE_NUM;
S_err_bit[ii] = 1<<({$random}%C_DWIDTH_THREAD);
end
@(posedge I_clk);
end
end
 
integer jj;
 
always @(posedge I_clk)
begin
if(S_data_v)
S_encode_cnt <= S_encode_cnt + 'd1;
else
S_encode_cnt <= 'd0;
end
 
always @(posedge I_clk)
begin
if(S_data_v)
begin
S_data_d = S_data;
for(jj=0;jj<C_COEF_NUM2;jj=jj+1)
begin
if(S_encode_cnt==S_err_byte[jj])
S_data_d = S_data ^ S_err_bit[jj];
end
end
end
 
always @(posedge I_clk)
begin
S_data_sof_d <= S_data_sof;
S_data_eof_d <= S_data_eof;
S_data_v_d <= S_data_v;
S_data_v_2d <= S_data_v_d;
end
 
tb_encode
#(
.C_DWIDTH (C_DWIDTH_THREAD),
.C_COEF_NUM (C_COEF_NUM),
.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
.C_GENPOLY (C_GENPOLY),
.C_INPUT_NUM (C_INPUT_NUM),
.C_SEARCH_THREAD_NUM (C_SEARCH_THREAD_NUM),
.C_TOTALBIT_NUM (C_TOTALBIT_NUM)
)
tb_encode_inst
(
.I_clk (I_clk),
.I_rst (I_rst),
.I_data (S_data_d),
.I_data_v (S_data_v_d),
.I_data_sof (S_data_sof_d),
.I_data_eof (S_data_eof_d),
.I_data_ori (S_data_random[C_DWIDTH_THREAD-1:0]),
.I_data_v_ori (I_data_v),
.I_data_sof_ori (I_data_sof),
.I_data_eof_ori (I_data_eof),
.O_result (S_result)
);
integer fid1;
integer fid2;
initial
begin
fid1 = $fopen("data1.txt");
fid2 = $fopen("data2.txt");
end
always @(posedge I_clk)
begin
if(S_data_v_2d)
$fdisplay(fid1,"%d",S_data_d);
if(I_data_v)
$fdisplay(fid2,"%d",S_data_random[C_DWIDTH_THREAD-1:0]);
end
 
always @(posedge I_clk)
begin
if(S_result[1])
begin
$display("width is %d,input number is %d,C_COEF_NUM is %d,total number is %d,prime order is %d,search thread is %d",C_DWIDTH_THREAD,C_INPUT_NUM,C_COEF_NUM,C_TOTALBIT_NUM,C_PRIMPOLY_ORDER,C_SEARCH_THREAD_NUM);
if(S_result[0])
begin
$display("bch is right");
end
else
begin
$display("bch is wrong");
$stop();
end
end
end
 
end
endgenerate
 
 
 
endmodule

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