URL
https://opencores.org/ocsvn/cordic/cordic/trunk
Subversion Repositories cordic
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/rect2polar/CordicPipe.vhd
1,3 → 1,10
-- |
-- file: CordicPipe.vhd |
-- author: Richard Herveille |
-- rev. 1.0 initial release |
-- rev. 1.1 19/03/2001 Changed function Delta, it is compatible with Xilinx WebPack software now |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
4,9 → 11,10
|
entity CordicPipe is |
generic( |
WIDTH : natural; |
AWIDTH : natural; |
PIPEID : natural); |
WIDTH : natural := 16; |
AWIDTH : natural := 16; |
PIPEID : natural := 1 |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
16,7 → 24,8
Zi : in std_logic_vector(AWIDTH -1 downto 0); |
Xo : out std_logic_vector(WIDTH -1 downto 0); |
Yo : out std_logic_vector(WIDTH -1 downto 0); |
Zo : out std_logic_vector(AWIDTH -1 downto 0)); |
Zo : out std_logic_vector(AWIDTH -1 downto 0) |
); |
end entity CordicPipe; |
|
architecture dataflow of CordicPipe is |
50,13 → 59,18
return result; |
end CATAN; |
|
-- function Delta is actually an arithmatic shift right |
-- This strange construction is needed for compatibility with Xilinx WebPack |
function Delta(Arg : std_logic_vector; Cnt : natural) return std_logic_vector is |
variable tmp : std_logic_vector(Arg'range); |
constant lo : integer := Arg'high -cnt +1; |
begin |
tmp := Arg; |
for n in 1 to cnt loop |
tmp := ( tmp(Arg'high) & tmp(Arg'high downto 1) ); |
for n in Arg'high downto lo loop |
tmp(n) := Arg(Arg'high); |
end loop; |
for n in Arg'high -cnt downto 0 loop |
tmp(n) := Arg(n +cnt); |
end loop; |
return tmp; |
end function Delta; |
|
/trunk/rect2polar/cordic.vhd
1,8 → 1,11
-- |
-- VHDL implementation of cordic algorithm |
-- |
-- File: cordic.vhd |
-- author: Richard Herveille |
-- rev. 1.0 initial release |
-- rev. 1.1 changed CordicPipe component declaration, Xilinx WebPack issue |
-- |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
41,18 → 44,22
-- COMPONENT declarations |
-- |
component CordicPipe |
generic( |
WIDTH : natural; |
AWIDTH : natural; |
PIPEID : natural); |
port( |
clk : in std_logic; |
ena : in std_logic; |
generic( |
WIDTH : natural := 16; |
AWIDTH : natural := 16; |
PIPEID : natural := 1 |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
|
Xi, Yi : in std_logic_vector(PRECISION downto 0); |
Zi : in std_logic_vector(ANG -1 downto 0); |
Xo, Yo : out std_logic_vector(PRECISION downto 0); |
Zo : out std_logic_vector(ANG -1 downto 0)); |
Xi : in std_logic_vector(WIDTH -1 downto 0); |
Yi : in std_logic_vector(WIDTH -1 downto 0); |
Zi : in std_logic_vector(AWIDTH -1 downto 0); |
Xo : out std_logic_vector(WIDTH -1 downto 0); |
Yo : out std_logic_vector(WIDTH -1 downto 0); |
Zo : out std_logic_vector(AWIDTH -1 downto 0) |
); |
end component CordicPipe; |
|
-- |