URL
https://opencores.org/ocsvn/dirac/dirac/trunk
Subversion Repositories dirac
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- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/src/testbench/ArithmeticCoderTestbench.vhd
27,8 → 27,6
PORT( |
ENABLE : IN std_logic; |
DATA_IN : IN std_logic; |
CONTEXT_ENABLE : in std_logic; |
CONTEXT_IN : in std_logic_vector (5 downto 0); |
RESET : IN std_logic; |
CLOCK : IN std_logic; |
SENDING : OUT std_logic; |
55,9 → 53,7
signal TRANSMIT : std_logic; |
signal DATA_TRANSFER : std_logic; |
constant PERIOD : time := 10 ns; |
signal CONTEXT_ENABLE : std_logic; |
signal CONTEXT : std_logic_vector (5 downto 0) := "000000"; |
file TESTDATA : text is in ""; |
file TESTDATA : text is in "raw_data"; |
file RESULTS : text is out "results"; |
|
BEGIN |
68,8 → 64,6
PORT MAP( |
ENABLE => ENABLE, |
DATA_IN => DATA_IN, |
CONTEXT_ENABLE => CONTEXT_ENABLE, |
CONTEXT_IN => CONTEXT, |
RESET => RESET, |
CLOCK => CLOCK, |
SENDING => TRANSMIT, |
135,6 → 129,7
if (WRITTEN mod 32) = 31 then |
writeline(RESULTS,OUTLINE); |
end if; |
end if; |
end loop; |
end process; |
|
/trunk/src/common/ARITHMETIC_UNIT.vhd
1,6 → 1,6
-- ***** BEGIN LICENSE BLOCK ***** |
-- |
-- $Id: ARITHMETIC_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ |
-- $Id: ARITHMETIC_UNIT.vhd,v 1.2 2005-04-26 13:40:14 petebleackley Exp $ $Name: not supported by cvs2svn $ |
-- * |
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 |
-- * |
20,7 → 20,7
-- * Portions created by the Initial Developer are Copyright (C) 2004. |
-- * All Rights Reserved. |
-- * |
-- * Contributor(s): Peter Bleackley (Original author) |
|
-- * |
-- * Alternatively, the contents of this file may be used under the terms of |
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser |
70,7 → 70,7
signal PRODUCT : std_logic_vector (26 downto 0); |
signal PRODUCT2 : std_logic_vector (16 downto 0); |
signal RESULT : std_logic_vector (16 downto 0); |
signal RESULT0 : std_logic_vector (15 downto 0); |
signal RESULT0 : std_logic_vector (16 downto 0); |
signal DIFFERENCE1 : std_logic_vector (16 downto 0); |
signal DIFFERENCE2 : std_logic_vector(16 downto 0); |
signal DIFFERENCE3 : std_logic_vector(16 downto 0); |