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/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_in.v File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_out.v File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.ucf File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/README.txt File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.mhs File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/makefile File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.c File deleted
/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.h File deleted
/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v File deleted
/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_in.v File deleted
/trunk/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v File deleted
/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_out.v File deleted
/trunk/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v File deleted
/trunk/fsl2serial_v1_00_a/docs/fsl2serial.ucf File deleted
/trunk/fsl2serial_v1_00_a/docs/README.txt File deleted
/trunk/fsl2serial_v1_00_a/docs/fsl2serial.mhs File deleted
/trunk/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd File deleted
/trunk/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao File deleted
/trunk/fsl2serial_v1_00_a/code/fsl_interface.c File deleted
/trunk/fsl2serial_v1_00_a/code/fsl_interface.h File deleted
/trunk/fsl2serial_v1_00_a/code/makefile File deleted
/fsl2serial/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v
0,0 → 1,157
// This module controls the serial modules.
//
// Alex Marschner
// 2007.02.20
 
`timescale 1 ns / 100 ps
 
module serial_ctrl (
fsl_data_i, fsl_senddata_i, fsl_cts_o,
fsl_data_o, fsl_rxdata_o, fsl_cts_i,
rs232_tx_data_o, rs232_rx_data_i, rs232_rts_i, rs232_cts_o,
clock, reset
);
 
parameter CLOCK_FREQ_MHZ = 50;
parameter BAUD_RATE = 115200;
 
input wire [7:0] fsl_data_i;
input wire fsl_senddata_i;
output reg fsl_cts_o;
output reg [7:0] fsl_data_o;
output reg fsl_rxdata_o;
input wire fsl_cts_i;
output wire rs232_tx_data_o;
input wire rs232_rx_data_i; // serial == 1 wire :)
input wire rs232_rts_i;
output reg rs232_cts_o;
 
input wire clock, reset;
 
wire [7:0] rs232_rx_data;
wire rs232_tx_ready;
reg rs232_rts;
wire rs232_rx_have_data;
 
///////////////////////////////////////////////////////////////////////////
// Serial In Module
serial_in
#(
.clk_freq(CLOCK_FREQ_MHZ * 1000000),
.data_rate(BAUD_RATE),
.delay_size(14)
) serial_in0 (
.clk(clock),
.rst(reset),
.serial_i(rs232_rx_data_i), // serial input line
.data_o(rs232_rx_data), // parallel data received
.have_data_o(rs232_rx_have_data) // data_exists line
);
///////////////////////////////////////////////////////////////////////////
// Serial Out Module
serial_out
#(
.clk_freq(CLOCK_FREQ_MHZ * 1000000),
.data_rate(BAUD_RATE))
serial_out0(
.clk(clock),
.rst(reset),
.data_size_i(8),
.data_i(fsl_data_i), // data to send out serially
.start_i(fsl_senddata_i), // start sending trigger
.serial_o(rs232_tx_data_o), // serial output line
.ready_o(rs232_tx_ready) // serial out !busy
);
 
always @ (posedge clock) begin
if(reset) begin
fsl_cts_o <= 1'b0;
fsl_data_o <= 8'h00;
fsl_rxdata_o <= 1'b0;
rs232_cts_o <= 1'b0;
rs232_rts <= 1'b0;
end
else begin
rs232_cts_o <= 1'b1; // always accept data from outside
fsl_cts_o <= rs232_tx_ready;
fsl_data_o <= rs232_rx_data;
rs232_rts <= rs232_rts_i; // incoming data?
fsl_rxdata_o <= fsl_cts_i ? rs232_rx_have_data : fsl_rxdata_o; // we have data
end
end
 
endmodule
 
///////////////////////////////////////////////////////////////////////////////
 
module serial_ctrl_tb ( );
 
reg [7:0] fsl_data_i;
reg fsl_senddata_i;
wire fsl_cts_o;
wire [7:0] fsl_data_o;
wire fsl_rxdata_o;
reg fsl_cts_i;
wire rs232_tx_data_o;
reg rs232_rx_data_i;
reg rs232_rts_i;
wire rs232_cts_o;
reg clock, reset;
 
serial_ctrl serial_ctrl_0(
.fsl_data_i (fsl_data_i),
.fsl_senddata_i (fsl_senddata_i),
.fsl_cts_o (fsl_cts_o),
.fsl_data_o (fsl_data_o),
.fsl_rxdata_o (fsl_rxdata_o),
.fsl_cts_i (fsl_cts_i),
.rs232_tx_data_o (rs232_tx_data_o),
.rs232_rx_data_i (rs232_rx_data_i),
.rs232_rts_i (rs232_rts_i),
.rs232_cts_o (rs232_cts_o),
.clock (clock),
.reset (reset)
);
 
initial begin
clock <= 1'b0;
reset <= 1'b1;
fsl_data_i <= 8'h00;
fsl_senddata_i <= 1'b0;
fsl_cts_i <= 1'b0;
rs232_rx_data_i <= 1'b1;
rs232_rts_i <= 1'b0;
 
#1000 reset <= 1'b0;
 
#1000 fsl_data_i <= 8'hAB;
fsl_senddata_i <= 1'b1;
#60 fsl_senddata_i <= 1'b0;
 
#4166400 rs232_rx_data_i <= 1'b0; // start bit
#416640 rs232_rx_data_i <= 1'b1;
#416640 rs232_rx_data_i <= 1'b1;
#416640 rs232_rx_data_i <= 1'b0;
#416640 rs232_rx_data_i <= 1'b1;
#416640 rs232_rx_data_i <= 1'b0;
#416640 rs232_rx_data_i <= 1'b1;
#416640 rs232_rx_data_i <= 1'b0;
#416640 rs232_rx_data_i <= 1'b1;
#416640 rs232_rx_data_i <= 1'b1; // stop bit
 
// test logic goes here . . .
 
end
 
 
always @ (posedge clock) begin
// fsl_senddata_i <= 1'b0;
end
 
always begin
#20 clock <= ~clock;
end
 
endmodule
 
/fsl2serial/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_in.v
0,0 → 1,111
// Todd Fleming 2005
 
`timescale 1 ns / 100 ps
 
module serial_in(
clk,
rst,
serial_i,
data_o,
have_data_o,
frame_error_o,
serial_samping_o);
input clk, rst, serial_i;
output[7:0] data_o;
output have_data_o, frame_error_o, serial_samping_o;
 
parameter clk_freq = 100000000;
parameter data_rate = 115200;
parameter bit_length = clk_freq / data_rate;
parameter delay_size = 12; // Must be large enough to store bit_length
parameter use_parity = 0;
parameter parity_is_odd = 1;
reg[7:0] data_o;
reg parity;
reg have_data_o, frame_error_o, serial_samping_o;
reg temp, buffered_serial;
reg[2:0] state;
reg[delay_size-1:0] delay;
reg[3:0] bits_received;
parameter state_wait_for_start = 3'd0;
parameter state_wait_for_bit = 3'd1;
parameter state_wait_for_stop = 3'd2;
parameter state_wait_for_parity = 3'd3;
parameter state_frame_error = 3'd4;
always @(posedge clk) begin
temp <= serial_i;
buffered_serial <= temp;
serial_samping_o <= 1'd0;
if(rst) begin
data_o <= 8'd0;
have_data_o <= 1'd0;
frame_error_o <= 1'd0;
state <= state_wait_for_start;
end else begin
case(state)
state_wait_for_start: begin
have_data_o <= 1'b0;
frame_error_o <= 1'b0;
if(!buffered_serial) begin
serial_samping_o <= 1'd1;
state <= state_wait_for_bit;
delay <= bit_length + bit_length / 2;
bits_received <= 0;
end
end
state_wait_for_bit: begin
if(delay == 1) begin
serial_samping_o <= 1'd1;
data_o <= {buffered_serial, data_o[7:1]};
delay <= bit_length;
bits_received <= bits_received + 1;
if(bits_received == 7)
if(use_parity)
state <= state_wait_for_parity;
else
state <= state_wait_for_stop;
end else
delay <= delay - 1;
end
state_wait_for_parity: begin
if(delay == 1) begin
serial_samping_o <= 1'd1;
parity <= buffered_serial;
delay <= bit_length;
state <= state_wait_for_stop;
end else
delay <= delay - 1;
end
state_wait_for_stop: begin
if(delay == 1) begin
serial_samping_o <= 1'd1;
if(buffered_serial) begin
if(!use_parity || ((^data_o) ^ parity) == parity_is_odd)
have_data_o <= 1'b1;
frame_error_o <= 1'b0;
state <= state_wait_for_start;
end else begin
have_data_o <= 1'b0;
frame_error_o <= 1'b1;
state <= state_frame_error;
end
end else
delay <= delay - 1;
end
state_frame_error: begin
if(buffered_serial)
state <= state_wait_for_start;
end
endcase
end
end
endmodule // serial_in
/fsl2serial/trunk/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v
0,0 → 1,249
// This top level module ties together the FSL control and Serial control
// modules to make an active, two way serial to FSL / FSL to serial bridge.
//
// Alex Marschner
// 2007.02.20
 
`timescale 1 ns / 100 ps
 
module fsl2serial( clock, reset, // clock and reset
rs232_tx_data_o, //
rs232_rx_data_i,
rs232_rts_i,
rs232_cts_o,
 
FSL_S_CLK, FSL_S_DATA, FSL_S_CONTROL, FSL_S_EXISTS, FSL_S_READ,
FSL_M_CLK, FSL_M_DATA, FSL_M_CONTROL, FSL_M_FULL, FSL_M_WRITE
);
 
parameter EXT_RESET_ACTIVE_HI = 0;
parameter CLOCK_FREQ_MHZ = 50;
parameter BAUD_RATE = 115200;
 
input wire clock, reset;
output wire rs232_tx_data_o;
input wire rs232_rx_data_i;
input wire rs232_rts_i;
output wire rs232_cts_o;
 
input wire [0:31] FSL_S_DATA;
input wire FSL_S_CONTROL;
input wire FSL_S_EXISTS;
input wire FSL_M_FULL;
 
output wire [0:31] FSL_M_DATA;
output wire FSL_M_CONTROL;
output wire FSL_M_WRITE;
output wire FSL_S_READ;
 
output wire FSL_M_CLK;
output wire FSL_S_CLK;
 
wire ser2fsl_cts, fsl2ser_cts;
wire fsl2ser_start, ser2fsl_dataexists;
wire [7:0] ser2fsl_data;
wire [7:0] fsl2ser_data;
wire reset_correct_polarity;
 
assign reset_correct_polarity = EXT_RESET_ACTIVE_HI ? reset : ~reset;
 
assign FSL_M_DATA[0:23] = 24'b0; // only use last byte since we are dealing with serial characters
 
fsl_ctrl fsl_ctrl0(
.FSL_S_CLK (FSL_S_CLK),
.FSL_S_DATA (FSL_S_DATA[24:31]),
.FSL_S_CONTROL (FSL_S_CONTROL),
.FSL_S_EXISTS (FSL_S_EXISTS),
.FSL_S_READ (FSL_S_READ),
.FSL_M_CLK (FSL_M_CLK),
.FSL_M_DATA (FSL_M_DATA[24:31]),
.FSL_M_CONTROL (FSL_M_CONTROL),
.FSL_M_FULL (FSL_M_FULL),
.FSL_M_WRITE (FSL_M_WRITE),
.rs232_tx_ready (ser2fsl_cts),
.rs232_tx_data (fsl2ser_data),
.rs232_tx_start (fsl2ser_start),
.rs232_rx_ready (fsl2ser_cts),
.rs232_rx_data (ser2fsl_data),
.rs232_rx_exists (ser2fsl_dataexists),
.clock (clock),
.reset (reset_correct_polarity)
);
 
serial_ctrl #(
.CLOCK_FREQ_MHZ(CLOCK_FREQ_MHZ),
.BAUD_RATE(BAUD_RATE)
) serial_ctrl0 (
.fsl_data_i (fsl2ser_data),
.fsl_senddata_i (fsl2ser_start),
.fsl_cts_o (ser2fsl_cts),
.fsl_data_o (ser2fsl_data),
.fsl_rxdata_o (ser2fsl_dataexists),
.fsl_cts_i (fsl2ser_cts),
.rs232_tx_data_o (rs232_tx_data_o),
.rs232_rx_data_i (rs232_rx_data_i),
.rs232_rts_i (rs232_rts_i),
.rs232_cts_o (rs232_cts_o),
.clock (clock),
.reset (reset_correct_polarity)
);
 
/*
//-----------------------------------------------------------------
//
// ICON/ILA core wire declarations
//
//-----------------------------------------------------------------
wire [35:0] control0;
wire [31:0] trig0;
 
assign trig0 = {FSL_S_DATA[24:31],FSL_S_READ,FSL_S_EXISTS,
fsl2ser_data,fsl2ser_start,ser2fsl_cts,
rs232_tx_data_o, rs232_cts_o, reset_correct_polarity, 9'b0};
 
//-----------------------------------------------------------------
//
// ICON core instance
//
//-----------------------------------------------------------------
icon i_icon
(
.control0(control0)
);
 
//-----------------------------------------------------------------
//
// ILA core instance
//
//-----------------------------------------------------------------
ila i_ila
(
.control(control0),
.clk(clock),
.trig0(trig0)
);
 
endmodule
 
 
//-------------------------------------------------------------------
//
// ICON core module declaration
//
//-------------------------------------------------------------------
module icon
(
control0
);
output [35:0] control0;
endmodule
 
//-------------------------------------------------------------------
//
// ILA core module declaration
//
//-------------------------------------------------------------------
module ila
(
control,
clk,
trig0
);
input [35:0] control;
input clk;
input [31:0] trig0;*/
endmodule
 
///////////////////////////////////////////////////////////////////////////////
 
// TBD:
// [x] test the FSL 2 Serial direction
// [ ] test the Serial 2 FSL direction
 
module fsl2serial_tb ( );
 
reg clock, reset_n;
wire rs232_tx_data_o;
reg rs232_rx_data_i;
reg rs232_rts_i;
wire rs232_cts_o;
 
reg [0:31] FSL_S_DATA;
reg FSL_S_CONTROL;
wire [0:31] FSL_M_DATA;
wire FSL_M_CONTROL;
wire FSL_S_CLK, FSL_M_CLK;
wire FSL_M_WRITE, FSL_S_READ;
reg FSL_M_FULL, FSL_S_EXISTS;
 
initial begin
clock <= 1'b0;
reset_n <= 1'b0;
rs232_rx_data_i <= 1'b1;
rs232_rts_i <= 1'b0;
FSL_S_DATA <= 32'h00000000;
FSL_S_CONTROL <= 1'b0;
FSL_M_FULL <= 1'b0;
FSL_S_EXISTS <= 1'b0;
 
#1000 reset_n <= 1'b1;
#1000 FSL_S_DATA <= 8'hA0;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
 
#1000 FSL_S_DATA <= FSL_S_DATA + 1;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
#1000 FSL_S_DATA <= FSL_S_DATA + 1;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
#2070750 rs232_rx_data_i <= 1'b0; // start bit
#207075 rs232_rx_data_i <= 1'b1;
#207075 rs232_rx_data_i <= 1'b1;
#207075 rs232_rx_data_i <= 1'b0;
#207075 rs232_rx_data_i <= 1'b1;
#207075 rs232_rx_data_i <= 1'b0;
#207075 rs232_rx_data_i <= 1'b1;
#207075 rs232_rx_data_i <= 1'b0;
#207075 rs232_rx_data_i <= 1'b1;
#207075 rs232_rx_data_i <= 1'b1; // stop bit
 
 
end
 
always begin
#10 clock <= ~clock; // 50MHz
end
 
fsl2serial bridge(
.clock (clock),
.reset (reset_n),
.rs232_tx_data_o (rs232_tx_data_o),
.rs232_rx_data_i (rs232_rx_data_i),
.rs232_rts_i (rs232_rts_i),
.rs232_cts_o (rs232_cts_o),
.FSL_S_CLK (FSL_S_CLK),
.FSL_S_DATA (FSL_S_DATA),
.FSL_S_CONTROL (FSL_S_CONTROL),
.FSL_S_EXISTS (FSL_S_EXISTS),
.FSL_S_READ (FSL_S_READ),
.FSL_M_CLK (FSL_M_CLK),
.FSL_M_DATA (FSL_M_DATA),
.FSL_M_CONTROL (FSL_M_CONTROL),
.FSL_M_FULL (FSL_M_FULL),
.FSL_M_WRITE (FSL_M_WRITE)
);
 
endmodule
 
/fsl2serial/trunk/fsl2serial_v1_00_a/hdl/verilog/serial_out.v
0,0 → 1,162
// Todd Fleming 2005
 
`timescale 1 ns / 100 ps
 
module serial_out(
clk,
rst,
data_size_i,
data_i,
start_i,
serial_o,
ready_o,
bit_sync_o);
parameter clk_freq = 100000000;
parameter data_rate = 115200;
parameter bit_length = clk_freq / data_rate;
parameter delay_size = 32; // Must be large enough to store bit_length
parameter max_data_size = 8;
parameter data_size_size = 4; // Must be large enough to store max_data_size
parameter use_start = 1;
parameter use_stop = 1;
parameter use_parity = 0;
parameter stop_value = 1;
parameter parity_is_odd = 1;
input clk, rst;
input[data_size_size-1:0] data_size_i;
input[max_data_size-1:0] data_i;
input start_i;
output serial_o;
output ready_o;
output bit_sync_o;
reg[2:0] state;
reg[data_size_size-1:0] data_size;
reg[max_data_size-1:0] data;
reg[delay_size-1:0] delay;
reg[max_data_size-1:0] num_sent;
reg serial_o;
reg bit_sync_o;
parameter state_wait_for_start = 3'd0;
parameter state_send_start = 3'd1;
parameter state_send_bit = 3'd2;
parameter state_send_parity = 3'd3;
parameter state_send_stop = 3'd4;
assign ready_o =
(state == state_wait_for_start || state == state_send_stop && delay == 1) && !start_i;
always @(posedge clk) begin
bit_sync_o <= 0;
if(rst) begin
state <= state_wait_for_start;
end else begin
delay <= delay - 1;
case(state)
state_wait_for_start: begin
serial_o <= stop_value;
if(start_i) begin
data_size <= data_size_i;
data <= data_i;
num_sent <= 0;
if(use_start) begin
serial_o <= ~stop_value;
delay <= bit_length - 1;
state <= state_send_start;
end else begin
serial_o <= data_i[0];
delay <= bit_length - 1;
state <= state_send_bit;
end
end
end
state_send_start: begin
serial_o <= ~stop_value;
if(delay == 1) begin
delay <= bit_length;
state <= state_send_bit;
end
end
state_send_bit: begin
serial_o <= data[0];
if(delay == bit_length - 2)
bit_sync_o <= 1;
if(delay == 1) begin
delay <= bit_length;
data <= data >> 1;
num_sent <= num_sent + 1;
if(num_sent == data_size - 1)
if(use_parity)
state <= state_send_parity;
else if(use_stop)
state <= state_send_stop;
else
state <= state_wait_for_start;
end
end
state_send_parity: begin
serial_o <= (^data[0]) ^ parity_is_odd;
if(delay == 1) begin
delay <= bit_length;
state <= state_send_stop;
end
end
state_send_stop: begin
serial_o <= stop_value;
if(delay == 1) begin
delay <= bit_length;
state <= state_wait_for_start;
end
end
endcase
end
end
endmodule // serial_out
 
///////////////////////////////////////////////////////////////////////////////
 
module serial_out_tb ( );
 
reg clock, reset;
reg [7:0] fsl_data_i;
reg fsl_senddata_i;
wire rs232_tx_data_o;
wire rs232_tx_ready;
 
initial begin
clock <= 1'b0;
reset <= 1'b1;
fsl_data_i <= 8'h00;
fsl_senddata_i <= 1'b0;
 
#1000 reset <= 1'b0;
#1000 fsl_data_i <= 8'h0A;
fsl_senddata_i <= 1'b1;
#60 fsl_senddata_i <= 1'b0;
end
 
always begin
#10 clock <= ~clock;
end
 
// Serial Out Module
serial_out
#(
.clk_freq(50000000),
.data_rate(115200))
serial_out0(
.clk(clock),
.rst(reset),
.data_size_i(8),
.data_i(fsl_data_i), // data to send out serially
.start_i(fsl_senddata_i), // start sending trigger
.serial_o(rs232_tx_data_o), // serial output line
.ready_o(rs232_tx_ready) // serial out !busy
);
 
endmodule
/fsl2serial/trunk/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v
0,0 → 1,149
// This module sends the correct control signals to the slave FSL port in
// order to get the data out.
//
// Alex Marschner
// 2007.02.20
 
`timescale 1 ns / 100 ps
 
module fsl_ctrl (
FSL_S_CLK, FSL_S_DATA, FSL_S_CONTROL, FSL_S_EXISTS, FSL_S_READ,
FSL_M_CLK, FSL_M_DATA, FSL_M_CONTROL, FSL_M_FULL, FSL_M_WRITE,
rs232_tx_ready, rs232_tx_data, rs232_tx_start,
rs232_rx_ready, rs232_rx_data, rs232_rx_exists,
clock, reset
);
 
output wire FSL_S_CLK;
input wire [0:7] FSL_S_DATA;
input wire FSL_S_CONTROL;
input wire FSL_S_EXISTS;
output reg FSL_S_READ;
 
output wire FSL_M_CLK;
output reg [0:7] FSL_M_DATA;
output reg FSL_M_CONTROL;
input wire FSL_M_FULL;
output reg FSL_M_WRITE;
 
output reg rs232_rx_ready;
input wire [7:0] rs232_rx_data;
input wire rs232_rx_exists;
 
input wire rs232_tx_ready;
output wire [7:0] rs232_tx_data;
output wire rs232_tx_start;
 
input wire clock, reset;
 
assign FSL_S_CLK = clock;
//assign FSL_M_CLK = clock;
 
assign rs232_tx_data = FSL_S_DATA;
assign rs232_tx_start = FSL_S_READ;
 
always @ (posedge clock) begin
if(reset) begin
FSL_S_READ <= 1'b0;
FSL_M_DATA <= 8'h00;
FSL_M_CONTROL <= 1'b0;
FSL_M_WRITE <= 1'b0;
rs232_rx_ready <= 1'b0;
end
else begin
FSL_S_READ <= (FSL_S_EXISTS & (~FSL_S_READ) & rs232_tx_ready) ? 1'b1 : 1'b0;
FSL_M_DATA <= rs232_rx_data;
FSL_M_CONTROL <= 1'b0;
FSL_M_WRITE <= (!FSL_M_FULL & (~FSL_M_WRITE) & rs232_rx_exists) ? 1'b1 : 1'b0;
rs232_rx_ready <= 1'b1; // always ready to get data from outside
end
end
 
endmodule
 
///////////////////////////////////////////////////////////////////////////////
 
module fsl_ctrl_tb ( );
 
reg clock, reset;
wire FSL_S_CLK, FSL_S_READ;
reg [0:7] FSL_S_DATA;
reg FSL_S_CONTROL;
reg FSL_S_EXISTS;
reg rs232_tx_ready;
wire [7:0] rs232_tx_data;
wire rs232_tx_start;
reg [7:0] registered_out;
 
 
fsl_ctrl fsl_ctrl_0(
.FSL_S_CLK (FSL_S_CLK),
.FSL_S_DATA (FSL_S_DATA),
.FSL_S_CONTROL (FSL_S_CONTROL),
.FSL_S_EXISTS (FSL_S_EXISTS),
.FSL_S_READ (FSL_S_READ),
.rs232_tx_ready (rs232_tx_ready),
.rs232_tx_data (rs232_tx_data),
.rs232_tx_start (rs232_tx_start),
.clock (clock),
.reset (reset)
);
 
initial begin
clock <= 1'b0;
reset <= 1'b1;
FSL_S_DATA <= 8'h00;
FSL_S_CONTROL <= 1'b0;
FSL_S_EXISTS <= 1'b0;
rs232_tx_ready <= 1'b0;
 
#1000 reset <= 1'b0;
#20 rs232_tx_ready <= 1'b1;
 
#1000 FSL_S_DATA <= 8'hA0;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
 
#1000 FSL_S_DATA <= FSL_S_DATA + 1;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
#1000 FSL_S_DATA <= FSL_S_DATA + 1;
FSL_S_EXISTS <= 1'b1;
while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1;
FSL_S_EXISTS <= 1'b0;
#1000 while(1) FSL_S_EXISTS <= 1'b0;
end
 
always @ (posedge clock) begin
if(reset) registered_out <= 8'b0;
else registered_out <= rs232_tx_start ? rs232_tx_data : registered_out;
end
 
always @ (posedge clock) begin
if(reset) rs232_tx_ready <= 1'b0;
else begin
if(rs232_tx_start) begin
rs232_tx_ready <= 1'b0;
#4000 rs232_tx_ready <= 1'b1;
end
end
end
 
always @ (posedge clock) begin
FSL_S_EXISTS <= (FSL_S_EXISTS && FSL_S_READ) ? 1'b0 : FSL_S_EXISTS;
FSL_S_DATA <= (FSL_S_EXISTS && FSL_S_READ) ? (FSL_S_DATA+1) : FSL_S_DATA;
end
 
always begin
#20 clock <= ~clock;
end
 
endmodule
 
/fsl2serial/trunk/fsl2serial_v1_00_a/docs/fsl2serial.ucf
0,0 → 1,7
#### Module FSL2Serial Constraints ####
 
NET "rs232_tx_data_o_pin" LOC = "AE7" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW;
NET "rs232_rx_data_i_pin" LOC = "AJ8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW;
NET "rs232_rts_i_pin" LOC = "AK8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW;
NET "rs232_cts_o_pin" LOC = "AE8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW;
 
/fsl2serial/trunk/fsl2serial_v1_00_a/docs/README.txt
0,0 → 1,48
In order to use the FSL2Serial module in XPS, follow these steps:
 
1) Place the entire containing folder, fsl2serial_v1_00_a, into your pcores directory.
2) Start XPS (or restart - this may be necessary).
 
3) Click on the "IP Catalog" tab, expand "Project Repository", and insert the FSL2Serial module.
4) Right click on the module name in the "System Assembly View", and select "Configure IP."
- make sure you indicate the correct system reset polarity (usually board reset polarity)
- set your clock speed in MHz (eg, 100). The range is 0-200.
- set your baud rate. Default is 115200, normal people use 9600
5) Insert the following information into the following places:
- pcores/fsl2serial_v1_00_a/docs/fsl2serial.ucf --> data/system.ucf
- pcores/fsl2serial_v1_00_a/docs/fsl2serial.mhs --> system.mhs
 
Note: if XPS is open and you make this change using some other editor,
XPS will override your changes!!
 
6) In the "Ports" view, expand fsl2serial and connect the clock, rst, and rs232 pins.
 
 
Adding the FSL busses:
 
1) In the "IP Catalog" tab, expand "Bus", and add TWO instances of the fsl_v20 bus.
2) For each of these instances,
 
- right click, select "Configure IP"
- uncheck the box that says "External Reset Active High" (if appropriate)
- click "Ok"
 
- in the "Ports" view, expand the bus
- connect the FSL_Clk and FSL_Rst to the system clock and reset
 
3) Back in the "Bus Interface" view:
- attach the Master port of your processor and the Slave port of FSL2serial to one FSL bus.
- attach the Slave port of your processor and the Master port of FSL2serial to the other.
 
 
You should now be ready to write programs that use the FSL2Serial link as serial output.
Sample code is available in the fsl2serial_v1_00_a/code/ directory.
 
 
2007.03.12
Alex Marschner
 
 
 
 
 
/fsl2serial/trunk/fsl2serial_v1_00_a/docs/fsl2serial.mhs
0,0 → 1,4
PORT rs232_tx_data_o_pin = rs232_tx_data_o, DIR = O
PORT rs232_rx_data_i_pin = rs232_rx_data_i, DIR = I
PORT rs232_rts_i_pin = rs232_rts_i, DIR = I
PORT rs232_cts_o_pin = rs232_cts_o, DIR = O
/fsl2serial/trunk/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao
0,0 → 1,11
##############################################################################
## Filename: /home/amarschn/projects/OpenFire_OPB/openfire_2/pcores/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Thu Feb 22 14:37:13 2007 (by Create and Import Peripheral Wizard)
##############################################################################
 
lib fsl2serial_v1_00_a fsl2serial verilog
lib fsl2serial_v1_00_a fsl_ctrl verilog
lib fsl2serial_v1_00_a serial_ctrl verilog
lib fsl2serial_v1_00_a serial_in verilog
lib fsl2serial_v1_00_a serial_out verilog
/fsl2serial/trunk/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd
0,0 → 1,47
###################################################################
##
## Name : fsl2serial
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
 
BEGIN fsl2serial
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
 
## Parameters / Generics
PARAMETER EXT_RESET_ACTIVE_HI = 0, DT = INTEGER, RANGE = (0:1), DESC = Reset signal is active high:
PARAMETER CLOCK_FREQ_MHZ = 50, DT = INTEGER, RANGE = (0:200), DESC = Processor speed in MHz:
PARAMETER BAUD_RATE = 115200, DT = INTEGER, VALUES = (2400=2400, 9600=9600, 115200=115200), DESC = Serial communication speed:
 
## Bus Interfaces
BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL
BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL
 
## Generics for VHDL or Parameters for Verilog
 
## Ports
PORT clock = "", DIR = I, SIGIS = CLK
PORT reset = "", DIR = I, SIGIS = RST
PORT rs232_tx_data_o = "", DIR = O
PORT rs232_rx_data_i = "", DIR = I
PORT rs232_rts_i = "", DIR = I
PORT rs232_cts_o = "", DIR = O
PORT FSL_S_DATA = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL
PORT FSL_S_CONTROL = FSL_S_Control, DIR = I, BUS = SFSL
PORT FSL_S_EXISTS = FSL_S_Exists, DIR = I, BUS = SFSL
PORT FSL_M_FULL = FSL_M_Full, DIR = I, BUS = MFSL
PORT FSL_M_DATA = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL
PORT FSL_M_CONTROL = FSL_M_Control, DIR = O, BUS = MFSL
PORT FSL_M_WRITE = FSL_M_Write, DIR = O, BUS = MFSL
PORT FSL_S_READ = FSL_S_Read, DIR = O, BUS = SFSL
PORT FSL_M_CLK = FSL_M_Clk, DIR = O, BUS = MFSL
PORT FSL_S_CLK = FSL_S_Clk, DIR = O, BUS = SFSL
 
END
/fsl2serial/trunk/fsl2serial_v1_00_a/code/fsl_interface.c
0,0 → 1,97
// This is the source file implementing the FSL interface developed for use with the FSL2Serial
// module. Data can also be sent over this link, but the assumption is that text will be sent.
//
// This requires the Xilinx FSL interface code, which can generally be found in fsl.h,
// mb_interface.h, and xbasic_types.h
//
// Alex Marschner
// 2007.03.12
 
#include "fsl_interface.h"
 
// Put a string of data through the specified FSL port.
void fsl0print(const char* s)
{
while(*s)
{
putfsl(*s, FSL0);
++s;
}
return;
}
 
// Put a string of data through the specified FSL port.
void fsl0nprint(const char* s)
{
while(*s)
{
nputfsl(*s, FSL0);
++s;
}
return;
}
 
// Print a single character to the specified FSL port. (BLOCKING)
void fsl0put(const char s)
{
putfsl(s, FSL0);
return;
}
 
// Print a single character to the specified FSL port. (NONBLOCKING)
void fsl0nput(const char s)
{
nputfsl(s, FSL0);
return;
}
 
// Get a single character from the specified FSL port. (BLOCKING)
char fsl0get(char * s)
{
char inchar;
getfsl(inchar, FSL0);
if(s!=NULL) (*s) = inchar;
 
return inchar;
}
 
// Get a single character from the specified FSL port. (NONBLOCKING)
char fsl0nget(char * s)
{
char inchar;
ngetfsl(inchar, FSL0);
if(s!=NULL) (*s) = inchar;
 
return inchar;
}
 
// Print the hexadecimal representation of a 32-bit integer to the specified FSL port.
void fsl0hex(const unsigned int val)
{
char hexstring[10];
unsigned int shiftval = val;
char maskval;
int ctr;
 
for(ctr=9; ctr>1; ctr--)
{
maskval = shiftval & 0x0000000F;
 
if(maskval < 10)
hexstring[ctr] = maskval + 0x30;
else
hexstring[ctr] = maskval + (0x41-0xA);
 
shiftval = shiftval >> 4;
}
 
hexstring[0] = '0';
hexstring[1] = 'x';
 
fsl0print(hexstring);
return;
}
 
/fsl2serial/trunk/fsl2serial_v1_00_a/code/fsl_interface.h
0,0 → 1,47
// This is a header file describing the FSL interface developed for use with the FSL2Serial
// module. Data can also be sent over this link, but the assumption is that text will be sent.
//
// This requires the Xilinx FSL interface code, which can generally be found in fsl.h,
// mb_interface.h, and xbasic_types.h
//
// These functions cannot take the FSL ID as a parameter because the fsl functions used are
// actually macros for asm inline commands.
//
// Alex Marschner
// 2007.03.12
 
#ifndef FSL_INTERFACE_H
#define FSL_INTERFACE_H
 
#include "fsl.h" // getfsl(val, id), putfsl(val, id), (blocking)
// ngetfsl(val, id), nputfsl(val,id) (non blocking)
 
#define BOOL int
#define TRUE 1
#define FALSE 0
 
#define FSL_BLOCKING 1
#define FSL_NONBLOCKING 0
 
#define FSL0 0
 
// Put a string of data through the specified FSL port.
void fsl0print(const char* s);
void fsl0nprint(const char* s);
 
// Print a single character to the specified FSL port.
void fsl0put(const char s);
void fsl0nput(const char s);
 
// Get a single character from the specified FSL port.
char fsl0get(char * s);
char fsl0nget(char * s);
 
// Print the hexadecimal representation of a 32-bit integer to the specified FSL port.
void fsl0hex(const unsigned int val);
 
// Print the decimal representation of a 32-bit unsigned int to the specified FSL port.
//void fsldec(const unsigned int val, const unsigned int id);
 
#endif
 
/fsl2serial/trunk/fsl2serial_v1_00_a/code/makefile
0,0 → 1,10
HDRDIR_1=-I/project/software/Xilinx/EDK8.2/sw/XilinxProcessorIPLib/drivers/common_v1_00_a/src/
HDRDIR_2=-I/project/software/Xilinx/EDK8.2/sw/lib/bsp/standalone_v1_00_a/src/microblaze/
 
all:
mb-gcc -Wall -o ../executable.elf fsl_interface.c openfire_src.c $(HDRDIR_1) $(HDRDIR_2)
 
clean:
rm -rf *~
rm -rf *.o
rm -rf ../executable.elf
/fsl2serial/trunk
fsl2serial/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: fsl2serial/web_uploads =================================================================== --- fsl2serial/web_uploads (nonexistent) +++ fsl2serial/web_uploads (revision 4)
fsl2serial/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: fsl2serial/branches =================================================================== --- fsl2serial/branches (nonexistent) +++ fsl2serial/branches (revision 4)
fsl2serial/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_ctrl.v (revision 4) @@ -0,0 +1,157 @@ +// This module controls the serial modules. +// +// Alex Marschner +// 2007.02.20 + +`timescale 1 ns / 100 ps + +module serial_ctrl ( + fsl_data_i, fsl_senddata_i, fsl_cts_o, + fsl_data_o, fsl_rxdata_o, fsl_cts_i, + rs232_tx_data_o, rs232_rx_data_i, rs232_rts_i, rs232_cts_o, + clock, reset +); + +parameter CLOCK_FREQ_MHZ = 50; +parameter BAUD_RATE = 115200; + +input wire [7:0] fsl_data_i; +input wire fsl_senddata_i; +output reg fsl_cts_o; +output reg [7:0] fsl_data_o; +output reg fsl_rxdata_o; +input wire fsl_cts_i; +output wire rs232_tx_data_o; +input wire rs232_rx_data_i; // serial == 1 wire :) +input wire rs232_rts_i; +output reg rs232_cts_o; + +input wire clock, reset; + +wire [7:0] rs232_rx_data; +wire rs232_tx_ready; +reg rs232_rts; +wire rs232_rx_have_data; + + /////////////////////////////////////////////////////////////////////////// + // Serial In Module + serial_in + #( + .clk_freq(CLOCK_FREQ_MHZ * 1000000), + .data_rate(BAUD_RATE), + .delay_size(14) + ) serial_in0 ( + .clk(clock), + .rst(reset), + .serial_i(rs232_rx_data_i), // serial input line + .data_o(rs232_rx_data), // parallel data received + .have_data_o(rs232_rx_have_data) // data_exists line + ); + + /////////////////////////////////////////////////////////////////////////// + // Serial Out Module + serial_out + #( + .clk_freq(CLOCK_FREQ_MHZ * 1000000), + .data_rate(BAUD_RATE)) + serial_out0( + .clk(clock), + .rst(reset), + .data_size_i(8), + .data_i(fsl_data_i), // data to send out serially + .start_i(fsl_senddata_i), // start sending trigger + .serial_o(rs232_tx_data_o), // serial output line + .ready_o(rs232_tx_ready) // serial out !busy + ); + + always @ (posedge clock) begin + if(reset) begin + fsl_cts_o <= 1'b0; + fsl_data_o <= 8'h00; + fsl_rxdata_o <= 1'b0; + rs232_cts_o <= 1'b0; + rs232_rts <= 1'b0; + end + else begin + rs232_cts_o <= 1'b1; // always accept data from outside + fsl_cts_o <= rs232_tx_ready; + fsl_data_o <= rs232_rx_data; + rs232_rts <= rs232_rts_i; // incoming data? + fsl_rxdata_o <= fsl_cts_i ? rs232_rx_have_data : fsl_rxdata_o; // we have data + end + end + +endmodule + +/////////////////////////////////////////////////////////////////////////////// + +module serial_ctrl_tb ( ); + +reg [7:0] fsl_data_i; +reg fsl_senddata_i; +wire fsl_cts_o; +wire [7:0] fsl_data_o; +wire fsl_rxdata_o; +reg fsl_cts_i; +wire rs232_tx_data_o; +reg rs232_rx_data_i; +reg rs232_rts_i; +wire rs232_cts_o; +reg clock, reset; + +serial_ctrl serial_ctrl_0( + .fsl_data_i (fsl_data_i), + .fsl_senddata_i (fsl_senddata_i), + .fsl_cts_o (fsl_cts_o), + .fsl_data_o (fsl_data_o), + .fsl_rxdata_o (fsl_rxdata_o), + .fsl_cts_i (fsl_cts_i), + .rs232_tx_data_o (rs232_tx_data_o), + .rs232_rx_data_i (rs232_rx_data_i), + .rs232_rts_i (rs232_rts_i), + .rs232_cts_o (rs232_cts_o), + .clock (clock), + .reset (reset) +); + +initial begin + clock <= 1'b0; + reset <= 1'b1; + fsl_data_i <= 8'h00; + fsl_senddata_i <= 1'b0; + fsl_cts_i <= 1'b0; + rs232_rx_data_i <= 1'b1; + rs232_rts_i <= 1'b0; + + #1000 reset <= 1'b0; + + #1000 fsl_data_i <= 8'hAB; + fsl_senddata_i <= 1'b1; + #60 fsl_senddata_i <= 1'b0; + + #4166400 rs232_rx_data_i <= 1'b0; // start bit + #416640 rs232_rx_data_i <= 1'b1; + #416640 rs232_rx_data_i <= 1'b1; + #416640 rs232_rx_data_i <= 1'b0; + #416640 rs232_rx_data_i <= 1'b1; + #416640 rs232_rx_data_i <= 1'b0; + #416640 rs232_rx_data_i <= 1'b1; + #416640 rs232_rx_data_i <= 1'b0; + #416640 rs232_rx_data_i <= 1'b1; + #416640 rs232_rx_data_i <= 1'b1; // stop bit + + // test logic goes here . . . + +end + + +always @ (posedge clock) begin +// fsl_senddata_i <= 1'b0; +end + +always begin + #20 clock <= ~clock; +end + +endmodule + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_in.v =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_in.v (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_in.v (revision 4) @@ -0,0 +1,111 @@ +// Todd Fleming 2005 + +`timescale 1 ns / 100 ps + +module serial_in( + clk, + rst, + serial_i, + data_o, + have_data_o, + frame_error_o, + serial_samping_o); + + input clk, rst, serial_i; + output[7:0] data_o; + output have_data_o, frame_error_o, serial_samping_o; + + parameter clk_freq = 100000000; + parameter data_rate = 115200; + parameter bit_length = clk_freq / data_rate; + parameter delay_size = 12; // Must be large enough to store bit_length + parameter use_parity = 0; + parameter parity_is_odd = 1; + + reg[7:0] data_o; + reg parity; + reg have_data_o, frame_error_o, serial_samping_o; + reg temp, buffered_serial; + reg[2:0] state; + reg[delay_size-1:0] delay; + reg[3:0] bits_received; + + parameter state_wait_for_start = 3'd0; + parameter state_wait_for_bit = 3'd1; + parameter state_wait_for_stop = 3'd2; + parameter state_wait_for_parity = 3'd3; + parameter state_frame_error = 3'd4; + + always @(posedge clk) begin + temp <= serial_i; + buffered_serial <= temp; + serial_samping_o <= 1'd0; + + if(rst) begin + data_o <= 8'd0; + have_data_o <= 1'd0; + frame_error_o <= 1'd0; + state <= state_wait_for_start; + end else begin + case(state) + state_wait_for_start: begin + have_data_o <= 1'b0; + frame_error_o <= 1'b0; + if(!buffered_serial) begin + serial_samping_o <= 1'd1; + state <= state_wait_for_bit; + delay <= bit_length + bit_length / 2; + bits_received <= 0; + end + end + + state_wait_for_bit: begin + if(delay == 1) begin + serial_samping_o <= 1'd1; + data_o <= {buffered_serial, data_o[7:1]}; + delay <= bit_length; + bits_received <= bits_received + 1; + if(bits_received == 7) + if(use_parity) + state <= state_wait_for_parity; + else + state <= state_wait_for_stop; + end else + delay <= delay - 1; + end + + state_wait_for_parity: begin + if(delay == 1) begin + serial_samping_o <= 1'd1; + parity <= buffered_serial; + delay <= bit_length; + state <= state_wait_for_stop; + end else + delay <= delay - 1; + end + + state_wait_for_stop: begin + if(delay == 1) begin + serial_samping_o <= 1'd1; + if(buffered_serial) begin + if(!use_parity || ((^data_o) ^ parity) == parity_is_odd) + have_data_o <= 1'b1; + frame_error_o <= 1'b0; + state <= state_wait_for_start; + end else begin + have_data_o <= 1'b0; + frame_error_o <= 1'b1; + state <= state_frame_error; + end + end else + delay <= delay - 1; + end + + state_frame_error: begin + if(buffered_serial) + state <= state_wait_for_start; + end + endcase + end + end +endmodule // serial_in Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl2serial.v (revision 4) @@ -0,0 +1,249 @@ +// This top level module ties together the FSL control and Serial control +// modules to make an active, two way serial to FSL / FSL to serial bridge. +// +// Alex Marschner +// 2007.02.20 + +`timescale 1 ns / 100 ps + +module fsl2serial( clock, reset, // clock and reset + rs232_tx_data_o, // + rs232_rx_data_i, + rs232_rts_i, + rs232_cts_o, + + FSL_S_CLK, FSL_S_DATA, FSL_S_CONTROL, FSL_S_EXISTS, FSL_S_READ, + FSL_M_CLK, FSL_M_DATA, FSL_M_CONTROL, FSL_M_FULL, FSL_M_WRITE +); + + parameter EXT_RESET_ACTIVE_HI = 0; + parameter CLOCK_FREQ_MHZ = 50; + parameter BAUD_RATE = 115200; + + input wire clock, reset; + output wire rs232_tx_data_o; + input wire rs232_rx_data_i; + input wire rs232_rts_i; + output wire rs232_cts_o; + + input wire [0:31] FSL_S_DATA; + input wire FSL_S_CONTROL; + input wire FSL_S_EXISTS; + input wire FSL_M_FULL; + + output wire [0:31] FSL_M_DATA; + output wire FSL_M_CONTROL; + output wire FSL_M_WRITE; + output wire FSL_S_READ; + + output wire FSL_M_CLK; + output wire FSL_S_CLK; + + wire ser2fsl_cts, fsl2ser_cts; + wire fsl2ser_start, ser2fsl_dataexists; + wire [7:0] ser2fsl_data; + wire [7:0] fsl2ser_data; + + wire reset_correct_polarity; + + assign reset_correct_polarity = EXT_RESET_ACTIVE_HI ? reset : ~reset; + + assign FSL_M_DATA[0:23] = 24'b0; // only use last byte since we are dealing with serial characters + +fsl_ctrl fsl_ctrl0( + .FSL_S_CLK (FSL_S_CLK), + .FSL_S_DATA (FSL_S_DATA[24:31]), + .FSL_S_CONTROL (FSL_S_CONTROL), + .FSL_S_EXISTS (FSL_S_EXISTS), + .FSL_S_READ (FSL_S_READ), + .FSL_M_CLK (FSL_M_CLK), + .FSL_M_DATA (FSL_M_DATA[24:31]), + .FSL_M_CONTROL (FSL_M_CONTROL), + .FSL_M_FULL (FSL_M_FULL), + .FSL_M_WRITE (FSL_M_WRITE), + .rs232_tx_ready (ser2fsl_cts), + .rs232_tx_data (fsl2ser_data), + .rs232_tx_start (fsl2ser_start), + .rs232_rx_ready (fsl2ser_cts), + .rs232_rx_data (ser2fsl_data), + .rs232_rx_exists (ser2fsl_dataexists), + .clock (clock), + .reset (reset_correct_polarity) +); + +serial_ctrl #( + .CLOCK_FREQ_MHZ(CLOCK_FREQ_MHZ), + .BAUD_RATE(BAUD_RATE) + ) serial_ctrl0 ( + .fsl_data_i (fsl2ser_data), + .fsl_senddata_i (fsl2ser_start), + .fsl_cts_o (ser2fsl_cts), + .fsl_data_o (ser2fsl_data), + .fsl_rxdata_o (ser2fsl_dataexists), + .fsl_cts_i (fsl2ser_cts), + .rs232_tx_data_o (rs232_tx_data_o), + .rs232_rx_data_i (rs232_rx_data_i), + .rs232_rts_i (rs232_rts_i), + .rs232_cts_o (rs232_cts_o), + .clock (clock), + .reset (reset_correct_polarity) +); + +/* + //----------------------------------------------------------------- + // + // ICON/ILA core wire declarations + // + //----------------------------------------------------------------- + wire [35:0] control0; + wire [31:0] trig0; + + assign trig0 = {FSL_S_DATA[24:31],FSL_S_READ,FSL_S_EXISTS, + fsl2ser_data,fsl2ser_start,ser2fsl_cts, + rs232_tx_data_o, rs232_cts_o, reset_correct_polarity, 9'b0}; + + //----------------------------------------------------------------- + // + // ICON core instance + // + //----------------------------------------------------------------- + icon i_icon + ( + .control0(control0) + ); + + //----------------------------------------------------------------- + // + // ILA core instance + // + //----------------------------------------------------------------- + ila i_ila + ( + .control(control0), + .clk(clock), + .trig0(trig0) + ); + +endmodule + + +//------------------------------------------------------------------- +// +// ICON core module declaration +// +//------------------------------------------------------------------- +module icon + ( + control0 + ); + output [35:0] control0; +endmodule + +//------------------------------------------------------------------- +// +// ILA core module declaration +// +//------------------------------------------------------------------- +module ila + ( + control, + clk, + trig0 + ); + input [35:0] control; + input clk; + input [31:0] trig0;*/ +endmodule + +/////////////////////////////////////////////////////////////////////////////// + +// TBD: +// [x] test the FSL 2 Serial direction +// [ ] test the Serial 2 FSL direction + +module fsl2serial_tb ( ); + +reg clock, reset_n; +wire rs232_tx_data_o; +reg rs232_rx_data_i; +reg rs232_rts_i; +wire rs232_cts_o; + +reg [0:31] FSL_S_DATA; +reg FSL_S_CONTROL; +wire [0:31] FSL_M_DATA; +wire FSL_M_CONTROL; +wire FSL_S_CLK, FSL_M_CLK; +wire FSL_M_WRITE, FSL_S_READ; +reg FSL_M_FULL, FSL_S_EXISTS; + +initial begin + clock <= 1'b0; + reset_n <= 1'b0; + rs232_rx_data_i <= 1'b1; + rs232_rts_i <= 1'b0; + FSL_S_DATA <= 32'h00000000; + FSL_S_CONTROL <= 1'b0; + FSL_M_FULL <= 1'b0; + FSL_S_EXISTS <= 1'b0; + + #1000 reset_n <= 1'b1; + + #1000 FSL_S_DATA <= 8'hA0; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #1000 FSL_S_DATA <= FSL_S_DATA + 1; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #1000 FSL_S_DATA <= FSL_S_DATA + 1; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #2070750 rs232_rx_data_i <= 1'b0; // start bit + #207075 rs232_rx_data_i <= 1'b1; + #207075 rs232_rx_data_i <= 1'b1; + #207075 rs232_rx_data_i <= 1'b0; + #207075 rs232_rx_data_i <= 1'b1; + #207075 rs232_rx_data_i <= 1'b0; + #207075 rs232_rx_data_i <= 1'b1; + #207075 rs232_rx_data_i <= 1'b0; + #207075 rs232_rx_data_i <= 1'b1; + #207075 rs232_rx_data_i <= 1'b1; // stop bit + + + +end + +always begin + #10 clock <= ~clock; // 50MHz +end + +fsl2serial bridge( + .clock (clock), + .reset (reset_n), + .rs232_tx_data_o (rs232_tx_data_o), + .rs232_rx_data_i (rs232_rx_data_i), + .rs232_rts_i (rs232_rts_i), + .rs232_cts_o (rs232_cts_o), + .FSL_S_CLK (FSL_S_CLK), + .FSL_S_DATA (FSL_S_DATA), + .FSL_S_CONTROL (FSL_S_CONTROL), + .FSL_S_EXISTS (FSL_S_EXISTS), + .FSL_S_READ (FSL_S_READ), + .FSL_M_CLK (FSL_M_CLK), + .FSL_M_DATA (FSL_M_DATA), + .FSL_M_CONTROL (FSL_M_CONTROL), + .FSL_M_FULL (FSL_M_FULL), + .FSL_M_WRITE (FSL_M_WRITE) +); + +endmodule + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_out.v =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_out.v (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/serial_out.v (revision 4) @@ -0,0 +1,162 @@ +// Todd Fleming 2005 + +`timescale 1 ns / 100 ps + +module serial_out( + clk, + rst, + data_size_i, + data_i, + start_i, + serial_o, + ready_o, + bit_sync_o); + + parameter clk_freq = 100000000; + parameter data_rate = 115200; + parameter bit_length = clk_freq / data_rate; + parameter delay_size = 32; // Must be large enough to store bit_length + parameter max_data_size = 8; + parameter data_size_size = 4; // Must be large enough to store max_data_size + parameter use_start = 1; + parameter use_stop = 1; + parameter use_parity = 0; + parameter stop_value = 1; + parameter parity_is_odd = 1; + + input clk, rst; + input[data_size_size-1:0] data_size_i; + input[max_data_size-1:0] data_i; + input start_i; + output serial_o; + output ready_o; + output bit_sync_o; + + reg[2:0] state; + reg[data_size_size-1:0] data_size; + reg[max_data_size-1:0] data; + reg[delay_size-1:0] delay; + reg[max_data_size-1:0] num_sent; + reg serial_o; + reg bit_sync_o; + + parameter state_wait_for_start = 3'd0; + parameter state_send_start = 3'd1; + parameter state_send_bit = 3'd2; + parameter state_send_parity = 3'd3; + parameter state_send_stop = 3'd4; + + assign ready_o = + (state == state_wait_for_start || state == state_send_stop && delay == 1) && !start_i; + + always @(posedge clk) begin + bit_sync_o <= 0; + + if(rst) begin + state <= state_wait_for_start; + end else begin + delay <= delay - 1; + + case(state) + state_wait_for_start: begin + serial_o <= stop_value; + if(start_i) begin + data_size <= data_size_i; + data <= data_i; + num_sent <= 0; + if(use_start) begin + serial_o <= ~stop_value; + delay <= bit_length - 1; + state <= state_send_start; + end else begin + serial_o <= data_i[0]; + delay <= bit_length - 1; + state <= state_send_bit; + end + end + end + state_send_start: begin + serial_o <= ~stop_value; + if(delay == 1) begin + delay <= bit_length; + state <= state_send_bit; + end + end + state_send_bit: begin + serial_o <= data[0]; + if(delay == bit_length - 2) + bit_sync_o <= 1; + if(delay == 1) begin + delay <= bit_length; + data <= data >> 1; + num_sent <= num_sent + 1; + if(num_sent == data_size - 1) + if(use_parity) + state <= state_send_parity; + else if(use_stop) + state <= state_send_stop; + else + state <= state_wait_for_start; + end + end + state_send_parity: begin + serial_o <= (^data[0]) ^ parity_is_odd; + if(delay == 1) begin + delay <= bit_length; + state <= state_send_stop; + end + end + state_send_stop: begin + serial_o <= stop_value; + if(delay == 1) begin + delay <= bit_length; + state <= state_wait_for_start; + end + end + endcase + end + end +endmodule // serial_out + +/////////////////////////////////////////////////////////////////////////////// + +module serial_out_tb ( ); + +reg clock, reset; +reg [7:0] fsl_data_i; +reg fsl_senddata_i; +wire rs232_tx_data_o; +wire rs232_tx_ready; + +initial begin + clock <= 1'b0; + reset <= 1'b1; + fsl_data_i <= 8'h00; + fsl_senddata_i <= 1'b0; + + #1000 reset <= 1'b0; + #1000 fsl_data_i <= 8'h0A; + fsl_senddata_i <= 1'b1; + #60 fsl_senddata_i <= 1'b0; +end + +always begin + #10 clock <= ~clock; +end + +// Serial Out Module + serial_out + #( + .clk_freq(50000000), + .data_rate(115200)) + serial_out0( + .clk(clock), + .rst(reset), + .data_size_i(8), + .data_i(fsl_data_i), // data to send out serially + .start_i(fsl_senddata_i), // start sending trigger + .serial_o(rs232_tx_data_o), // serial output line + .ready_o(rs232_tx_ready) // serial out !busy + ); + +endmodule Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/hdl/verilog/fsl_ctrl.v (revision 4) @@ -0,0 +1,149 @@ +// This module sends the correct control signals to the slave FSL port in +// order to get the data out. +// +// Alex Marschner +// 2007.02.20 + +`timescale 1 ns / 100 ps + +module fsl_ctrl ( + FSL_S_CLK, FSL_S_DATA, FSL_S_CONTROL, FSL_S_EXISTS, FSL_S_READ, + FSL_M_CLK, FSL_M_DATA, FSL_M_CONTROL, FSL_M_FULL, FSL_M_WRITE, + rs232_tx_ready, rs232_tx_data, rs232_tx_start, + rs232_rx_ready, rs232_rx_data, rs232_rx_exists, + clock, reset +); + +output wire FSL_S_CLK; +input wire [0:7] FSL_S_DATA; +input wire FSL_S_CONTROL; +input wire FSL_S_EXISTS; +output reg FSL_S_READ; + +output wire FSL_M_CLK; +output reg [0:7] FSL_M_DATA; +output reg FSL_M_CONTROL; +input wire FSL_M_FULL; +output reg FSL_M_WRITE; + +output reg rs232_rx_ready; +input wire [7:0] rs232_rx_data; +input wire rs232_rx_exists; + +input wire rs232_tx_ready; +output wire [7:0] rs232_tx_data; +output wire rs232_tx_start; + +input wire clock, reset; + +assign FSL_S_CLK = clock; +//assign FSL_M_CLK = clock; + +assign rs232_tx_data = FSL_S_DATA; +assign rs232_tx_start = FSL_S_READ; + +always @ (posedge clock) begin + if(reset) begin + FSL_S_READ <= 1'b0; + FSL_M_DATA <= 8'h00; + FSL_M_CONTROL <= 1'b0; + FSL_M_WRITE <= 1'b0; + rs232_rx_ready <= 1'b0; + end + else begin + FSL_S_READ <= (FSL_S_EXISTS & (~FSL_S_READ) & rs232_tx_ready) ? 1'b1 : 1'b0; + FSL_M_DATA <= rs232_rx_data; + FSL_M_CONTROL <= 1'b0; + FSL_M_WRITE <= (!FSL_M_FULL & (~FSL_M_WRITE) & rs232_rx_exists) ? 1'b1 : 1'b0; + rs232_rx_ready <= 1'b1; // always ready to get data from outside + end +end + +endmodule + +/////////////////////////////////////////////////////////////////////////////// + +module fsl_ctrl_tb ( ); + +reg clock, reset; +wire FSL_S_CLK, FSL_S_READ; +reg [0:7] FSL_S_DATA; +reg FSL_S_CONTROL; +reg FSL_S_EXISTS; +reg rs232_tx_ready; +wire [7:0] rs232_tx_data; +wire rs232_tx_start; +reg [7:0] registered_out; + + +fsl_ctrl fsl_ctrl_0( + .FSL_S_CLK (FSL_S_CLK), + .FSL_S_DATA (FSL_S_DATA), + .FSL_S_CONTROL (FSL_S_CONTROL), + .FSL_S_EXISTS (FSL_S_EXISTS), + .FSL_S_READ (FSL_S_READ), + .rs232_tx_ready (rs232_tx_ready), + .rs232_tx_data (rs232_tx_data), + .rs232_tx_start (rs232_tx_start), + .clock (clock), + .reset (reset) +); + +initial begin + clock <= 1'b0; + reset <= 1'b1; + FSL_S_DATA <= 8'h00; + FSL_S_CONTROL <= 1'b0; + FSL_S_EXISTS <= 1'b0; + rs232_tx_ready <= 1'b0; + + #1000 reset <= 1'b0; + #20 rs232_tx_ready <= 1'b1; + + #1000 FSL_S_DATA <= 8'hA0; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #1000 FSL_S_DATA <= FSL_S_DATA + 1; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #1000 FSL_S_DATA <= FSL_S_DATA + 1; + FSL_S_EXISTS <= 1'b1; + while(~&FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + while( &FSL_S_READ) #1 FSL_S_EXISTS <= 1'b1; + FSL_S_EXISTS <= 1'b0; + + #1000 while(1) FSL_S_EXISTS <= 1'b0; +end + +always @ (posedge clock) begin + if(reset) registered_out <= 8'b0; + else registered_out <= rs232_tx_start ? rs232_tx_data : registered_out; +end + +always @ (posedge clock) begin + if(reset) rs232_tx_ready <= 1'b0; + else begin + if(rs232_tx_start) begin + rs232_tx_ready <= 1'b0; + #4000 rs232_tx_ready <= 1'b1; + end + end +end + +always @ (posedge clock) begin + FSL_S_EXISTS <= (FSL_S_EXISTS && FSL_S_READ) ? 1'b0 : FSL_S_EXISTS; + FSL_S_DATA <= (FSL_S_EXISTS && FSL_S_READ) ? (FSL_S_DATA+1) : FSL_S_DATA; +end + +always begin + #20 clock <= ~clock; +end + +endmodule + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.ucf =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.ucf (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.ucf (revision 4) @@ -0,0 +1,7 @@ +#### Module FSL2Serial Constraints #### + +NET "rs232_tx_data_o_pin" LOC = "AE7" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW; +NET "rs232_rx_data_i_pin" LOC = "AJ8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW; +NET "rs232_rts_i_pin" LOC = "AK8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW; +NET "rs232_cts_o_pin" LOC = "AE8" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = SLOW; + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/README.txt =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/README.txt (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/README.txt (revision 4) @@ -0,0 +1,48 @@ +In order to use the FSL2Serial module in XPS, follow these steps: + +1) Place the entire containing folder, fsl2serial_v1_00_a, into your pcores directory. +2) Start XPS (or restart - this may be necessary). + +3) Click on the "IP Catalog" tab, expand "Project Repository", and insert the FSL2Serial module. +4) Right click on the module name in the "System Assembly View", and select "Configure IP." + - make sure you indicate the correct system reset polarity (usually board reset polarity) + - set your clock speed in MHz (eg, 100). The range is 0-200. + - set your baud rate. Default is 115200, normal people use 9600 +5) Insert the following information into the following places: + - pcores/fsl2serial_v1_00_a/docs/fsl2serial.ucf --> data/system.ucf + - pcores/fsl2serial_v1_00_a/docs/fsl2serial.mhs --> system.mhs + + Note: if XPS is open and you make this change using some other editor, + XPS will override your changes!! + +6) In the "Ports" view, expand fsl2serial and connect the clock, rst, and rs232 pins. + + +Adding the FSL busses: + +1) In the "IP Catalog" tab, expand "Bus", and add TWO instances of the fsl_v20 bus. +2) For each of these instances, + + - right click, select "Configure IP" + - uncheck the box that says "External Reset Active High" (if appropriate) + - click "Ok" + + - in the "Ports" view, expand the bus + - connect the FSL_Clk and FSL_Rst to the system clock and reset + +3) Back in the "Bus Interface" view: + - attach the Master port of your processor and the Slave port of FSL2serial to one FSL bus. + - attach the Slave port of your processor and the Master port of FSL2serial to the other. + + +You should now be ready to write programs that use the FSL2Serial link as serial output. +Sample code is available in the fsl2serial_v1_00_a/code/ directory. + + +2007.03.12 +Alex Marschner + + + + + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.mhs =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.mhs (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/docs/fsl2serial.mhs (revision 4) @@ -0,0 +1,4 @@ + PORT rs232_tx_data_o_pin = rs232_tx_data_o, DIR = O + PORT rs232_rx_data_i_pin = rs232_rx_data_i, DIR = I + PORT rs232_rts_i_pin = rs232_rts_i, DIR = I + PORT rs232_cts_o_pin = rs232_cts_o, DIR = O Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao (revision 4) @@ -0,0 +1,11 @@ +############################################################################## +## Filename: /home/amarschn/projects/OpenFire_OPB/openfire_2/pcores/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Thu Feb 22 14:37:13 2007 (by Create and Import Peripheral Wizard) +############################################################################## + +lib fsl2serial_v1_00_a fsl2serial verilog +lib fsl2serial_v1_00_a fsl_ctrl verilog +lib fsl2serial_v1_00_a serial_ctrl verilog +lib fsl2serial_v1_00_a serial_in verilog +lib fsl2serial_v1_00_a serial_out verilog Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/data/fsl2serial_v2_1_0.mpd (revision 4) @@ -0,0 +1,47 @@ +################################################################### +## +## Name : fsl2serial +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN fsl2serial + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VERILOG +OPTION CORE_STATE = ACTIVE +OPTION IP_GROUP = MICROBLAZE:PPC:USER + +## Parameters / Generics +PARAMETER EXT_RESET_ACTIVE_HI = 0, DT = INTEGER, RANGE = (0:1), DESC = Reset signal is active high: +PARAMETER CLOCK_FREQ_MHZ = 50, DT = INTEGER, RANGE = (0:200), DESC = Processor speed in MHz: +PARAMETER BAUD_RATE = 115200, DT = INTEGER, VALUES = (2400=2400, 9600=9600, 115200=115200), DESC = Serial communication speed: + +## Bus Interfaces +BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL +BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL + +## Generics for VHDL or Parameters for Verilog + +## Ports +PORT clock = "", DIR = I, SIGIS = CLK +PORT reset = "", DIR = I, SIGIS = RST +PORT rs232_tx_data_o = "", DIR = O +PORT rs232_rx_data_i = "", DIR = I +PORT rs232_rts_i = "", DIR = I +PORT rs232_cts_o = "", DIR = O +PORT FSL_S_DATA = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL +PORT FSL_S_CONTROL = FSL_S_Control, DIR = I, BUS = SFSL +PORT FSL_S_EXISTS = FSL_S_Exists, DIR = I, BUS = SFSL +PORT FSL_M_FULL = FSL_M_Full, DIR = I, BUS = MFSL +PORT FSL_M_DATA = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL +PORT FSL_M_CONTROL = FSL_M_Control, DIR = O, BUS = MFSL +PORT FSL_M_WRITE = FSL_M_Write, DIR = O, BUS = MFSL +PORT FSL_S_READ = FSL_S_Read, DIR = O, BUS = SFSL +PORT FSL_M_CLK = FSL_M_Clk, DIR = O, BUS = MFSL +PORT FSL_S_CLK = FSL_S_Clk, DIR = O, BUS = SFSL + +END Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.c =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.c (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.c (revision 4) @@ -0,0 +1,97 @@ +// This is the source file implementing the FSL interface developed for use with the FSL2Serial +// module. Data can also be sent over this link, but the assumption is that text will be sent. +// +// This requires the Xilinx FSL interface code, which can generally be found in fsl.h, +// mb_interface.h, and xbasic_types.h +// +// Alex Marschner +// 2007.03.12 + +#include "fsl_interface.h" + +// Put a string of data through the specified FSL port. +void fsl0print(const char* s) +{ + while(*s) + { + putfsl(*s, FSL0); + ++s; + } + return; +} + +// Put a string of data through the specified FSL port. +void fsl0nprint(const char* s) +{ + while(*s) + { + nputfsl(*s, FSL0); + ++s; + } + return; +} + +// Print a single character to the specified FSL port. (BLOCKING) +void fsl0put(const char s) +{ + putfsl(s, FSL0); + return; +} + +// Print a single character to the specified FSL port. (NONBLOCKING) +void fsl0nput(const char s) +{ + nputfsl(s, FSL0); + return; +} + +// Get a single character from the specified FSL port. (BLOCKING) +char fsl0get(char * s) +{ + char inchar; + + getfsl(inchar, FSL0); + if(s!=NULL) (*s) = inchar; + + return inchar; +} + +// Get a single character from the specified FSL port. (NONBLOCKING) +char fsl0nget(char * s) +{ + char inchar; + + ngetfsl(inchar, FSL0); + if(s!=NULL) (*s) = inchar; + + return inchar; +} + +// Print the hexadecimal representation of a 32-bit integer to the specified FSL port. +void fsl0hex(const unsigned int val) +{ + char hexstring[10]; + unsigned int shiftval = val; + char maskval; + int ctr; + + for(ctr=9; ctr>1; ctr--) + { + maskval = shiftval & 0x0000000F; + + if(maskval < 10) + hexstring[ctr] = maskval + 0x30; + else + hexstring[ctr] = maskval + (0x41-0xA); + + shiftval = shiftval >> 4; + } + + hexstring[0] = '0'; + hexstring[1] = 'x'; + + fsl0print(hexstring); + + return; +} + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.h =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.h (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/fsl_interface.h (revision 4) @@ -0,0 +1,47 @@ +// This is a header file describing the FSL interface developed for use with the FSL2Serial +// module. Data can also be sent over this link, but the assumption is that text will be sent. +// +// This requires the Xilinx FSL interface code, which can generally be found in fsl.h, +// mb_interface.h, and xbasic_types.h +// +// These functions cannot take the FSL ID as a parameter because the fsl functions used are +// actually macros for asm inline commands. +// +// Alex Marschner +// 2007.03.12 + +#ifndef FSL_INTERFACE_H +#define FSL_INTERFACE_H + +#include "fsl.h" // getfsl(val, id), putfsl(val, id), (blocking) + // ngetfsl(val, id), nputfsl(val,id) (non blocking) + +#define BOOL int +#define TRUE 1 +#define FALSE 0 + +#define FSL_BLOCKING 1 +#define FSL_NONBLOCKING 0 + +#define FSL0 0 + +// Put a string of data through the specified FSL port. +void fsl0print(const char* s); +void fsl0nprint(const char* s); + +// Print a single character to the specified FSL port. +void fsl0put(const char s); +void fsl0nput(const char s); + +// Get a single character from the specified FSL port. +char fsl0get(char * s); +char fsl0nget(char * s); + +// Print the hexadecimal representation of a 32-bit integer to the specified FSL port. +void fsl0hex(const unsigned int val); + +// Print the decimal representation of a 32-bit unsigned int to the specified FSL port. +//void fsldec(const unsigned int val, const unsigned int id); + +#endif + Index: fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/makefile =================================================================== --- fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/makefile (nonexistent) +++ fsl2serial/tags/fsl2serial_v1_00_a/fsl2serial_v1_00_a/code/makefile (revision 4) @@ -0,0 +1,10 @@ +HDRDIR_1=-I/project/software/Xilinx/EDK8.2/sw/XilinxProcessorIPLib/drivers/common_v1_00_a/src/ +HDRDIR_2=-I/project/software/Xilinx/EDK8.2/sw/lib/bsp/standalone_v1_00_a/src/microblaze/ + +all: + mb-gcc -Wall -o ../executable.elf fsl_interface.c openfire_src.c $(HDRDIR_1) $(HDRDIR_2) + +clean: + rm -rf *~ + rm -rf *.o + rm -rf ../executable.elf Index: fsl2serial/tags =================================================================== --- fsl2serial/tags (nonexistent) +++ fsl2serial/tags (revision 4)
fsl2serial/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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