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https://opencores.org/ocsvn/spislave/spislave/trunk
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/spislave/trunk/spislave/rtl/verilog/spigpio.v
0,0 → 1,47
// RTL program for SPI GPIO -- shift 8 bit register |
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`define P0_P9_OP 8'b10101010 //0xAA |
`define P0_P3_OP 8'b11111111 //0xFF |
`define P4_P7_OP 8'b11111110 //0xFE |
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module spigpio(clk, cs, sr_in, gpioout, sr_out); |
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input clk, cs; |
input sr_in; |
output sr_out; |
output [7:0] gpioout; |
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reg [7:0] gpioout; |
reg sr_out; |
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wire rw; |
reg [7:0] sr; |
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assign rw = sr[7]; |
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always@(posedge clk ) |
begin |
if (cs == 1'b0) |
begin |
sr_out <= sr[7]; |
sr[7:1] <= sr[6:0]; |
sr[0] <= sr_in; |
end |
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if (cs == 1'b1) |
begin |
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if (rw == 1'b1) |
begin |
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case (sr) |
`P0_P9_OP : gpioout[7:0] <= { sr[0], sr[1], sr[2], sr[3], |
sr[4], sr[5], sr[6], sr[7]}; |
`P0_P3_OP : gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]}; |
`P4_P7_OP : gpioout[7:4] <= { sr[4], sr[5], sr[6], sr[7]}; |
default : gpioout[0] <= sr[0]; |
endcase |
end |
end |
end |
endmodule |