Jamil Khatib

TDM controller core

+ +

+ +

Contents

+

+1  List of authors and changes

+ +

+

+2  Project Definition

+

+2.1  Introduction

+

+2.2  Objectives

+

+3  Specifications

+

+3.1  System Features Specification

+ +
1. Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps) + +
2. Supports ST-Bus (Serial Telecom bus) interface. + +
3. Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory. + +
4. Supports read for all or partial TDM slots from the ST-bus. + +
5. Supports write for all or partial TDM slots to ST-bus. + +
6. It supports N×64 mode (i.e. it supports sampling (or writing) to N consecutive time slots) + +
7. Supports two serial lines one input and one output. + +
8. Can be connected to other ST-Bus compatible devices via serial or star configurations. + +
9. If no data is available for transmission it sends all ones. + +
10. Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer. + +
11. Optional External FIFO buffer, configuration and status registers. + +
12. The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel. + +
13. ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots. +

+

+3.2  External Interfaces

+ +

+

+3.2.1  Back-end interface mapping to Wishbone SoC bus

+ +

+ Figure +

+

+ +

+

+3.2.2  CPU interface

+ +

+

+4  Internal Blocks

+

+5  Design description

+

+5.1  ST-Bus interface

+

+5.1.1  Design notes

+

+5.1.2  Timing

+

+5.2  External FIFO

+The current implementation supports the following configuration: +The size of the Transmit and receive FIFOs is (8×32) bits which enables the whole TDM frame to be buffered. + +

+The transmit buffer is used to prevent underflow while transmitting bytes to the line. All bytes will be available once the transmit is enabled. If the transmit FIFO is empty the core will transmit ones. The Receive buffer is used to provide data burst transfer to the Back end interface which prevents the back end from reading each byte alone. The FIFO size is suitable for operating frequencies 2.048MHz on the serial interface and 20 MHz on the back end interface. Other frequencies can operate if the back end can read the entire TDM frame before the first byte of the next frame is written (the next calculations is an example to be applied for different frequencies) + +

+8 bits (Time needed to receive the first byte of the next frame) / 2.048MHz = 3.9 us + +

+32 Bytes (Maximum frame size) / 20MHz = 1.6 us + +

+These FIFOs are implemented on Single port memory. It is the responsibility of the external interface to write/read data to/from the FIFOs. TxDone and RxRdy interrupts are generated when the Tx buffer is empty and Rx buffer has data respectively . + +

+

+5.2.1  Notes

+ +

+ +

• Transmit Operation: If the transmit FIFO is empty not enough data bytes is available according to no. of channels (caused by incomplete burst transfer, the core sets the Aborted bit in the TX status and control register and sends all ones in the transmit serial line. + +

  + +

• Transmit Operation: The back end (software) should write data to the Tx buffer register according to the configured number of time slots. The transmission will start only after the specified number of slots are available in the buffer other wise Aborted bit of the Tx Status register will be set and all ones will be transmitted in this slot. + +

  + +

• Receive Operation: When Receive FIFO is full It drops the second FIFO contents and sets overflow bit in the Rx Status and Control register. + +

  + +

• Receive Operation: When RxRdy Interrupt is asserted (or RxRdy bit is set) the back end interface (software) must read the specified number of slots from the Rx Data buffer register or the buffer will not be marked as empty. +

+

+5.3  ISDN support

+Eventhoush the ISDN controller is based on TDM but separate controller will be used that extracts and writes 2B+D only. + +

+ +

+ Figure

+

+

+5.4  Registers

+

+5.4.1  Transmit

+ +

+ +

+ +

+ +

+

+5.4.2  Receive

+ +

+ +

+RxLineOverflow: Overflow on serial Line buffer. + +

+ +

+ +

+ +

+ +

+Example number of channels to be read is 2 starting after 3 channels from the framing pulse: NoChannels = 0x04 and DropChannels = 0x03
+ +

+ISDN registers The ISDN controller is a separate core that has three HDLC controllers. Each HDLC controller has its own Wishbone interface and registers for information about the HDLC registers refer to the HDLC core document. + +

+

+5.5  Diagrams

+ +

+ Figure

+

+ +

+ Figure

+

+

+6  Testing and verifications

+ +

+6.1  Simulation and Test benches

+

+6.2  Verification techniques and algorithms

+

+6.3  Test plans

+

+7  Implementations

+The design is implemented using the VHDL language. The design is divided into three blocks, serial interface, Buffers and Wishbone interface with internal registers. The TDM controller uses the wishbone clock as its main clock and uses the ST-bus clock as enables for the internal logic. + +

+

+7.1  Scripts, files and any other information

+

+8  Reviews and comments

+

+9  References

Index: trunk/code/ISDN_cont/core/ISDN_cont_top.vhd =================================================================== --- trunk/code/ISDN_cont/core/ISDN_cont_top.vhd (nonexistent) +++ trunk/code/ISDN_cont/core/ISDN_cont_top.vhd (revision 4) @@ -0,0 +1,217 @@ +------------------------------------------------------------------------------- +-- Title : ISDN tdm controller +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : ISDN_cont_top.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/06 +-- Last update:2001/05/06 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164 +-- tdm.components_pkg +-- hdlc.hdlc_components_pkg +------------------------------------------------------------------------------- +-- Description: ISDN tdm controller that extracts 2B+D channels from 3 time +-- slots of the incoming streem (Top Block) +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/06 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2001/05/08 21:10:41 jamil +-- Initial release +-- +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY hdlc; +USE hdlc.hdlc_components_pkg.ALL; + +LIBRARY tdm; +USE tdm.components_pkg.ALL; + +ENTITY isdn_cont_top_ent IS + + PORT ( + C2 : IN STD_LOGIC; -- ST-Bus clock + DSTi : IN STD_LOGIC; -- ST-Bus input Data + DSTo : OUT STD_LOGIC; -- ST-Bus output Data + F0_n : IN STD_LOGIC; -- St-Bus Framing pulse + F0od_n : OUT STD_LOGIC; -- ST-Bus Delayed Framing pulse + RST_I : IN STD_LOGIC; + CLK_I : IN STD_LOGIC; + +-- B1 Channel + ADR_I_B1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + DAT_O_B1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + DAT_I_B1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + WE_I_B1 : IN STD_LOGIC; + STB_I_B1 : IN STD_LOGIC; + ACK_O_B1 : OUT STD_LOGIC; + CYC_I_B1 : IN STD_LOGIC; + RTY_O_B1 : OUT STD_LOGIC; + TAG0_O_B1 : OUT STD_LOGIC; + TAG1_O_B1 : OUT STD_LOGIC; + +-- B2 Channel + ADR_I_B2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + DAT_O_B2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + DAT_I_B2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + WE_I_B2 : IN STD_LOGIC; + STB_I_B2 : IN STD_LOGIC; + ACK_O_B2 : OUT STD_LOGIC; + CYC_I_B2 : IN STD_LOGIC; + RTY_O_B2 : OUT STD_LOGIC; + TAG0_O_B2 : OUT STD_LOGIC; + TAG1_O_B2 : OUT STD_LOGIC; + +-- D Channel + ADR_I_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + DAT_O_D : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + DAT_I_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + WE_I_D : IN STD_LOGIC; + STB_I_D : IN STD_LOGIC; + ACK_O_D : OUT STD_LOGIC; + CYC_I_D : IN STD_LOGIC; + RTY_O_D : OUT STD_LOGIC; + TAG0_O_D : OUT STD_LOGIC; + TAG1_O_D : OUT STD_LOGIC + + ); + +END isdn_cont_top_ent; + +------------------------------------------------------------------------------- + +ARCHITECTURE isdn_cont_top_str OF isdn_cont_top_ent IS + + SIGNAL HDLCen1 : STD_LOGIC; + SIGNAL HDLCen2 : STD_LOGIC; + SIGNAL HDLCen3 : STD_LOGIC; + SIGNAL HDLCTxen1 : STD_LOGIC; + SIGNAL HDLCTxen2 : STD_LOGIC; + SIGNAL HDLCTxen3 : STD_LOGIC; + SIGNAL Dout : STD_LOGIC; + SIGNAL Din1 : STD_LOGIC; + SIGNAL Din2 : STD_LOGIC; + SIGNAL Din3 : STD_LOGIC; + +BEGIN -- isdn_cont_top_str +------------------------------------------------------------------------------- + + + ST_IF : isdn_cont_ent + PORT MAP ( + rst_n => RST_I, + C2 => C2, + DSTi => DSTi, + DSTo => DSTo, + F0_n => F0_n, + F0od_n => F0od_n, + HDLCen1 => HDLCen1, + HDLCen2 => HDLCen2, + HDLCen3 => HDLCen3, + HDLCTxen1 => HDLCTxen1, + HDLCTxen2 => HDLCTxen2, + HDLCTxen3 => HDLCTxen3, + Dout => Dout, + Din1 => Din1, + Din2 => Din2, + Din3 => Din3); + + B1_Channel : hdlc_ent + GENERIC MAP ( + FCS_TYPE => 2, + ADD_WIDTH => 7) + PORT MAP ( + Txclk => C2, + RxClk => C2, + Tx => Din1, + Rx => Dout, + TxEN => HDLCTxen1, + RxEn => HDLCen1, + RST_I => RST_I, + CLK_I => CLK_I, + ADR_I => ADR_I_B1, + DAT_O => DAT_O_B1, + DAT_I => DAT_I_B1, + WE_I => WE_I_B1, + STB_I => STB_I_B1, + ACK_O => ACK_O_B1, + CYC_I => CYC_I_B1, + RTY_O => RTY_O_B1, + TAG0_O => TAG0_O_B1, + TAG1_O => TAG1_O_B1); + + + B2_Channel : hdlc_ent + GENERIC MAP ( + FCS_TYPE => 2, + ADD_WIDTH => 7) + PORT MAP ( + Txclk => c2, + RxClk => c2, + Tx => Din2, + Rx => Dout, + TxEN => HDLCTxen2, + RxEn => HDLCen2, + RST_I => RST_I, + CLK_I => CLK_I, + ADR_I => ADR_I_B2, + DAT_O => DAT_O_B2, + DAT_I => DAT_I_B2, + WE_I => WE_I_B2, + STB_I => STB_I_B2, + ACK_O => ACK_O_B2, + CYC_I => CYC_I_B2, + RTY_O => RTY_O_B2, + TAG0_O => TAG0_O_B2, + TAG1_O => TAG1_O_B2); + + + D_Channel : hdlc_ent + GENERIC MAP ( + FCS_TYPE => 2, + ADD_WIDTH => 7) + PORT MAP ( + Txclk => c2, + RxClk => c2, + Tx => Din3, + Rx => Dout, + TxEN => HDLCTxen3, + RxEn => HDLCen3, + RST_I => RST_I, + CLK_I => CLK_I, + ADR_I => ADR_I_D, + DAT_O => DAT_O_D, + DAT_I => DAT_I_D, + WE_I => WE_I_D, + STB_I => STB_I_D, + ACK_O => ACK_O_D, + CYC_I => CYC_I_D, + RTY_O => RTY_O_D, + TAG0_O => TAG0_O_D, + TAG1_O => TAG1_O_D); + +------------------------------------------------------------------------------- +END isdn_cont_top_str; Index: trunk/code/tdm_cont/tb/tdm_cont_tb.vhd =================================================================== --- trunk/code/tdm_cont/tb/tdm_cont_tb.vhd (nonexistent) +++ trunk/code/tdm_cont/tb/tdm_cont_tb.vhd (revision 4) @@ -0,0 +1,310 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller test bench +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : tdm_cont_tb.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/09 +-- Last update:2001/05/18 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164, ieee.std_logic_unsigned +-- tdm.components_pkg +------------------------------------------------------------------------------- +-- Description: tdm controller test bench +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/09 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2001/05/18 16:56:16 jamil +-- Serial Data added +-- +-- Revision 1.1 2001/05/13 21:13:54 jamil +-- Initial Release +-- +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +LIBRARY TDM; +USE TDM.components_pkg.ALL; + +------------------------------------------------------------------------------- + +ENTITY tdm_cont_tb IS + +END tdm_cont_tb; + +------------------------------------------------------------------------------- + +ARCHITECTURE tdm_cont_beh OF tdm_cont_tb IS + + + SIGNAL rst_n : STD_LOGIC := '0'; + SIGNAL C2 : STD_LOGIC := '0'; + SIGNAL DSTi : STD_LOGIC; + SIGNAL DSTo : STD_LOGIC; + SIGNAL F0_n : STD_LOGIC; + SIGNAL F0od_n : STD_LOGIC; + SIGNAL CLK_I : STD_LOGIC := '0'; + SIGNAL RST_I : STD_LOGIC; + SIGNAL NoChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL DropChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL RxD : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL RxValidData : STD_LOGIC; + SIGNAL FramErr : STD_LOGIC; + SIGNAL RxRead : STD_LOGIC; + SIGNAL RxRdy : STD_LOGIC; + SIGNAL TxErr : STD_LOGIC; + SIGNAL TxD : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL TxValidData : STD_LOGIC; + SIGNAL TxWrite : STD_LOGIC; + SIGNAL TxRdy : STD_LOGIC; + + SIGNAL EnableSerialIF : STD_LOGIC := '0'; -- Enable Serial Interface + + SIGNAL Tx_en0 : STD_LOGIC; -- Tx enable channel 0 + SIGNAL Tx_en1 : STD_LOGIC; -- Tx enable channel 1 + SIGNAL Tx_en2 : STD_LOGIC; -- Tx enable channel 2 + + SIGNAL Rx_en0 : STD_LOGIC; -- Rx enable channel 0 + SIGNAL Rx_en1 : STD_LOGIC; -- Rx enable channel 1 + SIGNAL Rx_en2 : STD_LOGIC; -- Rx enable channel 2 + + SIGNAL SerDo : STD_LOGIC; -- serial Data out + SIGNAL SerDi : STD_LOGIC := '0'; -- Serial Data in + + + TYPE SERIAL_typ IS ARRAY (0 TO 1023) OF STD_LOGIC; -- Serial Data array + + SIGNAL RxData : SERIAL_typ; -- Rx Serial Data +BEGIN -- tdm_cont_beh + + NoChannels <= "00101"; + DropChannels <= "00011"; + + CLK_I <= NOT CLK_I AFTER 20 NS; + C2 <= NOT C2 AFTER 244 NS; + rst_n <= '0', + '1' AFTER 730 NS; + + +------------------------------------------------------------------------------- + -- purpose: Initialization + -- type : combinational + -- inputs : rst_n + -- outputs: + INIT : PROCESS (rst_n) + VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; -- Internal Counter + BEGIN -- PROCESS INIT + + IF (rst_n = '0') THEN + + RxData(0) <= '1'; + RxData(1) <= '1'; + RxData(2) <= '1'; + RxData(3) <= '1'; + RxData(4) <= '1'; + RxData(5) <= '1'; + RxData(6) <= '1'; + RxData(7) <= '1'; + + RxData(8) <= '1'; + RxData(9) <= '1'; + RxData(10) <= '1'; + RxData(11) <= '1'; + RxData(12) <= '1'; + RxData(13) <= '1'; + RxData(14) <= '1'; + RxData(15) <= '1'; + + RxData(16) <= '1'; + RxData(17) <= '1'; + RxData(18) <= '1'; + RxData(19) <= '1'; + RxData(20) <= '1'; + RxData(21) <= '1'; + RxData(22) <= '1'; + RxData(23) <= '1'; + + -- Idle + RxData(24) <= '0'; + RxData(25) <= '1'; + RxData(26) <= '1'; + RxData(27) <= '1'; + RxData(28) <= '1'; + RxData(29) <= '1'; + RxData(30) <= '1'; + RxData(31) <= '0'; + -- Opening Flag + + -- Data pattern + FOR i IN 0 TO 59 LOOP + RxData(32+8*i+0) <= Counter(0); + RxData(32+8*i+1) <= Counter(1); + RxData(32+8*i+2) <= Counter(2); + RxData(32+8*i+3) <= Counter(3); + RxData(32+8*i+4) <= Counter(4); + RxData(32+8*i+5) <= Counter(5); + RxData(32+8*i+6) <= Counter(6); + RxData(32+8*i+7) <= Counter(7); + + Counter := Counter +1; + END LOOP; -- i + + END IF; + END PROCESS INIT; +------------------------------------------------------------------------------- + + Frame_gen : PROCESS + + BEGIN -- process Frame_gen + F0_n <= '1'; + WAIT UNTIL rst_n = '1'; + WAIT UNTIL C2 = '0'; + + WHILE TRUE LOOP + + F0_n <= '0'; + WAIT UNTIL C2 = '1'; + WAIT UNTIL C2 = '0'; + F0_n <= '1'; + + FOR i IN 0 TO 254 LOOP + WAIT UNTIL C2 = '1'; + WAIT UNTIL C2 = '0'; + + END LOOP; -- i + END LOOP; + + END PROCESS Frame_gen; + +------------------------------------------------------------------------------- + -- purpose: Rx Data generator + -- type : combinational + -- inputs : C2, rst_n + -- outputs: + Rx_gen : PROCESS + VARIABLE i : INTEGER := 0; + BEGIN -- PROCESS Rx_gen + DSTi <= '1'; + + WAIT UNTIL rst_n = '1'; + WHILE (TRUE) LOOP + + WAIT UNTIL F0_n = '0'; + + FOR counter IN 0 TO 255 LOOP + + DSTi <= RxData(i); --(counter+i*8); + + WAIT UNTIL C2 = '1'; + + i := i +1; + + END LOOP; -- counter + + END LOOP; -- while + + END PROCESS Rx_gen; +------------------------------------------------------------------------------- + + read_backend : PROCESS + + BEGIN -- PROCESS HDLC_read + RxRead <= '0'; + + WHILE (TRUE) LOOP + WAIT UNTIL Rxrdy = '1'; + WAIT UNTIL CLK_I = '1'; + WAIT UNTIL CLK_I = '0'; + RxRead <= '1'; + WAIT UNTIL Rxrdy = '0'; + WAIT UNTIL CLK_I = '0'; + RxRead <= '0'; + + END LOOP; + + END PROCESS read_backend; +------------------------------------------------------------------------------- + -- purpose: Tx Data generation + -- type : combinational + -- inputs : + -- outputs: + Tx_gen : PROCESS + VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; -- Interal counter + BEGIN -- process Tx_gen + + TxWrite <= '0'; + + WHILE TRUE LOOP + WAIT UNTIL TxRdy = '1'; + WAIT UNTIL CLK_I = '1'; + WAIT UNTIL CLK_I = '0'; + TxD <= counter; + TxWrite <= '1'; + counter := counter + 1; + WAIT UNTIL TxRdy = '0'; + WAIT UNTIL CLK_I = '0'; + TxWrite <= '0'; + END LOOP; + + END PROCESS Tx_gen; +------------------------------------------------------------------------------- + TxValidData <= '0', + '1' AFTER 20000 NS, + '0' AFTER 144000 NS; +------------------------------------------------------------------------------- + + DUT: tdm_cont_ent + PORT MAP ( + rst_n => rst_n, + C2 => C2, + DSTi => DSTi, + DSTo => DSTo, + F0_n => F0_n, + F0od_n => F0od_n, + CLK_I => CLK_I, + NoChannels => NoChannels, + DropChannels => DropChannels, + RxD => RxD, + RxValidData => RxValidData, + FramErr => FramErr, + RxRead => RxRead, + RxRdy => RxRdy, + TxErr => TxErr, + TxD => TxD, + TxValidData => TxValidData, + TxWrite => TxWrite, + TxRdy => TxRdy, + EnableSerialIF => EnableSerialIF, + Tx_en0 => Tx_en0, + Tx_en1 => Tx_en1, + Tx_en2 => Tx_en2, + Rx_en0 => Rx_en0, + Rx_en1 => Rx_en1, + Rx_en2 => Rx_en2, + SerDo => SerDo, + SerDi => SerDi); + +END tdm_cont_beh; + +------------------------------------------------------------------------------- Index: trunk/code/tdm_cont/tb/tdm_cont_top_tb.vhd =================================================================== --- trunk/code/tdm_cont/tb/tdm_cont_top_tb.vhd (nonexistent) +++ trunk/code/tdm_cont/tb/tdm_cont_top_tb.vhd (revision 4) @@ -0,0 +1,373 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller top test bench +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : tdm_cont_top_tb.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/18 +-- Last update:2001/05/25 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +-- tdm.components_pkg +------------------------------------------------------------------------------- +-- Description: tdm controller test bench +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/18 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2001/05/24 22:48:56 jamil +-- TDM Initial release +-- +------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +LIBRARY tdm; +USE tdm.components_pkg.ALL; + +------------------------------------------------------------------------------- + +ENTITY tdm_cont_top_tb IS + +END tdm_cont_top_tb; + +------------------------------------------------------------------------------- + +ARCHITECTURE tdm_cont_top_tb_beh OF tdm_cont_top_tb IS + + + SIGNAL CLK_I : STD_LOGIC := '0'; + SIGNAL RST_I : STD_LOGIC := '1'; + SIGNAL ACK_O : STD_LOGIC; + SIGNAL ADR_I : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL CYC_I : STD_LOGIC; + SIGNAL DAT_I : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL DAT_O : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL RTY_O : STD_LOGIC; + SIGNAL STB_I : STD_LOGIC; + SIGNAL WE_I : STD_LOGIC; + SIGNAL TAG0_O : STD_LOGIC; + SIGNAL TAG1_O : STD_LOGIC; + SIGNAL C2 : STD_LOGIC := '0'; + SIGNAL DSTi : STD_LOGIC; + SIGNAL DSTo : STD_LOGIC; + SIGNAL F0_n : STD_LOGIC; + SIGNAL F0od_n : STD_LOGIC; + + SIGNAL NoChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Number of TDM channels + SIGNAL DropChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- Number of TDM channels to be dropped + + TYPE SERIAL_typ IS ARRAY (0 TO 1023) OF STD_LOGIC; -- Serial Data array + + SIGNAL RxData : SERIAL_typ; -- Rx Serial Data + + +BEGIN -- tdm_cont_top_tb_beh + + + CLK_I <= NOT CLK_I AFTER 20 NS; + RST_I <= '1', + '0' AFTER 50 NS; + + C2 <= NOT C2 AFTER 244 NS; + +------------------------------------------------------------------------------- + -- purpose: Initialization + -- type : combinational + -- inputs : rst_I + -- outputs: + INIT : PROCESS (RST_I) + VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; -- Internal Counter + BEGIN -- PROCESS INIT + + IF (RST_I = '1') THEN + + -- Data pattern + FOR i IN 0 TO 127 LOOP + RxData(0+8*i+0) <= Counter(0); + RxData(0+8*i+1) <= Counter(1); + RxData(0+8*i+2) <= Counter(2); + RxData(0+8*i+3) <= Counter(3); + RxData(0+8*i+4) <= Counter(4); + RxData(0+8*i+5) <= Counter(5); + RxData(0+8*i+6) <= Counter(6); + RxData(0+8*i+7) <= Counter(7); + + Counter := Counter +1; + END LOOP; -- i + + END IF; + END PROCESS INIT; +------------------------------------------------------------------------------- + -- purpose: Tx Taskes generation + -- type : combinational + -- inputs : + -- outputs: + Tasks : PROCESS + VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Internal counter + BEGIN -- PROCESS TxTasks + + NoChannels <= "00110"; + DropChannels <= "00000"; + WAIT UNTIL CLK_I = '0'; + + WE_I <= '0'; + + STB_I <= '0'; + CYC_I <= '0'; + ADR_I <= "100"; + DAT_I <= (OTHERS => '0'); + + WAIT UNTIL CLK_I = '0'; + + STB_I <= '1'; + CYC_I <= '1'; + WE_I <= '1'; + ADR_I <= "100"; -- Channels + DAT_I <= "0000000000000000" & "000" & DropChannels & "000" & NoChannels; + + WAIT UNTIL ACK_O = '1'; + WAIT UNTIL CLK_I = '0'; + + WE_I <= '0'; + + STB_I <= '0'; + CYC_I <= '0'; + ADR_I <= "010"; + + WAIT UNTIL TAG1_O = '1'; -- wait for RxRdy + STB_I <= '1'; + CYC_I <= '1'; + ADR_I <= "010"; -- Rx_Sc + + WAIT UNTIL ACK_O = '1'; + WAIT UNTIL CLK_I = '0'; + + STB_I <= '0'; + CYC_I <= '0'; + + ADR_I <= "011"; -- Rx_Buff + +-- wait until CLK_I = '0'; + WAIT UNTIL CLK_I = '1'; + WAIT UNTIL CLK_I = '0'; + + STB_I <= '1'; + CYC_I <= '1'; + + Counter := (OTHERS => '0'); + + + FOR i IN 0 TO conv_integer(NoChannels - DropChannels) LOOP + + + WAIT UNTIL ACK_O = '1'; + + ASSERT (DAT_O(7 DOWNTO 0) = counter) + REPORT "Data byte 1 missmatch" + SEVERITY WARNING; + + + IF (counter = (NoChannels - DropChannels) ) THEN + EXIT; + END IF; + + counter := counter +1; + ASSERT (DAT_O(15 DOWNTO 8) = counter) + REPORT "Data byte 2 missmatch" + SEVERITY WARNING; + + + IF (counter = (NoChannels - DropChannels) ) THEN + EXIT; + END IF; + + counter := counter +1; + ASSERT (DAT_O(23 DOWNTO 16) = counter) + REPORT "Data byte 3 missmatch" + SEVERITY WARNING; + + IF (counter = (NoChannels - DropChannels) ) THEN + EXIT; + END IF; + + counter := counter +1; + ASSERT (DAT_O(31 DOWNTO 24) = counter) + REPORT "Data byte 4 missmatch" + SEVERITY WARNING; + + + counter := counter +1; + + END LOOP; -- i + + + WAIT UNTIL CLK_I = '0'; + + STB_I <= '0'; + CYC_I <= '0'; + ADR_I <= "000"; +------------------------------------------------------------------------------- +-- -- -- -- +------------------------------------------------------------------------------- + -- Transmit + IF TAG0_O = '0' THEN + WAIT UNTIL TAG0_O = '1'; + END IF; + + WAIT UNTIL CLK_I = '0'; + counter := (OTHERS => '0'); + + STB_I <= '1'; + CYC_I <= '1'; + ADR_I <= "001"; -- Tx_Buff + WE_I <= '1'; -- Write + + + FOR i IN 0 TO conv_integer(NoChannels - DropChannels)/4 LOOP + + DAT_I(7 DOWNTO 0) <= counter; + counter := counter +1; + DAT_I(15 DOWNTO 8) <= counter; + counter := counter +1; + DAT_I(23 DOWNTO 16) <= counter; + counter := counter +1; + DAT_I(31 DOWNTO 24) <= counter; + counter := counter +1; + + WAIT UNTIL ACK_O = '1'; + + WAIT UNTIL CLK_I = '0'; + + END LOOP; -- i + + + STB_I <= '0'; + CYC_I <= '0'; + WE_I <= '0'; + + WAIT UNTIL CLK_I = '1'; + WAIT UNTIL CLK_I = '0'; + STB_I <= '1'; + CYC_I <= '1'; + WE_I <= '0'; + ADR_I <= "000"; -- Tx_Sc + + WAIT UNTIL ACK_O = '1'; + WAIT UNTIL CLK_I = '0'; + + STB_I <= '0'; + CYC_I <= '0'; + WE_I <= '0'; + + END PROCESS Tasks; + +------------------------------------------------------------------------------- + Frame_gen : PROCESS + BEGIN -- process Frame_gen + F0_n <= '1'; + WAIT UNTIL RST_I = '0'; + WAIT UNTIL C2 = '0'; + + WHILE TRUE LOOP + + F0_n <= '0'; + WAIT UNTIL C2 = '1'; + WAIT UNTIL C2 = '0'; + F0_n <= '1'; + + FOR i IN 0 TO 254 LOOP + WAIT UNTIL C2 = '1'; + WAIT UNTIL C2 = '0'; + + END LOOP; -- i + END LOOP; + + END PROCESS Frame_gen; +------------------------------------------------------------------------------- + -- purpose: Rx Data generator + -- type : combinational + -- inputs : C2, RST_I + -- outputs: + Rx_gen : PROCESS +-- VARIABLE i : INTEGER := 0; + BEGIN -- PROCESS Rx_gen + DSTi <= '1'; + + WAIT UNTIL RST_I = '0'; + WHILE (TRUE) LOOP + + WAIT UNTIL F0_n = '0'; + WAIT UNTIL C2 = '1'; + + FOR i IN 0 TO 127 LOOP + DSTi <= RxData(0+8*i+7); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+6); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+5); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+4); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+3); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+2); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+1); + WAIT UNTIL C2 = '1'; + DSTi <= RxData(0+8*i+0); + WAIT UNTIL C2 = '1'; + END LOOP; -- i + + END LOOP; -- while + + END PROCESS Rx_gen; +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- + DUT : tdm_cont_top_ent + PORT MAP ( + CLK_I => CLK_I, + RST_I => RST_I, + ACK_O => ACK_O, + ADR_I => ADR_I, + CYC_I => CYC_I, + DAT_I => DAT_I, + DAT_O => DAT_O, + RTY_O => RTY_O, + STB_I => STB_I, + WE_I => WE_I, + TAG0_O => TAG0_O, + TAG1_O => TAG1_O, + C2 => C2, + DSTi => DSTi, + DSTo => DSTo, + F0_n => F0_n, + F0od_n => F0od_n); + + + +END tdm_cont_top_tb_beh; + +------------------------------------------------------------------------------- Index: trunk/code/tdm_cont/scripts/nc-sim/build_TDM_cont.csh =================================================================== --- trunk/code/tdm_cont/scripts/nc-sim/build_TDM_cont.csh (nonexistent) +++ trunk/code/tdm_cont/scripts/nc-sim/build_TDM_cont.csh (revision 4) @@ -0,0 +1,76 @@ +#! /bin/tcsh -f +# By Jamil Khatib +# This file for compiling the tdm project files using Cadence nc-sim tool +# You need to create sim directory in the same level of the code directory +# From OpenCores CVS +# You have to start the simulation in this directory +#$Log: not supported by cvs2svn $ +#Revision 1.1 2001/05/24 22:48:56 jamil +#TDM Initial release +# +mkdir -p work +mkdir -p utility +mkdir -p hdlc +mkdir -p memLib +mkdir -p tdm + +# Utility files +ncvhdl -work utility -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tools_pkg.vhd + +#memLib +ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/mem_pkg.vhd + +ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/spmem.vhd + + +#HDLC files +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/libs/hdlc_components_pkg.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/Rxcont.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/Zero_detect.vhd + + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/flag_detect.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/RxChannel.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/TXcont.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/flag_ins.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/zero_ins.vhd + +#ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/TxChannel.vhd + +#ISDN files +#ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/core/ISDN_cont.vhd + +#ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/libs/components_pkg.vhd + +#ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/core/ISDN_cont_top.vhd + + +#ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/tb/ISDN_cont_tb.vhd + + +#TDM files +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/core/tdm_cont.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/libs/components_pkg.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/tb/tdm_cont_tb.vhd + + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/core/RxTDMBuff.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/core/TxTDMBuff.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/core/tdm_wb_if.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/core/tdm_core_top.vhd + +ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/tdm_cont/tb/tdm_cont_top_tb.vhd + +#elaborating design +#ncelab -work work -cdslib ./cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 work.isdn_cont_tb:isdn_cont_tb Index: trunk/code/tdm_cont/scripts/nc-sim/cds.lib =================================================================== --- trunk/code/tdm_cont/scripts/nc-sim/cds.lib (nonexistent) +++ trunk/code/tdm_cont/scripts/nc-sim/cds.lib (revision 4) @@ -0,0 +1,8 @@ +include $CDS_INST_DIR/tools/inca/files/cds.lib + +undefine ambit +define work ./work +define utility ./utility +define hdlc ./hdlc +define memLib ./memLib +define tdm ./tdm Index: trunk/code/tdm_cont/scripts/nc-sim/hdl.var =================================================================== --- trunk/code/tdm_cont/scripts/nc-sim/hdl.var (nonexistent) +++ trunk/code/tdm_cont/scripts/nc-sim/hdl.var (revision 4) @@ -0,0 +1,5 @@ +DEFINE work work +DEFINE tdm tdm +DEFINE hdlc hdlc +DEFINE memLib memLib +DEFINE utility utility Index: trunk/code/tdm_cont/core/RxTDMBuff.vhd =================================================================== --- trunk/code/tdm_cont/core/RxTDMBuff.vhd (nonexistent) +++ trunk/code/tdm_cont/core/RxTDMBuff.vhd (revision 4) @@ -0,0 +1,211 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller Rx Buffer +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : RxTDMBuff.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/14 +-- Last update:2001/05/23 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164 +------------------------------------------------------------------------------- +-- Description: Receive Buffer that uses internal Sram +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/14 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2001/05/24 22:48:55 jamil +-- TDM Initial release +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +LIBRARY memLib; +USE memLib.mem_pkg.ALL; + + +ENTITY RxTDMBuff IS + + PORT ( + CLK_I : IN STD_LOGIC; + rst_n : IN STD_LOGIC; -- System reset + RxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data + RxRead : OUT STD_LOGIC; -- Rx Read + RxRdy : IN STD_LOGIC; -- Rx Ready to provide data + RxValidData : IN STD_LOGIC; -- Valid Data strobe + BufferDataAvail : OUT STD_LOGIC; -- Buffer Data Available strobe + ReadBuff : IN STD_LOGIC; -- Read Byte from Buffer + RxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Byte output from buffer + RxError : OUT STD_LOGIC -- Rx Error (buffer over flow) + ); +END RxTDMBuff; + + + +ARCHITECTURE RxTDMBuff OF RxTDMBuff IS + + + TYPE States_type IS (IDLE_st, READ_st, WRITE_st,WAITWRITE_st); -- Buffer states + + SIGNAL Address : STD_LOGIC_VECTOR(4 DOWNTO 0); -- memory address + + SIGNAL cs : STD_LOGIC := '1'; -- dummy signal + + SIGNAL wr_i : STD_LOGIC; -- Read/Write signal + SIGNAL Data_In : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Memory Data in + + SIGNAL Data_Out : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Memory Data out + + + +BEGIN -- RxTDMBuff +------------------------------------------------------------------------------- + RxData <= Data_Out; + +------------------------------------------------------------------------------- +-- purpose: FSM process +-- type : sequential +-- inputs : CLK_I, rst_n +-- outputs: + fsm : PROCESS (CLK_I, rst_n) + + VARIABLE state : States_type; -- internal state + VARIABLE counter : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Internal Counter + VARIABLE value : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Max count value + + BEGIN -- PROCESS fsm + + IF rst_n = '0' THEN -- asynchronous reset (active low) + state := IDLE_st; + RxRead <= '0'; + Counter := "00000"; + BufferDataAvail <= '0'; + value := "00000"; + WR_I <= '1'; + RxError <= '0'; + Data_In <= (OTHERS => '1'); + address <= (OTHERS => '0'); + + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + address <= Counter; + + Data_In <= RxD; + + CASE state IS + WHEN IDLE_st => + + IF (RxValidData = '1') THEN + state := WRITE_st; + END IF; + + wr_i <= '1'; + RxRead <= '0'; + Counter := "00000"; + BufferDataAvail <= '0'; + value := "00000"; + RxError <= '0'; + + WHEN READ_st => + + BufferDataAvail <= '1'; + RxRead <= '0'; + + wr_i <= '1';--ReadBuff; + RxError <= RxValidData; + + IF (counter = value) OR RxValidData = '1' THEN + state := IDLE_st; + counter := "00000"; + + ELSE + IF (ReadBuff = '1') THEN + Counter := Counter + 1; + END IF; + + END if; + + WHEN WRITE_st => + BufferDataAvail <= '0'; + + RxError <= '0'; + RxRead <= RxRdy; + wr_i <= NOT RxRdy; + + IF (counter = "11111" OR RxValidData = '0') THEN + state := READ_st; + value := counter; + + counter := "00000"; + +-- wr_i <= '1'; +-- RxRead <= '0'; + ELSE + IF (RxRdy = '1') THEN +-- wr_i <= '0'; --write to buffer + counter := counter + 1; + state := WAITWRITE_st; +-- RxRead <= '1'; +-- ELSE +-- wr_i <= '1'; +-- RxRead <= '0'; + END IF; + + END IF; + + WHEN WAITWRITE_st => + BufferDataAvail <= '0'; + RxError <= '0'; + RxRead <= '1'; + wr_i <= '0'; + IF (RxRdy = '0') THEN + state := WRITE_st; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + + END PROCESS fsm; + + + Buff : Spmem_ent + GENERIC MAP ( + USE_RESET => FALSE, + USE_CS => FALSE, + DEFAULT_OUT => '1', + OPTION => 0, + ADD_WIDTH => 5, + WIDTH => 8) + PORT MAP ( + cs => cs, + clk => clk_I, + reset => rst_n, + add => Address, + Data_In => Data_In, + Data_Out => Data_Out, + WR => WR_i); + + + END RxTDMBuff; Index: trunk/code/tdm_cont/core/TxTDMBuff.vhd =================================================================== --- trunk/code/tdm_cont/core/TxTDMBuff.vhd (nonexistent) +++ trunk/code/tdm_cont/core/TxTDMBuff.vhd (revision 4) @@ -0,0 +1,233 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller Tx Buffer +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : TxTDMBuff.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/14 +-- Last update:2001/05/22 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +-- memLib.mem_pkg +------------------------------------------------------------------------------- +-- Description: Transmit Buffer that uses internal Sram +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/15 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2001/05/24 22:48:56 jamil +-- TDM Initial release +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +LIBRARY memLib; +USE memLib.mem_pkg.ALL; + +ENTITY TxTDMBuff IS + + PORT ( + CLK_I : IN STD_LOGIC; -- System Clock + rst_n : IN STD_LOGIC; -- System reset + TxD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx output data + TxValidData : OUT STD_LOGIC; -- Tx Valid Data + TxWrite : OUT STD_LOGIC; -- Write byte + TxRdy : IN STD_LOGIC; -- Ready to send data + + WrBuff : IN STD_LOGIC; -- Write to buffer + TxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Byte output from buffer + NoChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- No of channels + DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- No of channels to be dropped + TxDone : OUT STD_LOGIC; -- Transmission completed + TxOverflow : OUT STD_LOGIC -- Tx buffer overflow + + ); + +END TxTDMBuff; + +ARCHITECTURE TxTDMBuff_rtl OF TxTDMBuff IS + + TYPE States_type IS (IDLE_st, READ_st, WAITREAD_st, WRITE_st); -- Buffer states + + SIGNAL Address : STD_LOGIC_VECTOR(4 DOWNTO 0); -- memory address + + SIGNAL cs : STD_LOGIC := '1'; -- dummy signal + + SIGNAL wr_i : STD_LOGIC; -- Read/Write signal + SIGNAL Data_In : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Memory Data in + + SIGNAL Data_Out : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Memory Data out + + SIGNAL TotalChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Totoal Channels + +BEGIN -- TxTDMBuff_rtl + +------------------------------------------------------------------------------- + TxD <= Data_Out; + TotalChannels <= NoChannels - DropChannels; + +------------------------------------------------------------------------------- +-- purpose: FSM process +-- type : sequential +-- inputs : CLK_I, rst_n +-- outputs: + fsm : PROCESS (CLK_I, rst_n) + + VARIABLE state : States_type; -- internal state + VARIABLE counter : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Internal Counter +-- VARIABLE TxwriteDelayed : STD_LOGIC; -- Delayed TxWrite + + BEGIN -- PROCESS fsm + + IF rst_n = '0' THEN -- asynchronous reset (active low) + state := IDLE_st; + TxWrite <= '0'; + Counter := "00000"; + TxValidData <= '0'; + + TxOverflow <= '0'; + + address <= (OTHERS => '0'); + Data_In <= (OTHERS => '0'); + + TxDone <= '0'; + wr_i <= '1'; + + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + + CASE state IS + WHEN IDLE_st => + TxValidData <= '0'; + TxOverflow <= '0'; + + Counter := "00000"; + address <= Counter; + Data_In <= TxData; + + Txwrite <= '0'; + TxDone <= '1'; + + IF (WrBuff = '1') THEN + + state := WRITE_st; + Counter := Counter +1; + + END IF; + + wr_i <= NOT WrBuff; + + TxOverflow <= '0'; + + WHEN READ_st => + TxValidData <= '1'; + TxDone <= '0'; + TxOverflow <= '0'; + + wr_i <= '1'; + Txwrite <= '0'; + + address <= Counter; + + IF (TxRdy = '1') THEN + + state := WAITREAD_st; + + END IF; + + WHEN WAITREAD_st => + TxDone <= '0'; + TxValidData <= '1'; + Txwrite <= '1'; + TxOverflow <= '0'; + + address <= counter; + + wr_i <= '1'; + + IF (TxRdy = '0') THEN + IF (counter = TotalChannels) THEN + + counter := (OTHERS => '0'); + state := IDLE_st; + + else + counter := counter +1; + state := READ_st; + END IF; + + END IF; + + WHEN WRITE_st => + TxDone <= '0'; + + TxValidData <= '0'; + + TxOverflow <= '0'; + + Txwrite <= '0'; + + wr_i <= NOT WrBuff; + + address <= Counter; + Data_In <= TxData; + + IF (counter = TotalChannels) THEN + + counter := "00000"; + state := READ_st; + + ELSIF (WrBuff = '1') THEN + counter := counter + 1; + END IF; + + + WHEN OTHERS => NULL; + END CASE; + END IF; + + END PROCESS fsm; +------------------------------------------------------------------------------ + + Buff : Spmem_ent + GENERIC MAP ( + USE_RESET => FALSE, + USE_CS => FALSE, + DEFAULT_OUT => '1', + OPTION => 0, + ADD_WIDTH => 5, + WIDTH => 8) + PORT MAP ( + cs => cs, + clk => clk_I, + reset => rst_n, + add => Address, + Data_In => Data_In, + Data_Out => Data_Out, + WR => WR_i); + +END TxTDMBuff_rtl; + + + Index: trunk/code/tdm_cont/core/tdm_cont.vhd =================================================================== --- trunk/code/tdm_cont/core/tdm_cont.vhd (nonexistent) +++ trunk/code/tdm_cont/core/tdm_cont.vhd (revision 4) @@ -0,0 +1,479 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : tdm_cont.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/09 +-- Last update:2001/05/23 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164 +------------------------------------------------------------------------------- +-- Description: tdm controller that reads and writes E1 bit rate through +-- ST-bis interface +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/09 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2001/05/24 22:48:56 jamil +-- TDM Initial release +-- +-- Revision 1.2 2001/05/18 08:49:23 jamil +-- Serial interface added +-- +-- Revision 1.1 2001/05/13 21:13:35 jamil +-- Initial Release +-- +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +ENTITY tdm_cont_ent IS + + PORT ( + rst_n : IN STD_LOGIC; -- System asynchronous reset + C2 : IN STD_LOGIC; -- ST-Bus clock + DSTi : IN STD_LOGIC; -- ST-Bus input Data + DSTo : OUT STD_LOGIC; -- ST-Bus output Data + F0_n : IN STD_LOGIC; -- St-Bus Framing pulse + F0od_n : OUT STD_LOGIC; -- ST-Bus Delayed Framing pulse + + CLK_I : IN STD_LOGIC; -- System clock + +--Backend interface + NoChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- no of Time slots + DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- No of channels to be dropped + + RxD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Parellel Rx output + RxValidData : OUT STD_LOGIC; -- Valid Data + FramErr : OUT STD_LOGIC; -- Frame Error due to + -- buffer overflow + RxRead : IN STD_LOGIC; -- Read Byte + RxRdy : OUT STD_LOGIC; -- Byte ready + TxErr : OUT STD_LOGIC; + -- Tx Error in transmission due to buffer underflow + TxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Parellal Tx Input + TxValidData : IN STD_LOGIC; -- Tx Valid Data + TxWrite : IN STD_LOGIC; -- Write byte + TxRdy : OUT STD_LOGIC; -- Byte Ready + + -- Serial Interfaces + EnableSerialIF : IN STD_LOGIC; -- Enable Serial Interface + + Tx_en0 : OUT STD_LOGIC; -- Tx enable channel 0 + Tx_en1 : OUT STD_LOGIC; -- Tx enable channel 1 + Tx_en2 : OUT STD_LOGIC; -- Tx enable channel 2 + + Rx_en0 : OUT STD_LOGIC; -- Rx enable channel 0 + Rx_en1 : OUT STD_LOGIC; -- Rx enable channel 1 + Rx_en2 : OUT STD_LOGIC; -- Rx enable channel 2 + + SerDo : OUT STD_LOGIC; -- serial Data out + SerDi : IN STD_LOGIC -- Serial Data in + + ); + + +END tdm_cont_ent; + +ARCHITECTURE tdm_cont_rtl OF tdm_cont_ent IS + SIGNAL Tot_count : STD_LOGIC_VECTOR(7 DOWNTO 0); -- total store counter + SIGNAL drop_count : STD_LOGIC_VECTOR(7 DOWNTO 0); -- total droped counter + + TYPE States_type IS (IDLE_st, WRITE_st, READ_st); --States type + + SIGNAL state : States_type; -- FSM state + + SIGNAL DSTi_reg : STD_LOGIC; -- DSTi register + + SIGNAL Tx_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data register + SIGNAL Tx_reg_i : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data register + SIGNAL Tx_En : STD_LOGIC; -- Tx Enable + SIGNAL Rx_En : STD_LOGIC; -- Rx Enable + SIGNAL Rx_Reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data register + + SIGNAL RxFrame : STD_LOGIC; -- Rx Frame Valid + SIGNAL RxFlag : STD_LOGIC; -- Rx Flag + + SIGNAL TxFlag : STD_LOGIC; -- Tx Flag + SIGNAL TxDisable : STD_LOGIC; -- disable Tx from Backend + + SIGNAL GetNew : STD_LOGIC; -- Get New byte + + SIGNAL EnableRegister : STD_LOGIC_VECTOR(31 DOWNTO 0); + -- Enable register + SIGNAL EnShift : STD_LOGIC; -- Enable shift + +BEGIN -- tdm_cont_rtl +------------------------------------------------------------------------------- +-- Global constants +------------------------------------------------------------------------------- + Tot_count <= NoChannels & "111"; + drop_count <= DropChannels & "000"; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Main machine +------------------------------------------------------------------------------- +-- purpose: FSM +-- type : sequential +-- inputs : CLK_I, rst_n +-- outputs: + fsm : PROCESS (CLK_I, rst_n) + + VARIABLE counter : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Bit counter + VARIABLE Drop : STD_LOGIC; -- Drop bit + VARIABLE ExtendFrame : STD_LOGIC; -- Extend Delayed Frame pulse + BEGIN -- process fsm + IF rst_n = '0' THEN -- asynchronous reset (active low) + state <= IDLE_st; + counter := (OTHERS => '0'); + Tx_En <= '0'; + Rx_en <= '0'; + DSTi_reg <= '1'; + Drop := '0'; + DSTo <= 'Z'; + TxDisable <= '1'; + F0od_n <= '1'; + RxFrame <= '0'; + GetNew <= '0'; + ExtendFrame := '0'; + SerDo <= '1'; + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + CASE State IS + WHEN IDLE_st => + DSTo <= 'Z'; + Drop := '0'; + + Tx_En <= '0'; + Rx_en <= '0'; + + IF F0_n = '0' THEN + + State <= WRITE_st; + counter := (OTHERS => '0'); + TxDisable <= NOT TxValidData; + GetNew <= '1'; + + END IF; + + RxFrame <= '0'; + + IF ExtendFrame = '1' AND C2 = '0' THEN + F0od_n <= '1'; + END IF; + + IF C2 = '1' THEN + ExtendFrame := '1'; + END IF; + + + WHEN WRITE_st => + ExtendFrame := '0'; + GetNew <= '0'; + RxFrame <= '1'; + + F0od_n <= '1'; + Rx_en <= '0'; + + IF C2 = '1' THEN + + IF counter >= drop_count THEN + IF TxDisable = '1' THEN + DSTo <= '1'; + Tx_En <= '0'; + ELSE + + IF (EnableSerialIF = '1') THEN + DSTo <= SerDi; + ELSE + DSTo <= Tx_reg(7); + END IF; + + Tx_En <= '1'; + END IF; + + Drop := '0'; + + ELSE + DSTo <= 'Z'; + Tx_En <= '0'; + Drop := '1'; + END IF; + + State <= READ_st; + + ELSE + + Tx_En <= '0'; + + END IF; + + WHEN READ_st => + ExtendFrame := '0'; + GetNew <= '0'; + RxFrame <= '1'; + Tx_En <= '0'; + + IF C2 = '0' THEN + + DSTi_reg <= DSTi; + SerDo <= DSTi; + + IF counter = Tot_count THEN + + State <= IDLE_st; + F0od_n <= '0'; + + ELSE + State <= WRITE_st; + F0od_n <= '1'; + + END IF; + + counter := counter + 1; + + Rx_En <= NOT Drop; + ELSE + Rx_En <= '0'; + END IF; + + END CASE; + + END IF; + END PROCESS fsm; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Rx Machines +------------------------------------------------------------------------------- + -- purpose: Rx Serial To parellel + -- type : sequential + RxS2P : PROCESS (CLK_I, rst_n) + VARIABLE Rx_count : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Rx Internal bit counter + + BEGIN -- process RxS2P + IF rst_n = '0' THEN -- asynchronous reset (active low) + Rx_count := "000"; + RxFlag <= '0'; + Rx_Reg <= (OTHERS => '1'); + EnShift <= '0'; + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + IF Rx_En = '1' THEN + + Rx_Reg <= Rx_Reg(6 DOWNTO 0) & DSTi_reg; + + IF Rx_count = "111" THEN + Rx_count := "000"; + + RxFlag <= '1'; + + EnShift <= '1'; + ELSE + Rx_count := Rx_count + 1; + RxFlag <= '0'; + EnShift <= '0'; + END IF; + ELSE + RxFlag <= '0'; + EnShift <= '0'; + END IF; + + END IF; + END PROCESS RxS2P; +------------------------------------------------------------------------------- + -- purpose: Rx Backend + -- type : sequential + -- inputs : CLK_I, rst_n + -- outputs: + RxBackend : PROCESS (CLK_I, rst_n) + VARIABLE state : STD_LOGIC; -- Internal State + BEGIN -- process RxBackend + IF rst_n = '0' THEN -- asynchronous reset (active low) + State := '0'; + RxD <= (OTHERS => '0'); + RxRdy <= '0'; + FramErr <= '0'; + RxValidData <= '0'; + + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + CASE State IS + + WHEN '0' => + RxRdy <= '0'; + FramErr <= '0'; + + IF RxFlag = '1' THEN + RxD <= Rx_Reg; + State := '1'; + END IF; + + WHEN '1' => + RxRdy <= '1'; + RxValidData <= RxFrame; + IF RxFlag = '1' THEN + State := '0'; + FramErr <= '1'; +-- RxValidData <= RxFrame; + ELSIF RxRead = '1' THEN + +-- RxValidData <= RxFrame; + + State := '0'; + FramErr <= '0'; + END IF; + + WHEN OTHERS => + RxRdy <= '0'; + State := '0'; + FramErr <= '1'; + RxValidData <= RxFrame; + END CASE; + END IF; + END PROCESS RxBackend; +------------------------------------------------------------------------------- +-- Tx Machines +------------------------------------------------------------------------------- + -- purpose: Tx Parellel to serial + -- type : sequential + -- inputs : CLK_I, rst_n + -- outputs: + TxP2S : PROCESS (CLK_I, rst_n) + VARIABLE Tx_Count : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Tx Bit counter + BEGIN -- process TxP2S + IF rst_n = '0' THEN -- asynchronous reset (active low) + Tx_Count := "000"; + Tx_reg <= (OTHERS => '1'); + TxFlag <= '0'; + + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + IF TxDisable = '0' AND GetNew = '1' THEN + Tx_reg <= Tx_reg_i; + TxFlag <= '1'; + + ELSE + IF Tx_En = '1' THEN + + IF Tx_count = "111" THEN + Tx_count := "000"; + + Tx_Reg <= Tx_Reg_i; + TxFlag <= '1'; + ELSE + Tx_count := Tx_count + 1; + TxFlag <= '0'; + Tx_Reg <= Tx_Reg(6 DOWNTO 0) & '1'; + + END IF; + + ELSE + TxFlag <= '0'; + END IF; + END IF; + END IF; + END PROCESS TxP2S; +------------------------------------------------------------------------------- + -- purpose: Tx Backend machine + -- type : sequential + -- inputs : CLK_I, rst_n + -- outputs: + TxBackend : PROCESS (CLK_I, rst_n) + VARIABLE state : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Internal State + BEGIN -- process TxBackend + IF rst_n = '0' THEN -- asynchronous reset (active low) + + State := "11"; -- Wait for NewValidFrame + TxRdy <= '0'; + TxErr <= '0'; + Tx_Reg_i <= (OTHERS => '1'); + + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + CASE State IS + WHEN"11" => + TxRdy <= '1'; + + IF TxValidData = '1' THEN + State := "01"; -- Get New byte + END IF; + + WHEN "00" => + TxRdy <= '0'; + + IF TxFlag = '1' THEN -- and TxDisable = '0' then + + State := "01"; -- Get New Byte + END IF; + + WHEN "01" => + TxRdy <= '1'; + + IF TxFlag = '1' OR TxValidData = '0' THEN + State := "11"; -- Wait for New frame + TxErr <= '1'; + Tx_Reg_i <= (OTHERS => '1'); + ELSIF TxWrite = '1' THEN + State := "00"; + TxErr <= '0'; + Tx_Reg_i <= TxD; + END IF; + + WHEN OTHERS => + TxRdy <= '0'; + State := "11"; + TxErr <= '1'; + Tx_Reg_i <= (OTHERS => '1'); + END CASE; + END IF; + END PROCESS TxBackend; +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Serial Interface logic +------------------------------------------------------------------------------- + Tx_en0 <= EnableRegister(0) AND Tx_En; + Tx_en1 <= EnableRegister(1) AND Tx_En; + Tx_en2 <= EnableRegister(2) AND Tx_En; + Rx_en0 <= EnableRegister(0) AND Rx_En; + Rx_en1 <= EnableRegister(1) AND Rx_En; + Rx_en2 <= EnableRegister(2) AND Rx_En; +------------------------------------------------------------------------------- + -- purpose: Serial Enable shift register + -- type : sequential + -- inputs : clock, rst_n + -- outputs: + SerialEnShift : PROCESS (CLK_I, rst_n) + + BEGIN -- PROCESS SerialEnShift + + IF rst_n = '0' THEN -- asynchronous reset (active low) + EnableRegister <= "00000000000000000000000000000001"; + ELSIF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + IF (EnShift = '1') THEN + EnableRegister <= EnableRegister(30 DOWNTO 0) & EnableRegister(31); + END IF; + END IF; + + END PROCESS SerialEnShift; +END tdm_cont_rtl; Index: trunk/code/tdm_cont/core/tdm_wb_if.vhd =================================================================== --- trunk/code/tdm_cont/core/tdm_wb_if.vhd (nonexistent) +++ trunk/code/tdm_cont/core/tdm_wb_if.vhd (revision 4) @@ -0,0 +1,525 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller wishbone interface +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : tdm_wb_if.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/18 +-- Last update:2001/05/24 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned +------------------------------------------------------------------------------- +-- Description: tdm controller Wishbone Bus interface +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/18 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2001/05/24 22:48:56 jamil +-- TDM Initial release +-- +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +ENTITY tdm_wb_if_ent IS + + PORT ( + -- WB Bus ports + CLK_I : IN STD_LOGIC; -- System Clock + RST_I : IN STD_LOGIC; -- System Reset + ACK_O : OUT STD_LOGIC; -- acknowledge + ADR_I : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- address + CYC_I : IN STD_LOGIC; -- Bus cycle + DAT_I : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Input data + DAT_O : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Output data + RTY_O : OUT STD_LOGIC; -- retry + STB_I : IN STD_LOGIC; -- strobe + WE_I : IN STD_LOGIC; -- Write + TAG0_O : OUT STD_LOGIC; -- TAG0 (TxDone) + TAG1_O : OUT STD_LOGIC; -- TAG1_O (RxRdy) + +-- Internal ports + -- Tx + TxDone : IN STD_LOGIC; -- Transmission Done (Read Frame completed) + WrBuff : OUT STD_LOGIC; -- Write to buffer + TxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Byte output from buffer + TxOverflow : IN STD_LOGIC; -- Tx buffer overflow + TxUnderflow : IN STD_LOGIC; -- Tx Buffer under flow + -- Rx + RxRdy : IN STD_LOGIC; -- Rx Ready + ReadBuff : OUT STD_LOGIC; -- Read Byte from Buffer + RxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Byte output from buffer + RxOverflow : IN STD_LOGIC; -- Rx Buffer Overflow + RxLineOverflow : IN STD_LOGIC; -- Rx Line conversion error + HDLCen : OUT STD_LOGIC; -- Enable HDLC + NoChannels : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- No of channels + DropChannels : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) -- No of channels to be dropped + ); +END tdm_wb_if_ent; + + +ARCHITECTURE WB_IF_rtl OF tdm_WB_IF_ent IS + SIGNAL ack_0 : STD_LOGIC; -- ack Reg 0 + SIGNAL ack_1 : STD_LOGIC; -- ack Reg 1 + SIGNAL ack_2 : STD_LOGIC; -- ack Reg 2 + SIGNAL ack_3 : STD_LOGIC; -- ack Reg 3 + SIGNAL ack_4 : STD_LOGIC; -- ack Reg 4 + + SIGNAL DATO_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- data out 0 + SIGNAL DATO_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- data out 1 + SIGNAL DATO_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- data out 2 + SIGNAL DATO_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- data out 3 + SIGNAL DATO_4 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- data out 4 + + SIGNAL en_0 : STD_LOGIC; -- Enable reg 0 + SIGNAL en_1 : STD_LOGIC; -- Enable reg 1 + SIGNAL en_2 : STD_LOGIC; -- Enable reg 2 + SIGNAL en_3 : STD_LOGIC; -- Enable reg 3 + SIGNAL en_4 : STD_LOGIC; -- Enable reg 4 + + SIGNAL counter : INTEGER RANGE 0 TO 8; -- System counter + SIGNAL rst_count : STD_LOGIC; -- Reset counter + +BEGIN -- WB_IF_rtl + +-- purpose: WB fsm +-- type : sequential +-- inputs : CLK_I, RST_I +-- outputs: + WB_fsm : PROCESS (CLK_I, RST_I) + + BEGIN -- PROCESS WB_fsm + IF (CLK_I'event AND CLK_I = '1') THEN + RTY_O <= '0'; + + IF (RST_I = '1') THEN -- synchronous reset + + ACK_O <= '0'; + DAT_O <= (OTHERS => '0'); + RTY_O <= '0'; + TAG0_O <= '0'; + TAG1_O <= '0'; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '0'; + rst_count <= '1'; + + ELSE + TAG0_O <= TxDone; + TAG1_O <= RxRdy; + + IF (CYC_I = '1' AND STB_I = '1') THEN + + CASE ADR_I IS + WHEN "000" => -- Tx_SC + ACK_O <= ack_0; + DAT_O <= DATO_0; + + en_0 <= '1'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '0'; + rst_count <= '1'; + + WHEN "001" => -- Tx_Buff + ACK_O <= ack_1; + DAT_O <= DATO_1; + + en_0 <= '0'; + en_1 <= '1' AND NOT ack_1; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '0'; + + IF counter = 4 THEN + rst_count <= '1'; + ELSE + rst_count <= '0'; + END IF; + + WHEN "010" => -- Rx_SC + ACK_O <= ack_2; + DAT_O <= DATO_2; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '1'; + en_3 <= '0'; + en_4 <= '0'; + + WHEN "011" => -- Rx_Buff + ACK_O <= ack_3; + DAT_O <= DATO_3; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '1' AND NOT ack_3; + en_4 <= '0'; + + IF (ack_3 = '1') THEN + rst_count <= '1'; + else + rst_count <= '0'; + END IF; +-- IF counter = 6 THEN +-- rst_count <= '1'; +-- ELSE +-- rst_count <= '0'; +-- END IF; + + WHEN "100" => -- Channels configuration + ACK_O <= ack_4; + DAT_O <= DATO_4; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '1'; + + WHEN OTHERS => + DAT_O <= (OTHERS => '0'); + ACK_O <= '1'; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '0'; + + END CASE; + + ELSE + + DAT_O <= (OTHERS => '0'); + ACK_O <= '0'; + + en_0 <= '0'; + en_1 <= '0'; + en_2 <= '0'; + en_3 <= '0'; + en_4 <= '0'; + + END IF; -- cycle + + END IF; --clock + + END IF; -- reset + + END PROCESS WB_fsm; + +------------------------------------------------------------------------------- + -- purpose: Register0 + -- type : sequential + -- inputs : CLK_I, RST_I + -- outputs: + reg0 : PROCESS (CLK_I, RST_I) + + VARIABLE HDLCen_var : STD_LOGIC; -- Internal HDLc enable + VARIABLE TxOverflow_var : STD_LOGIC; -- Internal Overflow reg + VARIABLE TxUnderflow_var : STD_LOGIC; -- Internal underflow re + + BEGIN -- PROCESS reg0 + IF (CLK_I'event AND CLK_I = '1') THEN + + IF (RST_I = '1') THEN + ack_0 <= '0'; + DATO_0 <= (OTHERS => '0'); + HDLCen <= '0'; + HDLCen_var := '0'; + TxOverflow_var := '0'; + TxUnderflow_var := '0'; + + ELSE + + DATO_0 <= "000000000000000000000000"& + "0000" & HDLCen_var & TxUnderflow_var & TxOverflow_var & TxDone; + ack_0 <= en_0; + + IF (TxOverflow = '1') THEN + TxOverflow_var := '1'; + ELSIF (en_0 = '1') THEN + TxOverflow_var := '0'; + END IF; + + IF (TxUnderflow = '1') THEN + TxUnderflow_var := '1'; + ELSIF (en_0 = '1') THEN + TxUnderflow_var := '0'; + END IF; + + + IF (en_0 = '1' AND WE_I = '1') THEN + + HDLCen_var := DAT_I(3); + + END IF; -- Write and en_0 + + HDLCen <= HDLCen_var; + + END IF; -- rst + END IF; -- clk + + END PROCESS reg0; +------------------------------------------------------------------------------- + -- purpose: Register1 + -- type : sequential + -- inputs : CLK_I, RST_I + -- outputs: + reg1 : PROCESS (CLK_I, RST_I) + + BEGIN -- PROCESS reg1 + IF (CLK_I'event AND CLK_I = '1') THEN + + IF (RST_I = '1') THEN + ack_1 <= '0'; + DATO_1 <= (OTHERS => '0'); + + ELSE -- reset + DATO_1 <= (OTHERS => '0'); + + IF (WE_I = '1' AND en_1 = '1') THEN + + CASE counter IS + WHEN 0 => + WrBuff <= '1'; + TxData <= DAT_I(7 DOWNTO 0); + ack_1 <= '0'; + + WHEN 1 => + WrBuff <= '1'; + TxData <= DAT_I(15 DOWNTO 8); + ack_1 <= '0'; + + WHEN 2 => + WrBuff <= '1'; + TxData <= DAT_I(23 DOWNTO 16); + ack_1 <= '0'; + + WHEN 3 => + WrBuff <= '1'; + TxData <= DAT_I(31 DOWNTO 24); + ack_1 <= '1'; + + WHEN OTHERS => + WrBuff <= '0'; + TxData <= (OTHERS => '0'); + ack_1 <= '0'; + END CASE; + + ELSE -- WE_I + + TxData <= (OTHERS => '0'); + WrBuff <= '0'; + ack_1 <= '0'; + END IF; -- WE_I and en_1 + + END IF; -- rst + END IF; -- clk + + END PROCESS reg1; + +------------------------------------------------------------------------------- + -- purpose: Register2 + -- type : sequential + -- inputs : CLK_I, RST_I + -- outputs: + reg2 : PROCESS (CLK_I, RST_I) + VARIABLE RxOverflow_var : STD_LOGIC; -- RxOverflow internal register + VARIABLE RxLineOverflow_var : STD_LOGIC; -- Rx Line Over flow (cased by line + -- serial to parallel conversion error) + BEGIN -- PROCESS reg3 + IF (CLK_I'event AND CLK_I = '1') THEN + + IF (RST_I = '1') THEN + ack_2 <= '0'; + DATO_2 <= (OTHERS => '0'); + RxLineOverflow_var := '0'; + RxOverflow_var := '0'; + ELSE + DATO_2 <= "000000000000000000000000"& + "00000" & RxOverflow_var & RxLineOverflow_var & RxRdy; + ack_2 <= en_2; + + IF (RxOverflow = '1') THEN + RxOverflow_var := '1'; + ELSIF (en_2 = '1') THEN + RxOverflow_var := '0'; + END IF; + + IF (RxLineOverflow = '1') THEN + RxLineOverflow_var := '1'; + ELSIF (en_2 = '1') THEN + RxLineOverflow_var := '0'; + END IF; + + END IF; -- rst + END IF; -- clk + + END PROCESS reg2; +------------------------------------------------------------------------------- + -- purpose: Register3 + -- type : sequential + -- inputs : CLK_I, RST_I + -- outputs: + reg3 : PROCESS (CLK_I, RST_I) + + BEGIN -- PROCESS reg3 + IF (CLK_I'event AND CLK_I = '1') THEN + + IF (RST_I = '1') THEN + ack_3 <= '0'; + DATO_3 <= (OTHERS => '0'); + + ELSE + + IF (en_3 = '1' AND WE_I = '0') THEN + + CASE counter IS + WHEN 0 => + ReadBuff <= '1'; + DATO_3 <= (OTHERS => '0'); + ack_3 <= '0'; + + WHEN 1 => + ReadBuff <= '1'; + + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + + ack_3 <= '0'; + + WHEN 2 => + ReadBuff <= '1'; + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + ack_3 <= '0'; + + WHEN 3 => + ReadBuff <= '1'; + + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + ack_3 <= '0'; + + WHEN 4 => + ReadBuff <= '0'; + + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + ack_3 <= '0'; + + WHEN 5 => + ReadBuff <= '0'; + + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + ack_3 <= '0'; + + WHEN 6 => + ReadBuff <= '0'; + + DATO_3 <= RxData & DATO_3(31 DOWNTO 8); + ack_3 <= '1'; + + WHEN OTHERS => + ReadBuff <= '0'; + + DATO_3 <= (OTHERS => '0'); + ack_3 <= '0'; + END CASE; + + ELSE + DATO_3 <= (OTHERS => '0'); + + ReadBuff <= '0'; + ack_3 <= '0'; + + END IF; -- en + + END IF; -- rst + END IF; -- clk + + END PROCESS reg3; + + ----------------------------------------------------------------------------- + -- purpose: Register4 + -- type : sequential + -- inputs : CLK_I, RST_I + -- outputs: + reg4 : PROCESS (CLK_I, RST_I) +variable NoChannels_var : STD_LOGIC_VECTOR(4 downto 0); -- Internal register +variable DropChannels_var : STD_LOGIC_VECTOR(4 downto 0); -- Internal register + + BEGIN -- PROCESS reg4 + IF (CLK_I'event AND CLK_I = '1') THEN + + IF (RST_I = '1') THEN + ack_4 <= '0'; + DATO_4 <= (OTHERS => '0'); + + NoChannels_var := (OTHERS => '0'); + DropChannels_var := (OTHERS => '0'); + + ELSE + DATO_4 <= "0000000000000000" & "000" & DropChannels_var& "000" & NoChannels_var; + + if( WE_I = '1' and en_4 = '1')then + NoChannels_var := DAT_I(4 DOWNTO 0); + DropChannels_var := DAT_I(12 DOWNTO 8); + NoChannels <= DAT_I(4 DOWNTO 0); + DropChannels <= DAT_I(12 DOWNTO 8); + end if; + + ack_4 <= en_4; + + END IF; -- rst + END IF; -- clk + + END PROCESS reg4; + ----------------------------------------------------------------------------- + +-- purpose: system counter +-- type : sequential +-- inputs : CLK_I +-- outputs: + sys_counter : PROCESS (CLK_I) + BEGIN -- process sys_counter + + IF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge + + IF rst_count = '1' THEN + + counter <= 0; + + ELSIF en_1 = '1' OR en_3 = '1' THEN + + counter <= counter +1; + + ELSE + counter <= 0; + END IF; + END IF; + END PROCESS sys_counter; +----------------------------------------------------------------------------- + +END WB_IF_rtl; Index: trunk/code/tdm_cont/core/tdm_core_top.vhd =================================================================== --- trunk/code/tdm_cont/core/tdm_core_top.vhd (nonexistent) +++ trunk/code/tdm_cont/core/tdm_core_top.vhd (revision 4) @@ -0,0 +1,208 @@ +------------------------------------------------------------------------------- +-- Title : TDM controller top +-- Project : TDM controller +------------------------------------------------------------------------------- +-- File : tdm_cont_top.vhd +-- Author : Jamil Khatib +-- Organization: OpenCores.org +-- Created : 2001/05/14 +-- Last update:2001/05/22 +-- Platform : +-- Simulators : NC-sim/linux, Modelsim XE/windows98 +-- Synthesizers: Leonardo +-- Target : +-- Dependency : ieee.std_logic_1164 +-- tdm.components_pkg +------------------------------------------------------------------------------- +-- Description: tdm controller that reads and writes E1 bit rate through +-- ST-bus interface +------------------------------------------------------------------------------- +-- Copyright (c) 2001 Jamil Khatib +-- +-- This VHDL design file is an open design; you can redistribute it and/or +-- modify it and/or implement it after contacting the author +-- You can check the draft license at +-- http://www.opencores.org/OIPC/license.shtml +------------------------------------------------------------------------------- +-- Revisions : +-- Revision Number : 1 +-- Version : 0.1 +-- Date : 2001/05/09 +-- Modifier : Jamil Khatib +-- Desccription : Created +-- ToOptimize : +-- Known Bugs : +------------------------------------------------------------------------------- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2001/05/24 22:48:56 jamil +-- TDM Initial release +-- +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY tdm; +USE tdm.components_pkg.ALL; + +ENTITY tdm_cont_top_ent IS + + PORT ( + -- Wishbone Interface + CLK_I : IN STD_LOGIC; -- system clock + RST_I : IN STD_LOGIC; -- system reset + ACK_O : OUT STD_LOGIC; -- acknowledge + ADR_I : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- address + CYC_I : IN STD_LOGIC; -- Bus cycle + DAT_I : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Input data + DAT_O : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Output data + RTY_O : OUT STD_LOGIC; -- retry + STB_I : IN STD_LOGIC; -- strobe + WE_I : IN STD_LOGIC; -- Write + TAG0_O : OUT STD_LOGIC; -- TAG0 (TxDone) + TAG1_O : OUT STD_LOGIC; -- TAG1_O (RxRdy) +-- ST-Bus interface + C2 : IN STD_LOGIC; -- ST-Bus clock + DSTi : IN STD_LOGIC; -- ST-Bus input Data + DSTo : OUT STD_LOGIC; -- ST-Bus output Data + F0_n : IN STD_LOGIC; -- St-Bus Framing pulse + F0od_n : OUT STD_LOGIC -- ST-Bus Delayed Framing pulse + + ); + +END tdm_cont_top_ent; + + +ARCHITECTURE tdm_top_str OF tdm_cont_top_ent IS + + + SIGNAL rst_n : STD_LOGIC; + SIGNAL NoChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL DropChannels : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL RxD : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL TxD : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL Tx_en0 : STD_LOGIC; + SIGNAL Tx_en1 : STD_LOGIC; + SIGNAL Tx_en2 : STD_LOGIC; + SIGNAL Rx_en0 : STD_LOGIC; + SIGNAL Rx_en1 : STD_LOGIC; + SIGNAL Rx_en2 : STD_LOGIC; + SIGNAL SerDo : STD_LOGIC; + SIGNAL SerDi : STD_LOGIC; + + SIGNAL TxValidData : STD_LOGIC; + SIGNAL TxWrite : STD_LOGIC; + SIGNAL TxRdy : STD_LOGIC; + + SIGNAL RxRead : STD_LOGIC; + SIGNAL RxRdy : STD_LOGIC; + SIGNAL RxValidData : STD_LOGIC; + SIGNAL BufferDataAvail : STD_LOGIC; + SIGNAL RxLineOverflow : STD_LOGIC; + + + SIGNAL TxDone : STD_LOGIC; + SIGNAL WrBuff : STD_LOGIC; + SIGNAL TxData : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL TxOverflow : STD_LOGIC; + SIGNAL TxUnderflow : STD_LOGIC; + SIGNAL ReadBuff : STD_LOGIC; + SIGNAL RxData : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL RxOverflow : STD_LOGIC; + SIGNAL HDLCen : STD_LOGIC; + + +BEGIN -- tdm_top_str + + rst_n <= NOT RST_I; + + + tdm_cont : tdm_cont_ent + PORT MAP ( + rst_n => rst_n, + C2 => C2, + DSTi => DSTi, + DSTo => DSTo, + F0_n => F0_n, + F0od_n => F0od_n, + CLK_I => CLK_I, + NoChannels => NoChannels, + DropChannels => DropChannels, + RxD => RxD, + RxValidData => RxValidData, + FramErr => RxLineOverflow, + RxRead => RxRead, + RxRdy => RxRdy, + TxErr => TxUnderflow, + TxD => TxD, + TxValidData => TxValidData, + TxWrite => TxWrite, + TxRdy => TxRdy, + EnableSerialIF => HDLCen, + Tx_en0 => Tx_en0, + Tx_en1 => Tx_en1, + Tx_en2 => Tx_en2, + Rx_en0 => Rx_en0, + Rx_en1 => Rx_en1, + Rx_en2 => Rx_en2, + SerDo => SerDo, + SerDi => SerDi); + + TxBuff : TxTDMBuff + PORT MAP ( + CLK_I => CLK_I, + rst_n => rst_n, + TxD => TxD, + TxValidData => TxValidData, + TxWrite => TxWrite, + TxRdy => TxRdy, + WrBuff => WrBuff, + TxData => TxData, + NoChannels => NoChannels, + DropChannels => DropChannels, + TxDone => TxDone, + TxOverflow => TxOverflow); + + RxBuff : RxTDMBuff + PORT MAP ( + CLK_I => CLK_I, + rst_n => rst_n, + RxD => RxD, + RxRead => RxRead, + RxRdy => RxRdy, + RxValidData => RxValidData, + BufferDataAvail => BufferDataAvail, + ReadBuff => ReadBuff, + RxData => RxData, + RxError => RxOverflow); + + + wb_if : tdm_wb_if_ent + PORT MAP ( + CLK_I => CLK_I, + RST_I => RST_I, + ACK_O => ACK_O, + ADR_I => ADR_I, + CYC_I => CYC_I, + DAT_I => DAT_I, + DAT_O => DAT_O, + RTY_O => RTY_O, + STB_I => STB_I, + WE_I => WE_I, + TAG0_O => TAG0_O, + TAG1_O => TAG1_O, + TxDone => TxDone, + WrBuff => WrBuff, + TxData => TxData, + TxOverflow => TxOverflow, + TxUnderflow => TxUnderflow, + RxRdy => BufferDataAvail, + ReadBuff => ReadBuff, + RxData => RxData, + RxOverflow => RxOverflow, + RxLineOverflow => RxLineOverflow, + HDLCen => HDLCen, + NoChannels => NoChannels, + DropChannels => DropChannels); + + +END tdm_top_str; Index: trunk/code/libs/components_pkg.vhd =================================================================== --- trunk/code/libs/components_pkg.vhd (revision 3) +++ trunk/code/libs/components_pkg.vhd (revision 4) @@ -6,7 +6,7 @@ -- Author : Jamil Khatib -- Organization: OpenCores.org -- Created : 2001/05/06 --- Last update:2001/05/06 +-- Last update:2001/05/22 -- Platform : -- Simulators : NC-sim/linux, Modelsim XE/windows98 -- Synthesizers: Leonardo @@ -32,7 +32,13 @@ -- Known Bugs : ------------------------------------------------------------------------------- -- $Log: not supported by cvs2svn $ +-- Revision 1.3 2001/05/24 22:46:33 jamil +-- TDM components added -- +-- Revision 1.2 2001/05/18 09:09:02 jamil +-- TDM components added +-- +-- ------------------------------------------------------------------------------- LIBRARY ieee; @@ -42,23 +48,139 @@ COMPONENT isdn_cont_ent PORT ( - rst_n : in std_logic; - C2 : in std_logic; - DSTi : in std_logic; - DSTo : out std_logic; - F0_n : in std_logic; - F0od_n : out std_logic; - HDLCen1 : out std_logic; - HDLCen2 : out std_logic; - HDLCen3 : out std_logic; - HDLCTxen1 : out std_logic; - HDLCTxen2 : out std_logic; - HDLCTxen3 : out std_logic; - Dout : out std_logic; - Din1 : in std_logic; - Din2 : in std_logic; - Din3 : in std_logic); + rst_n : IN STD_LOGIC; + C2 : IN STD_LOGIC; + DSTi : IN STD_LOGIC; + DSTo : OUT STD_LOGIC; + F0_n : IN STD_LOGIC; + F0od_n : OUT STD_LOGIC; + HDLCen1 : OUT STD_LOGIC; + HDLCen2 : OUT STD_LOGIC; + HDLCen3 : OUT STD_LOGIC; + HDLCTxen1 : OUT STD_LOGIC; + HDLCTxen2 : OUT STD_LOGIC; + HDLCTxen3 : OUT STD_LOGIC; + Dout : OUT STD_LOGIC; + Din1 : IN STD_LOGIC; + Din2 : IN STD_LOGIC; + Din3 : IN STD_LOGIC); END COMPONENT; - + + + COMPONENT tdm_cont_ent + PORT ( + rst_n : IN STD_LOGIC; + C2 : IN STD_LOGIC; + DSTi : IN STD_LOGIC; + DSTo : OUT STD_LOGIC; + F0_n : IN STD_LOGIC; + F0od_n : OUT STD_LOGIC; + CLK_I : IN STD_LOGIC; + NoChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + RxD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + RxValidData : OUT STD_LOGIC; + FramErr : OUT STD_LOGIC; + RxRead : IN STD_LOGIC; + RxRdy : OUT STD_LOGIC; + TxErr : OUT STD_LOGIC; + TxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + TxValidData : IN STD_LOGIC; + TxWrite : IN STD_LOGIC; + TxRdy : OUT STD_LOGIC; + EnableSerialIF : IN STD_LOGIC; + Tx_en0 : OUT STD_LOGIC; + Tx_en1 : OUT STD_LOGIC; + Tx_en2 : OUT STD_LOGIC; + Rx_en0 : OUT STD_LOGIC; + Rx_en1 : OUT STD_LOGIC; + Rx_en2 : OUT STD_LOGIC; + SerDo : OUT STD_LOGIC; + SerDi : IN STD_LOGIC); + END COMPONENT; + + + COMPONENT TxTDMBuff + PORT ( + CLK_I : IN STD_LOGIC; + rst_n : IN STD_LOGIC; + TxD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + TxValidData : OUT STD_LOGIC; + TxWrite : OUT STD_LOGIC; + TxRdy : IN STD_LOGIC; + WrBuff : IN STD_LOGIC; + TxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DropChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + NoChannels : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + TxDone : OUT STD_LOGIC; + TxOverflow : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT RxTDMBuff + PORT ( + CLK_I : IN STD_LOGIC; + rst_n : IN STD_LOGIC; + RxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RxRead : OUT STD_LOGIC; + RxRdy : IN STD_LOGIC; + RxValidData : IN STD_LOGIC; + BufferDataAvail : OUT STD_LOGIC; + ReadBuff : IN STD_LOGIC; + RxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + RxError : OUT STD_LOGIC); + END COMPONENT; + + + COMPONENT tdm_cont_top_ent + PORT ( + CLK_I : IN STD_LOGIC; + RST_I : IN STD_LOGIC; + ACK_O : OUT STD_LOGIC; + ADR_I : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + CYC_I : IN STD_LOGIC; + DAT_I : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + DAT_O : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + RTY_O : OUT STD_LOGIC; + STB_I : IN STD_LOGIC; + WE_I : IN STD_LOGIC; + TAG0_O : OUT STD_LOGIC; + TAG1_O : OUT STD_LOGIC; + C2 : IN STD_LOGIC; + DSTi : IN STD_LOGIC; + DSTo : OUT STD_LOGIC; + F0_n : IN STD_LOGIC; + F0od_n : OUT STD_LOGIC); + END COMPONENT; + + + COMPONENT tdm_wb_if_ent + PORT ( + CLK_I : IN STD_LOGIC; + RST_I : IN STD_LOGIC; + ACK_O : OUT STD_LOGIC; + ADR_I : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + CYC_I : IN STD_LOGIC; + DAT_I : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + DAT_O : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + RTY_O : OUT STD_LOGIC; + STB_I : IN STD_LOGIC; + WE_I : IN STD_LOGIC; + TAG0_O : OUT STD_LOGIC; + TAG1_O : OUT STD_LOGIC; + TxDone : IN STD_LOGIC; + WrBuff : OUT STD_LOGIC; + TxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + TxOverflow : IN STD_LOGIC; + TxUnderflow : IN STD_LOGIC; + RxRdy : IN STD_LOGIC; + ReadBuff : OUT STD_LOGIC; + RxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + RxOverflow : IN STD_LOGIC; + RxLineOverflow : IN STD_LOGIC; + HDLCen : OUT STD_LOGIC; + NoChannels : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + DropChannels : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); + END COMPONENT; + END components_pkg;