Subversion Repositories tlc2

tlc2/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: tlc2/web_uploads =================================================================== --- tlc2/web_uploads (nonexistent) +++ tlc2/web_uploads (revision 4)

tlc2/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: tlc2/branches =================================================================== --- tlc2/branches (nonexistent) +++ tlc2/branches (revision 4)

tlc2/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: tlc2/tags/vers/wave.do =================================================================== --- tlc2/tags/vers/wave.do (nonexistent) +++ tlc2/tags/vers/wave.do (revision 4) @@ -0,0 +1,42 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tlc_tb/uut/clk +add wave -noupdate -format Logic /tlc_tb/uut/rst +add wave -noupdate -format Logic /tlc_tb/uut/j_left +add wave -noupdate -format Logic /tlc_tb/uut/j_right +add wave -noupdate -format Literal /tlc_tb/uut/led +add wave -noupdate -format Literal /tlc_tb/uut/pr_state +add wave -noupdate -format Literal /tlc_tb/uut/nxt_state +add wave -noupdate -format Logic /tlc_tb/uut/pr_state_mode +add wave -noupdate -format Logic /tlc_tb/uut/nxt_state_mode +add wave -noupdate -format Literal /tlc_tb/uut/led_int +add wave -noupdate -format Logic /tlc_tb/uut/one_sec +add wave -noupdate -format Logic /tlc_tb/uut/go +add wave -noupdate -format Logic /tlc_tb/uut/mode +add wave -noupdate -format Logic /tlc_tb/uut/green_period +add wave -noupdate -format Logic /tlc_tb/uut/orange_period +add wave -noupdate -format Logic /tlc_tb/uut/red_period +add wave -noupdate -format Logic /tlc_tb/uut/red_orange_period +add wave -noupdate -format Logic /tlc_tb/uut/stb_period +add wave -noupdate -format Logic /tlc_tb/uut/rst_int +add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp0 +add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp1 +add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp2 +add wave -noupdate -format Literal /tlc_tb/uut/time_p/temp3 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2053550 ns} 1} +configure wave -namecolwidth 208 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {2202166 ns} {2234934 ns} Index: tlc2/tags/vers/modelsim.ini =================================================================== --- tlc2/tags/vers/modelsim.ini (nonexistent) +++ tlc2/tags/vers/modelsim.ini (revision 4) @@ -0,0 +1,1058 @@ +; Copyright 1991-2007 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release + +work = modelsim/work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile=1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VcomZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VcomZeroInOptions = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageNoSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VHDL generate blocks. Default is on. +CoverGenerate = 1 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +vlog95compat = 0 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal to or more than 1M are +; marked as sparse) +SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VlogZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VlogZeroInOptions = "" + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VoptZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VoptZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VLOG generate blocks. Default is on. +CoverGenerate = 1 + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is on. +CoverCells = 0 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; Allow VHDL FF recognition. This may make major reductions in +; coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Allow VHDL subprogram inlining. Change Verilog gates to +; continuous assignments. +CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobeDefault". +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupPerInstanceDefault". +; SVCovergroupPerInstanceDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vsim] + +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Enables certain code coverage exclusions automatically. Set AutoExclusions = none to disable. +AutoExclusions = fsm + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use MessageFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use MessageFormatBreak; +; - otherwise, use MessageFormat. +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; Info and Warning are disabled by default +; IgnoreSVAInfo = 0 +; IgnoreSVAWarning = 0 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI out-of-the-blue call. +; Out-of-the-blue call refers to a SystemVerilog export function call +; directly from a C function that don't have the proper context setup +; as done in DPI-C import C functions. When this is enabled, one can +; call a DPI export function (but not task) from any C code. +; The default is 0 (disabled). +; DpiOutOfTheBlue = 1 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + + +; Should the tool conform to the 2001 or 2005 VPI object model +; Note that System Verilog objects are only available in the 2005 object model +; The tool default is the latest available LRM behavior +; Options here are: 2001 2005 latest +; PliCompatDefault = 2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading. +; This is necessary when C++ files have been compiled with aCC's -AA option. +; The default behavior is to use /usr/lib/libCsup.sl. +; UseCsupV2 = 1 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. +; For SVA, Default is on when the assertion has a pass action block or vsim switch -assertdebug is used and the visibility flag "+acc=a" is turned on in vopt. +; For PSL, Default is on only when vsim switch "-assertdebug" is used and the visibility flag "+acc=a" is turned on in vopt. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to not include them. +; ToggleVlogIntegers = 1 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off. +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enable or disable generation of more detailed information about the sampling of covergroup, +; cross, and coverpoints. It provides the details of the number of times the covergroup +; instance and type were sampled, as well as details about why covergroup, cross and +; coverpoint were not covered. A non-zero value is to enable this feature. 0 is to +; disable this feature. Default is 0; +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VsimZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VsimZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the algorithm used to +; discover conflicts between constraints for randomize() failures. +; The default is "many". +; +; Valid schemes are: +; "many" = best for determining conflicts due to many related constraints +; "few" = best for determining conflicts due to few related constraints +; +; SolveFailDebugScheme = many + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum number of constraint subsets that will be tested for +; conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value +; specifies the maximum size of constraint subsets that will be tested for +; conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the complexity of +; the constraint scenario (both in memory and time spent during evaluation) +; exceeds the specified limit. This value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; n = disable bit interleaving for all constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both + +; Control transcripting of Verilog display system task messages. +; These system tasks include $display[bho], $strobe[bho], +; Smonitor{bho], and $write[bho]. They also include the analogous +; file I/O tasks that write to STDOUT (i.e. $fwrite or $fdisplay). +; The default is to have messages appear only in the transcript. +; The other settings are to send messages to the wlf file only +; (messages that are recorded in the wlf file can be viewed in the +; MsgViewer) or to both the transcript and the wlf file. The valid +; values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + Index: tlc2/tags/vers/src/tlc2.ucf =================================================================== --- tlc2/tags/vers/src/tlc2.ucf (nonexistent) +++ tlc2/tags/vers/src/tlc2.ucf (revision 4) @@ -0,0 +1,34 @@ +#NET "led(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +#NET "led(1)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +#NET "led(2)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +#NET "led(3)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) +#NET "j_up" LOC = "AD4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick up low active +#NET "j_down" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low active +NET "j_left" LOC = "AE4" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick left low active +NET "j_right" LOC = "AC6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick right low active +NET "rst" LOC = "AA7" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick push low active + +#NET "turn_on" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) #dip switch low active +#NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + +#NET "out_vector(0)" LOC = "A6" | IOSTANDARD = LVCMOS33; #led(0) +NET "led(0)" LOC = "D7" | IOSTANDARD = LVCMOS33; #led(1) +NET "led(1)" LOC = "F23" | IOSTANDARD = LVCMOS33; #led(2) +NET "led(2)" LOC = "F24" | IOSTANDARD = LVCMOS33; #led(3) +#NET "out_vector(4)" LOC = "G21" | IOSTANDARD = LVCMOS33; #led(4) +#NET "out_vector(5)" LOC = "G23" | IOSTANDARD = LVCMOS33; #led(5) +#NET "out_vector(6)" LOC = "H23" | IOSTANDARD = LVCMOS33; #led(6) +#NET "out_vector(7)" LOC = "J21" | IOSTANDARD = LVCMOS33; #led(7) + +#NET "in_vector(0)" LOC = "AA20" | IOSTANDARD = LVCMOS25; #dip_sw(0) dip switches are low-active +#NET "in_vector(1)" LOC = "AD15" | IOSTANDARD = LVCMOS25; #dip_sw(1) +#NET "in_vector(2)" LOC = "AD19" | IOSTANDARD = LVCMOS25; #dip_sw(2) +#NET "in_vector(3)" LOC = "AD23" | IOSTANDARD = LVCMOS25; #dip_sw(3) +#NET "in_vector(4)" LOC = "AF21" | IOSTANDARD = LVCMOS25; #dip_sw(4) +#NET "in_vector(5)" LOC = "AF22" | IOSTANDARD = LVCMOS25; #dip_sw(5) +#NET "in_vector(6)" LOC = "W15" | IOSTANDARD = LVCMOS25; #dip_sw(6) +#NET "in_vector(7)" LOC = "W16" | IOSTANDARD = LVCMOS25; #dip_sw(7) + +#NET "enable" LOC = "AD6" | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; #joystick down low-active +NET "clk" LOC = "B13" | IOSTANDARD = LVCMOS33; #clk + Index: tlc2/tags/vers/src/tlc2.vhd =================================================================== --- tlc2/tags/vers/src/tlc2.vhd (nonexistent) +++ tlc2/tags/vers/src/tlc2.vhd (revision 4) @@ -0,0 +1,219 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tlc2 is + generic( freq : integer := 1e8; -- 100 MHz, use 100 Hz (1e2) for simulation and run 5 ms + max_period_factor : INTEGER := 45; --the period of the longest signal (green) + idle_period_factor : integer := 1; -- 1 sec blinking interval + green_period_factor : integer := 45; -- 45 sec green interval + orange_period_factor : integer := 5; -- 5 sec orange interval + red_period_factor : integer := 30; -- 30 sec red interval + red_orange_period_factor : integer := 5); -- 5 sec red_orange interval + port( clk, rst : in std_logic; -- low - active reset + j_left, j_right : IN std_logic; -- j_right turns normal mode, j_left turns test mode, both signals are low active + led : out std_logic_vector (2 downto 0) ); -- {RED|ORANGE|GREEN}, RED is MSB +end tlc2; + +architecture behavioral of tlc2 is + type state is (idle0, idle1, green, orange, red, red_orange, rst_before_idle1, rst_before_idle0, rst_before_green, rst_before_orange, rst_before_red, rst_before_red_orange); + signal pr_state, nxt_state : state; + signal pr_state_mode, nxt_state_mode : std_logic :='0'; -- state signals for the joystick encoder + signal led_int : std_logic_vector (2 downto 0); -- internal led signal used to invert the output if neccessary + SIGNAL one_sec : std_logic := '0'; -- signal with 1s period used as time basis + SIGNAL mode : std_logic := '0'; -- changes between test end normal mode, triggered by the joystick decoder + SIGNAL rst_int : STD_LOGIC := '1'; --used to reset the period-signals after state transition + SIGNAL counter : INTEGER RANGE 0 TO max_period_factor := 0; + constant one_sec_factor : integer := freq-1; +begin + +------------------------------------------------------------------------------- +-- Simple FSM for the joystick encoder. Generats the mode - signal. +------------------------------------------------------------------------------- +mode_s_p: process(clk) +begin + if clk'event and clk='1' then + IF rst='0' THEN + pr_state_mode <= '0'; + else + pr_state_mode <= nxt_state_mode; + END if; + end if; +end process; + +mode_c_p: process(pr_state_mode,j_right,j_left) +begin + CASE pr_state_mode IS + WHEN '0' => IF j_right='0' and j_left='1' THEN + nxt_state_mode <= '1'; + ELSE + nxt_state_mode <= '0'; + END if; + mode <= '0'; + WHEN OTHERS => IF j_left='0' THEN + nxt_state_mode <= '0'; + ELSE + nxt_state_mode <= '1'; + END if; + mode <= '1'; + END CASE; +END process; + +------------------------------------------------------------------------------- +-- period-signal generator +------------------------------------------------------------------------------- +time_p: process(clk) + variable temp0 : integer RANGE 0 TO max_period_factor; + VARIABLE flag : STD_LOGIC := '0'; +BEGIN + IF clk'EVENT AND clk='1' THEN + IF rst_int='0' THEN -- a 0 level signal is needed by the current state of the main fsm + temp0 := 0; + else + IF one_sec='0' THEN + flag := '0'; + END IF; + IF one_sec='1' AND flag='0' THEN --this part is executed only on a +--positive transition of the one_sec signal. The counter factors multiply the +--period of the one_sec signal. If you need to speed up the execution change +--the on_sec_factor to a lower value. This us usefull for simulation purposes + flag := '1'; + IF + temp0=max_period_factor THEN + temp0 := 0; + ELSE + temp0 := temp0 + 1; + end if; + END if; + END if; + END if; + counter <= temp0; +END process; + +------------------------------------------------------------------------------- +-- 1 sec time basis signal generator. Generate a signal with 2 sec period. +------------------------------------------------------------------------------- +one_sec_p: process(clk) + VARIABLE temp : integer RANGE 0 TO one_sec_factor; +begin + IF clk'event AND clk='1' THEN + IF rst_int='0' THEN + temp := 0; + one_sec <= '0'; + else + iF temp>=one_sec_factor THEN + temp := 0; + one_sec <= '1'; + else + temp := temp + 1; + one_sec <= '0'; + END if; + END if; + END IF; +END process; + +------------------------------------------------------------------------------- +-- main FSM +------------------------------------------------------------------------------- +main_s_p: process(clk) + begin + if clk'event and clk='1' then + IF rst='0' THEN + pr_state <= idle0; + else + pr_state <= nxt_state; + end if; + END if; + end process; + +main_c_p: process(pr_state,mode,counter) +begin + case pr_state is + WHEN idle0 => IF mode='0' then + IF counter>=idle_period_factor THEN + nxt_state <= rst_before_idle1; + ELSE + nxt_state <= idle0; + END IF; + ELSE + nxt_state <= rst_before_green; + END if; + led_int <= "010"; + rst_int <= '1'; + when idle1 => if mode='0' then + IF counter>=idle_period_factor THEN + nxt_state <= rst_before_idle0; + ELSE + nxt_state <= idle1; + END IF; + ELSE + nxt_state <= rst_before_green; + END if; + led_int <= "000"; + rst_int <= '1'; + when green => if mode='1' then + if counter>=green_period_factor THEN + nxt_state <= rst_before_orange; + ELSE + nxt_state <= green; + END if; + ELSE + nxt_state <= rst_before_idle0; + end if; + led_int <= "001"; + rst_int <= '1'; + WHEN orange => if mode='1'then + if counter>=orange_period_factor THEN + nxt_state <= rst_before_red; + ELSE + nxt_state <= orange; + END if; + ELSE + nxt_state <= rst_before_idle0; + END if; + led_int <= "010"; + rst_int <= '1'; + WHEN red => if mode='1' THEN + if counter>=red_period_factor THEN + nxt_state <= rst_before_red_orange; + ELSE + nxt_state <= red; + END if; + ELSE + nxt_state <= rst_before_idle0; + END if; + led_int <= "100"; + rst_int <= '1'; + WHEN red_orange => if mode='1' THEN + if counter>=red_orange_period_factor THEN + nxt_state <= rst_before_green; + ELSE + nxt_state <= red_orange; + END if; + ELSE + nxt_state <= rst_before_idle0; + END if; + led_int <= "110"; + rst_int <= '1'; + WHEN rst_before_idle1 => nxt_state <= idle1; + led_int <= "000"; + rst_int <= '0'; + WHEN rst_before_green => nxt_state <= green; + led_int <= "001"; + rst_int <= '0'; + WHEN rst_before_orange => nxt_state <= orange; + led_int <= "010"; + rst_int <= '0'; + WHEN rst_before_red => nxt_state <= red; + led_int <= "100"; + rst_int <= '0'; + WHEN rst_before_red_orange => nxt_state <= red_orange; + led_int <= "110"; + rst_int <= '0'; + WHEN OTHERS => nxt_state <= idle0; + led_int <= "010"; + rst_int <= '0'; + END case; + END process; + led <= led_int; +END behavioral; Index: tlc2/tags/vers/src/tlc2.do =================================================================== --- tlc2/tags/vers/src/tlc2.do (nonexistent) +++ tlc2/tags/vers/src/tlc2.do (revision 4) @@ -0,0 +1,3 @@ +add wave * +run 1000 ns +restart -nowave Index: tlc2/tags/vers/src/tlc2_tb.vhd =================================================================== --- tlc2/tags/vers/src/tlc2_tb.vhd (nonexistent) +++ tlc2/tags/vers/src/tlc2_tb.vhd (revision 4) @@ -0,0 +1,100 @@ + +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:44:54 03/26/2008 +-- Design Name: counter +-- Module Name: counter_tb.vhd +-- Project Name: clk_tb +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: counter +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY tlc2_tb IS +END tlc2_tb; + +ARCHITECTURE behavior OF tlc2_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT tlc2 + PORT( + clk : IN std_logic; + rst, j_left, j_right : IN std_logic; + led : OUT std_logic_vector(2 downto 0) ); + END COMPONENT; + + --Inputs + SIGNAL clk : std_logic := '0'; + SIGNAL rst : std_logic := '0'; + SIGNAL j_right : std_logic := '1'; + SIGNAL j_left : std_logic := '1'; + + --Outputs + SIGNAL led : std_logic_vector(2 downto 0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: tlc2 PORT MAP( + clk => clk, + rst => rst, j_left => j_left, j_right => j_right, + led => led + ); + + tb_clk : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + --wait for 100 ns; + + clk <= not clk; + wait for 5 ns; + -- Place stimulus here + END PROCESS; + + tb_s: PROCESS + BEGIN + wait for 15 ns; + rst <= '0'; + wait for 25 ns; + rst <= '1'; + wait for 15 ns; + j_left <= '0'; + wait for 30 ns; + j_left <= '1'; + wait for 13000 ns; + j_right <= '0'; + wait for 100 ns; + j_right <= '1'; + -- wait for 1000 ns; + -- j_left <= '0'; + -- wait for 100 ns ; + -- j_left <= '1'; + -- wait for 1500 ns; + -- j_right <= '0'; + -- wait for 50 ns; + --- j_right <= '1'; + wait; + + END PROCESS; +END; Index: tlc2/tags/vers/src/tlc2.ut =================================================================== --- tlc2/tags/vers/src/tlc2.ut (nonexistent) +++ tlc2/tags/vers/src/tlc2.ut (revision 4) @@ -0,0 +1,30 @@ + +-g DebugBitstream:No +-g Binary:no +-b +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFF0001 +-g DCMShutDown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:NoWait +-g Security:None +-g Persist:No +-g ReadBack +-g DonePipe:No +-g DriveDone:No Index: tlc2/tags/vers/bin/route_ngc =================================================================== --- tlc2/tags/vers/bin/route_ngc (nonexistent) +++ tlc2/tags/vers/bin/route_ngc (revision 4) @@ -0,0 +1,15 @@ +#!/bin/sh +# route entity ucf-file device effort bitgen +#ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6 +rm -f $1.ngd +echo ngdbuild $1.ngc -aul -uc $2 -p $3# -sd $6/xst -sd $6 +ngdbuild $1.ngc -aul -uc $2 -p $3 #-sd $6/xst -sd $6 +#ngdbuild $1.ngc -aul -uc $2 -p $3 +echo map -pr b -p $3 $1 +map -pr b -p $3 $1 +echo par -ol $4 -w $1 $1.ncd +par -ol $4 -w $1 $1.ncd +echo trce -v 25 $1.ncd $1.pcf +trce -v 25 $1.ncd $1.pcf +echo bitgen $1 -l -m -w -d -f $5 +bitgen $1 -l -m -w -d -f $5

tlc2/tags/vers/bin/route_ngc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tlc2/tags/vers/bin/load_modules =================================================================== --- tlc2/tags/vers/bin/load_modules (nonexistent) +++ tlc2/tags/vers/bin/load_modules (revision 4) @@ -0,0 +1,4 @@ +module load mentor/modelsim/6.3d-64 +module load xilinx/ise-9.2i-64 + + Index: tlc2/tags/vers/bin/vscript =================================================================== --- tlc2/tags/vers/bin/vscript (nonexistent) +++ tlc2/tags/vers/bin/vscript (revision 4) @@ -0,0 +1 @@ +echo vcom $1

tlc2/tags/vers/bin/vscript Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tlc2/tags/vers/bin/xstvhdl =================================================================== --- tlc2/tags/vers/bin/xstvhdl (nonexistent) +++ tlc2/tags/vers/bin/xstvhdl (revision 4) @@ -0,0 +1 @@ +echo vhdl work $1 \ No newline at end of file

tlc2/tags/vers/bin/xstvhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tlc2/tags/vers/modelsim/work/_opt/voptdzqxgz =================================================================== --- tlc2/tags/vers/modelsim/work/_opt/voptdzqxgz (nonexistent) +++ tlc2/tags/vers/modelsim/work/_opt/voptdzqxgz (revision 4) @@ -0,0 +1,73 @@ +m255 +K3 +Z0 cModel Technology Builtin Library +13 +Z1 dD:\qa\buildsites\6.3d\builds\win32\modeltech +Penv +Z2 OL;C;6.3d;37 +32 +b1 +Z3 OP;C;6.3d;37 +Z4 w1196138599 +Z5 d$MODEL_TECH/.. +Z6 8vhdl_src/std/env.vhd +Z7 Fvhdl_src/std/env.vhd +l0 +L1 +VMSh;Gmh>9BN
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Use source bin/load_modules if modules are not loaded " + @echo " make files : prints info about the used files " + @echo " make vsim-help : prints appropriate steps for simulation" + @echo " make warnings-xst : prints warnings and info from the XST log file" + @echo " make warnings-implement : prints warnings and info from the PAR log file" + @echo " make clear : clears all XST output files" + @echo + +use-xst: $(VHDLSYNFILES) + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + @for i in $(VHDLSYNFILES); do bin/xstvhdl $$i >> $(PROJECTFILE); done + @echo run -ifn $(PROJECTFILE) -ifmt vhdl -ofn $(TOP).ngc -ofmt NGC -p $(DEVICE) -opt_mode $(OPTMODE) -opt_level $(OPTLEVEL) -top $(TOP) -rtlview yes > $(SCRIPTFILE) + @xst -ifn $(SCRIPTFILE) -ofn $(LOGFILE) + +implement: $(TOP).ngc + @mv -f src/*.ucf $(UCF)TMP + @mv -f $(UCF)TMP $(UCF) + @mv -f src/*.ut $(BITGEN)TMP + @mv -f $(BITGEN)TMP $(BITGEN) + bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN) + +ml: + @/home/4all/packages/modules-2.0/sun5/bin/modulecmd tcsh list + +use-vsim: it $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run -all > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) + vsim -c work.$(TOPSIM) -do $(DOFILE) + +use-vsim-gui: $(ALLFILES) + @rm -f it + @for i in $(ALLFILES); do bin/vscript $$i >> it0; done + @echo restart > it1 + @echo run 1000 ns > it2 + @cat it0 it1 it2 > it + @rm -f it0 it1 it2 + @vmap -del work + @rm -rf modelsim/ + @mkdir modelsim + @vlib modelsim/work + @vmap work modelsim/work + @vcom -93 -check_synthesis -work work $(VHDLSYNFILES) + @vcom -93 -work work src/$(TOPSIM).vhd + @mv -f src/*.do $(DOFILE)TMP + @mv -f $(DOFILE)TMP $(DOFILE) +# vsim -gui work.$(TOPSIM) -do $(DOFILE) & + vsim -gui work.$(TOPSIM) -do it & + +clear: + @rm -f $(TOP).ngr $(TOP).msd $(TOP).msk $(TOP).rbt $(TOP).twr $(TOP).xpi $(TOP)_pad.csv $(TOP)_pad.txt $(TOP).bld + @rm -f $(TOP).ngc $(TOP).ncd $(TOP).ngd $(TOP).rba $(TOP).rbd $(TOP).rbb netlist.lst $(TOP).mrp $(TOP).ll $(TOP).bit + @rm -f $(TOP).lso $(TOP).ngm $(TOP).ngr $(TOP).pad $(TOP).par $(TOP).pcf transcript vsim.wlf $(TOP).log $(TOP).bgn *.twr *.xml *.map *.unroutes + @rm -f $(SCRIPTFILE) + @rm -f $(LOGFILE) + @rm -f $(PROJECTFILE) + +files: + @echo + @echo $(TOP)".ngc : netlist output from XST" + @echo $(TOP)".ngr : netlist output from XST for RTL and Technology viewers" + @echo $(TOP)".scr : script file for XST, generated by Makefile" + @echo $(TOP)".prj : contains the vhdl source files, generated by Makefile." + @echo $(TOP)".log : log file, output from XST" + @echo $(TOP)".ucf : user constraints file with pins description, write yourself" + @echo $(TOP)".ut : config. script for BITGEN, write yourself" + @echo "it : do-script for Modelsim in batchmode, write yourself" + @echo $(TOP)".do : do-script for Modelsim in GUI-mode, write yourself" + @echo $(TOP)".par : PAR report file, generated by make implement" + @echo + +vsim-help: + @echo + @echo " mkdir modelsim : create main directoriy for simulation" + @echo " vlib modelsim/work : create work library for simulation" + @echo " vmap : prints all logical mapped librarys" + @echo " vmap -del work : delete actual mapping for work library" + @echo " vmap work modelsim/work : map logical library work to modelsim/work" + @echo " vcom -93 -check_synthesis -work work : compile source vhdl files" + @echo " vcom -93 -work work : compile top level testbench" + @echo " do it : use in batch mode to recompile the testbench and the top entity and to restart the simulation" + @echo + +warnings-xst: + @grep -n -i warning *.log + @grep -n -i info *.log + +warnings-implement: + @grep -n -i warning *.par *.twr + @grep -n -i info *.par *.twr Index: tlc2/tags/vers/xst/work/hdpdeps.ref =================================================================== --- tlc2/tags/vers/xst/work/hdpdeps.ref (nonexistent) +++ tlc2/tags/vers/xst/work/hdpdeps.ref (revision 4) @@ -0,0 +1,33 @@ +V3 16 +FL /export/jack/dimo/vhdl/tlc/src/tlc.vhd 2008/05/13.14:36:57 J.40 +FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd 2008/06/17.17:42:45 J.40 +EN work/tlc2 1213717396 FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/tlc2/behavioral 1213717397 \ + FL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd EN work/tlc2 1213717396 +FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd 2008/05/09.12:27:02 J.40 +EN work/FSM_COUNTER 1210328828 \ + FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/FSM_COUNTER/BEHAVIORAL 1210328829 \ + FL /home/students/dimo/vhdl/Book/fsm_counter/src/fsm_counter.vhd \ + EN work/FSM_COUNTER 1210328828 +FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd 2008/05/09.13:20:51 J.40 +EN work/FSM_DETECTOR 1210332468 \ + FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/FSM_DETECTOR/BEHAVIORAL 1210332469 \ + FL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd \ + EN work/FSM_DETECTOR 1210332468 +FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd 2008/05/08.11:45:00 J.40 +EN work/GENERIC_DELAY 1210239907 \ + FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd \ + PB ieee/std_logic_1164 1106404628 PH ieee/NUMERIC_STD 1106404639 +AR work/GENERIC_DELAY/BEHAVIORAL 1210239908 \ + FL /home/students/dimo/vhdl/Book/generic_delay/src/generic_delay.vhd \ + EN work/GENERIC_DELAY 1210239907 +FL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd 2008/05/07.11:24:01 J.40 +PH work/ARRAY_TYPES 1210154389 \ + FL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd \ + PB ieee/std_logic_1164 1106404628 +FL /home/students/dimo/vhdl/Book/tlc/src/tlc.vhd 2008/05/09.17:02:45 J.40 Index: tlc2/tags/vers/xst/work/hdllib.ref =================================================================== --- tlc2/tags/vers/xst/work/hdllib.ref (nonexistent) +++ tlc2/tags/vers/xst/work/hdllib.ref (revision 4) @@ -0,0 +1,14 @@ +PH array_types NULL /home/students/dimo/vhdl/Book/generic_ram/src/array_types.vhd sub00/vhpl01 1210154389 +EN fsm_detector NULL /home/students/dimo/vhdl/Book/fsm_detector/src/fsm_detector.vhd sub00/vhpl08 1210332468 +AR generic_ram behavioral /home/students/dimo/vhdl/Book/generic_ram/src/generic_ram.vhd sub00/vhpl03 1210156112 +EN tlc NULL /export/jack/dimo/vhdl/tlc2/src/tlc2.vhd sub00/vhpl10 1210751748 +AR tlc2 behavioral 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tlc2/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##