URL
https://opencores.org/ocsvn/versatile_io/versatile_io/trunk
Subversion Repositories versatile_io
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/versatile_io/trunk/rtl/verilog/top/versatile_io_top.v
8,7 → 8,7
input [3:0] wbs_sel_i, |
input wbs_we_i, wbs_stb_i, wbs_cyc_i, |
output [31:0] wbs_dat_o, |
output wbs_ack_o; |
output wbs_ack_o, |
`ifdef B4 |
output wbs_stall_o, |
`endif |
20,11 → 20,17
input clk, rst |
); |
|
`ifdef UART0 |
parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI; |
parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO; |
parameter [31:0] uart0_base_adr = `UART0_BASE_ADR; |
`endif |
function [7:0] tobyte; |
input [3:0] sel_i; |
input [31:0] dat_i; |
begin |
tobyte = ({8{sel_i[3]}} & dat_i[31:24]) | ({8{sel_i[2]}} & dat_i[23:16]) | ({8{sel_i[1]}} & dat_i[15:8]) | ({8{sel_i[0]}} & dat_i[7:0]); |
end |
endfunction |
|
function [31:0] toword; |
31,6 → 37,7
input [7:0] dat_i; |
begin |
toword = {4{dat_i}}; |
end |
endfunction |
|
function [31:0] mask; |
39,22 → 46,15
begin |
mask = {32{sel}} & dat_i; |
end |
|
function cs; |
input [31:0] adr; |
input [31:0] mem_map; |
input [4:0] mem_map_hi; |
input [4:0] mem_map_lo; |
begin |
cs = adr[mem_map_hi:mem_map_lo] == mem_map[mem_map_hi:mem_map_lo]; |
endfunction |
|
`ifdef UART0 |
wire uart0_cs = cs( wbs_adr_i, `UART0_BASE, `UART0_MEM_MAP_HI, `UART0_MEM_MAP_LO); |
wire uart0_cs; |
assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo]; |
wire [7:0] uart0_temp; |
wire uart0_ack_o; |
uart_top uart0 ( |
.wb_clk_i(wbs_clk), wb_rst_i(wbs_rst), |
.wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst), |
// Wishbone signals |
.wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0), |
.int_o(uart0_irq), // interrupt request |
/versatile_io/trunk/rtl/verilog/include/versatile_io_defines.v
2,7 → 2,7
//=comment <b>Versatile IO</b> |
//=tab UART |
`define UART0 |
`define UART0_BASE 32'h92000000 |
`define UART0_BASE_ADR 32'h92000000 |
`define UART0_MEM_MAP_HI 31 |
`define UART0_MEM_MAP_LO 24 |
//=comment |
/versatile_io/trunk/Makefile
7,7 → 7,7
ip: |
make -C rtl/verilog ip |
|
all: config ip |
all: export config ip |
|
clean: |
make -C rtl/verilog clean |