URL
https://opencores.org/ocsvn/waveform_gen/waveform_gen/trunk
Subversion Repositories waveform_gen
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/docs/waveform_gen.pdf
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svn:mime-type = application/octet-stream
/trunk/vhdl/waveform_gen.vhd
10,7 → 10,7
-- Senior Design Consultant -- |
-- www.zipcores.com -- |
-- -- |
-- Date last modified : 23.10.2008 -- |
-- Date last modified : 24.10.2008 -- |
-- -- |
-- Description : NCO / Periodic Waveform Generator -- |
-- -- |
30,6 → 30,9
clk : in std_logic; |
reset : in std_logic; |
|
-- clock-enable |
en : in std_logic; |
|
-- NCO frequency control |
phase_inc : in std_logic_vector(31 downto 0); |
|
50,6 → 53,7
port ( |
|
clk : in std_logic; |
en : in std_logic; |
addr : in std_logic_vector(11 downto 0); |
sin_out : out std_logic_vector(11 downto 0); |
cos_out : out std_logic_vector(11 downto 0)); |
77,7 → 81,9
if reset = '0' then |
phase_acc <= (others => '0'); |
elsif clk'event and clk = '1' then |
phase_acc <= unsigned(phase_acc) + unsigned(phase_inc); |
if en = '1' then |
phase_acc <= unsigned(phase_acc) + unsigned(phase_inc); |
end if; |
end if; |
end process phase_acc_reg; |
|
99,6 → 105,7
port map ( |
|
clk => clk, |
en => en, |
addr => lut_addr, |
sin_out => sin_out, |
cos_out => cos_out ); |
110,7 → 117,9
delay_regs: process(clk) |
begin |
if clk'event and clk = '1' then |
lut_addr_reg <= lut_addr; |
if en = '1' then |
lut_addr_reg <= lut_addr; |
end if; |
end if; |
end process delay_regs; |
|
/trunk/vhdl/sincos_lut.vhd
10,7 → 10,7
-- Senior Design Consultant -- |
-- www.zipcores.com -- |
-- -- |
-- Date last modified : 26.05.2008 -- |
-- Date last modified : 24.10.2008 -- |
-- -- |
-- Description : 4096 x 12-bit SIN/COS Look-up table -- |
-- -- |
27,6 → 27,7
port ( |
|
clk : in std_logic; |
en : in std_logic; |
addr : in std_logic_vector(11 downto 0); |
sin_out : out std_logic_vector(11 downto 0); |
cos_out : out std_logic_vector(11 downto 0) |
1082,8 → 1083,10
rom_select: process (clk) |
begin |
if clk'event and clk = '1' then |
sin_out <= SIN_ROM(conv_integer(addr)); |
cos_out <= COS_ROM(conv_integer(addr)); |
if en = '1' then |
sin_out <= SIN_ROM(conv_integer(addr)); |
cos_out <= COS_ROM(conv_integer(addr)); |
end if; |
end if; |
end process rom_select; |
|
/trunk/vhdl/waveform_gen_bench.vhd
10,7 → 10,7
-- Senior Design Consultant -- |
-- www.zipcores.com -- |
-- -- |
-- Date last modified : 23.10.2008 -- |
-- Date last modified : 24.10.2008 -- |
-- -- |
-- Description : NCO / Periodic Waveform Generator TB -- |
-- -- |
41,6 → 41,9
clk : in std_logic; |
reset : in std_logic; |
|
-- clock-enable |
en : in std_logic; |
|
-- NCO frequency control |
phase_inc : in std_logic_vector(31 downto 0); |
|
56,8 → 59,9
signal clk : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal capture : std_logic := '0'; |
signal en : std_logic := '1'; |
|
signal phase_inc : std_logic_vector(31 downto 0); |
signal phase_inc : std_logic_vector(31 downto 0) := (others => '0'); |
|
signal sin_out : std_logic_vector(11 downto 0); |
signal cos_out : std_logic_vector(11 downto 0); |
94,7 → 98,7
wait for 1 us; |
wait until clk'event and clk = '1'; |
capture <= '1'; |
|
|
-- run sim for a while |
wait for 100 us; |
wait until clk'event and clk = '1'; |
111,6 → 115,9
clk => clk, |
reset => reset, |
|
-- clock-enable |
en => en, |
|
-- NCO frequency control |
phase_inc => phase_inc, |
|