OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

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  • This comparison shows the changes necessary to convert path 
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    from Rev 30 to Rev 31
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  •

Rev 30 → Rev 31

/oms8051mini/trunk/verif/run/run_irun
13,7 → 13,7
set all_testsx = 0;
 
set misc_tests=(uart_test_1 spi_test_1 i2cm_test_1)
set risc_int_tests=(fib divmul sort gcd cast xram)
set risc_int_tests=(fib divmul sort gcd cast xram i2cm_burst_wrrd)
 
 
echo " Compiling with cadence tools - irun "
/oms8051mini/trunk/verif/run/run_modelsim
11,7 → 11,7
set misc_tests=(uart_test_1 spi_test_1)
#set misc_tests=( )
 
set risc_int_tests=(fib divmul sort gcd cast xram )
set risc_int_tests=(fib divmul sort gcd cast xram i2cm_burst_wrrd)
#set risc_int_tests=(fib divmul sort gcd cast xram all_instr)
 
echo " Compiling with MODELSIM "
/oms8051mini/trunk/verif/sw/C/i2cm_burst_wrrd.c
0,0 → 1,112
/*
* I2C Master Burst Write and Read Test
*
* I2C Master Write to Slave Chip with Id: 0x20
*
* Burst 4 Byte Write to address starting from 0x66 with 0x12, 0x34, 0x56 and 0x78
* Read Back in Burst mode and verify the expected data
*/
 
/*---------------------------------------------------------------------------*/
 
#include <8051.h>
 
char cErrCnt;
/*---------------------------------------------------------------------------*/
 
__xdata __at (0xA000) unsigned char i2c_prescale_low;
__xdata __at (0xA001) unsigned char i2c_prescale_high;
__xdata __at (0xA002) unsigned char i2c_control;
volatile __xdata __at (0xA003) unsigned char i2c_data;
volatile __xdata __at (0xA004) unsigned char i2c_cmd;
 
void main() {
int ErrCnt = 0;
 
//Wrire Prescale registers
i2c_prescale_low = 0xC7;
i2c_prescale_high = 0x00;
 
// Core Enable
i2c_control = 0x80;
// Writing Data
i2c_data = 0x20; // Slave Addr + WR
i2c_cmd = 0x90;
while(i2c_cmd & 0x2);
// Memory Address
i2c_data = 0x66;
i2c_cmd = 0x10;
while(i2c_cmd & 0x2);
/* Byte1: 12 */
i2c_data = 0x12;
i2c_cmd = 0x10;
while(i2c_cmd & 0x2);
/* Byte2: 34 */
i2c_data = 0x34;
i2c_cmd = 0x10;
while(i2c_cmd & 0x2);
 
/* Byte3: 56 */
i2c_data = 0x56;
i2c_cmd = 0x10;
while(i2c_cmd & 0x2);
 
/* Byte4: 78 */
i2c_data = 0x78;
i2c_cmd = 0x50; // Stop + Write
while(i2c_cmd & 0x2);
 
//Reading Data
// Slave Address + Write
i2c_data = 0x20;
i2c_cmd = 0x90;
while(i2c_cmd & 0x2);
// Memorry Address
i2c_data = 0x66;
i2c_cmd = 0x50; // Stop
while(i2c_cmd & 0x2);
 
//Burst Read
i2c_data = 0x21;
i2c_cmd = 0x90;
while(i2c_cmd & 0x2);
 
/* BYTE-1 : 0x12 */
i2c_cmd = 0x20;
while(i2c_cmd & 0x2);
if(i2c_data != 0x12) ErrCnt++;
 
 
/* BYTE-2 : 0x34 */
i2c_cmd = 0x20;
while(i2c_cmd & 0x2);
if(i2c_data != 0x34) ErrCnt++;
 
/* BYTE-3 : 0x56 */
i2c_cmd = 0x20;
while(i2c_cmd & 0x2);
if(i2c_data != 0x56) ErrCnt++;
 
/* BYTE-4 : 0x78 */
i2c_cmd = 0x68; // STOP + RD + NACK
while(i2c_cmd & 0x2);
if(i2c_data != 0x78) ErrCnt++;
 
if(ErrCnt !=0) {
P2 = 0x55; // Test Fail
P3 = ErrCnt;
} else {
P2 = 0xAA; // Test PASS
P3 = 0xAA; // Test PASS
}
 
while(1);
 
}
/oms8051mini/trunk/verif/sw/hex/i2cm_burst_wrrd.hex
0,0 → 1,34
:03000000020006F5
:03005F0002000399
:0300030002006296
:100062007E007F0090A00074C7F090A001E4F090A1
:10007200A0027480F090A0037420F090A004749009
:10008200F090A004E0FD20E1F890A0037466F090E7
:10009200A0047410F090A004E0FD20E1F890A00309
:1000A2007412F090A0047410F090A004E0FD20E11E
:1000B200F890A0037434F090A0047410F090A0049F
:1000C200E0FD20E1F890A0037456F090A0047410B3
:1000D200F090A004E0FD20E1F890A0037478F09085
:1000E200A0047450F090A004E0FD20E1F890A00379
:1000F2007420F090A0047490F090A004E0FD20E140
:10010200F890A0037466F090A0047450F090A004DC
:10011200E0FD20E1F890A0037421F090A00403F028
:1001220090A004E0FD20E1F890A0047420F090A0DB
:1001320004E0FD20E1F890A003E0FDBD120280047E
:100142007E017F0090A0047420F090A004E0FD20C6
:10015200E1F890A003E0FDBD340280050EBE00016F
:100162000F90A0047420F090A004E0FD20E1F8902C
:10017200A003E0FDBD560280050EBE00010F90A057
:10018200047468F090A004E0FD20E1F890A003E080
:10019200FDBD780280050EBE00010FEE4F600775AF
:0E01A200A0558EB0800675A0AA75B0AA80FE8A
:06003500E478FFF6D8FD9F
:100013007900E94400601B7A009001B4780175A06F
:1000230000E493F2A308B8000205A0D9F4DAF2754C
:02003300A0FF2C
:10003B007800E84400600A790175A000E4F309D860
:10004B00FC7800E84400600C7900900001E4F0A318
:04005B00D8FCD9FAFA
:0D0006007581081201B0E58260030200035D
:0401B0007582002232
:00000001FF
/oms8051mini/trunk/verif/testcase/dat/i2cm_burst_wrrd.dat
0,0 → 1,444
///
/// created by oc8051 rom maker
/// author: Simon Teran (simont@opencores.org)
///
/// source file: F:\i2cm_burst_wrrd.hex
/// date: 07-01-2017
/// time: 21:57:45
///
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