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https://opencores.org/ocsvn/t80/t80/trunk
Subversion Repositories t80
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- from Rev 30 to Rev 31
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Rev 30 → Rev 31
/trunk/bench/vhdl/SRAM.vhd
1,7 → 1,7
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-- Simple SRAM model without timing |
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-- Version : 0240 |
-- Version : 0241 |
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-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org) |
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65,8 → 65,8
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architecture behaviour of SRAM is |
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type Memory_Image is array (natural range <>) of std_logic_vector(Data_Width - 1 downto 0); |
signal RAM : Memory_Image(0 to 2 ** Addr_Width - 1); |
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0); |
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1); |
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signal Write : std_logic; |
signal D_del : std_logic_vector(7 downto 0); |