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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/trunk/sim/bench/usbHostSlaveTB.cpp
172,7 → 172,7
readXCReg(SLAVE, tempDataFromHost2, SC_FRAME_NUM_LSP, (expectedFrameNum % 256), 0xff);
}
printf("SOF Frame count %d = 0x%0x\n", i, (tempDataFromHost * 256) + tempDataFromHost2);
readXCReg(HOST, tempDataFromHost, RA_HC_RX_SOF_TIMER_MSB_REG, 0x0, 0x0);
readXCReg(HOST, tempDataFromHost, SOF_TIMER_MSB_REG, 0x0, 0x0);
printf("Host SOF Timer MSB = 0x%0x\n", tempDataFromHost);
}
cout << "Disabling SOF transmission\n";
513,10 → 513,10
for (i=0; i<dataSize; i++)
hostBusWrite(data[i], HOST_TX_FIFO_BASE + FIFO_DATA_REG);
if ((endPControlReg & (1 << ENDPOINT_ISO_ENABLE_BIT)) == 0) //if not iso mode
writeXCReg(HOST, (1 << TRANS_REQ_BIT), RA_HC_TX_CONTROL_REG); //then
writeXCReg(HOST, (1 << TRANS_REQ_BIT), TX_CONTROL_REG); //then
else
//writeXCReg(HOST, (1 << TRANS_REQ_BIT) & (1 << ISO_ENABLE_BIT), RA_HC_TX_CONTROL_REG);
writeXCReg(HOST, 0x9, RA_HC_TX_CONTROL_REG);
//writeXCReg(HOST, (1 << TRANS_REQ_BIT) & (1 << ISO_ENABLE_BIT), TX_CONTROL_REG);
writeXCReg(HOST, 0x9, TX_CONTROL_REG);
if (fullSpeedRate == 1)
waitUSBClockTicks(500+dataSize*100); //suspend test bench so that DUT can process the packet
else
660,7 → 660,7
 
for (i=0; i<dataSize; i++)
slaveBusWrite(data[i], fifoBaseAddress + FIFO_DATA_REG);
writeXCReg(HOST, (1 << TRANS_REQ_BIT), RA_HC_TX_CONTROL_REG);
writeXCReg(HOST, (1 << TRANS_REQ_BIT), TX_CONTROL_REG);
waitUSBClockTicks(500+dataSize*100); //suspend test bench so that DUT can process the packet
 
 
701,8 → 701,8
 
cancelInterrupt(SLAVE, SC_NAK_SENT_INT_BIT);
cancelInterrupt(HOST, TRANS_DONE_BIT);
readXCReg(HOST, tempDataFromHost, RA_HC_TX_CONTROL_REG, 0, (1 << TRANS_REQ_BIT)); //check that the bit was set
printf("RA_HC_TX_CONTROL_REG = 0x%0x\n", tempDataFromHost);
readXCReg(HOST, tempDataFromHost, TX_CONTROL_REG, 0, (1 << TRANS_REQ_BIT)); //check that the bit was set
printf("TX_CONTROL_REG = 0x%0x\n", tempDataFromHost);
 
 
if (endPControlReg & (1 << ENDPOINT_OUTDATA_SEQUENCE_BIT) )
/trunk/sim/bench/usbHostSlaveMemMap.h
39,107 → 39,6
HOST_SLAVE_CONTROL_BASE = 0xe0 };
 
 
// Host registers
enum hostMemMap {
RA_HC_TX_CONTROL_REG = HCREG_BASE+TX_CONTROL_REG,
RA_HC_TX_TRANS_TYPE_REG = HCREG_BASE+TX_TRANS_TYPE_REG,
RA_HC_TX_LINE_CONTROL_REG = HCREG_BASE+TX_LINE_CONTROL_REG,
RA_HC_TX_SOF_ENABLE_REG = HCREG_BASE+TX_SOF_ENABLE_REG,
RA_HC_TX_ADDR_REG = HCREG_BASE+TX_ADDR_REG,
RA_HC_TX_ENDP_REG = HCREG_BASE+TX_ENDP_REG,
RA_HC_FRAME_NUM_MSB_REG = HCREG_BASE+FRAME_NUM_MSB_REG,
RA_HC_FRAME_NUM_LSB_REG = HCREG_BASE+FRAME_NUM_LSB_REG,
RA_HC_INTERRUPT_STATUS_REG = HCREG_BASE+INTERRUPT_STATUS_REG,
RA_HC_INTERRUPT_MASK_REG = HCREG_BASE+INTERRUPT_MASK_REG,
RA_HC_RX_STATUS_REG = HCREG_BASE+RX_STATUS_REG,
RA_HC_RX_PID_REG = HCREG_BASE+RX_PID_REG,
RA_HC_RX_ADDR_REG = HCREG_BASE+RX_ADDR_REG,
RA_HC_RX_ENDP_REG = HCREG_BASE+RX_ENDP_REG,
RA_HC_RX_CONNECT_STATE_REG = HCREG_BASE+RX_CONNECT_STATE_REG,
RA_HC_RX_SOF_TIMER_MSB_REG = HCREG_BASE+SOF_TIMER_MSB_REG,
RA_HC_RX_FIFO_DATA_REG = HOST_RX_FIFO_BASE + FIFO_DATA_REG,
RA_HC_RX_FIFO_STATUS_REG = HOST_RX_FIFO_BASE + FIFO_STATUS_REG,
RA_HC_RX_FIFO_DATA_COUNT_MSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_HC_RX_FIFO_DATA_COUNT_LSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_HC_RX_FIFO_CONTROL_REG = HOST_RX_FIFO_BASE + FIFO_CONTROL_REG,
RA_HC_TX_FIFO_DATA_REG = HOST_TX_FIFO_BASE + FIFO_DATA_REG,
RA_HC_TX_FIFO_STATUS_REG = HOST_TX_FIFO_BASE + FIFO_STATUS_REG,
RA_HC_TX_FIFO_DATA_COUNT_MSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_HC_TX_FIFO_DATA_COUNT_LSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_HC_TX_FIFO_CONTROL_REG = HOST_TX_FIFO_BASE + FIFO_CONTROL_REG,
};
 
 
enum slaveMemMap {
RA_EP0_CONTROL_REG = SCREG_BASE + ENDPOINT_CONTROL_REG,
RA_EP0_STATUS_REG = SCREG_BASE + ENDPOINT_STATUS_REG,
RA_EP0_TRANSTYPE_STATUS_REG = SCREG_BASE + ENDPOINT_TRANSTYPE_STATUS_REG,
RA_EP0_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NAK_TRANSTYPE_STATUS_REG,
RA_EP1_CONTROL_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_CONTROL_REG,
RA_EP1_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_STATUS_REG,
RA_EP1_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT+ ENDPOINT_TRANSTYPE_STATUS_REG,
RA_EP1_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + NAK_TRANSTYPE_STATUS_REG,
RA_EP2_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_CONTROL_REG,
RA_EP2_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_STATUS_REG,
RA_EP2_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_TRANSTYPE_STATUS_REG,
RA_EP2_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + NAK_TRANSTYPE_STATUS_REG,
RA_EP3_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_CONTROL_REG,
RA_EP3_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_STATUS_REG,
RA_EP3_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_TRANSTYPE_STATUS_REG,
RA_EP3_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + NAK_TRANSTYPE_STATUS_REG,
RA_SC_CONTROL_REG = SCREG_BASE + SC_CONTROL_REG,
RA_SC_LINE_STATUS_REG = SCREG_BASE + SC_LINE_STATUS_REG,
RA_SC_INTERRUPT_STATUS_REG = SCREG_BASE + SC_INTERRUPT_STATUS_REG,
RA_SC_INTERRUPT_MASK_REG = SCREG_BASE + SC_INTERRUPT_MASK_REG,
RA_SC_ADDRESS = SCREG_BASE + SC_ADDRESS,
RA_SC_FRAME_NUM_MSP = SCREG_BASE + SC_FRAME_NUM_MSP,
RA_SC_FRAME_NUM_LSP = SCREG_BASE + SC_FRAME_NUM_LSP,
 
RA_EP0_RX_FIFO_DATA_REG = EP0_RX_FIFO_BASE + FIFO_DATA_REG,
RA_EP0_RX_FIFO_STATUS_REG = EP0_RX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP0_RX_FIFO_DATA_COUNT_MSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP0_RX_FIFO_DATA_COUNT_LSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP0_RX_FIFO_CONTROL_REG = EP0_RX_FIFO_BASE + FIFO_CONTROL_REG,
RA_EP0_TX_FIFO_DATA_REG = EP0_TX_FIFO_BASE + FIFO_DATA_REG,
RA_EP0_TX_FIFO_STATUS_REG = EP0_TX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP0_TX_FIFO_DATA_COUNT_MSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP0_TX_FIFO_DATA_COUNT_LSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP0_TX_FIFO_CONTROL_REG = EP0_TX_FIFO_BASE + FIFO_CONTROL_REG,
 
RA_EP1_RX_FIFO_DATA_REG = EP1_RX_FIFO_BASE + FIFO_DATA_REG,
RA_EP1_RX_FIFO_STATUS_REG = EP1_RX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP1_RX_FIFO_DATA_COUNT_MSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP1_RX_FIFO_DATA_COUNT_LSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP1_RX_FIFO_CONTROL_REG = EP1_RX_FIFO_BASE + FIFO_CONTROL_REG,
RA_EP1_TX_FIFO_DATA_REG = EP1_TX_FIFO_BASE + FIFO_DATA_REG,
RA_EP1_TX_FIFO_STATUS_REG = EP1_TX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP1_TX_FIFO_DATA_COUNT_MSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP1_TX_FIFO_DATA_COUNT_LSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP1_TX_FIFO_CONTROL_REG = EP1_TX_FIFO_BASE + FIFO_CONTROL_REG,
 
RA_EP2_RX_FIFO_DATA_REG = EP2_RX_FIFO_BASE + FIFO_DATA_REG,
RA_EP2_RX_FIFO_STATUS_REG = EP2_RX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP2_RX_FIFO_DATA_COUNT_MSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP2_RX_FIFO_DATA_COUNT_LSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP2_RX_FIFO_CONTROL_REG = EP2_RX_FIFO_BASE + FIFO_CONTROL_REG,
RA_EP2_TX_FIFO_DATA_REG = EP2_TX_FIFO_BASE + FIFO_DATA_REG,
RA_EP2_TX_FIFO_STATUS_REG = EP2_TX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP2_TX_FIFO_DATA_COUNT_MSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP2_TX_FIFO_DATA_COUNT_LSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP2_TX_FIFO_CONTROL_REG = EP2_TX_FIFO_BASE + FIFO_CONTROL_REG,
 
RA_EP3_RX_FIFO_DATA_REG = EP3_RX_FIFO_BASE + FIFO_DATA_REG,
RA_EP3_RX_FIFO_STATUS_REG = EP3_RX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP3_RX_FIFO_DATA_COUNT_MSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP3_RX_FIFO_DATA_COUNT_LSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP3_RX_FIFO_CONTROL_REG = EP3_RX_FIFO_BASE + FIFO_CONTROL_REG,
RA_EP3_TX_FIFO_DATA_REG = EP3_TX_FIFO_BASE + FIFO_DATA_REG,
RA_EP3_TX_FIFO_STATUS_REG = EP3_TX_FIFO_BASE + FIFO_STATUS_REG,
RA_EP3_TX_FIFO_DATA_COUNT_MSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
RA_EP3_TX_FIFO_DATA_COUNT_LSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
RA_EP3_TX_FIFO_CONTROL_REG = EP3_TX_FIFO_BASE + FIFO_CONTROL_REG
};
 
enum hostSlaveCommonMemMap {
RA_HOST_SLAVE_MODE = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_MODE_CTRL,
RA_HOST_SLAVE_VERSION = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_VERSION_NUM

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