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URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v
358,7 → 358,7
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clkt));
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
/versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_top.v
52,7 → 52,7
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clkt));
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};

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