OpenCores
URL https://opencores.org/ocsvn/atlas_core/atlas_core/trunk

Subversion Repositories atlas_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 31 to Rev 32
    ↔ Reverse comparison
  •

Rev 31 → Rev 32

/atlas_core/trunk/asm/atlas_asm.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/atlas_core/trunk/asm/src/main.cpp
1752,10 → 1752,12
else if ((strcmp(arg[0], "RBRL") == 0) or (strcmp(arg[0], "RBRLAL") == 0)) // register-base branch relative & link - always
opcode = (61<<10) | (1<<9) | (0<<8) | (1<<7) | (15<<3) | (conv_reg(arg[1], line)<<0);
 
// MUL-Instruction
// MUL-Instructions
// ---------------------------------------------------------------------------------------------------------
else if (strcmp(arg[0], "MUL") == 0) // increment with #0 = move register
else if (strcmp(arg[0], "MUL") == 0) // 16-bit multiplication result
opcode = (15<<12) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | (0<<3) | (conv_reg(arg[3], line)<<0);
else if (strcmp(arg[0], "MULH") == 0) // 32-bit multiplication high result
opcode = (15<<12) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | (1<<3) | (conv_reg(arg[3], line)<<0);
 
// Pseudo-Instructions
// ---------------------------------------------------------------------------------------------------------
1902,7 → 1904,7
int p_size = 0;
int i = 0;
 
printf("ATLAS 2k Assembler, Version 2014.04.14\n");
printf("ATLAS 2k Assembler, Version 2014.04.29\n");
printf("by Stephan Nolting (stnolting@gmail.com), Hanover, Germany\n");
printf("www.opencores.org/project,atlas_core\n\n");
 
/atlas_core/trunk/rtl/BOOT_MEM.vhd
3,7 → 3,7
-- # **************************************************** #
-- # 2kB ROM initialized with Atlas-2k bootloader. #
-- # **************************************************** #
-- # Last modified: 19.04.2014 #
-- # Last modified: 24.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
53,7 → 53,7
000007 => x"ec8a", -- MCR
000008 => x"cc19", -- LDIH
000009 => x"ed0f", -- MCR
000010 => x"c51e", -- LDIL
000010 => x"c526", -- LDIL
000011 => x"c907", -- LDIH
000012 => x"be73", -- BL
000013 => x"bc00", -- B
91,15 → 91,15
000045 => x"ec22", -- MRC
000046 => x"d406", -- SBR
000047 => x"ed0a", -- MCR
000048 => x"c534", -- LDIL
000048 => x"c53c", -- LDIL
000049 => x"c905", -- LDIH
000050 => x"be4d", -- BL
000051 => x"c12a", -- LDIL
000051 => x"c132", -- LDIL
000052 => x"c906", -- LDIH
000053 => x"be4a", -- BL
000054 => x"ee11", -- MRC
000055 => x"be4c", -- BL
000056 => x"c13a", -- LDIL
000056 => x"c142", -- LDIL
000057 => x"c906", -- LDIH
000058 => x"be45", -- BL
000059 => x"ee97", -- MRC
114,13 → 114,13
000068 => x"c330", -- LDIL
000069 => x"0b60", -- ADD
000070 => x"bc0f", -- B
000071 => x"c552", -- LDIL
000071 => x"c55a", -- LDIL
000072 => x"c906", -- LDIH
000073 => x"be36", -- BL
000074 => x"c142", -- LDIL
000074 => x"c14a", -- LDIL
000075 => x"c907", -- LDIH
000076 => x"be33", -- BL
000077 => x"c508", -- LDIL
000077 => x"c510", -- LDIL
000078 => x"c907", -- LDIH
000079 => x"be30", -- BL
000080 => x"be32", -- BL
143,7 → 143,7
000097 => x"c0b4", -- LDIL
000098 => x"181e", -- CMP
000099 => x"8021", -- BEQ
000100 => x"c294", -- LDIL
000100 => x"c29c", -- LDIL
000101 => x"ca83", -- LDIH
000102 => x"c0f0", -- LDIL
000103 => x"181e", -- CMP
151,7 → 151,7
000105 => x"c0e4", -- LDIL
000106 => x"181e", -- CMP
000107 => x"80e4", -- BEQ
000108 => x"c2c8", -- LDIL
000108 => x"c2d0", -- LDIL
000109 => x"ca85", -- LDIH
000110 => x"c0f7", -- LDIL
000111 => x"181e", -- CMP
164,7 → 164,7
000118 => x"cc80", -- LDIH
000119 => x"ec99", -- MCR
000120 => x"3400", -- GT
000121 => x"c14a", -- LDIL
000121 => x"c152", -- LDIL
000122 => x"c906", -- LDIH
000123 => x"be04", -- BL
000124 => x"2800", -- CLR
175,7 → 175,7
000129 => x"bc98", -- B
000130 => x"bc98", -- B
000131 => x"bc9b", -- B
000132 => x"c528", -- LDIL
000132 => x"c530", -- LDIL
000133 => x"c906", -- LDIH
000134 => x"be91", -- BL
000135 => x"be99", -- BL
182,7 → 182,7
000136 => x"edca", -- MCR
000137 => x"be97", -- BL
000138 => x"edc9", -- MCR
000139 => x"c036", -- LDIL
000139 => x"c03e", -- LDIL
000140 => x"c805", -- LDIH
000141 => x"3404", -- GTL
000142 => x"be8a", -- BL
266,7 → 266,7
000220 => x"be3f", -- BL
000221 => x"26d3", -- ORR
000222 => x"3460", -- RET
000223 => x"c162", -- LDIL
000223 => x"c16a", -- LDIL
000224 => x"c906", -- LDIH
000225 => x"be36", -- BL
000226 => x"be38", -- BL
305,7 → 305,7
000259 => x"85f9", -- BNE
000260 => x"ec11", -- MRC
000261 => x"ec8a", -- MCR
000262 => x"c506", -- LDIL
000262 => x"c50e", -- LDIL
000263 => x"c906", -- LDIH
000264 => x"be0f", -- BL
000265 => x"ec06", -- MRC
312,10 → 312,10
000266 => x"2491", -- LDUB
000267 => x"1809", -- CMP
000268 => x"8015", -- BEQ
000269 => x"c52c", -- LDIL
000269 => x"c534", -- LDIL
000270 => x"c907", -- LDIH
000271 => x"be08", -- BL
000272 => x"bccb", -- B
000272 => x"bccf", -- B
000273 => x"0370", -- MOV
000274 => x"be08", -- BL
000275 => x"3c80", -- SFT
322,23 → 322,23
000276 => x"be06", -- BL
000277 => x"2490", -- ORR
000278 => x"3460", -- RET
000279 => x"bcc7", -- B
000280 => x"bcd0", -- B
000281 => x"bcd4", -- B
000282 => x"bcd8", -- B
000283 => x"bc6d", -- B
000284 => x"bcbc", -- B
000279 => x"bccb", -- B
000280 => x"bcd4", -- B
000281 => x"bcd8", -- B
000282 => x"bcdc", -- B
000283 => x"bc71", -- B
000284 => x"bcc0", -- B
000285 => x"bd30", -- B
000286 => x"bc6b", -- B
000287 => x"bcbe", -- B
000288 => x"bcd7", -- B
000289 => x"c176", -- LDIL
000286 => x"bc6f", -- B
000287 => x"bcc2", -- B
000288 => x"bcdb", -- B
000289 => x"c17e", -- LDIL
000290 => x"c906", -- LDIH
000291 => x"bebb", -- BL
000291 => x"bebf", -- BL
000292 => x"24aa", -- LDUBS
000293 => x"8016", -- BEQ
000294 => x"c0a2", -- LDIL
000295 => x"bec6", -- BL
000295 => x"beca", -- BL
000296 => x"24a2", -- LDUB
000297 => x"be20", -- BL
000298 => x"24b3", -- LDUB
350,17 → 350,17
000304 => x"24e6", -- LDUB
000305 => x"be18", -- BL
000306 => x"c0a2", -- LDIL
000307 => x"beba", -- BL
000308 => x"beb4", -- BL
000309 => x"c546", -- LDIL
000307 => x"bebe", -- BL
000308 => x"beb8", -- BL
000309 => x"c54e", -- LDIL
000310 => x"c906", -- LDIH
000311 => x"bea7", -- BL
000311 => x"beab", -- BL
000312 => x"ee06", -- MRC
000313 => x"bee3", -- BL
000314 => x"beae", -- BL
000315 => x"bead", -- BL
000316 => x"beac", -- BL
000317 => x"beab", -- BL
000313 => x"bee7", -- BL
000314 => x"beb2", -- BL
000315 => x"beb1", -- BL
000316 => x"beb0", -- BL
000317 => x"beaf", -- BL
000318 => x"c080", -- LDIL
000319 => x"ccc0", -- LDIH
000320 => x"1c01", -- STSR
374,691 → 374,695
000328 => x"3400", -- GT
000329 => x"0370", -- MOV
000330 => x"3c90", -- SFT
000331 => x"bea2", -- BL
000331 => x"bea6", -- BL
000332 => x"3c90", -- SFT
000333 => x"bea0", -- BL
000333 => x"bea4", -- BL
000334 => x"3460", -- RET
000335 => x"c51a", -- LDIL
000335 => x"c522", -- LDIL
000336 => x"c906", -- LDIH
000337 => x"be8d", -- BL
000338 => x"bea5", -- BL
000339 => x"c136", -- LDIL
000337 => x"be91", -- BL
000338 => x"bea9", -- BL
000339 => x"c13e", -- LDIL
000340 => x"c905", -- LDIH
000341 => x"3424", -- GTL
000342 => x"ecca", -- MCR
000343 => x"be91", -- BL
000343 => x"be95", -- BL
000344 => x"c280", -- LDIL
000345 => x"c00f", -- LDIL
000346 => x"2058", -- ANDS
000347 => x"840a", -- BNE
000348 => x"be8c", -- BL
000347 => x"840e", -- BNE
000348 => x"be90", -- BL
000349 => x"c0a4", -- LDIL
000350 => x"be8f", -- BL
000351 => x"0250", -- MOV
000352 => x"bebc", -- BL
000353 => x"c0ba", -- LDIL
000354 => x"be8b", -- BL
000355 => x"c0a0", -- LDIL
000356 => x"be89", -- BL
000357 => x"7a5a", -- LDR
000358 => x"c0a0", -- LDIL
000359 => x"be86", -- BL
000360 => x"beb4", -- BL
000361 => x"c00f", -- LDIL
000362 => x"2058", -- ANDS
000363 => x"8414", -- BNE
000364 => x"c0a0", -- LDIL
000365 => x"be80", -- BL
000366 => x"be7f", -- BL
000367 => x"c010", -- LDIL
000368 => x"1250", -- SUB
000369 => x"c470", -- LDIL
000370 => x"2240", -- AND
000371 => x"c12e", -- LDIL
000372 => x"78c9", -- LDR
000373 => x"3c90", -- SFT
000374 => x"c880", -- LDIH
000375 => x"c020", -- LDIL
000376 => x"1818", -- CMP
000377 => x"f8c2", -- MVHI
000378 => x"be73", -- BL
000379 => x"c08f", -- LDIL
000380 => x"2014", -- AND
000381 => x"3409", -- TEQ
000382 => x"85f6", -- BNE
000383 => x"ec20", -- MRC
000384 => x"dc0f", -- STB
000385 => x"b804", -- BTS
000386 => x"c5fe", -- LDIL
000387 => x"343d", -- TEQ
000388 => x"85d5", -- BNE
000389 => x"be6d", -- BL
000390 => x"2800", -- CLR
000391 => x"3400", -- GT
000392 => x"bc54", -- B
000393 => x"bc93", -- B
000394 => x"c001", -- LDIL
000395 => x"ed0c", -- MCR
000396 => x"c050", -- LDIL
000397 => x"c83f", -- LDIH
000398 => x"ed0a", -- MCR
000399 => x"c000", -- LDIL
000400 => x"c801", -- LDIH
000401 => x"bea9", -- BL
000402 => x"c154", -- LDIL
000403 => x"c906", -- LDIH
000404 => x"be4a", -- BL
000405 => x"c162", -- LDIL
000406 => x"c906", -- LDIH
000407 => x"be47", -- BL
000408 => x"be5a", -- BL
000409 => x"3c80", -- SFT
000410 => x"be58", -- BL
000411 => x"2410", -- ORR
000412 => x"c4fe", -- LDIL
000413 => x"ccca", -- LDIH
000414 => x"1809", -- CMP
000415 => x"8439", -- BNE
000416 => x"c100", -- LDIL
000417 => x"0290", -- MOV
000418 => x"be2f", -- BL
000419 => x"be4f", -- BL
000420 => x"3c80", -- SFT
000421 => x"be4d", -- BL
000422 => x"2690", -- ORR
000423 => x"3ed4", -- SFT
000424 => x"2055", -- STUB
000425 => x"c102", -- LDIL
000426 => x"be27", -- BL
000427 => x"be47", -- BL
000428 => x"3c80", -- SFT
000429 => x"be45", -- BL
000430 => x"2690", -- ORR
000431 => x"20d5", -- STUB
000432 => x"c104", -- LDIL
000433 => x"be20", -- BL
000434 => x"c106", -- LDIL
000435 => x"be3f", -- BL
000436 => x"0180", -- MOV
000437 => x"be8b", -- BL
000438 => x"0121", -- INC
000439 => x"c010", -- LDIL
000440 => x"1828", -- CMP
000441 => x"85fa", -- BNE
000442 => x"2ad5", -- CLR
000443 => x"be37", -- BL
000444 => x"0180", -- MOV
000445 => x"be83", -- BL
000446 => x"0121", -- INC
000447 => x"2400", -- LDUB
000448 => x"02d1", -- INC
000449 => x"1858", -- CMP
000450 => x"85f9", -- BNE
000451 => x"c001", -- LDIL
000452 => x"ed0c", -- MCR
000453 => x"c050", -- LDIL
000454 => x"c83f", -- LDIH
000455 => x"ed0a", -- MCR
000456 => x"c00c", -- LDIL
000457 => x"c801", -- LDIH
000458 => x"be70", -- BL
000459 => x"c506", -- LDIL
000460 => x"c906", -- LDIH
000461 => x"be11", -- BL
000462 => x"c68e", -- LDIL
000463 => x"ca80", -- LDIH
000464 => x"3450", -- GT
000465 => x"0370", -- MOV
000466 => x"3dd0", -- SFT
000467 => x"be6d", -- BL
000468 => x"0121", -- INC
000469 => x"01d0", -- MOV
000470 => x"be6a", -- BL
000471 => x"3460", -- RET
000472 => x"c510", -- LDIL
000473 => x"c907", -- LDIH
000474 => x"be04", -- BL
000475 => x"bcba", -- B
000476 => x"bc94", -- B
000477 => x"bca5", -- B
000478 => x"01f0", -- MOV
000479 => x"7829", -- LDR
000480 => x"c080", -- LDIL
000481 => x"ccff", -- LDIH
000482 => x"2081", -- AND
000483 => x"3c98", -- SFTS
000484 => x"8003", -- BEQ
000485 => x"be08", -- BL
000486 => x"bdf9", -- B
000487 => x"3430", -- RET
000488 => x"0170", -- MOV
000489 => x"c08d", -- LDIL
000490 => x"be03", -- BL
000491 => x"c08a", -- LDIL
000492 => x"03a0", -- MOV
000493 => x"ec22", -- MRC
000494 => x"dc05", -- STB
000495 => x"b9fe", -- BTS
000496 => x"ed18", -- MCR
000497 => x"3470", -- RET
000498 => x"ec20", -- MRC
000499 => x"dc8f", -- STBI
000500 => x"b9fe", -- BTS
000501 => x"c800", -- LDIH
000502 => x"3470", -- RET
000503 => x"0170", -- MOV
000504 => x"c200", -- LDIL
000505 => x"c184", -- LDIL
000506 => x"bff8", -- BL
000507 => x"c0c6", -- LDIL
000508 => x"1809", -- CMP
000509 => x"9003", -- BMI
000510 => x"c0a0", -- LDIL
000511 => x"1001", -- SUB
000512 => x"c0b0", -- LDIL
000513 => x"1809", -- CMP
000514 => x"91f8", -- BMI
000515 => x"c0c6", -- LDIL
000516 => x"1818", -- CMP
000517 => x"91f5", -- BMI
000518 => x"c0b9", -- LDIL
000519 => x"1818", -- CMP
000520 => x"a404", -- BLS
000521 => x"c0c1", -- LDIL
000522 => x"1809", -- CMP
000523 => x"a1ef", -- BHI
000524 => x"0080", -- MOV
000525 => x"bfe0", -- BL
000526 => x"c030", -- LDIL
000527 => x"1090", -- SUB
000528 => x"c009", -- LDIL
000529 => x"1809", -- CMP
000530 => x"a402", -- BLS
000531 => x"0497", -- DEC
000532 => x"3e42", -- SFT
000533 => x"3e42", -- SFT
000534 => x"3e42", -- SFT
000535 => x"3e42", -- SFT
000536 => x"2641", -- ORR
000537 => x"05b9", -- DECS
000538 => x"85e0", -- BNE
000539 => x"3420", -- RET
000540 => x"0370", -- MOV
000541 => x"3d42", -- SFT
000542 => x"3d22", -- SFT
000543 => x"3d22", -- SFT
000544 => x"3d22", -- SFT
000545 => x"be0f", -- BL
000546 => x"bfcb", -- BL
000547 => x"3d40", -- SFT
000548 => x"be0c", -- BL
000549 => x"bfc8", -- BL
000550 => x"3d45", -- SFT
000551 => x"3d25", -- SFT
000552 => x"3d25", -- SFT
000553 => x"3d25", -- SFT
000554 => x"be06", -- BL
000555 => x"bfc2", -- BL
000556 => x"0140", -- MOV
000557 => x"be03", -- BL
000558 => x"bfbf", -- BL
000559 => x"3460", -- RET
000560 => x"c08f", -- LDIL
000561 => x"2121", -- AND
000562 => x"c089", -- LDIL
000563 => x"181a", -- CMP
000564 => x"8803", -- BCS
000565 => x"c0b0", -- LDIL
000566 => x"bc02", -- B
000567 => x"c0b7", -- LDIL
000568 => x"0892", -- ADD
000569 => x"3470", -- RET
000570 => x"ed0b", -- MCR
000571 => x"ec22", -- MRC
000572 => x"dc03", -- STB
000573 => x"b9fe", -- BTS
000574 => x"ec23", -- MRC
000575 => x"3470", -- RET
000576 => x"00f0", -- MOV
000577 => x"c050", -- LDIL
000578 => x"c837", -- LDIH
000579 => x"ed0a", -- MCR
000580 => x"c001", -- LDIL
000581 => x"ed0c", -- MCR
000582 => x"c006", -- LDIL
000583 => x"bff3", -- BL
000584 => x"c050", -- LDIL
000585 => x"c83f", -- LDIH
000586 => x"ed0a", -- MCR
000587 => x"c000", -- LDIL
000588 => x"c805", -- LDIH
000589 => x"bfed", -- BL
000590 => x"dc01", -- STB
000591 => x"b805", -- BTS
000592 => x"c53c", -- LDIL
000593 => x"c907", -- LDIH
000594 => x"bf8c", -- BL
000595 => x"bc42", -- B
000596 => x"c040", -- LDIL
000597 => x"c83f", -- LDIH
000598 => x"ed0a", -- MCR
000599 => x"c001", -- LDIL
000600 => x"ed0c", -- MCR
000601 => x"3c20", -- SFT
000602 => x"c802", -- LDIH
000603 => x"bfdf", -- BL
000604 => x"03a0", -- MOV
000605 => x"cb80", -- LDIH
000606 => x"3ff0", -- SFT
000607 => x"0030", -- MOV
000608 => x"c800", -- LDIH
000609 => x"2407", -- ORR
000610 => x"bfd8", -- BL
000611 => x"2800", -- CLR
000612 => x"ed0c", -- MCR
000613 => x"c050", -- LDIL
000614 => x"c83f", -- LDIH
000615 => x"ed0a", -- MCR
000616 => x"c001", -- LDIL
000617 => x"ed0c", -- MCR
000618 => x"c000", -- LDIL
000619 => x"c805", -- LDIH
000620 => x"bfce", -- BL
000621 => x"dc00", -- STB
000622 => x"b9fc", -- BTS
000623 => x"3410", -- RET
000624 => x"00f0", -- MOV
000625 => x"c040", -- LDIL
000626 => x"c83f", -- LDIH
000627 => x"ed0a", -- MCR
000628 => x"c001", -- LDIL
000629 => x"ed0c", -- MCR
000630 => x"3c20", -- SFT
000631 => x"c803", -- LDIH
000632 => x"bfc2", -- BL
000633 => x"0020", -- MOV
000634 => x"c800", -- LDIH
000635 => x"3c00", -- SFT
000636 => x"bfbe", -- BL
000637 => x"29b3", -- CLR
000638 => x"ed3c", -- MCR
000639 => x"0180", -- MOV
000640 => x"c980", -- LDIH
000641 => x"3410", -- RET
000642 => x"e5b0", -- CDP
000643 => x"ec30", -- MRC
000644 => x"dc06", -- STB
000645 => x"b9fe", -- BTS
000646 => x"c306", -- LDIL
000647 => x"200e", -- ANDS
000648 => x"840a", -- BNE
000649 => x"ecb1", -- MRC
000650 => x"ef32", -- MRC
000651 => x"2800", -- CLR
000652 => x"009a", -- INCS
000653 => x"0f60", -- ADC
000654 => x"ed99", -- MCR
000655 => x"edea", -- MCR
000656 => x"ef34", -- MRC
000657 => x"3470", -- RET
000658 => x"c54e", -- LDIL
000659 => x"c907", -- LDIH
000660 => x"bf4a", -- BL
000661 => x"c55c", -- LDIL
000662 => x"c907", -- LDIH
000663 => x"bf47", -- BL
000664 => x"bf5a", -- BL
000665 => x"2800", -- CLR
000666 => x"3400", -- GT
000667 => x"0170", -- MOV
000668 => x"bf56", -- BL
000669 => x"c08d", -- LDIL
000670 => x"1809", -- CMP
000671 => x"f702", -- RBAEQ
000672 => x"c088", -- LDIL
000673 => x"1809", -- CMP
000674 => x"8034", -- BEQ
000675 => x"bdf9", -- B
000676 => x"c528", -- LDIL
000677 => x"c906", -- LDIH
000678 => x"bf38", -- BL
000679 => x"bf50", -- BL
000680 => x"edca", -- MCR
000681 => x"bf4e", -- BL
000682 => x"edc9", -- MCR
000683 => x"bff0", -- BL
000684 => x"bf3c", -- BL
000685 => x"c536", -- LDIL
000686 => x"c906", -- LDIH
000687 => x"bf2f", -- BL
000688 => x"bf47", -- BL
000689 => x"02c0", -- MOV
000690 => x"bfe9", -- BL
000691 => x"bf35", -- BL
000692 => x"345d", -- TEQ
000693 => x"8021", -- BEQ
000694 => x"06d1", -- DEC
000695 => x"bf31", -- BL
000696 => x"c0a4", -- LDIL
000697 => x"bf34", -- BL
000698 => x"ee32", -- MRC
000699 => x"bf61", -- BL
000700 => x"ee31", -- MRC
000701 => x"bf5f", -- BL
000702 => x"c0ba", -- LDIL
000703 => x"bf2e", -- BL
000704 => x"c0a0", -- LDIL
000705 => x"bf2c", -- BL
000706 => x"bfc0", -- BL
000707 => x"0260", -- MOV
000708 => x"bf58", -- BL
000709 => x"c320", -- LDIL
000710 => x"c1ae", -- LDIL
000711 => x"00e0", -- MOV
000712 => x"bf25", -- BL
000713 => x"3cc0", -- SFT
000714 => x"c880", -- LDIH
000715 => x"181e", -- CMP
000716 => x"f8c3", -- MVHI
000717 => x"bf20", -- BL
000718 => x"00c0", -- MOV
000719 => x"c880", -- LDIH
000720 => x"181e", -- CMP
000721 => x"f8c3", -- MVHI
000722 => x"bf1b", -- BL
000723 => x"eca0", -- MRC
000724 => x"dc9f", -- STBI
000725 => x"b9df", -- BTS
000726 => x"bf12", -- BL
000727 => x"c69a", -- LDIL
000728 => x"ca80", -- LDIH
000729 => x"3450", -- GT
000730 => x"0d0a", -- .DW
000731 => x"0d0a", -- .DW
000732 => x"4174", -- .DW
000733 => x"6c61", -- .DW
000734 => x"732d", -- .DW
000735 => x"324b", -- .DW
000736 => x"2042", -- .DW
000737 => x"6f6f", -- .DW
000738 => x"746c", -- .DW
000739 => x"6f61", -- .DW
000740 => x"6465", -- .DW
000741 => x"7220", -- .DW
000742 => x"2d20", -- .DW
000743 => x"5632", -- .DW
000744 => x"3031", -- .DW
000745 => x"3430", -- .DW
000746 => x"3431", -- .DW
000747 => x"390d", -- .DW
000748 => x"0a62", -- .DW
000749 => x"7920", -- .DW
000750 => x"5374", -- .DW
000751 => x"6570", -- .DW
000752 => x"6861", -- .DW
000753 => x"6e20", -- .DW
000754 => x"4e6f", -- .DW
000755 => x"6c74", -- .DW
000756 => x"696e", -- .DW
000757 => x"672c", -- .DW
000758 => x"2073", -- .DW
000759 => x"746e", -- .DW
000760 => x"6f6c", -- .DW
000761 => x"7469", -- .DW
000762 => x"6e67", -- .DW
000763 => x"4067", -- .DW
000764 => x"6d61", -- .DW
000765 => x"696c", -- .DW
000766 => x"2e63", -- .DW
000767 => x"6f6d", -- .DW
000768 => x"0d0a", -- .DW
000769 => x"7777", -- .DW
000770 => x"772e", -- .DW
000771 => x"6f70", -- .DW
000772 => x"656e", -- .DW
000773 => x"636f", -- .DW
000774 => x"7265", -- .DW
000775 => x"732e", -- .DW
000776 => x"6f72", -- .DW
000777 => x"672f", -- .DW
000778 => x"7072", -- .DW
000779 => x"6f6a", -- .DW
000780 => x"6563", -- .DW
000781 => x"742c", -- .DW
000782 => x"6174", -- .DW
000783 => x"6c61", -- .DW
000784 => x"735f", -- .DW
000785 => x"636f", -- .DW
000786 => x"7265", -- .DW
000787 => x"0d0a", -- .DW
000788 => x"0000", -- .DW
000789 => x"0d0a", -- .DW
000790 => x"426f", -- .DW
000791 => x"6f74", -- .DW
000792 => x"2070", -- .DW
000793 => x"6167", -- .DW
000794 => x"653a", -- .DW
000795 => x"2030", -- .DW
000796 => x"7800", -- .DW
000797 => x"0d0a", -- .DW
000798 => x"436c", -- .DW
000799 => x"6f63", -- .DW
000800 => x"6b28", -- .DW
000801 => x"487a", -- .DW
000802 => x"293a", -- .DW
000803 => x"2030", -- .DW
000804 => x"7800", -- .DW
000805 => x"426f", -- .DW
000806 => x"6f74", -- .DW
000807 => x"696e", -- .DW
000808 => x"670d", -- .DW
000809 => x"0a00", -- .DW
000810 => x"4275", -- .DW
000811 => x"726e", -- .DW
000812 => x"2045", -- .DW
000813 => x"4550", -- .DW
000814 => x"524f", -- .DW
000815 => x"4d0d", -- .DW
000816 => x"0a00", -- .DW
000817 => x"4177", -- .DW
000818 => x"6169", -- .DW
000819 => x"7469", -- .DW
000820 => x"6e67", -- .DW
000821 => x"2064", -- .DW
000822 => x"6174", -- .DW
000823 => x"612e", -- .DW
000824 => x"2e2e", -- .DW
000825 => x"0d0a", -- .DW
000826 => x"0000", -- .DW
000827 => x"5374", -- .DW
000828 => x"6172", -- .DW
000829 => x"7469", -- .DW
000830 => x"6e67", -- .DW
000831 => x"2069", -- .DW
000832 => x"6d61", -- .DW
000833 => x"6765", -- .DW
000834 => x"2000", -- .DW
000835 => x"446f", -- .DW
000836 => x"776e", -- .DW
000837 => x"6c6f", -- .DW
000838 => x"6164", -- .DW
000839 => x"2063", -- .DW
000840 => x"6f6d", -- .DW
000841 => x"706c", -- .DW
000842 => x"6574", -- .DW
000843 => x"650d", -- .DW
000844 => x"0a00", -- .DW
000845 => x"5061", -- .DW
000846 => x"6765", -- .DW
000847 => x"2028", -- .DW
000848 => x"3468", -- .DW
000849 => x"293a", -- .DW
000850 => x"2024", -- .DW
000851 => x"0000", -- .DW
000852 => x"4164", -- .DW
000853 => x"6472", -- .DW
000854 => x"2028", -- .DW
000855 => x"3868", -- .DW
000856 => x"293a", -- .DW
000857 => x"2024", -- .DW
000858 => x"0000", -- .DW
000859 => x"2377", -- .DW
000860 => x"6f72", -- .DW
000861 => x"6473", -- .DW
000862 => x"2028", -- .DW
000863 => x"3468", -- .DW
000864 => x"293a", -- .DW
000865 => x"2024", -- .DW
000866 => x"0000", -- .DW
000867 => x"4368", -- .DW
000868 => x"6563", -- .DW
000869 => x"6b73", -- .DW
000870 => x"756d", -- .DW
000871 => x"3a20", -- .DW
000872 => x"2400", -- .DW
000873 => x"0d0a", -- .DW
000874 => x"636d", -- .DW
000875 => x"642f", -- .DW
000876 => x"626f", -- .DW
000877 => x"6f74", -- .DW
000878 => x"2d73", -- .DW
000879 => x"7769", -- .DW
000880 => x"7463", -- .DW
000881 => x"683a", -- .DW
000882 => x"0d0a", -- .DW
000883 => x"2030", -- .DW
000884 => x"2f27", -- .DW
000885 => x"3030", -- .DW
000886 => x"273a", -- .DW
000887 => x"2052", -- .DW
000888 => x"6573", -- .DW
000889 => x"7461", -- .DW
000890 => x"7274", -- .DW
000891 => x"2063", -- .DW
000892 => x"6f6e", -- .DW
000893 => x"736f", -- .DW
000894 => x"6c65", -- .DW
000895 => x"0d0a", -- .DW
000896 => x"2031", -- .DW
000897 => x"2f27", -- .DW
000898 => x"3031", -- .DW
000899 => x"273a", -- .DW
000900 => x"2042", -- .DW
000901 => x"6f6f", -- .DW
000902 => x"7420", -- .DW
000903 => x"5541", -- .DW
000904 => x"5254", -- .DW
000905 => x"0d0a", -- .DW
000906 => x"2032", -- .DW
000907 => x"2f27", -- .DW
000908 => x"3130", -- .DW
000909 => x"273a", -- .DW
000910 => x"2042", -- .DW
000911 => x"6f6f", -- .DW
000912 => x"7420", -- .DW
000913 => x"4545", -- .DW
000914 => x"5052", -- .DW
000915 => x"4f4d", -- .DW
000916 => x"0d0a", -- .DW
000917 => x"2033", -- .DW
000918 => x"2f27", -- .DW
000919 => x"3131", -- .DW
000920 => x"273a", -- .DW
000921 => x"2042", -- .DW
000922 => x"6f6f", -- .DW
000923 => x"7420", -- .DW
000924 => x"6d65", -- .DW
000925 => x"6d6f", -- .DW
000926 => x"7279", -- .DW
000927 => x"0d0a", -- .DW
000928 => x"0000", -- .DW
000929 => x"2034", -- .DW
000930 => x"3a20", -- .DW
000931 => x"426f", -- .DW
000932 => x"6f74", -- .DW
000933 => x"2057", -- .DW
000934 => x"420d", -- .DW
000935 => x"0a20", -- .DW
000936 => x"703a", -- .DW
000937 => x"2042", -- .DW
000938 => x"7572", -- .DW
000939 => x"6e20", -- .DW
000940 => x"4545", -- .DW
000941 => x"5052", -- .DW
000942 => x"4f4d", -- .DW
000943 => x"0d0a", -- .DW
000944 => x"2064", -- .DW
000945 => x"3a20", -- .DW
000946 => x"5241", -- .DW
000947 => x"4d20", -- .DW
000948 => x"6475", -- .DW
000949 => x"6d70", -- .DW
000950 => x"0d0a", -- .DW
000951 => x"2072", -- .DW
000952 => x"3a20", -- .DW
000953 => x"5265", -- .DW
000954 => x"7365", -- .DW
000955 => x"740d", -- .DW
000956 => x"0a20", -- .DW
000957 => x"773a", -- .DW
000958 => x"2057", -- .DW
000959 => x"4220", -- .DW
000960 => x"6475", -- .DW
000961 => x"6d70", -- .DW
000962 => x"0d0a", -- .DW
000963 => x"0000", -- .DW
000964 => x"636d", -- .DW
000965 => x"643a", -- .DW
000966 => x"3e20", -- .DW
000350 => x"be93", -- BL
000351 => x"ee12", -- MRC
000352 => x"bec0", -- BL
000353 => x"c0ae", -- LDIL
000354 => x"be8f", -- BL
000355 => x"0250", -- MOV
000356 => x"bebc", -- BL
000357 => x"c0ba", -- LDIL
000358 => x"be8b", -- BL
000359 => x"c0a0", -- LDIL
000360 => x"be89", -- BL
000361 => x"7a5a", -- LDR
000362 => x"c0a0", -- LDIL
000363 => x"be86", -- BL
000364 => x"beb4", -- BL
000365 => x"c00f", -- LDIL
000366 => x"2058", -- ANDS
000367 => x"8414", -- BNE
000368 => x"c0a0", -- LDIL
000369 => x"be80", -- BL
000370 => x"be7f", -- BL
000371 => x"c010", -- LDIL
000372 => x"1250", -- SUB
000373 => x"c470", -- LDIL
000374 => x"2240", -- AND
000375 => x"c12e", -- LDIL
000376 => x"78c9", -- LDR
000377 => x"3c90", -- SFT
000378 => x"c880", -- LDIH
000379 => x"c020", -- LDIL
000380 => x"1818", -- CMP
000381 => x"f8c2", -- MVHI
000382 => x"be73", -- BL
000383 => x"c08f", -- LDIL
000384 => x"2014", -- AND
000385 => x"3409", -- TEQ
000386 => x"85f6", -- BNE
000387 => x"ec20", -- MRC
000388 => x"dc0f", -- STB
000389 => x"b804", -- BTS
000390 => x"c5fe", -- LDIL
000391 => x"343d", -- TEQ
000392 => x"85d1", -- BNE
000393 => x"be6d", -- BL
000394 => x"2800", -- CLR
000395 => x"3400", -- GT
000396 => x"bc54", -- B
000397 => x"bc93", -- B
000398 => x"c001", -- LDIL
000399 => x"ed0c", -- MCR
000400 => x"c050", -- LDIL
000401 => x"c83f", -- LDIH
000402 => x"ed0a", -- MCR
000403 => x"c000", -- LDIL
000404 => x"c801", -- LDIH
000405 => x"bea9", -- BL
000406 => x"c15c", -- LDIL
000407 => x"c906", -- LDIH
000408 => x"be4a", -- BL
000409 => x"c16a", -- LDIL
000410 => x"c906", -- LDIH
000411 => x"be47", -- BL
000412 => x"be5a", -- BL
000413 => x"3c80", -- SFT
000414 => x"be58", -- BL
000415 => x"2410", -- ORR
000416 => x"c4fe", -- LDIL
000417 => x"ccca", -- LDIH
000418 => x"1809", -- CMP
000419 => x"8439", -- BNE
000420 => x"c100", -- LDIL
000421 => x"0290", -- MOV
000422 => x"be2f", -- BL
000423 => x"be4f", -- BL
000424 => x"3c80", -- SFT
000425 => x"be4d", -- BL
000426 => x"2690", -- ORR
000427 => x"3ed4", -- SFT
000428 => x"2055", -- STUB
000429 => x"c102", -- LDIL
000430 => x"be27", -- BL
000431 => x"be47", -- BL
000432 => x"3c80", -- SFT
000433 => x"be45", -- BL
000434 => x"2690", -- ORR
000435 => x"20d5", -- STUB
000436 => x"c104", -- LDIL
000437 => x"be20", -- BL
000438 => x"c106", -- LDIL
000439 => x"be3f", -- BL
000440 => x"0180", -- MOV
000441 => x"be8b", -- BL
000442 => x"0121", -- INC
000443 => x"c010", -- LDIL
000444 => x"1828", -- CMP
000445 => x"85fa", -- BNE
000446 => x"2ad5", -- CLR
000447 => x"be37", -- BL
000448 => x"0180", -- MOV
000449 => x"be83", -- BL
000450 => x"0121", -- INC
000451 => x"2400", -- LDUB
000452 => x"02d1", -- INC
000453 => x"1858", -- CMP
000454 => x"85f9", -- BNE
000455 => x"c001", -- LDIL
000456 => x"ed0c", -- MCR
000457 => x"c050", -- LDIL
000458 => x"c83f", -- LDIH
000459 => x"ed0a", -- MCR
000460 => x"c00c", -- LDIL
000461 => x"c801", -- LDIH
000462 => x"be70", -- BL
000463 => x"c50e", -- LDIL
000464 => x"c906", -- LDIH
000465 => x"be11", -- BL
000466 => x"c68e", -- LDIL
000467 => x"ca80", -- LDIH
000468 => x"3450", -- GT
000469 => x"0370", -- MOV
000470 => x"3dd0", -- SFT
000471 => x"be6d", -- BL
000472 => x"0121", -- INC
000473 => x"01d0", -- MOV
000474 => x"be6a", -- BL
000475 => x"3460", -- RET
000476 => x"c518", -- LDIL
000477 => x"c907", -- LDIH
000478 => x"be04", -- BL
000479 => x"bcba", -- B
000480 => x"bc94", -- B
000481 => x"bca5", -- B
000482 => x"01f0", -- MOV
000483 => x"7829", -- LDR
000484 => x"c080", -- LDIL
000485 => x"ccff", -- LDIH
000486 => x"2081", -- AND
000487 => x"3c98", -- SFTS
000488 => x"8003", -- BEQ
000489 => x"be08", -- BL
000490 => x"bdf9", -- B
000491 => x"3430", -- RET
000492 => x"0170", -- MOV
000493 => x"c08d", -- LDIL
000494 => x"be03", -- BL
000495 => x"c08a", -- LDIL
000496 => x"03a0", -- MOV
000497 => x"ec22", -- MRC
000498 => x"dc05", -- STB
000499 => x"b9fe", -- BTS
000500 => x"ed18", -- MCR
000501 => x"3470", -- RET
000502 => x"ec20", -- MRC
000503 => x"dc8f", -- STBI
000504 => x"b9fe", -- BTS
000505 => x"c800", -- LDIH
000506 => x"3470", -- RET
000507 => x"0170", -- MOV
000508 => x"c200", -- LDIL
000509 => x"c184", -- LDIL
000510 => x"bff8", -- BL
000511 => x"c0c6", -- LDIL
000512 => x"1809", -- CMP
000513 => x"9003", -- BMI
000514 => x"c0a0", -- LDIL
000515 => x"1001", -- SUB
000516 => x"c0b0", -- LDIL
000517 => x"1809", -- CMP
000518 => x"91f8", -- BMI
000519 => x"c0c6", -- LDIL
000520 => x"1818", -- CMP
000521 => x"91f5", -- BMI
000522 => x"c0b9", -- LDIL
000523 => x"1818", -- CMP
000524 => x"a404", -- BLS
000525 => x"c0c1", -- LDIL
000526 => x"1809", -- CMP
000527 => x"a1ef", -- BHI
000528 => x"0080", -- MOV
000529 => x"bfe0", -- BL
000530 => x"c030", -- LDIL
000531 => x"1090", -- SUB
000532 => x"c009", -- LDIL
000533 => x"1809", -- CMP
000534 => x"a402", -- BLS
000535 => x"0497", -- DEC
000536 => x"3e42", -- SFT
000537 => x"3e42", -- SFT
000538 => x"3e42", -- SFT
000539 => x"3e42", -- SFT
000540 => x"2641", -- ORR
000541 => x"05b9", -- DECS
000542 => x"85e0", -- BNE
000543 => x"3420", -- RET
000544 => x"0370", -- MOV
000545 => x"3d42", -- SFT
000546 => x"3d22", -- SFT
000547 => x"3d22", -- SFT
000548 => x"3d22", -- SFT
000549 => x"be0f", -- BL
000550 => x"bfcb", -- BL
000551 => x"3d40", -- SFT
000552 => x"be0c", -- BL
000553 => x"bfc8", -- BL
000554 => x"3d45", -- SFT
000555 => x"3d25", -- SFT
000556 => x"3d25", -- SFT
000557 => x"3d25", -- SFT
000558 => x"be06", -- BL
000559 => x"bfc2", -- BL
000560 => x"0140", -- MOV
000561 => x"be03", -- BL
000562 => x"bfbf", -- BL
000563 => x"3460", -- RET
000564 => x"c08f", -- LDIL
000565 => x"2121", -- AND
000566 => x"c089", -- LDIL
000567 => x"181a", -- CMP
000568 => x"8803", -- BCS
000569 => x"c0b0", -- LDIL
000570 => x"bc02", -- B
000571 => x"c0b7", -- LDIL
000572 => x"0892", -- ADD
000573 => x"3470", -- RET
000574 => x"ed0b", -- MCR
000575 => x"ec22", -- MRC
000576 => x"dc03", -- STB
000577 => x"b9fe", -- BTS
000578 => x"ec23", -- MRC
000579 => x"3470", -- RET
000580 => x"00f0", -- MOV
000581 => x"c050", -- LDIL
000582 => x"c837", -- LDIH
000583 => x"ed0a", -- MCR
000584 => x"c001", -- LDIL
000585 => x"ed0c", -- MCR
000586 => x"c006", -- LDIL
000587 => x"bff3", -- BL
000588 => x"c050", -- LDIL
000589 => x"c83f", -- LDIH
000590 => x"ed0a", -- MCR
000591 => x"c000", -- LDIL
000592 => x"c805", -- LDIH
000593 => x"bfed", -- BL
000594 => x"dc01", -- STB
000595 => x"b805", -- BTS
000596 => x"c544", -- LDIL
000597 => x"c907", -- LDIH
000598 => x"bf8c", -- BL
000599 => x"bc42", -- B
000600 => x"c040", -- LDIL
000601 => x"c83f", -- LDIH
000602 => x"ed0a", -- MCR
000603 => x"c001", -- LDIL
000604 => x"ed0c", -- MCR
000605 => x"3c20", -- SFT
000606 => x"c802", -- LDIH
000607 => x"bfdf", -- BL
000608 => x"03a0", -- MOV
000609 => x"cb80", -- LDIH
000610 => x"3ff0", -- SFT
000611 => x"0030", -- MOV
000612 => x"c800", -- LDIH
000613 => x"2407", -- ORR
000614 => x"bfd8", -- BL
000615 => x"2800", -- CLR
000616 => x"ed0c", -- MCR
000617 => x"c050", -- LDIL
000618 => x"c83f", -- LDIH
000619 => x"ed0a", -- MCR
000620 => x"c001", -- LDIL
000621 => x"ed0c", -- MCR
000622 => x"c000", -- LDIL
000623 => x"c805", -- LDIH
000624 => x"bfce", -- BL
000625 => x"dc00", -- STB
000626 => x"b9fc", -- BTS
000627 => x"3410", -- RET
000628 => x"00f0", -- MOV
000629 => x"c040", -- LDIL
000630 => x"c83f", -- LDIH
000631 => x"ed0a", -- MCR
000632 => x"c001", -- LDIL
000633 => x"ed0c", -- MCR
000634 => x"3c20", -- SFT
000635 => x"c803", -- LDIH
000636 => x"bfc2", -- BL
000637 => x"0020", -- MOV
000638 => x"c800", -- LDIH
000639 => x"3c00", -- SFT
000640 => x"bfbe", -- BL
000641 => x"29b3", -- CLR
000642 => x"ed3c", -- MCR
000643 => x"0180", -- MOV
000644 => x"c980", -- LDIH
000645 => x"3410", -- RET
000646 => x"e5b0", -- CDP
000647 => x"ec30", -- MRC
000648 => x"dc06", -- STB
000649 => x"b9fe", -- BTS
000650 => x"c306", -- LDIL
000651 => x"200e", -- ANDS
000652 => x"840a", -- BNE
000653 => x"ecb1", -- MRC
000654 => x"ef32", -- MRC
000655 => x"2800", -- CLR
000656 => x"009a", -- INCS
000657 => x"0f60", -- ADC
000658 => x"ed99", -- MCR
000659 => x"edea", -- MCR
000660 => x"ef34", -- MRC
000661 => x"3470", -- RET
000662 => x"c556", -- LDIL
000663 => x"c907", -- LDIH
000664 => x"bf4a", -- BL
000665 => x"c564", -- LDIL
000666 => x"c907", -- LDIH
000667 => x"bf47", -- BL
000668 => x"bf5a", -- BL
000669 => x"2800", -- CLR
000670 => x"3400", -- GT
000671 => x"0170", -- MOV
000672 => x"bf56", -- BL
000673 => x"c08d", -- LDIL
000674 => x"1809", -- CMP
000675 => x"f702", -- RBAEQ
000676 => x"c088", -- LDIL
000677 => x"1809", -- CMP
000678 => x"8034", -- BEQ
000679 => x"bdf9", -- B
000680 => x"c530", -- LDIL
000681 => x"c906", -- LDIH
000682 => x"bf38", -- BL
000683 => x"bf50", -- BL
000684 => x"edca", -- MCR
000685 => x"bf4e", -- BL
000686 => x"edc9", -- MCR
000687 => x"bff0", -- BL
000688 => x"bf3c", -- BL
000689 => x"c53e", -- LDIL
000690 => x"c906", -- LDIH
000691 => x"bf2f", -- BL
000692 => x"bf47", -- BL
000693 => x"02c0", -- MOV
000694 => x"bfe9", -- BL
000695 => x"bf35", -- BL
000696 => x"345d", -- TEQ
000697 => x"8021", -- BEQ
000698 => x"06d1", -- DEC
000699 => x"bf31", -- BL
000700 => x"c0a4", -- LDIL
000701 => x"bf34", -- BL
000702 => x"ee32", -- MRC
000703 => x"bf61", -- BL
000704 => x"ee31", -- MRC
000705 => x"bf5f", -- BL
000706 => x"c0ba", -- LDIL
000707 => x"bf2e", -- BL
000708 => x"c0a0", -- LDIL
000709 => x"bf2c", -- BL
000710 => x"bfc0", -- BL
000711 => x"0260", -- MOV
000712 => x"bf58", -- BL
000713 => x"c320", -- LDIL
000714 => x"c1ae", -- LDIL
000715 => x"00e0", -- MOV
000716 => x"bf25", -- BL
000717 => x"3cc0", -- SFT
000718 => x"c880", -- LDIH
000719 => x"181e", -- CMP
000720 => x"f8c3", -- MVHI
000721 => x"bf20", -- BL
000722 => x"00c0", -- MOV
000723 => x"c880", -- LDIH
000724 => x"181e", -- CMP
000725 => x"f8c3", -- MVHI
000726 => x"bf1b", -- BL
000727 => x"eca0", -- MRC
000728 => x"dc9f", -- STBI
000729 => x"b9df", -- BTS
000730 => x"bf12", -- BL
000731 => x"c69a", -- LDIL
000732 => x"ca80", -- LDIH
000733 => x"3450", -- GT
000734 => x"0d0a", -- .DW
000735 => x"0d0a", -- .DW
000736 => x"4174", -- .DW
000737 => x"6c61", -- .DW
000738 => x"732d", -- .DW
000739 => x"324b", -- .DW
000740 => x"2042", -- .DW
000741 => x"6f6f", -- .DW
000742 => x"746c", -- .DW
000743 => x"6f61", -- .DW
000744 => x"6465", -- .DW
000745 => x"7220", -- .DW
000746 => x"2d20", -- .DW
000747 => x"5632", -- .DW
000748 => x"3031", -- .DW
000749 => x"3430", -- .DW
000750 => x"3432", -- .DW
000751 => x"340d", -- .DW
000752 => x"0a62", -- .DW
000753 => x"7920", -- .DW
000754 => x"5374", -- .DW
000755 => x"6570", -- .DW
000756 => x"6861", -- .DW
000757 => x"6e20", -- .DW
000758 => x"4e6f", -- .DW
000759 => x"6c74", -- .DW
000760 => x"696e", -- .DW
000761 => x"672c", -- .DW
000762 => x"2073", -- .DW
000763 => x"746e", -- .DW
000764 => x"6f6c", -- .DW
000765 => x"7469", -- .DW
000766 => x"6e67", -- .DW
000767 => x"4067", -- .DW
000768 => x"6d61", -- .DW
000769 => x"696c", -- .DW
000770 => x"2e63", -- .DW
000771 => x"6f6d", -- .DW
000772 => x"0d0a", -- .DW
000773 => x"7777", -- .DW
000774 => x"772e", -- .DW
000775 => x"6f70", -- .DW
000776 => x"656e", -- .DW
000777 => x"636f", -- .DW
000778 => x"7265", -- .DW
000779 => x"732e", -- .DW
000780 => x"6f72", -- .DW
000781 => x"672f", -- .DW
000782 => x"7072", -- .DW
000783 => x"6f6a", -- .DW
000784 => x"6563", -- .DW
000785 => x"742c", -- .DW
000786 => x"6174", -- .DW
000787 => x"6c61", -- .DW
000788 => x"735f", -- .DW
000789 => x"636f", -- .DW
000790 => x"7265", -- .DW
000791 => x"0d0a", -- .DW
000792 => x"0000", -- .DW
000793 => x"0d0a", -- .DW
000794 => x"426f", -- .DW
000795 => x"6f74", -- .DW
000796 => x"2070", -- .DW
000797 => x"6167", -- .DW
000798 => x"653a", -- .DW
000799 => x"2030", -- .DW
000800 => x"7800", -- .DW
000801 => x"0d0a", -- .DW
000802 => x"436c", -- .DW
000803 => x"6f63", -- .DW
000804 => x"6b28", -- .DW
000805 => x"487a", -- .DW
000806 => x"293a", -- .DW
000807 => x"2030", -- .DW
000808 => x"7800", -- .DW
000809 => x"426f", -- .DW
000810 => x"6f74", -- .DW
000811 => x"696e", -- .DW
000812 => x"670d", -- .DW
000813 => x"0a00", -- .DW
000814 => x"4275", -- .DW
000815 => x"726e", -- .DW
000816 => x"2045", -- .DW
000817 => x"4550", -- .DW
000818 => x"524f", -- .DW
000819 => x"4d0d", -- .DW
000820 => x"0a00", -- .DW
000821 => x"4177", -- .DW
000822 => x"6169", -- .DW
000823 => x"7469", -- .DW
000824 => x"6e67", -- .DW
000825 => x"2064", -- .DW
000826 => x"6174", -- .DW
000827 => x"612e", -- .DW
000828 => x"2e2e", -- .DW
000829 => x"0d0a", -- .DW
000830 => x"0000", -- .DW
000831 => x"5374", -- .DW
000832 => x"6172", -- .DW
000833 => x"7469", -- .DW
000834 => x"6e67", -- .DW
000835 => x"2069", -- .DW
000836 => x"6d61", -- .DW
000837 => x"6765", -- .DW
000838 => x"2000", -- .DW
000839 => x"446f", -- .DW
000840 => x"776e", -- .DW
000841 => x"6c6f", -- .DW
000842 => x"6164", -- .DW
000843 => x"2063", -- .DW
000844 => x"6f6d", -- .DW
000845 => x"706c", -- .DW
000846 => x"6574", -- .DW
000847 => x"650d", -- .DW
000848 => x"0a00", -- .DW
000849 => x"5061", -- .DW
000850 => x"6765", -- .DW
000851 => x"2028", -- .DW
000852 => x"3468", -- .DW
000853 => x"293a", -- .DW
000854 => x"2024", -- .DW
000855 => x"0000", -- .DW
000856 => x"4164", -- .DW
000857 => x"6472", -- .DW
000858 => x"2028", -- .DW
000859 => x"3868", -- .DW
000860 => x"293a", -- .DW
000861 => x"2024", -- .DW
000862 => x"0000", -- .DW
000863 => x"2377", -- .DW
000864 => x"6f72", -- .DW
000865 => x"6473", -- .DW
000866 => x"2028", -- .DW
000867 => x"3468", -- .DW
000868 => x"293a", -- .DW
000869 => x"2024", -- .DW
000870 => x"0000", -- .DW
000871 => x"4368", -- .DW
000872 => x"6563", -- .DW
000873 => x"6b73", -- .DW
000874 => x"756d", -- .DW
000875 => x"3a20", -- .DW
000876 => x"2400", -- .DW
000877 => x"0d0a", -- .DW
000878 => x"636d", -- .DW
000879 => x"642f", -- .DW
000880 => x"626f", -- .DW
000881 => x"6f74", -- .DW
000882 => x"2d73", -- .DW
000883 => x"7769", -- .DW
000884 => x"7463", -- .DW
000885 => x"683a", -- .DW
000886 => x"0d0a", -- .DW
000887 => x"2030", -- .DW
000888 => x"2f27", -- .DW
000889 => x"3030", -- .DW
000890 => x"273a", -- .DW
000891 => x"2052", -- .DW
000892 => x"6573", -- .DW
000893 => x"7461", -- .DW
000894 => x"7274", -- .DW
000895 => x"2063", -- .DW
000896 => x"6f6e", -- .DW
000897 => x"736f", -- .DW
000898 => x"6c65", -- .DW
000899 => x"0d0a", -- .DW
000900 => x"2031", -- .DW
000901 => x"2f27", -- .DW
000902 => x"3031", -- .DW
000903 => x"273a", -- .DW
000904 => x"2042", -- .DW
000905 => x"6f6f", -- .DW
000906 => x"7420", -- .DW
000907 => x"5541", -- .DW
000908 => x"5254", -- .DW
000909 => x"0d0a", -- .DW
000910 => x"2032", -- .DW
000911 => x"2f27", -- .DW
000912 => x"3130", -- .DW
000913 => x"273a", -- .DW
000914 => x"2042", -- .DW
000915 => x"6f6f", -- .DW
000916 => x"7420", -- .DW
000917 => x"4545", -- .DW
000918 => x"5052", -- .DW
000919 => x"4f4d", -- .DW
000920 => x"0d0a", -- .DW
000921 => x"2033", -- .DW
000922 => x"2f27", -- .DW
000923 => x"3131", -- .DW
000924 => x"273a", -- .DW
000925 => x"2042", -- .DW
000926 => x"6f6f", -- .DW
000927 => x"7420", -- .DW
000928 => x"6d65", -- .DW
000929 => x"6d6f", -- .DW
000930 => x"7279", -- .DW
000931 => x"0d0a", -- .DW
000932 => x"0000", -- .DW
000933 => x"2034", -- .DW
000934 => x"3a20", -- .DW
000935 => x"426f", -- .DW
000936 => x"6f74", -- .DW
000937 => x"2057", -- .DW
000938 => x"420d", -- .DW
000939 => x"0a20", -- .DW
000940 => x"703a", -- .DW
000941 => x"2042", -- .DW
000942 => x"7572", -- .DW
000943 => x"6e20", -- .DW
000944 => x"4545", -- .DW
000945 => x"5052", -- .DW
000946 => x"4f4d", -- .DW
000947 => x"0d0a", -- .DW
000948 => x"2064", -- .DW
000949 => x"3a20", -- .DW
000950 => x"5241", -- .DW
000951 => x"4d20", -- .DW
000952 => x"6475", -- .DW
000953 => x"6d70", -- .DW
000954 => x"0d0a", -- .DW
000955 => x"2072", -- .DW
000956 => x"3a20", -- .DW
000957 => x"5265", -- .DW
000958 => x"7365", -- .DW
000959 => x"740d", -- .DW
000960 => x"0a20", -- .DW
000961 => x"773a", -- .DW
000962 => x"2057", -- .DW
000963 => x"4220", -- .DW
000964 => x"6475", -- .DW
000965 => x"6d70", -- .DW
000966 => x"0d0a", -- .DW
000967 => x"0000", -- .DW
000968 => x"494d", -- .DW
000969 => x"4147", -- .DW
000970 => x"4520", -- .DW
000971 => x"4552", -- .DW
000972 => x"5221", -- .DW
000973 => x"0d0a", -- .DW
000974 => x"0000", -- .DW
000975 => x"0d0a", -- .DW
000976 => x"4952", -- .DW
000977 => x"5120", -- .DW
000978 => x"4552", -- .DW
000979 => x"5221", -- .DW
000980 => x"0d0a", -- .DW
000981 => x"0000", -- .DW
000982 => x"4348", -- .DW
000983 => x"4543", -- .DW
000984 => x"4b53", -- .DW
000985 => x"554d", -- .DW
000986 => x"2045", -- .DW
000987 => x"5252", -- .DW
000988 => x"210d", -- .DW
000989 => x"0a00", -- .DW
000990 => x"5350", -- .DW
000991 => x"492f", -- .DW
000992 => x"4545", -- .DW
000993 => x"5052", -- .DW
000994 => x"4f4d", -- .DW
000995 => x"2045", -- .DW
000996 => x"5252", -- .DW
000997 => x"210d", -- .DW
000998 => x"0a00", -- .DW
000999 => x"5742", -- .DW
001000 => x"2042", -- .DW
001001 => x"5553", -- .DW
001002 => x"2045", -- .DW
001003 => x"5252", -- .DW
001004 => x"210d", -- .DW
001005 => x"0a00", -- .DW
001006 => x"5072", -- .DW
001007 => x"6573", -- .DW
001008 => x"7320", -- .DW
001009 => x"616e", -- .DW
001010 => x"7920", -- .DW
001011 => x"6b65", -- .DW
001012 => x"790d", -- .DW
001013 => x"0a00", -- .DW
000968 => x"636d", -- .DW
000969 => x"643a", -- .DW
000970 => x"3e20", -- .DW
000971 => x"0000", -- .DW
000972 => x"494d", -- .DW
000973 => x"4147", -- .DW
000974 => x"4520", -- .DW
000975 => x"4552", -- .DW
000976 => x"5221", -- .DW
000977 => x"0d0a", -- .DW
000978 => x"0000", -- .DW
000979 => x"0d0a", -- .DW
000980 => x"4952", -- .DW
000981 => x"5120", -- .DW
000982 => x"4552", -- .DW
000983 => x"5221", -- .DW
000984 => x"0d0a", -- .DW
000985 => x"0000", -- .DW
000986 => x"4348", -- .DW
000987 => x"4543", -- .DW
000988 => x"4b53", -- .DW
000989 => x"554d", -- .DW
000990 => x"2045", -- .DW
000991 => x"5252", -- .DW
000992 => x"210d", -- .DW
000993 => x"0a00", -- .DW
000994 => x"5350", -- .DW
000995 => x"492f", -- .DW
000996 => x"4545", -- .DW
000997 => x"5052", -- .DW
000998 => x"4f4d", -- .DW
000999 => x"2045", -- .DW
001000 => x"5252", -- .DW
001001 => x"210d", -- .DW
001002 => x"0a00", -- .DW
001003 => x"5742", -- .DW
001004 => x"2042", -- .DW
001005 => x"5553", -- .DW
001006 => x"2045", -- .DW
001007 => x"5252", -- .DW
001008 => x"210d", -- .DW
001009 => x"0a00", -- .DW
001010 => x"5072", -- .DW
001011 => x"6573", -- .DW
001012 => x"7320", -- .DW
001013 => x"616e", -- .DW
001014 => x"7920", -- .DW
001015 => x"6b65", -- .DW
001016 => x"790d", -- .DW
001017 => x"0a00", -- .DW
others => x"0000" -- NOP
);
);
------------------------------------------------------
 
begin
/atlas_core/trunk/rtl/ATLAS_pkg.vhd
4,7 → 4,7
-- # All architecture configurations, options, signal #
-- # definitions and components are listed here. #
-- # **************************************************** #
-- # Last modified: 19.04.2014 #
-- # Last modified: 29.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
15,18 → 15,18
 
package atlas_core_package is
 
-- Architecture Configuration for Application ---------------------------------------------
-- -------------------------------------------------------------------------------------------
constant big_endian_c : boolean := false; -- use little/big endian memory system
-- Architecture Configuration for Application ---------------------------------------------
-- -------------------------------------------------------------------------------------------
constant big_endian_c : boolean := false; -- use little/big endian memory system
constant build_mul_c : boolean := true; -- build a dedicated MUL unit
constant build_mac_c : boolean := false; -- build a dedicated MAC unit - do not change!
constant build_mul32_c : boolean := true; -- build 32-bit multiplier
constant word_mode_en_c : boolean := false; -- use word-addressed memory system instead of byte-addressed
constant wb_fifo_size_c : natural := 32; -- Wishbone fifo size in words (power of 2!)
constant wb_fifo_size_c : natural := 32; -- Wishbone fifo size in words (power of 2!)
 
---- DO NOT CHANGE ANYTHING BELOW UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ----
 
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 16; -- processing data width
constant data_bytes_c : natural := data_width_c/8; -- processing data width in bytes
constant align_lsb_c : natural := data_bytes_c/2; -- lsb of adr word boundary
41,11 → 41,11
constant branch_slots_en_c : boolean := false; -- use branch delay slots (highly experimental!!!)
constant ldil_sign_ext_c : boolean := true; -- use sign extension when loading low byte
constant reg_branches_en_c : boolean := true; -- synthesize register-based branches
constant cond_moves_en_c : boolean := true; -- synthesize conditional moves
constant cond_moves_en_c : boolean := true; -- synthesize conditional moves
 
 
-- Interrupt/Exception Vectors (word-address) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Interrupt/Exception Vectors (word-address) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
constant res_int_vec_c : std_logic_vector(15 downto 0) := x"0000"; -- use boot address instead!
constant irq0_int_vec_c : std_logic_vector(15 downto 0) := x"0001"; -- external int line 0 IRQ
constant irq1_int_vec_c : std_logic_vector(15 downto 0) := x"0002"; -- external int line 1 IRQ
53,8 → 53,8
constant swi_int_vec_c : std_logic_vector(15 downto 0) := x"0004"; -- software IRQ
 
 
-- Wishbone Bus Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Wishbone Bus Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant wb_classic_cyc_c : std_logic_vector(2 downto 0) := "000"; -- classic cycle
constant wb_con_bst_cyc_c : std_logic_vector(2 downto 0) := "001"; -- constant address burst
constant wb_inc_bst_cyc_c : std_logic_vector(2 downto 0) := "010"; -- incrementing address burst
61,8 → 61,8
constant wb_end_bst_cyc_c : std_logic_vector(2 downto 0) := "111"; -- burst end
 
 
-- Machine Status Register ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Machine Status Register ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant msr_usr_z_flag_c : natural := 0; -- user mode zero flag
constant msr_usr_c_flag_c : natural := 1; -- user mode carry flag
constant msr_usr_o_flag_c : natural := 2; -- user mode overflow flag
81,8 → 81,8
constant msr_mode_flag_c : natural := 15; -- system ('1') / user ('0') mode
 
 
-- Forwarding Bus -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Forwarding Bus -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant fwd_en_c : natural := 0; -- valid register signal
constant fwd_adr_0_c : natural := 1; -- address bit 0
constant fwd_adr_1_c : natural := 2; -- address bit 1
93,8 → 93,8
constant fwd_width_c : natural := 5+data_width_c; -- size of forwarding bus
 
 
-- Flag Bus -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Flag Bus -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant flag_z_c : natural := 0; -- user mode zero flag
constant flag_c_c : natural := 1; -- user mode carry flag
constant flag_o_c : natural := 2; -- user mode overflow flag
103,8 → 103,8
constant flag_bus_width_c : natural := 5; -- size of flag bus
 
 
-- Main Control Bus -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Main Control Bus -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Global Control --
constant ctrl_en_c : natural := 0; -- valid cycle
constant ctrl_mcyc_c : natural := 1; -- un-interruptable/atomic operation
176,16 → 176,16
constant ctrl_mem_bpba_c : natural := 49; -- use bypassed base address
constant ctrl_mem_daa_c : natural := 50; -- use delayed address
 
-- Multiply-and-Acuumulate Unit --
constant ctrl_use_mac_c : natural := 51; -- use MAC unit
constant ctrl_load_mac_c : natural := 52; -- load addition buffer for MAC
-- Multiply Unit --
constant ctrl_use_mul_c : natural := 51; -- use MUL unit
constant ctrl_ext_mul_c : natural := 52; -- get high mul result
constant ctrl_use_offs_c : natural := 53; -- use loaded offset
 
-- Sleep command --
constant ctrl_sleep_c : natural := 54; -- go to sleep
 
-- Conditional write back --
constant ctrl_cond_wb_c : natural := 55; -- is cond write back?
-- Conditional write back --
constant ctrl_cond_wb_c : natural := 55; -- is cond write back?
 
-- -- EX Forwarding --
-- constant ctrl_a_ex_ma_fw_c : natural := 56; -- obsolete
217,8 → 217,8
constant ctrl_msr_am_1_c : natural := ctrl_ra_2_c; -- MSR access mode bit 1
 
 
-- Coprocessor Control Bus ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Coprocessor Control Bus ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cp_cmd_lsb_c : natural := 0; -- command word lsb
constant cp_cmd_msb_c : natural := 2; -- command word msb
constant cp_op_b_lsb_c : natural := 3; -- operand B address lsb
228,8 → 228,8
constant cp_cmd_width_c : natural := 9; -- bus size
 
 
-- Condition Codes ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Condition Codes ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cond_eq_c : std_logic_vector(3 downto 0) := "0000"; -- equal
constant cond_ne_c : std_logic_vector(3 downto 0) := "0001"; -- not equal
constant cond_cs_c : std_logic_vector(3 downto 0) := "0010"; -- unsigned higher or same
248,8 → 248,8
constant cond_al_c : std_logic_vector(3 downto 0) := "1111"; -- always
 
 
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- ALU Function Select --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant fs_inc_c : std_logic_vector(3 downto 0) := "0000"; -- add immediate
constant fs_dec_c : std_logic_vector(3 downto 0) := "0001"; -- subtract immediate
constant fs_add_c : std_logic_vector(3 downto 0) := "0010"; -- add
286,8 → 286,8
constant alu_nand_c : std_logic_vector(2 downto 0) := "111"; -- logical nand
 
 
-- Shifter Control ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Shifter Control ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant sft_swp_c : std_logic_vector(2 downto 0) := "000"; -- swap halfwords
constant sft_asr_c : std_logic_vector(2 downto 0) := "001"; -- arithemtical right shift
constant sft_rol_c : std_logic_vector(2 downto 0) := "010"; -- rotate left
298,8 → 298,8
constant sft_rrc_c : std_logic_vector(2 downto 0) := "111"; -- rotate right through carry
 
 
-- Cool Stuff -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Cool Stuff -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- S: Carrie Underwood - Thank God For The Hometowns
-- M: Precious - Das Leben ist kostbar
-- M: Mean Creek
312,14 → 312,14
-- M: Brantley Gilbert - Bottoms Up
 
 
-- Functions ------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Functions ------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function log2(temp : natural) return natural; -- logarithm base 2
 
 
-- Component: Data Register File ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component REG_FILE
-- Component: Data Register File ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component REG_FILE
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
341,12 → 341,12
OP_B_DATA_O : out std_logic_vector(data_width_c-1 downto 0); -- operand B output
OP_C_DATA_O : out std_logic_vector(data_width_c-1 downto 0) -- operand C output
);
end component;
end component;
 
 
-- Component: Arithmetic/Logic Unit -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component ALU
-- Component: Arithmetic/Logic Unit -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component ALU
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
370,7 → 370,7
MASK_T_FLAG_O : out std_logic; -- T-Flag for mask generation
MSR_DATA_O : out std_logic_vector(data_width_c-1 downto 0); -- MSR write data
ALU_RES_O : out std_logic_vector(data_width_c-1 downto 0); -- ALU result
MAC_RES_O : out std_logic_vector(data_width_c-1 downto 0); -- MAC result
MUL_RES_O : out std_logic_vector(2*data_width_c-1 downto 0); -- MUL result
BP_OPA_O : out std_logic_vector(data_width_c-1 downto 0); -- operand A bypass
BP_OPC_O : out std_logic_vector(data_width_c-1 downto 0); -- operand C bypass
CP_CP0_EN_O : out std_logic; -- access to cp0
381,12 → 381,12
CP_DAT_O : out std_logic_vector(data_width_c-1 downto 0); -- write data
MEM_REQ_O : out std_logic -- data memory access request for next cycle
);
end component;
end component;
 
 
-- Component: Machine Status System -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_REG
-- Component: Machine Status System -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_REG
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
415,16 → 415,16
PC_O : out std_logic_vector(data_width_c-1 downto 0); -- pc output
PC_1D_O : out std_logic_vector(data_width_c-1 downto 0); -- pc 1x delayed
CP_PTC_O : out std_logic; -- user coprocessor protection
COND_TRUE_O : out std_logic; -- condition is true
COND_TRUE_O : out std_logic; -- condition is true
MODE_O : out std_logic; -- current operating mode
MODE_FF_O : out std_logic -- delayed current mode
);
end component;
end component;
 
 
-- Component: Memory Access Control -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component MEM_ACC
-- Component: Memory Access Control -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component MEM_ACC
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
436,7 → 436,7
 
-- Data Input --
ALU_RES_I : in std_logic_vector(data_width_c-1 downto 0); -- alu result
MAC_RES_I : in std_logic_vector(data_width_c-1 downto 0); -- mac result
MUL_RES_I : in std_logic_vector(2*data_width_c-1 downto 0); -- mul result
ADR_BASE_I : in std_logic_vector(data_width_c-1 downto 0); -- op_a bypass
DATA_BP_I : in std_logic_vector(data_width_c-1 downto 0); -- op_b bypass
CP_DATA_I : in std_logic_vector(data_width_c-1 downto 0); -- coprocessor rd data
453,12 → 453,12
MEM_DAT_O : out std_logic_vector(data_width_c-1 downto 0); -- write data output
MEM_RW_O : out std_logic -- read write
);
end component;
end component;
 
 
-- Component: Data Write Back Unit --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component WB_UNIT
-- Component: Data Write Back Unit --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component WB_UNIT
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
477,12 → 477,12
WB_DATA_O : out std_logic_vector(data_width_c-1 downto 0); -- write back data
WB_FWD_O : out std_logic_vector(fwd_width_c-1 downto 0) -- WB stage forwarding path
);
end component;
end component;
 
 
-- Component: Control System --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component CTRL
-- Component: Control System --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component CTRL
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
503,7 → 503,7
WB_CTRL_BUS_O : out std_logic_vector(ctrl_width_c-1 downto 0); -- wb stage control
 
-- Function Control --
COND_TRUE_I : in std_logic; -- condition is true
COND_TRUE_I : in std_logic; -- condition is true
VALID_BRANCH_I : in std_logic; -- valid branch detected
EXC_TAKEN_I : in std_logic; -- exception taken
WAKE_UP_I : in std_logic; -- wake up from sleep
511,12 → 511,12
STOP_PC_O : out std_logic; -- freeze program counter
IR_UPDATE_EN_O : out std_logic -- enable instruction reg update
);
end component;
end component;
 
 
-- Component: Opcode Decoder --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component OP_DEC
-- Component: Opcode Decoder --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component OP_DEC
port (
-- Decoder Interface Input --
INSTR_I : in std_logic_vector(data_width_c-1 downto 0); -- instruction input
531,12 → 531,12
CTRL_O : out std_logic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
IMM_O : out std_logic_vector(data_width_c-1 downto 0) -- immediate
);
end component;
end component;
 
 
-- Component: Atlas CPU Core --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component ATLAS_CPU
-- Component: Atlas CPU Core --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component ATLAS_CPU
port (
-- Global Control --
CLK_I : in std_logic; -- global clock line
572,12 → 572,12
EXT_INT_0_I : in std_logic; -- external interrupt request 0
EXT_INT_1_I : in std_logic -- external interrupt request 1
);
end component;
end component;
 
 
-- Component: System Controller Core 0 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_0_CORE
-- Component: System Controller Core 0 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_0_CORE
port (
-- Host Interface --
CLK_I : in std_logic; -- global clock line
594,11 → 594,11
IRQ_I : in std_logic_vector(07 downto 0); -- irq input
IRQ_O : out std_logic -- interrupt request
);
end component;
end component;
 
-- Component: System Controller Core 1 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_1_CORE
-- Component: System Controller Core 1 ----------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYS_1_CORE
generic (
-- Clock Speed Configuration --
CLK_SPEED_G : std_logic_vector(31 downto 0) := (others => '0') -- clock speed (in Hz)
620,11 → 620,11
MEM_IP_ADR_O : out std_logic_vector(15 downto 0); -- instruction page
MEM_DP_ADR_O : out std_logic_vector(15 downto 0) -- data page
);
end component;
end component;
 
-- Component: Communication Controller Core 0 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component COM_0_CORE
-- Component: Communication Controller Core 0 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component COM_0_CORE
port (
-- Host Interface --
CLK_I : in std_logic; -- global clock line
654,11 → 654,11
SYS_IO_I : in std_logic_vector(07 downto 0); -- system input
SYS_IO_O : out std_logic_vector(07 downto 0) -- system output
);
end component;
end component;
 
-- Component: Communication Controller Core 1 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component COM_1_CORE
-- Component: Communication Controller Core 1 ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component COM_1_CORE
port (
-- Host Interface --
CLK_I : in std_logic; -- global clock line
666,15 → 666,15
ICE_I : in std_logic; -- interface clock enable, high-active
W_EN_I : in std_logic; -- write enable
R_EN_I : in std_logic; -- read enable
CMD_EXE_I : in std_logic; -- execute command
CMD_EXE_I : in std_logic; -- execute command
ADR_I : in std_logic_vector(02 downto 0); -- access address/command
DAT_I : in std_logic_vector(15 downto 0); -- write data
DAT_O : out std_logic_vector(15 downto 0); -- read data
IRQ_O : out std_logic; -- interrupt request
IRQ_O : out std_logic; -- interrupt request
 
-- Wishbone Bus --
WB_CLK_O : out std_logic; -- bus clock
WB_RST_O : out std_logic; -- bus reset, sync, high active
-- Wishbone Bus --
WB_CLK_O : out std_logic; -- bus clock
WB_RST_O : out std_logic; -- bus reset, sync, high active
WB_ADR_O : out std_logic_vector(31 downto 0); -- address
WB_SEL_O : out std_logic_vector(01 downto 0); -- byte select
WB_DATA_O : out std_logic_vector(15 downto 0); -- data out
683,13 → 683,13
WB_CYC_O : out std_logic; -- cycle enable
WB_STB_O : out std_logic; -- strobe
WB_ACK_I : in std_logic; -- acknowledge
WB_ERR_I : in std_logic -- bus error
WB_ERR_I : in std_logic -- bus error
);
end component;
end component;
 
-- Component: System Coprocessor ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYSTEM_CP
-- Component: System Coprocessor ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component SYSTEM_CP
generic (
-- Configuration --
CLOCK_SPEED_G : std_logic_vector(31 downto 0) -- clock speed in Hz
728,9 → 728,9
SYS_IN_I : in std_logic_vector(07 downto 0); -- system input
IRQ_I : in std_logic; -- IRQ
 
-- Wishbone Bus --
WB_CLK_O : out std_logic; -- bus clock
WB_RST_O : out std_logic; -- bus reset, sync, high active
-- Wishbone Bus --
WB_CLK_O : out std_logic; -- bus clock
WB_RST_O : out std_logic; -- bus reset, sync, high active
WB_ADR_O : out std_logic_vector(31 downto 0); -- address
WB_SEL_O : out std_logic_vector(01 downto 0); -- byte select
WB_DATA_O : out std_logic_vector(15 downto 0); -- data out
739,13 → 739,13
WB_CYC_O : out std_logic; -- cycle enable
WB_STB_O : out std_logic; -- strobe
WB_ACK_I : in std_logic; -- acknowledge
WB_ERR_I : in std_logic -- bus error
WB_ERR_I : in std_logic -- bus error
);
end component;
end component;
 
-- Component: Memory Gateway --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component MEM_GATE
-- Component: Memory Gateway --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component MEM_GATE
port (
-- Host Interface --
CLK_I : in std_logic; -- global clock line
784,11 → 784,11
MEM_D_DAT_O : out std_logic_vector(15 downto 0); -- data in
MEM_D_DAT_I : in std_logic_vector(15 downto 0) -- data out
);
end component;
end component;
 
-- Component: Bootloader Memory -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component BOOT_MEM
-- Component: Bootloader Memory -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component BOOT_MEM
port (
-- Host Interface --
CLK_I : in std_logic; -- global clock line
801,14 → 801,14
D_DAT_I : in std_logic_vector(15 downto 0); -- data in
D_DAT_O : out std_logic_vector(15 downto 0) -- data out
);
end component;
end component;
 
end atlas_core_package;
 
package body atlas_core_package is
 
-- Function: Logarithm Base 2 -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Function: Logarithm Base 2 -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function log2(temp : natural) return natural is
variable result : natural;
begin
/atlas_core/trunk/rtl/ATLAS_CPU.vhd
95,7 → 95,7
signal BP_A_DATA : std_logic_vector(data_width_c-1 downto 0); -- operand A bypass
signal BP_C_DATA : std_logic_vector(data_width_c-1 downto 0); -- operand C bypass
signal ALU_RES : std_logic_vector(data_width_c-1 downto 0); -- alu result
signal MAC_RES : std_logic_vector(data_width_c-1 downto 0); -- mac result
signal MUL_RES : std_logic_vector(2*data_width_c-1 downto 0); -- mul result
signal IMMEDIATE : std_logic_vector(data_width_c-1 downto 0); -- immediate value
signal T_FLAG : std_logic; -- transfer flag
signal MA_DATA : std_logic_vector(data_width_c-1 downto 0); -- ma stage result
288,7 → 288,7
MASK_T_FLAG_O => T_FLAG, -- T-Flag for mask generation
MSR_DATA_O => MSR_W_DATA, -- MSR write data
ALU_RES_O => ALU_RES, -- ALU result
MAC_RES_O => MAC_RES, -- MAC result
MUL_RES_O => MUL_RES, -- MUL result
BP_OPA_O => BP_A_DATA, -- operand A bypass
BP_OPC_O => BP_C_DATA, -- operand C bypass
 
320,7 → 320,7
 
-- Data Input --
ALU_RES_I => ALU_RES, -- alu result
MAC_RES_I => MAC_RES, -- mac result
MUL_RES_I => MUL_RES, -- mul result
ADR_BASE_I => BP_A_DATA, -- op_a bypass
DATA_BP_I => BP_C_DATA, -- op_b bypass
CP_DATA_I => CP_DAT_I, -- coprocessor rd data
/atlas_core/trunk/rtl/ALU.vhd
4,7 → 4,7
-- # The main data processing is done here. Also the CP #
-- # interface emerges from this unit. #
-- # **************************************************** #
-- # Last modified: 23.11.2013 #
-- # Last modified: 30.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
55,7 → 55,7
 
MSR_DATA_O : out std_logic_vector(data_width_c-1 downto 0); -- MSR write data
ALU_RES_O : out std_logic_vector(data_width_c-1 downto 0); -- ALU result
MAC_RES_O : out std_logic_vector(data_width_c-1 downto 0); -- MAC result
MUL_RES_O : out std_logic_vector(2*data_width_c-1 downto 0); -- MUL result
BP_OPA_O : out std_logic_vector(data_width_c-1 downto 0); -- operand A bypass
BP_OPC_O : out std_logic_vector(data_width_c-1 downto 0); -- operand C bypass
 
99,7 → 99,8
signal EXTND_ZERO : std_logic;
 
-- Multiplier --
signal MAC_BUF : std_logic_vector(data_width_c-1 downto 0);
signal MUL_OP_A : std_logic_vector(data_width_c-1 downto 0);
signal MUL_OP_B : std_logic_vector(data_width_c-1 downto 0);
 
begin
 
232,7 → 233,7
op_b_v := (others => '0');
cflag_v := '0';
if (EX_CTRL_BUS_I(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_adc_c) or
(EX_CTRL_BUS_I(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_sbc_c) then
(EX_CTRL_BUS_I(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_sbc_c) then
op_a_v := OP_A_INT;
op_b_v := OP_B_INT;
cflag_v := FLAG_BUS_I(flag_c_c);
274,7 → 275,7
 
-- Arithmetic overflow flag --
FU_ARITH_FLG(1) <= ((not add_a_v(data_width_c-1)) and (not add_b_v(data_width_c-1)) and ( adder_tmp_v(data_width_c-1))) or
(( add_a_v(data_width_c-1)) and ( add_b_v(data_width_c-1)) and (not adder_tmp_v(data_width_c-1)));
(( add_a_v(data_width_c-1)) and ( add_b_v(data_width_c-1)) and (not adder_tmp_v(data_width_c-1)));
end process FU_ARITHMETIC_CORE;
 
 
351,8 → 352,8
when alu_eor_c => FU_LOGIC_RES <= OP_A_INT xor OP_B_INT;
when alu_bic_c => FU_LOGIC_RES <= OP_A_INT and (not OP_B_INT);
when others => FU_LOGIC_RES <= (others => '0');
FU_LOGIC_FLG(0) <= '0';
FU_LOGIC_FLG(1) <= '0';
FU_LOGIC_FLG(0) <= '0';
FU_LOGIC_FLG(1) <= '0';
end case;
end process FU_LOGIC_CORE;
 
409,62 → 410,26
 
 
 
-- MAC Operand Buffer ----------------------------------------------------------------------------------
-- Mltiplier Kernel ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
MAC_BUFFER: process(CLK_I)
-- Operand gating --
MUL_OP_A <= OP_A_INT when ((build_mul_c = true) and (EX_CTRL_BUS_I(ctrl_use_mul_c) = '1')) else (others => '0');
MUL_OP_B <= OP_B_INT when ((build_mul_c = true) and (EX_CTRL_BUS_I(ctrl_use_mul_c) = '1')) else (others => '0');
 
-- Multiplier core --
MUL_BUFFER: process(CLK_I)
begin
if rising_edge(CLK_I) then
if (RST_I = '1') then
MAC_BUF <= (others => '0');
MUL_RES_O <= (others => '0');
elsif (CE_I = '1') then
if (EX_CTRL_BUS_I(ctrl_load_mac_c) = '1') and (EX_CTRL_BUS_I(ctrl_en_c) = '1') and (build_mac_c = true) then -- load mac buffer
MAC_BUF <= OP_C_I;
else
MAC_BUF <= (others => '0');
end if;
MUL_RES_O <= std_logic_vector(unsigned(MUL_OP_A) * unsigned(MUL_OP_B));
end if;
end if;
end process MAC_BUFFER;
end process MUL_BUFFER;
 
 
 
-- MAC Kernel ------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
MULTIPLIER: process(EX_CTRL_BUS_I, OP_A_INT, OP_B_INT, MAC_BUF)
variable mul_op_a_v : std_logic_vector(data_width_c-1 downto 0);
variable mul_op_b_v : std_logic_vector(data_width_c-1 downto 0);
variable mul_res_v : std_logic_vector(2*data_width_c-1 downto 0);
variable mac_ofs_v : std_logic_vector(data_width_c-1 downto 0);
begin
-- Operand Gating --
mul_op_a_v := (others => '0');
mul_op_b_v := (others => '0');
if (build_mul_c = true) and (EX_CTRL_BUS_I(ctrl_use_mac_c) = '1') then
mul_op_a_v := OP_A_INT;
mul_op_b_v := OP_B_INT;
end if;
 
-- Multiplier Core --
mul_res_v := (others => '0');
if (build_mul_c = true) then
mul_res_v := std_logic_vector(unsigned(mul_op_a_v) * unsigned(mul_op_b_v));
end if;
 
-- Offset --
mac_ofs_v := (others => '0');
if (EX_CTRL_BUS_I(ctrl_use_offs_c) = '1') and (build_mac_c = true) then
mac_ofs_v := MAC_BUF;
end if;
 
-- Accumulate --
MAC_RES_O <= mul_res_v(data_width_c-1 downto 0);
if (build_mac_c = true) then
MAC_RES_O <= std_logic_vector(unsigned(mul_res_v(data_width_c-1 downto 0)) + unsigned(mac_ofs_v));
end if;
end process MULTIPLIER;
 
 
 
-- Module Data Output ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
/atlas_core/trunk/rtl/MEM_ACC.vhd
5,7 → 5,7
-- # data memory interface. Furthermore, internal data #
-- # switching networks are located here. #
-- # **************************************************** #
-- # Last modified: 01.02.2014 #
-- # Last modified: 29.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
38,7 → 38,7
-- ###############################################################################################
 
ALU_RES_I : in std_logic_vector(data_width_c-1 downto 0); -- alu result
MAC_RES_I : in std_logic_vector(data_width_c-1 downto 0); -- mac result
MUL_RES_I : in std_logic_vector(2*data_width_c-1 downto 0); -- mul result
ADR_BASE_I : in std_logic_vector(data_width_c-1 downto 0); -- op_a bypass
DATA_BP_I : in std_logic_vector(data_width_c-1 downto 0); -- op_b bypass
CP_DATA_I : in std_logic_vector(data_width_c-1 downto 0); -- coprocessor rd data
69,7 → 69,6
 
-- Pipeline register --
signal ALU_RES_FF : std_logic_vector(data_width_c-1 downto 0);
signal MAC_RES_FF : std_logic_vector(data_width_c-1 downto 0);
signal ADR_BASE_FF : std_logic_vector(data_width_c-1 downto 0);
signal DATA_BP_FF : std_logic_vector(data_width_c-1 downto 0);
 
81,6 → 80,7
signal ALU_MAC_DAT : std_logic_vector(data_width_c-1 downto 0);
signal SYS_CP_R_DAT : std_logic_vector(data_width_c-1 downto 0);
signal SYS_CP_ALU_R_DAT : std_logic_vector(data_width_c-1 downto 0);
signal MUL_RES_INT : std_logic_vector(data_width_c-1 downto 0);
 
begin
 
91,13 → 91,11
if rising_edge(CLK_I) then
if (RST_I = '1') then
ALU_RES_FF <= (others => '0');
MAC_RES_FF <= (others => '0');
ADR_BASE_FF <= (others => '0');
DATA_BP_FF <= (others => '0');
ALU_RES_BUF <= (others => '0');
elsif (CE_I = '1') then
ALU_RES_FF <= ALU_RES_I;
MAC_RES_FF <= MAC_RES_I;
ADR_BASE_FF <= ADR_BASE_I;
DATA_BP_FF <= DATA_BP_I;
ALU_RES_BUF <= ALU_RES_FF;
164,15 → 162,24
 
-- Stage Data Multiplexer ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
no_mac_mul_units: -- syntheszie no MAC and no MUL unit
if (build_mul_c = false) and (build_mac_c = false) generate
no_mul_unit: -- syntheszie no MUL unit at all
if (build_mul_c = false) generate
MUL_RES_INT <= (others => '0');
ALU_MAC_DAT <= ALU_RES_FF;
end generate no_mac_mul_units;
synhesize_mac_mul_units: -- synthesize MAC and/or MUL unit
if (build_mul_c = true) or (build_mac_c = true) generate
ALU_MAC_DAT <= MAC_RES_FF when (MA_CTRL_BUS_I(ctrl_use_mac_c) = '1') else ALU_RES_FF;
end generate synhesize_mac_mul_units;
end generate no_mul_unit;
 
synhesize_mul16_unit: -- synthesize 16-bit MUL unit
if (build_mul_c = true) and (build_mul32_c = false) generate
MUL_RES_INT <= (others => '0');
ALU_MAC_DAT <= MUL_RES_I(15 downto 0) when (MA_CTRL_BUS_I(ctrl_use_mul_c) = '1') else ALU_RES_FF;
end generate synhesize_mul16_unit;
 
synhesize_mul32_unit: -- synthesize 32-bit MUL unit
if (build_mul_c = true) and (build_mul32_c = true) generate
MUL_RES_INT <= MUL_RES_I(31 downto 16) when (MA_CTRL_BUS_I(ctrl_ext_mul_c) = '1') else MUL_RES_I(15 downto 0);
ALU_MAC_DAT <= MUL_RES_INT when (MA_CTRL_BUS_I(ctrl_use_mul_c) = '1') else ALU_RES_FF;
end generate synhesize_mul32_unit;
 
-- Coprocessor input --
SYS_CP_R_DAT <= CP_DATA_I when (MA_CTRL_BUS_I(ctrl_rd_cp_acc_c) = '1') else RD_MSR_I;
 
/atlas_core/trunk/rtl/OP_DEC.vhd
1,9 → 1,9
-- ########################################################
-- # << ATLAS Project - OpCode Decoder >> #
-- # **************************************************** #
-- # OpCode decoding unit. #
-- # OpCode (instruction) decoding unit. #
-- # **************************************************** #
-- # Last modified: 19.04.2014 #
-- # Last modified: 30.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
91,7 → 91,7
CTRL_O(ctrl_rd_3_c downto ctrl_rd_0_c) <= M_FLAG_I & INSTR_INT(9 downto 7); -- destination register
CTRL_O(ctrl_cond_3_c downto ctrl_cond_0_c) <= INSTR_INT(13 downto 10); -- branch condition
 
-- both operands have same addresses --
-- both operands have same addresses? --
redundant_reg_v := '0';
if (INSTR_INT(6 downto 4) = INSTR_INT(2 downto 0)) then
redundant_reg_v := '1';
430,29 → 430,41
-- ==============================================================================
case (INSTR_INT(11 downto 10)) is
 
when "00" => -- Class 3c0: Multiply-and-Accumulate
when "00" => -- Class 3c0: Multiplication
-- --------------------------------------------------------------------------------
CTRL_O(ctrl_rd_wb_c) <= '1'; -- allow write back
if (INSTR_INT(3) = '1') then -- MAC
if (build_mac_c = true) then -- unit present?
if (MULTI_CYC_I = '0') then -- fist cycle: load MAC buffer
CTRL_O(ctrl_rb_3_c downto ctrl_rb_0_c) <= M_FLAG_I & INSTR_INT(9 downto 7); -- mac offset
CTRL_O(ctrl_load_mac_c) <= '1'; -- load mac buffer
MULTI_CYC_REQ_O <= '1'; -- prepare second cycle
else -- second cycle: MUL operation with offset = MAC
CTRL_O(ctrl_use_offs_c) <= '1'; -- use loaded offset
CTRL_O(ctrl_use_mac_c) <= '1'; -- use mac unit
end if;
if (INSTR_INT(3) = '1') then -- MUL32
if (build_mul_c = true) and (build_mul32_c = true) then -- unit present?
CTRL_O(ctrl_ext_mul_c) <= '1'; -- use high result
CTRL_O(ctrl_use_mul_c) <= '1'; -- use mul unit
CTRL_O(ctrl_rd_wb_c) <= '1'; -- allow write back
else -- not present
CTRL_O(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
end if;
else -- MUL
else -- MUL16
if (build_mul_c = true) then -- unit present?
CTRL_O(ctrl_use_mac_c) <= '1'; -- use mac unit
CTRL_O(ctrl_use_mul_c) <= '1'; -- use mul unit
CTRL_O(ctrl_rd_wb_c) <= '1'; -- allow write back
else -- not present
CTRL_O(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
end if;
end if;
if (INSTR_INT(3) = '1') then -- MUL32
if (build_mul_c = true) and (build_mul32_c = true) then -- unit present?
CTRL_O(ctrl_ext_mul_c) <= '1'; -- use high result
CTRL_O(ctrl_use_mul_c) <= '1'; -- use mul unit
CTRL_O(ctrl_rd_wb_c) <= '1'; -- allow write back
else -- not present
CTRL_O(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
end if;
else -- MUL16
if (build_mul_c = true) then -- unit present?
CTRL_O(ctrl_use_mul_c) <= '1'; -- use mul unit
CTRL_O(ctrl_rd_wb_c) <= '1'; -- allow write back
else -- not present
CTRL_O(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
end if;
end if;
 
 
when "01" => -- Class 3c1: Special (Sleep, Reg-based branch)
/atlas_core/trunk/doc/Atlas 2k Processor Documentary.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/atlas_core/trunk/sim/xilinx_isim_atlas_2k_base_tb_wave.wcfg
12,7 → 12,7
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="155" />
<WVObjectSize size="156" />
<wvobject fp_name="divider11" type="divider">
<obj_property name="label">Global Control</obj_property>
<obj_property name="DisplayName">label</obj_property>
147,6 → 147,11
<obj_property name="ObjectShortName">flag_bus_o[4:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atlas_2k_base_tb/DUT/the_core_of_the_problem/cpu_core/Executor/fu_arith_res" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fu_arith_res[15:0]</obj_property>
<obj_property name="ObjectShortName">fu_arith_res[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/atlas_2k_base_tb/DUT/the_core_of_the_problem/cpu_core/Executor/alu_res_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">alu_res_o[15:0]</obj_property>
<obj_property name="ObjectShortName">alu_res_o[15:0]</obj_property>
/atlas_core/trunk/software/bootloader/atlas2k_bootloader.asm
649,6 → 649,10
bl uart_linebreak
ldil r1, #36 ; '$'
bl uart_sendbyte
mrc #1, r4, sys1_core, #2 ; get d-page
bl print_hex_string ; print 4hex page
ldil r1, #'.' ; ' '
bl uart_sendbyte
mov r4, r5
bl print_hex_string ; print 4hex byte address
ldil r1, #58 ; ':'
1347,7 → 1351,7
; *****************************************************************************************************************
; ROM: Text strings
; *****************************************************************************************************************
string_intro0: .stringz "\n\nAtlas-2K Bootloader - V20140419\nby Stephan Nolting, stnolting@gmail.com\nwww.opencores.org/project,atlas_core\n"
string_intro0: .stringz "\n\nAtlas-2K Bootloader - V20140424\nby Stephan Nolting, stnolting@gmail.com\nwww.opencores.org/project,atlas_core\n"
string_intro3: .stringz "\nBoot page: 0x"
string_intro4: .stringz "\nClock(Hz): 0x"
 
/atlas_core/web_uploads/instruction_set_card.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.