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    from Rev 316 to Rev 317
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Rev 316 → Rev 317

/t48/trunk/rtl/vhdl/t48_comp_pack-p.vhd
155,8 → 155,10
ibf_int_i : in boolean;
en_dma_i : in boolean;
en_flags_i : in boolean;
write_p2_i : in boolean;
mint_ibf_n_o : out std_logic;
mint_obf_o : out std_logic;
dma_o : out boolean;
drq_o : out std_logic;
dack_n_i : in std_logic;
a0_i : in std_logic;
/t48/trunk/rtl/vhdl/upi41_core.vhd
161,6 → 161,7
signal bus_write_sts_s : boolean;
signal bus_mint_ibf_n_s : std_logic;
signal bus_mint_obf_s : std_logic;
signal bus_dma_s : boolean;
signal bus_drq_s : std_logic;
 
-- Clock Controller signals
204,6 → 205,7
 
-- Port 2 signals
signal p2_s : word_t;
signal p26_s : std_logic;
signal p2_write_p2_s : boolean;
signal p2_write_exp_s : boolean;
signal p2_read_p2_s : boolean;
375,8 → 377,10
ibf_int_i => bus_ibf_int_s,
en_dma_i => bus_en_dma_s,
en_flags_i => bus_en_flags_s,
write_p2_i => p2_write_p2_s,
mint_ibf_n_o => bus_mint_ibf_n_s,
mint_obf_o => bus_mint_obf_s,
dma_o => bus_dma_s,
drq_o => bus_drq_s,
dack_n_i => p2_i(7),
a0_i => a0_i,
561,7 → 565,12
p2h_low_imp_o => p2h_low_imp_o
);
 
p2_o <= p2_s and '1' & bus_drq_s & bus_mint_ibf_n_s & bus_mint_obf_s & "1111";
p26_s <= p2_s(6) when not bus_dma_s else bus_drq_s;
p2_o <= p2_s(7)
& p26_s
& (p2_s(5) and bus_mint_ibf_n_s)
& (p2_s(4) and bus_mint_obf_s)
& p2_s(3 downto 0);
 
pmem_ctrl_b : t48_pmem_ctrl
port map (
/t48/trunk/rtl/vhdl/upi41_db_bus.vhd
73,8 → 73,11
ibf_int_i : in boolean;
en_dma_i : in boolean;
en_flags_i : in boolean;
-- P2 interface -----------------------------------------------------------
write_p2_i : in boolean;
mint_ibf_n_o : out std_logic;
mint_obf_o : out std_logic;
dma_o : out boolean;
drq_o : out std_logic;
dack_n_i : in std_logic;
-- BUS Interface ----------------------------------------------------------
102,6 → 105,8
write_s, write_q,
read_pulse_s, write_pulse_s : boolean;
 
signal a0_q : std_logic;
 
signal ibf_q, obf_q : std_logic;
 
-- the BUS output register
113,6 → 118,9
signal dma_q,
flags_q : boolean;
 
signal ext_acc_s : boolean;
signal dack_s : boolean;
 
begin
 
-- pragma translate_off
131,8 → 139,10
-- Purpose:
-- Generate read and write pulses based on master access.
--
read_s <= cs_n_i = '0' and rd_n_i = '0';
write_s <= cs_n_i = '0' and wr_n_i = '0';
dack_s <= dack_n_i = '0' and dma_q;
ext_acc_s <= cs_n_i = '0' or dack_s;
read_s <= ext_acc_s and rd_n_i = '0';
write_s <= ext_acc_s and wr_n_i = '0';
--
master_access: process (res_i, clk_i)
begin
140,6 → 150,7
read_q <= false;
read_hold_q <= false;
write_q <= false;
a0_q <= '0';
 
elsif clk_i'event and clk_i = clk_active_c then
read_q <= read_s;
147,10 → 158,16
 
if read_s then
read_hold_q <= true;
elsif cs_n_i = '1' then
elsif ext_acc_s then
read_hold_q <= false;
end if;
 
if dack_s then
a0_q <= '0';
elsif read_s or write_s then
a0_q <= a0_i;
end if;
 
end if;
end process master_access;
--
166,18 → 183,19
bus_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
dbbin_q <= (others => '0');
dbbout_q <= (others => '0');
sts_q <= (others => '0');
ibf_q <= '0';
obf_q <= '0';
int_n_o <= '1';
dma_q <= false;
flags_q <= false;
dbbin_q <= (others => '0');
dbbout_q <= (others => '0');
sts_q <= (others => '0');
ibf_q <= '0';
obf_q <= '0';
int_n_o <= '1';
dma_q <= false;
drq_o <= '0';
flags_q <= false;
 
elsif clk_i'event and clk_i = clk_active_c then
-- master access
if read_pulse_s and a0_i = '0' then
if read_pulse_s and a0_q = '0' then
obf_q <= '0';
elsif write_pulse_s then
dbbin_q <= db_i;
202,10 → 220,17
if is_type_a_g = 1 then
if en_dma_i then
dma_q <= true;
drq_o <= '0';
end if;
if en_flags_i then
flags_q <= true;
end if;
 
if dack_s then
drq_o <= '0';
elsif dma_q and write_p2_i and data_i(6) = '1' then
drq_o <= '1';
end if;
end if;
 
end if;
220,14 → 245,14
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
set_f1_o <= write_pulse_s and a0_i = '1';
clear_f1_o <= write_pulse_s and a0_i = '0';
set_f1_o <= write_pulse_s and a0_q = '1';
clear_f1_o <= write_pulse_s and a0_q = '0';
ibf_o <= ibf_q;
obf_o <= obf_q;
db_o <= dbbout_q when a0_i = '0' else
db_o <= dbbout_q when a0_q = '0' else
sts_q & f1_i & f0_i & ibf_q & obf_q when is_type_a_g = 1 else
"0000" & f1_i & f0_i & ibf_q & obf_q;
db_dir_o <= '1' when cs_n_i = '0' and read_hold_q else '0';
db_dir_o <= '1' when ext_acc_s and read_hold_q else '0';
data_o <= dbbin_q
when read_bus_i else
(others => bus_idle_level_c);
235,8 → 260,6
mint_ibf_n_o <= '0' when flags_q and ibf_q = '1' else '1';
mint_obf_o <= '0' when flags_q and obf_q = '0' else '1';
 
-- TODO
drq_o <= '0' when dma_q else '1';
-- dack_n_i
dma_o <= dma_q;
 
end rtl;

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