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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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    from Rev 324 to Rev 325
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Rev 324 → Rev 325

/open8_urisc/trunk/VHDL/o8_mavg_8ch_16b_64d.vhd
70,10 → 70,10
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic;
signal Addr_Match : std_logic := '0';
 
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
127,7 → 127,7
 
signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
 
signal AVG_Out : std_logic_vector(15 downto 0);
signal AVG_Out : std_logic_vector(15 downto 0) := (others => '0');
alias AVG_Out_L is AVG_Out(7 downto 0);
alias AVG_Out_H is AVG_Out(7 downto 0);
 

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