URL https://opencores.org/ocsvn/atlas_core/atlas_core/trunk

Subversion Repositories atlas_core

Compare Revisions

This comparison shows the changes necessary to convert path
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from Rev 34 to Rev 35
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 34 → Rev 35

/atlas_core/trunk/rtl/BOOT_MEM.vhd

3,7 → 3,7

15,1079 → 15,1076

/atlas_core/trunk/rtl/CTRL.vhd

4,7 → 4,7

16,277 → 16,284

/atlas_core/trunk/rtl/ATLAS_pkg.vhd

4,7 → 4,7

17,176 → 17,176

195,613 → 195,613

810,16 → 810,16

/atlas_core/trunk/rtl/COM_0_CORE.vhd

6,7 → 6,7

18,476 → 18,476

/atlas_core/trunk/rtl/SYS_0_CORE.vhd

5,7 → 5,7

17,270 → 17,270

/atlas_core/trunk/rtl/SYS_1_CORE.vhd

4,7 → 4,7

16,183 → 16,183

/atlas_core/trunk/rtl/COM_1_CORE.vhd

6,7 → 6,7

18,379 → 18,379

/atlas_core/trunk/rtl/SYSTEM_CP.vhd

3,7 → 3,7

15,311 → 15,311

/atlas_core/trunk/rtl/WB_UNIT.vhd

3,7 → 3,7

15,117 → 15,117

/atlas_core/trunk/rtl/SYS_REG.vhd

6,7 → 6,7

18,402 → 18,402

/atlas_core/trunk/rtl/ATLAS_CPU.vhd

4,7 → 4,7

16,351 → 16,349

/atlas_core/trunk/rtl/ATLAS_2K_BASE_TOP.vhd

11,7 → 11,7

23,273 → 23,269

/atlas_core/trunk/rtl/REG_FILE.vhd

5,7 → 5,7

17,95 → 17,95

/atlas_core/trunk/rtl/MEM_GATE.vhd

4,7 → 4,7

16,95 → 16,90

/atlas_core/trunk/rtl/ALU.vhd

4,7 → 4,7

16,447 → 16,447

/atlas_core/trunk/rtl/ATLAS_2K_TOP.vhd

4,7 → 4,7

16,324 → 16,316

/atlas_core/trunk/rtl/MEM_ACC.vhd

5,7 → 5,7

18,188 → 18,188

/atlas_core/trunk/rtl/OP_DEC.vhd

3,7 → 3,7

15,512 → 15,512

/atlas_core/trunk/rtl/INT_RAM.vhd

3,7 → 3,7

15,86 → 15,83

/atlas_core/trunk/sim/atlas_2k_base_tb.vhd

12,173 → 12,173

/atlas_core/trunk/sim/xilinx_isim_atlas_2k_base_tb_wave.wcfg

45,28 → 45,28

111,6 → 111,10

157,11 → 161,6

/atlas_core/trunk/software/bootloader/init.vhd

0,0 → 1,1016

/atlas_core/trunk/software/bootloader/boot_init.vhd

0,0 → 1,1024

/atlas_core/trunk/software/bootloader/atlas2k_bootloader.asm

867,9 → 867,9

/atlas_core/trunk/software/bootloader/out.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/atlas_core/trunk/software/bootloader/out.bin

atlas_core/trunk/software/bootloader/out.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: atlas_core/trunk/software/examples/fft/pre_processor.asm =================================================================== --- atlas_core/trunk/software/examples/fft/pre_processor.asm (nonexistent) +++ atlas_core/trunk/software/examples/fft/pre_processor.asm (revision 35) @@ -0,0 +1,979 @@ +RESET_VEC: B RESET +X_INT0_VEC: B ERR_HANDLER +X_INT1_VEC: B ERR_HANDLER +CMD_ERR_VEC: B ERR_HANDLER +SWI_VEC: B ERR_HANDLER +ERR_HANDLER: BL UART_LINEBREAK +LDIL R2 LOW[ERR_STRING] +LDIH R2 HIGH[ERR_STRING] +BL UART_PRINT +BL UART_LINEBREAK +B #+0 +RESET: LDIL SP LOW[STACK_END] +LDIH SP HIGH[STACK_END] +LDIL R2 LOW[STRING_INTRO] +LDIH R2 HIGH[STRING_INTRO] +BL UART_PRINT +LDIL R0 #0XFF +MCR #1 SYS0_CORE R0 #3 +LDIL R0 #2 +MCR #1 SYS0_CORE R0 #4 +LDIL R0 LOW[FFT_N_C] +LDIH R0 HIGH[FFT_N_C] +LDIL R7 LOW[MATH_LOG2] +LDIH R7 HIGH[MATH_LOG2] +GTL R7 +PUSH R0 +LDIL R5 LOW[INPUT_SIGNAL] +LDIH R5 HIGH[INPUT_SIGNAL] +LDIL R2 LOW[FFT_RAM] +LDIH R2 HIGH[FFT_RAM] +CLR R3 #0 +FFT_STORE_LOOP: LDR R0 R5 +#2 POST ! +LDIL R1 #0X00 +PEEK R4 +LDIL R7 LOW[STORE_FFT_SAMPLE] +LDIH R7 HIGH[STORE_FFT_SAMPLE] +GTL R7 +INC R3 R3 #1 +LDIL R0 LOW[FFT_N_C] +LDIH R0 HIGH[FFT_N_C] +CMP R3 R0 +BNE FFT_STORE_LOOP +POP R0 +CLR R5 +MCR #1 SYS0_CORE R5 #2 +LDIL R0 LOW[FFT_RAM] +LDIH R0 HIGH[FFT_RAM] +LDIL R1 LOW[FFT_N_C] +LDIH R1 HIGH[FFT_N_C] +LDIL R2 LOW[FFT_SINCOS_LUT] +LDIH R2 HIGH[FFT_SINCOS_LUT] +BL MATH_FFT +MRC #1 R4 SYS0_CORE #2 +BL PRINT_HEX_STRING +BL UART_LINEBREAK +LDIL R5 LOW[FFT_RAM] +LDIH R5 HIGH[FFT_RAM] +LDIL R3 LOW[FFT_N_C] +LDIH R3 HIGH[FFT_N_C] +PRINT_RESULTS: LDR R4 R5 +#2 POST ! +BL PRINT_HEX_STRING +LDIL R1 #32 +BL UART_SENDBYTE +LDR R4 R5 +#2 POST ! +BL PRINT_HEX_STRING +BL UART_LINEBREAK +DECS R3 R3 #1 +BNE PRINT_RESULTS +B #+0 +UART_SENDBYTE: MRC #1 R0 COM0_CORE #2 +STB R0 #5 +BTS UART_SENDBYTE +MCR #1 COM0_CORE R1 #0 +RET LR +UART_RECEIVEBYTE: MRC #1 R0 COM0_CORE #0 +STBI R0 #15 +BTS UART_RECEIVEBYTE +LDIH R0 #0X00 +RET LR +PRINT_HEX_STRING: PUSH R0 +PUSH R1 +PUSH R2 +PUSH R3 +PUSH R4 +PUSH LR +SFT R2 R4 #ROL +SFT R2 R2 #ROL +SFT R2 R2 #ROL +SFT R2 R2 #ROL +BL CONV_HEX_COMP +BL UART_SENDBYTE +SFT R2 R4 #SWP +BL CONV_HEX_COMP +BL UART_SENDBYTE +SFT R2 R4 #LSR +SFT R2 R2 #LSR +SFT R2 R2 #LSR +SFT R2 R2 #LSR +BL CONV_HEX_COMP +BL UART_SENDBYTE +MOV R2 R4 +BL CONV_HEX_COMP +BL UART_SENDBYTE +POP LR +POP R4 +POP R3 +POP R2 +POP R1 +POP R0 +RET LR +CONV_HEX_COMP: LDIL R1 #0X0F +AND R2 R2 R1 +LDIL R1 #9 +CMP R1 R2 +BCS #+3 +LDIL R1 #48 +B #+2 +LDIL R1 #55 +ADD R1 R1 R2 +RET LR +UART_LINEBREAK: PUSH R0 +PUSH R1 +PUSH R2 +PUSH LR +MOV R2 LR +LDIL R1 #0X0D +BL UART_SENDBYTE +LDIL R1 #0X0A +MOV LR R2 +BL UART_SENDBYTE +POP LR +POP R2 +POP R1 +POP R0 +RET LR +UART_PRINT: MOV R4 LR +UART_PRINT_LOOP: LDR R0 R2 +#1 POST ! +LDIL R1 #0X00 +LDIH R1 #0XFF +AND R1 R0 R1 +SFTS R1 R1 #SWP +BEQ UART_PRINT_LOOP_END +BL UART_SENDBYTE +B UART_PRINT_LOOP +UART_PRINT_LOOP_END: RET R4 +MATH_FFT: PUSH R5 +PUSH R4 +PUSH R3 +PUSH R2 +PUSH R1 +PUSH R0 +PUSH LR +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +STR R0 R7 -#6 PRE +STR R1 R7 -#2 PRE +STR R2 R7 -#4 PRE +CLR R0 +MATH_FFT_GET_LVS: SFT R1 R1 #LSR +TEQ R1 R1 +BEQ #+3 +INC R0 R0 #1 +B MATH_FFT_GET_LVS +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +STR R0 R7 +#0 PRE +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +LDIL R5 #1 +STR R5 R7 +#2 PRE +STR R5 R7 +#4 PRE +STR R5 R7 +#6 PRE +LDIL R7 LOW[V_MATH_FFT_A_OFFS] +LDIH R7 HIGH[V_MATH_FFT_A_OFFS] +LDIL R5 #0 +STR R5 R7 +#0 PRE +MATH_FFT_LEVEL: LDIL R7 LOW[V_MATH_FFT_DFT] +LDIH R7 HIGH[V_MATH_FFT_DFT] +LDR R1 R7 -#2 PRE +LDR R2 R7 +#0 PRE +DEC R2 R2 #1 +LDIL R4 #4 +SFT R4 R4 #LSL +DECS R1 R1 #1 +BNE #-2 +MUL R2 R2 R4 +STR R2 R7 +#4 PRE +MATH_FFT_BUTTERFLY: LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +LDR R4 R7 -#6 PRE +LDR R1 R7 +#2 PRE +LDR R2 R7 +#6 PRE +LDR R3 R7 -#4 PRE +DEC R2 R2 #1 +SFT R2 R2 #LSL +SFT R2 R2 #LSL +ADD R2 R3 R2 +LDIL R7 LOW[V_MATH_FFT_A_OFFS] +LDIH R7 HIGH[V_MATH_FFT_A_OFFS] +LDR R0 R7 +#0 PRE +ADD R0 R0 R4 +LDIL R3 #2 +SFT R3 R3 #LSL +DECS R1 R1 #1 +BNE #-2 +ADD R1 R0 R3 +LDIL R7 LOW[V_MATH_FFT_A_PNT] +LDIH R7 HIGH[V_MATH_FFT_A_PNT] +STR R0 R7 +#0 PRE +STR R1 R7 +#2 PRE +STR R2 R7 +#4 PRE +MOV R3 R0 +MOV R4 R1 +MOV R5 R2 +PUSH R3 +PUSH R4 +LDR R0 R3 +#0 PRE +LDR R1 R3 +#2 PRE +LDR R2 R4 +#0 PRE +LDR R3 R4 +#2 PRE +LDR R4 R5 +#0 PRE +LDR R5 R5 +#2 PRE +BL FFT_BUTTERFLY +POP R5 +POP R4 +STR R2 R5 +#0 PRE +STR R3 R5 +#2 PRE +STR R0 R4 +#0 PRE +STR R1 R4 +#2 PRE +LDIL R7 LOW[V_MATH_FFT_A_OFFS] +LDIH R7 HIGH[V_MATH_FFT_A_OFFS] +LDR R0 R7 +#0 PRE +LDIL R1 #4 +ADD R0 R0 R1 +STR R0 R7 +#0 PRE +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +LDR R0 R7 +#2 PRE +LDR R2 R7 +#6 PRE +LDIL R1 #1 +DECS R0 R0 #1 +BEQ #+3 +SFT R1 R1 #LSL +B #-3 +CMP R1 R2 +INC R2 R2 #1 +STR R2 R7 +#6 PRE +BNE MATH_FFT_BUTTERFLY +LDIL R2 #1 +STR R2 R7 +#6 PRE +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +LDR R0 R7 -#2 PRE +LDR R1 R7 +#2 PRE +LDR R2 R7 +#4 PRE +SFT R0 R0 #LSR +DECS R1 R1 #1 +BNE #-2 +CMP R0 R2 +INC R2 R2 #1 +STR R2 R7 +#4 PRE +BNE MATH_FFT_LEVEL +LDIL R2 #1 +STR R2 R7 +#4 PRE +LDIL R7 LOW[V_MATH_FFT_NUM_LEVELS] +LDIH R7 HIGH[V_MATH_FFT_NUM_LEVELS] +LDR R0 R7 +#0 PRE +LDR R1 R7 +#2 PRE +CMP R0 R1 +INC R1 R1 #1 +STR R1 R7 +#2 PRE +BNE MATH_FFT_LEVEL +POP LR +POP R0 +POP R1 +POP R2 +POP R3 +POP R4 +POP R5 +RET LR +V_MATH_FFT_SIG_PNT: NOP +V_MATH_SINCOS_PNT: NOP +V_MATH_FFT_NUM_POINTS: NOP +V_MATH_FFT_NUM_LEVELS: NOP +V_MATH_FFT_LEVEL: NOP +V_MATH_FFT_DFT: NOP +V_MATH_FFT_BTFLY: NOP +V_MATH_FFT_A_OFFS: NOP +V_MATH_FFT_A_PNT: NOP +V_MATH_FFT_B_PNT: NOP +V_MATH_FFT_W_PNT: NOP +FFT_BUTTERFLY: PUSH LR +PUSH R0 +PUSH R1 +LDIL R7 LOW[FFT_BUTTERFLY_MEM] +LDIH R7 HIGH[FFT_BUTTERFLY_MEM] +MUL R0 R4 R2 +MULH R1 R4 R2 +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +STR R1 R7 +#0 PRE +MUL R0 R4 R3 +MULH R1 R4 R3 +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +STR R1 R7 +#2 PRE +MUL R0 R5 R2 +MULH R1 R5 R2 +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +STR R1 R7 +#4 PRE +MUL R0 R5 R3 +MULH R1 R5 R3 +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +SFTS R0 R0 #LSL +SFT R1 R1 #ROL +STR R1 R7 +#6 PRE +POP R1 +POP R0 +LDR R2 R7 +#0 PRE +LDR R3 R7 +#6 PRE +ADDS R2 R0 R2 +SBC R3 R2 R3 +PUSH R3 +LDR R2 R7 +#2 PRE +LDR R3 R7 +#4 PRE +ADDS R2 R1 R2 +ADC R3 R2 R3 +PUSH R3 +LDR R2 R7 +#0 PRE +LDR R3 R7 +#6 PRE +SUBS R2 R0 R2 +ADC R3 R2 R3 +PUSH R3 +LDR R2 R7 +#2 PRE +LDR R3 R7 +#4 PRE +SUBS R2 R1 R2 +SBC R3 R2 R3 +POP R2 +POP R1 +POP R0 +POP LR +RET LR +FFT_BUTTERFLY_MEM: NOP +NOP +NOP +NOP +STORE_FFT_SAMPLE: PUSH R3 +PUSH R4 +PUSH R5 +CLR R5 +STORE_FFT_SAMPLE_BREV: SFTS R3 R3 #LSR +SFT R5 R5 #RLC +DECS R4 R4 #1 +BNE STORE_FFT_SAMPLE_BREV +SFT R5 R5 #LSL +SFT R5 R5 #LSL +ADD R5 R2 R5 +STR R0 R5 +#0 PRE +STR R1 R5 +#2 PRE +POP R5 +POP R4 +POP R3 +RET LR +MATH_LOG2: PUSH R1 +CLR R1 +MATH_LOG2_LOOP: SFTS R0 R0 #LSR +BEQ MATH_LOG2_END +INC R1 R1 #1 +B MATH_LOG2_LOOP +MATH_LOG2_END: MOV R0 R1 +POP R1 +RET LR +FFT_SINCOS_LUT: .DW #16384 +.DW #0 +.DW #16364 +.DW #803 +.DW #16305 +.DW #1605 +.DW #16206 +.DW #2404 +.DW #16069 +.DW #3196 +.DW #15892 +.DW #3980 +.DW #15678 +.DW #4756 +.DW #15426 +.DW #5519 +.DW #15136 +.DW #6269 +.DW #14810 +.DW #7005 +.DW #14449 +.DW #7723 +.DW #14053 +.DW #8423 +.DW #13622 +.DW #9102 +.DW #13159 +.DW #9759 +.DW #12665 +.DW #10393 +.DW #12139 +.DW #11002 +.DW #11585 +.DW #11585 +.DW #11002 +.DW #12139 +.DW #10393 +.DW #12665 +.DW #9759 +.DW #13159 +.DW #9102 +.DW #13622 +.DW #8423 +.DW #14053 +.DW #7723 +.DW #14449 +.DW #7005 +.DW #14810 +.DW #6269 +.DW #15136 +.DW #5519 +.DW #15426 +.DW #4756 +.DW #15678 +.DW #3980 +.DW #15892 +.DW #3196 +.DW #16069 +.DW #2404 +.DW #16206 +.DW #1605 +.DW #16305 +.DW #803 +.DW #16364 +.DW #0 +.DW #16384 +.DW #64733 +.DW #16364 +.DW #63931 +.DW #16305 +.DW #63132 +.DW #16206 +.DW #62340 +.DW #16069 +.DW #61556 +.DW #15892 +.DW #60780 +.DW #15678 +.DW #60017 +.DW #15426 +.DW #59267 +.DW #15136 +.DW #58531 +.DW #14810 +.DW #57813 +.DW #14449 +.DW #57113 +.DW #14053 +.DW #56434 +.DW #13622 +.DW #55777 +.DW #13159 +.DW #55143 +.DW #12665 +.DW #54534 +.DW #12139 +.DW #53951 +.DW #11585 +.DW #53397 +.DW #11002 +.DW #52871 +.DW #10393 +.DW #52377 +.DW #9759 +.DW #51914 +.DW #9102 +.DW #51483 +.DW #8423 +.DW #51087 +.DW #7723 +.DW #50726 +.DW #7005 +.DW #50400 +.DW #6269 +.DW #50110 +.DW #5519 +.DW #49858 +.DW #4756 +.DW #49644 +.DW #3980 +.DW #49467 +.DW #3196 +.DW #49330 +.DW #2404 +.DW #49231 +.DW #1605 +.DW #49172 +.DW #803 +INPUT_SIGNAL: .DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +.DW #1024 +.DW #0 +.DW #0 +.DW #0 +FFT_RAM: NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +ERR_STRING: .DW #17784 +.DW #25445 +.DW #28788 +.DW #26991 +.DW #28207 +.DW #26990 +.DW #29797 +.DW #29298 +.DW #30064 +.DW #29728 +.DW #25970 +.DW #29295 +.DW #29217 +.DW #0 +STRING_INTRO: .DW #17263 +.DW #28016 +.DW #30068 +.DW #26990 +.DW #26400 +.DW #17990 +.DW #21550 +.DW #11822 +.DW #8192 +STACK_BEGIN: NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +NOP +STACK_END: NOP

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