Subversion Repositories spi_slave

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tags/V100/doc/src/Grafik/block_diagramm.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/V100/doc/src/Grafik/block_diagramm.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/V100/doc/src/Grafik/block_diagramm.odg =================================================================== --- tags/V100/doc/src/Grafik/block_diagramm.odg (revision 34) +++ tags/V100/doc/src/Grafik/block_diagramm.odg (nonexistent)

tags/V100/doc/src/Grafik/block_diagramm.odg Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/V100/doc/src/opb_spi_slave.tex =================================================================== --- tags/V100/doc/src/opb_spi_slave.tex (revision 34) +++ tags/V100/doc/src/opb_spi_slave.tex (nonexistent) @@ -1,46 +0,0 @@ -\documentclass[11pt, a4paper, german, oneside]{scrbook} -\textheight240mm -\usepackage{hyperref} -\usepackage[latin1]{inputenc} -\usepackage{graphicx} -\usepackage{colortbl} -\usepackage{tabularx} -\usepackage{longtable} -\definecolor{yellow1}{rgb}{0.98, 1.0, 0.6} -\pagestyle{plain} -\pagenumbering{arabic} -\usepackage{verbatim} - -\title{Specification OPB-SPI Slave} -\author{Daniel Koethe} -\date{\today} - - -\begin{document} - \maketitle -\tableofcontents - -\input{content/spec} - - -% Anhang (Bibliographie darf im deutschen nicht in den Anhang!) -\bibliography{bib/BibtexDatabase} -\bibliographystyle{plain} -\clearpage -\listoffigures -\listoftables - - - - - - - -% Anhang -\appendix -\input{content/Z-Anhang} - - -%% Dokument ENDE %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\end{document} - Index: tags/V100/doc/src/content/spec.tex =================================================================== --- tags/V100/doc/src/content/spec.tex (revision 34) +++ tags/V100/doc/src/content/spec.tex (nonexistent) @@ -1,410 +0,0 @@ -\chapter{Introduction} -This document describe a SPI Slave core designed for the Xilinx EDK. \cite{bib_xilinx_edk} - -\section{Features} -\begin{itemize} -\item OPB-Clock and SPI-Clock are complete independent -\item SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX-FIFO Overrunn occure. -\item variable transfer length 2..32 -\end{itemize} - - - - -\section{Limitations} -\begin{itemize} -\item designed only for Xilinx Spartan-3/Virtex-4 at the moment -\item only Slave Operation -\end{itemize} - -\chapter{Core configuration} -\begin{table} [h] - \centering - \begin{tabular} {|l|l|c|c|} \hline - Description & Parameter Name & Allowable Values & Default Value \\ \hline - \multicolumn{4} {|c|} {System Parameter} \\ \hline - Base address for OPB SPI& C\_BASEADDR & 0x00 & 0x00000000 \\ \hline - High address for OPB SPI& C\_HIGHADDR & BASEADDR+0x3F & BASEADDR+0x3f \\ \hline - OPB address bus width & C\_OPB\_AWIDTH & 32 & 32 \\ \hline - OPB data bus width & C\_OPB\_DWIDTH & 32 & 32 \\ \hline - Target FPGA Family & C\_FAMILY & spartan3,virtex4 & virtex4 \\ \hline - \multicolumn{4} {|c|} {User Parameter} \\ \hline - Shift register width & C\_SR\_WIDTH & 8-32 & 8 \\ \hline - Shift MSB First & C\_MSB\_FIRST & true, false & true \\ \hline - SPI Clock Polarity & C\_CPOL & 0,1 & 0 \\ \hline - SPI Clock Phase & C\_CPHA & 0,1 & 0 \\ \hline - FIFO Size Width(TX/RX)\footnotemark[1] & C\_FIFO\_DEPTH & 4-7 & 4 \\ \hline - DMA\_EN & C\_DMA\_EN & true, false & false \\ \hline - \end{tabular} - \caption{Generics} - \label{tab:Generics} -\end{table} - -\footnotetext[1]{FIFO depth is $2^{Value}$ =(16,32,64,128)} - - - -\chapter{IO-Ports} -\begin{table} [h] - \centering - \begin{tabular}{|l|l|l|l|} \hline - \textbf{Port} & \textbf{width} & \textbf{direction} & \textbf{Description} \\ \hline - SPI\_SCLK & 1 & input & Serial clock input \\ - SPI\_MOSI & 1 & input & Master Out Slave in \\ - SPI\_MISO & 1 & output & Master in Slave out \\ - SPI\_SS & 1 & input & Slave select \\ \hline - opb\_irq & 1 & output & IRQ Output \\ \hline - \end{tabular} - \caption{external ports} - \label{tab:externalPorts} -\end{table} - -\chapter{Registers} -\section{Adressmap} -\begin{table} [!h] - \centering - \begin{tabular}{|l|c|c|l|} \hline - \textbf{Name} & \textbf{Adress} & \textbf{Acess} & \textbf{Description} \\ \hline - SPI\_CR & 0x00 & R/W & SPI Control Register \\ \hline - SPI\_SR & 0x04 & R/W & SPI Status Register \\ \hline - SPI\_TD & 0x08 & W & SPI Transmit Data Register \\ \hline - SPI\_RD & 0x0C & R & SPI Receive Data Register \\ \hline - TX\_THRESH & 0x10 & R/W & TX-Threshold Prog Full/Emty \\ \hline - RX\_THRESH & 0x14 & R/W & RX-Threshold Prog Full/Emty \\ \hline - TX\_DMA\_CTL & 0x18 & R/W & TX DMA Control \\ \hline - TX\_DMA\_ADDR & 0x1C & R/W & TX DMA Base Adress Offset \\ \hline - TX\_DMA\_NUM & 0x20 & R/W & TX DMA Number of Transfers \\ \hline - RX\_DMA\_CTL & 0x24 & R/W & RX DMA Control \\ \hline - RX\_DMA\_ADDR & 0x28 & R/W & RX DMA Base Adress Offset \\ \hline - RX\_DMA\_NUM & 0x2C & R/W & RX DMA Number of Transfers \\ \hline - - DGIE & 0x40 & R/W & Device global IRQ Enable Register \\ \hline - IPISR & 0x44 & R/W & IRQ Status Register \\ \hline - IPIER & 0x48 & R/W & IRQ Enable Register \\ \hline - \end{tabular} - \caption{Address-Map} - \label{tab:registers} -\end{table} - -\section{SPI\_CR} -\begin{table} [!h] - \centering - \begin{tabular} {|l|c|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & DGE & R/W & 0 & Device Global Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 30 & TX\_EN & R/W & 0 & Transmit Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29 & RX\_EN & R/W & 0 & Receive Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29 & RESET & R/W & 0 & Reset Device(self cleared) \\ - & & & & 0: Normal Operation \\ - & & & & 1: Reset SPI-Core(SR/FIFO) \\ \hline 29..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} - \caption{SPI\_CR Register} - \label{tab:SPI_CR} -\end{table} - - -\section{SPI\_SR} -\begin{table} [!h] - \centering - \begin{tabular} {|l|l|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX Prog Full & R & 0 & Prog Full Flag \\ - & & & & 1: FIFO Prog Full \\ \hline - 30 & TX Full & R & 0 & Full Flag \\ - & & & & 1: FIFO Full \\ \hline - 29 & TX Overflow & R & 0 & Overflow Flag \\ - & & & & 1: FIFO Overflow \\ - & & & & (Cleared only at Reset) \\ \hline - 28 & TX Prog Empty & R & 0 & Prog Empty Flag \\ - & & & & 1: FIFO Prog Empty \\ \hline - 27 & TX Empty & R & 0 & Full Flag \\ - & & & & 1: FIFO Empty \\ \hline - 26 & TX Underflow & R & 0 & Underflow Flag \\ - & & & & 1: FIFO Underflow \\ - & & & & (Cleared only at Reset) \\ \hline - 25 & RX Prog Full & R & 0 & Prog Full Flag \\ - & & & & 1: FIFO Prog Full \\ \hline - 24 & RX Full & R & 0 & Full Flag \\ - & & & & 1: FIFO Full \\ \hline - 23 & RX Overflow & R & 0 & Overflow Flag \\ - & & & & 1: FIFO Overflow \\ - & & & & (Cleared only at Reset) \\ \hline - 22 & RX Prog Empty & R & 0 & Prog Empty Flag \\ - & & & & 1: FIFO Prog Empty \\ \hline - 21 & RX Empty & R & 0 & Full Flag \\ - & & & & 1: FIFO Empty \\ \hline - 20 & RX Underflow & R & 0 & Underflow Flag \\ - & & & & 1: FIFO Underflow \\ - & & & & (Cleared only at Reset) \\ \hline - 19 & Chip Select & R & 0 & Chip Select Flag \\ - & & & & 0: CS\_N Low \\ - & & & & 1: CS\_N High \\ \hline - 18 & TX DMA Done & R & 0 & Transmit DMA done \\ - & & & & 0: TX DMA in progress \\ - & & & & 1: TX DMA all Transfers done\\ \hline 17 & RX DMA Done & R & 0 & Receive DMA done \\ - & & & & 0: RX DMA in progress \\ - & & & & 1: RX DMA all Transfers done\\ \hline - 16..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} - \caption{SPI\_SR Register} - \label{tab:SPI_SR} -\end{table} - -\newpage -\section{TX\_THRESH} -\begin{table}[!h] - \centering - \begin{tabular} {|l|l|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ - & & & \textbf{Value} & \\ \hline - 31..16 & TX\_THRESH\_PROG\_FULL & R/W & 0 & Transmit Prog Full Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - 15..0 & TX\_THRESH\_PROG\_EMPTY & R/W & 0 & Transmit Prog Empty Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - \end{tabular} - \caption{TX\_THRESH Register} - \label{tab:TX_THRESH} -\end{table} - - -\section{RX\_THRESH} -\begin{table}[!h] - \centering - \begin{tabular} {|l|l|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ - & & & \textbf{Value} & \\ \hline - 31..16 & RX\_THRESH\_PROG\_FULL & R/W & 0 & Receive Prog Full Threshold \\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - 15..0 & RX\_THRESH\_PROG\_EMPTY & R/W & 0 & Receive Prog Empty Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline \end{tabular} - \caption{RX\_THRESH Register} - \label{tab:RX_THRESH} -\end{table} - - -\section{DGIE} -\begin{table} [!h] - \centering - \begin{tabular} {|l|c|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & DGIE & R/W & 0 & Global IRQ Ebable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} - \caption{DGIE Register} - \label{tab:dgie} -\end{table} - -\newpage -\section{IPISR} -\begin{table} [!h] - \centering - \begin{tabular} {|l|l|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX\_Prog\_Empty & R/ToW\footnotemark[1] & 0 & IRQ Prog Empty Flag \\ \hline - 29 & TX\_Empty & R/ToW & 0 & IRQ Full Flag \\ \hline - 28 & RX\_Prog\_Full& R/ToW & 0 & IRQ Prog Full Flag \\ \hline - 27 & RX\_Full & R/ToW & 0 & IRQ Full Flag \\ \hline - 26 & SS\_FALL & R/ToW & 0 & IRQ SS FALL Flag \\ \hline - 25 & SS\_RISE & R/ToW & 0 & IRQ SS RISE Flag \\ \hline - 24..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} - \caption{IPISR Register} - \label{tab:IPISR} -\end{table} - -\footnotetext[1]{Read and ToggleOnWrite (writing 1 clears the bit)} - -\section{IPISE} -\begin{table} [!h] - \centering - \begin{tabular} {|l|l|c|c|l|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX\_Prog\_Empty & R/W & 0 & IRQ Prog Empty Enable \\ \hline - 29 & TX\_Empty & R/W & 0 & IRQ Full Enable \\ \hline - 28 & RX\_Prog\_Full & R/W & 0 & IRQ Prog Full Enable \\ \hline - 27 & RX\_Full & R/W & 0 & IRQ Full Enable \\ \hline - 26 & SS\_FALL & R/W & 0 & IRQ SS FALL Enable \\ \hline - 25 & SS\_RISE & R/W & 0 & IRQ SS RISE Enable \\ \hline - 24 & TX\_DMA\_DONE & R/W & 0 & IRQ TX Transfer done Enable\\ \hline - 23 & TX\_DMA\_DONE & R/W & 0 & IRQ RX Transfer done Enable\\ \hline 22..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} - \caption{IPISE Register} - \label{tab:IPISE} -\end{table} - -1: IRQ enabled - -\chapter{System Integration} -To integrate this IP-Core in your System, unzip the opb\_spi\_slave.zip to your project-directory. Then Rescan the user repository with \textit{Project $\rightarrow$ Rescan User Repositories}. This will take some seconds. After this you find the core in the \textit{IP Catalog $\rightarrow$ Project Repository}. - -\section{MPD-File} -\begin{verbatim} -BEGIN opb_spi_slave - PARAMETER INSTANCE = opb_spi_slave_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0x7d600000 - PARAMETER C_HIGHADDR = 0x7d60ffff - BUS_INTERFACE MSOPB = mb_opb - PORT sclk = opb_spi_slave_0_sclk - PORT ss_n = opb_spi_slave_0_ss_n - PORT mosi = opb_spi_slave_0_mosi - PORT miso = opb_spi_slave_0_miso - PORT opb_irq = opb_spi_slave_0_opb_irq -END -\end{verbatim} - -\section{UCF-File} -\begin{verbatim} -# assign I/O Pins -NET opb_spi_slave_0_sclk_pin LOC= AA24; # must CC capable IO in virtex-4 -NET opb_spi_slave_0_ss_n_pin LOC= V20; -NET opb_spi_slave_0_mosi_pin LOC= AC25; -NET opb_spi_slave_0_miso_pin LOC= AC24; -NET opb_spi_slave_0_miso_pin SLEW = FAST; - -#### Module OPB_SPI_Slave constraints -Net opb_spi_slave_0_sclk_pin TNM_NET = spi_clk; -TIMESPEC TS_spi_clk = PERIOD spi_clk 40 ns; - -NET "opb_spi_slave_0_mosi_pin" TNM = "spi_in"; -#NET "opb_spi_slave_0_cs_n_pin" TNM = "spi_in"; -TIMEGRP "spi_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "opb_spi_slave_0_sclk_pin" HIGH ; - -NET "opb_spi_slave_0_miso_pin" TNM = "spi_out"; -TIMEGRP "spi_out" OFFSET = OUT 14 ns AFTER "opb_spi_slave_0_sclk_pin" LOW ; -\end{verbatim} - -\section{Register Header} - -\verbatiminput{opb_spi_slave.h} - - -\chapter{Operations} - -\chapter{Architecture} - -\begin{figure}[h] - \centering - \includegraphics[width=1.00\textwidth]{Grafik/block_diagramm} - \caption{Blockdiagramm} - \label{fig:blockdiagramm} -\end{figure} - -\section{Serial Shift Register} -\begin{table}[!h] - \centering - \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} - \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline - \multicolumn{3} {c|} {Generics} \\ \hline - C\_SR\_WIDTH & - & Shift register width \\ \hline - C\_MSB\_FIRST & - & Transfer MSB First \\ \hline - \multicolumn{3} {c|} {Global} \\ \hline - rst & input & Async-Reset \\ \hline - \multicolumn{3} {c|} {External Interface} \\ \hline - sclk & input & Serial clock input \\ \hline - cs\_n & input & Chip Select \\ \hline - mosi & input & Master Out Slave in \\ \hline - miso\_o & output & Master in Slave out \\ \hline - miso\_i & input & not used \\ \hline - miso\_t & output & MISO Tristate \\ \hline - \multicolumn{3} {c|} {TX-FIFO (1)} \\ \hline - sr\_tx\_clk & output & FIFO-TX CLK \\ \hline - sr\_tx\_en & output & FIFO-TX enable \\ \hline - sr\_tx\_data[C\_SR\_WIDTH:0] & input & FIFO-TX Data \\ \hline - \multicolumn{3} {c|} {RX-FIFO (3)} \\ \hline - sr\_rx\_clk & output & FIFO-RX CLK \\ \hline - sr\_rx\_en & output & FIFO-RX enable \\ \hline - sr\_rx\_data[C\_SR\_WIDTH:0] & output & FIFO-RX Data \\ \hline - \end{tabular} - \caption{Serial-Register} - \label{tab:SerialRegister} -\end{table} -\clearpage - -\section{FIFO} -\begin{table}[!h] - \centering - \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} - \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline - \multicolumn{3} { c|} {Generics} \\ \hline - C\_FIFO\_WIDTH & - & Shift register width \\ \hline - C\_FIFO\_SIZE & - & FIFO Size Width \\ \hline - C\_SYNC\_TO & - & FIFO Sync Flags to Clock \\ \hline - \multicolumn{3} { c|} {Global} \\ \hline - rst & input & Async-Reset \\ \hline - \multicolumn{3} { c|} {Write-Port (2,3)} \\ \hline - wr\_clk & input & FIFO Write CLK \\ \hline - wr\_en & input & FIFO Write enable \\ \hline - din[C\_FIFO\_WIDTH:0] & input & FIFO Write data \\ \hline - \multicolumn{3} { c|} {READ-Port (1,4)} \\ \hline - rd\_clk & input & FIFO Read CLK \\ \hline - rd\_en & input & FIFO Read enable \\ \hline - dout[C\_FIFO\_WIDTH:0] & output & FIFO Read data \\ \hline - \multicolumn{3} { c|} {Flags (4)} \\ \hline - empty & output & FIFO Emtpy \\ \hline - full & output & FIFO Full \\ \hline - overflow & output & FIFO Overflow \\ \hline - underflow & output & FIFO Underflow \\ \hline - prog\_full\_thresh[C\_FIFO\_WIDTH:0] & output & FIFO Programmable Full Threshold \\ \hline - prog\_empty\_thresh[C\_FIFO\_WIDTH:0] & output & FIFO Programmable Empty Threshold\\ \hline - prog\_full & output & FIFO Programmable Full \\ \hline - prog\_empty & output & FIFO Programmable Empty \\ \hline - \end{tabular} - \caption{TX-FIFO} - \label{tab:tx-fifo} -\end{table} - -\newpage -\section{OPB\_IF} -\begin{table}[!h] - \centering - \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} - \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline - \multicolumn{3} { c|} {Generics} \\ \hline - C\_BASEADDR & - & Base address for OPB SPI \\ \hline - C\_HIGHADDR & - & High address for OPB SPI \\ \hline - C\_OPB\_AWIDTH & - & OPB address bus width \\ \hline - C\_OPB\_DWIDTH & - & OPB data bus width \\ \hline - C\_FAMILY & - & Target FPGA Family \\ \hline - C\_SR\_WIDTH & - & Shift register width \\ \hline - C\_FIFO\_WIDTH & - & Shift register width \\ \hline - C\_FIFO\_SIZE & - & FIFO Size Width \\ \hline - C\_NUM\_FLG & - & Number of FIFO Status flags \\ \hline - C\_NUM\_INT & - & Number of IRQ Sources \\ \hline - \multicolumn{3} { c|} {OPB-Bus} \\ \hline - OPB\_rst & input & Async-Reset \\ \hline - OPB\_ABus[C\_OPB\_AWIDTH-1:0] & input & Adress-Bus \\ \hline - OPB\_BE[C\_OPB\_DWIDTH/8-1:0] & input & Bytes Enables \\ \hline - OPB\_Clk & input & Clock \\ \hline - OPB\_DBus[C\_OPB\_DWIDTH-1:0] & input & Data-Bus to slave \\ \hline - OPB\_RNW & input & Read/Write \\ \hline - OPB\_Rst & input & Reset \\ \hline - OPB\_select & input & Select \\ \hline - OPB\_seqAddr & input & Sequential Adress Enable \\ \hline - Sln\_DBus & output & Data-Bus to Master \\ \hline - Sln\_errAck & output & Error Acknowledge \\ \hline - Sln\_retry & output & Retry \\ \hline - Sln\_toutSup & output & Timeout Suppression \\ \hline - Sln\_xferAck & output & transfer Acknowledge \\ \hline - \multicolumn{3} { c|} {FIFO-PORT (2)} \\ \hline - opb\_tx\_en & output & FIFO-TX Write Enable \\ \hline - opb\_tx\_data[C\_SR\_WIDTH:0] & output & FIFO-TX Write Data \\ \hline - tx\_thresh[(2*C\_FIFO\_SIZE)-1:0] & output & FIFO-TX Prog Thresholds \\ \hline - \multicolumn{3} { c|} {FIFO-PORT (4)} \\ \hline - opb\_rx\_en & output & FIFO-RX Read Enable \\ \hline - opb\_rx\_data[C\_SR\_WIDTH:0] & input & FIFO-RX Read Data \\ \hline - rx\_thresh[(2*C\_FIFO\_SIZE)-1:0] & output & FIFO-RX Prog Thresholds \\ \hline - \multicolumn{3} { c|} {FIFO-Flags(2,4)} \\ \hline - opb\_fifo\_flg[C\_NUM\_FLG-1:0] & input & FIFO Flags \\ \hline - \multicolumn{3} { c|} {IRQ-Signals} \\ \hline - opb\_dgie & output & Device Global IRQ Enable \\ \hline - opb\_ier(C\_NUM\_INT-1:0) & output & IRQ Enable Register \\ \hline - opb\_isr(C\_NUM\_INT-1:0) & input & IRQ Status Register \\ \hline - opb\_isr\_clr(C\_NUM\_INT-1:0) & output & Clear IRQ Flags \\ \hline - \end{tabular} - \caption{OPB\_IF} - \label{tab:opb_if} -\end{table} Index: tags/V100/doc/src/content/Titel.tex =================================================================== --- tags/V100/doc/src/content/Titel.tex (revision 34) +++ tags/V100/doc/src/content/Titel.tex (nonexistent) @@ -1,13 +0,0 @@ -\begin{titlepage} - \mbox{}\vspace{5\baselineskip}\\ - \sffamily\huge - \centering - specification OPB-SPI-Slave - \vspace{2\baselineskip}\\ - \rmfamily\Large - Daniel Koethe - \vspace{1\baselineskip}\\ - \today -\end{titlepage} - - Index: tags/V100/doc/src/content/Z-Anhang.tex =================================================================== --- tags/V100/doc/src/content/Z-Anhang.tex (revision 34) +++ tags/V100/doc/src/content/Z-Anhang.tex (nonexistent) @@ -1,3 +0,0 @@ -% \input{content/Z-Anhang-01-Herleitungen} - -\chapter*{} Index: tags/V100/doc/src/opb_spi_slave.tcp =================================================================== --- tags/V100/doc/src/opb_spi_slave.tcp (revision 34) +++ tags/V100/doc/src/opb_spi_slave.tcp (nonexistent) @@ -1,12 +0,0 @@ -[FormatInfo] -Type=TeXnicCenterProjectInformation -Version=4 - -[ProjectInfo] -MainFile=opb_spi_slave.tex -UseBibTeX=0 -UseMakeIndex=0 -ActiveProfile=LaTeX => PDF -ProjectLanguage=de -ProjectDialect=DE - Index: tags/V100/doc/opb_spi_slave.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/V100/doc/opb_spi_slave.pdf =================================================================== --- tags/V100/doc/opb_spi_slave.pdf (revision 34) +++ tags/V100/doc/opb_spi_slave.pdf (nonexistent)

tags/V100/doc/opb_spi_slave.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (nonexistent) @@ -1,68 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short gray Adder ---* ---* @generic width with of adder vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity gray_adder is - generic ( - width : integer := 4); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); -end gray_adder; - -architecture behavior of gray_adder is - --* convert gray to bin - component gray2bin - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); - end component; - --* convert bin to gray - component bin2gray - generic ( - width : integer); - port ( - in_bin : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - signal out_bin : std_logic_vector(width-1 downto 0); - signal bin_add : std_logic_vector(width-1 downto 0); - -begin -- behavior - --* convert input gray signal to binary - gray2bin_1 : gray2bin - generic map ( - width => width) - port map ( - in_gray => in_gray, - out_bin => out_bin); - - --* add one to signal - bin_add <= out_bin + 1; - --* convert signal back to gray - bin2gray_1 : bin2gray - generic map ( - width => width) - port map ( - in_bin => bin_add, - out_gray => out_gray); - - - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (nonexistent) @@ -1,190 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Shift-Register ---* ---* Control Register Description: ---* @li Bit0: DGE : Global Device Enable ---* @li Bit1: TX_EN: Transmit enable ---* @li Bit2: RX_EN: Receive enable ---* ---* Generics described in top entity. ---* @port opb_ctl_reg Control Register ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.1 ---* @date: 2007-11-11 ---/ --- Version 1.0 Initial Release --- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; - -library work; -use work.opb_spi_slave_pack.all; - -entity shift_register is - - generic ( - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0); - - port ( - rst : in std_logic; - -- control register - opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - -- external - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - -- transmit fifo - sr_tx_clk : out std_logic; - sr_tx_en : out std_logic; - sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- receive fifo - sr_rx_clk : out std_logic; - sr_rx_en : out std_logic; - sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); -end shift_register; - - -architecture behavior of shift_register is - --* Global - signal sclk_int : std_logic; - signal sclk_int_inv : std_logic; - signal rx_cnt : integer range 0 to 31 := 0; - - -- RX - signal rx_sr_reg : std_logic_vector(C_SR_WIDTH-2 downto 0); - signal sr_rx_en_int : std_logic; - signal sr_rx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -- tx - signal miso_int : std_logic; - signal tx_cnt : integer range 0 to 31 := 0; - signal sr_tx_en_int : std_logic; - signal sr_tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -begin -- behavior - - miso_t <= ss_n; -- tristate - - - sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else - sclk when (C_PHA = 1 and C_CPOL = 1) else - not sclk; - - - sr_rx_en <= transport sr_rx_en_int after 1 ns; - sr_tx_en <= transport sr_tx_en_int after 1 ns; - - --* reorder received bits if not "MSB_First" - reorder_rx_bits : process(sr_rx_data_int) - begin - for i in 0 to C_SR_WIDTH-1 loop - if C_MSB_FIRST then - sr_rx_data(i) <= transport sr_rx_data_int(i) after 1 ns; - else - sr_rx_data(C_SR_WIDTH-1-i) <= transport sr_rx_data_int(i)after 1 ns; - end if; - end loop; -- i - end process reorder_rx_bits; - - --* reorder transmit bits if not "MSB_First" - reorder_tx_bits : process(sr_tx_data) - begin - for i in 0 to C_SR_WIDTH-1 loop - if C_MSB_FIRST then - sr_tx_data_int(i) <= sr_tx_data(i); - else - sr_tx_data_int(C_SR_WIDTH-1-i) <= sr_tx_data(i); - end if; - end loop; -- i - end process reorder_tx_bits; - - - ----------------------------------------------------------------------------- - - sr_rx_clk <= sclk_int; - - sr_rx_data_int <= rx_sr_reg & mosi; - - --* RX-Shift-Register - rx_shift_proc : process(rst, opb_ctl_reg, sclk_int) - begin - if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_RX_EN) = '0') then - rx_cnt <= 0; - sr_rx_en_int <= '0'; - rx_sr_reg <= (others => '0'); - - elsif rising_edge(sclk_int) then - if (ss_n = '0') then - rx_sr_reg <= rx_sr_reg(C_SR_WIDTH-3 downto 0) & mosi; - if (rx_cnt = C_SR_WIDTH-2) then - rx_cnt <= rx_cnt +1; - sr_rx_en_int <= '1'; - elsif (rx_cnt = C_SR_WIDTH-1) then - rx_cnt <= 0; - sr_rx_en_int <= '0'; - else - rx_cnt <= rx_cnt +1; - end if; - else - -- ss_n high - -- assert framing error if cnt != 0? - sr_rx_en_int <= '0'; - rx_cnt <= 0; - end if; - end if; - end process rx_shift_proc; - -------------------------------------------------------------------------------- - -- TX Shift Register - sr_tx_clk <= sclk_int_inv; - sclk_int_inv <= not sclk_int; - - miso_o <= sr_tx_data_int(C_SR_WIDTH-1) when (tx_cnt = 0) else - miso_int; - - - --* TX Shift-Register - tx_shift_proc : process(rst, opb_ctl_reg, sclk_int_inv) - begin - if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_TX_EN) = '0') then - tx_cnt <= 0; - sr_tx_en_int <= '0'; - miso_int <= '0'; - elsif rising_edge(sclk_int_inv) then - if (ss_n = '0') then - if (tx_cnt /= C_SR_WIDTH-1) then - miso_int <= sr_tx_data_int(C_SR_WIDTH-1-(tx_cnt+1)); - end if; - if (tx_cnt = C_SR_WIDTH-2) then - sr_tx_en_int <= '1'; - tx_cnt <= tx_cnt +1; - elsif (tx_cnt = C_SR_WIDTH-1) then - tx_cnt <= 0; - sr_tx_en_int <= '0'; - else - tx_cnt <= tx_cnt +1; - end if; - else - -- ss_n high - -- assert framing error if cnt != 0? - sr_tx_en_int <= '0'; - tx_cnt <= 0; - end if; - end if; - end process tx_shift_proc; -------------------------------------------------------------------------------- - - end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (nonexistent) @@ -1,262 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Configurable FIFO ---* ---* @generic C_FIFO_WIDTH RAM-With (1..xx) ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* @generic C_SYNC_TO Sync FIFO Flags to read or write clock ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - -entity fifo is - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4; - C_SYNC_TO : string := "RD"); - port ( - rst : in std_logic; - -- write port - wr_clk : in std_logic; - wr_en : in std_logic; - din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - -- read port - rd_clk : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); - -- flags - empty : out std_logic; - full : out std_logic; - overflow : out std_logic; - underflow : out std_logic; - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - -end fifo; - -architecture behavior of fifo is - --* ram with sync write and async read - component ram - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4); - port ( - clk : in std_logic; - we : in std_logic; - a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); - end component; - - --* component generates fifo flag - component fifo_prog_flags - generic ( - C_FIFO_SIZE_WIDTH : integer; - C_SYNC_TO : string); - port ( - rst : in std_logic; - clk : in std_logic; - cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - end component; - - --* logic coded gray counter - component gray_adder - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - signal wr_cnt_gray_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal wr_cnt_next_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal rd_cnt_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - attribute fsm_extract : string; - -- wr_clock domain - -- main wr grey code counter - signal wr_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of wr_cnt_grey : signal is "no"; - - -- main grey code counter for full - signal wr_cnt_next_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of wr_cnt_next_grey : signal is "no"; - - -- rd_clk domain - -- main rd grey code counter - signal rd_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of rd_cnt_grey : signal is "no"; - - -- binary counter for prog full/empty - signal rd_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal wr_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - signal empty_int : std_logic; - signal full_int : std_logic; - -begin -- behavior - - empty <= empty_int; - full <= full_int; - ---* write counter generation - fifo_write_proc: process(rst, wr_clk) - begin - if (rst = '1') then - wr_cnt_grey <= (others => '0'); - wr_cnt <= (others => '0'); - wr_cnt_next_grey(C_FIFO_SIZE_WIDTH-1 downto 1) <= (others => '0'); - wr_cnt_next_grey(0) <= '1'; - elsif rising_edge(wr_clk) then - if (wr_en = '1') then - wr_cnt <= wr_cnt+1; - - -- wr_cnt_grey <= add_grey_rom(conv_integer(wr_cnt_grey)); - wr_cnt_grey <= wr_cnt_gray_add_one; - - -- wr_cnt_next_grey <= add_grey_rom(conv_integer(wr_cnt_next_grey)); - wr_cnt_next_grey <= wr_cnt_next_grey_add_one; - - end if; - end if; - end process fifo_write_proc; - - --* add one to wr_cnt_gray - gray_adder_1 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => wr_cnt_grey, - out_gray => wr_cnt_gray_add_one); - - --* add one to wr_cnt_next_grey - gray_adder_2 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => wr_cnt_next_grey, - out_gray => wr_cnt_next_grey_add_one); - - ---* read counter generation - fifo_read_proc: process(rst, rd_clk) - begin - if (rst = '1') then - rd_cnt_grey <= (others => '0'); - rd_cnt <= (others => '0'); - elsif rising_edge(rd_clk) then - -- rd grey code counter - if (rd_en = '1') then - -- rd_cnt_grey <= add_grey_rom(conv_integer(rd_cnt_grey)); - rd_cnt_grey <= rd_cnt_grey_add_one; - rd_cnt <= rd_cnt+1; - end if; - end if; - end process fifo_read_proc; - - --* add one to rd_cnt_grey - gray_adder_3 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => rd_cnt_grey, - out_gray => rd_cnt_grey_add_one); - - - --* FIFO Memory - ram_1 : ram - generic map ( - C_FIFO_WIDTH => C_FIFO_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) - port map ( - clk => wr_clk, - we => wr_en, - a => wr_cnt_grey, - di => din, - dpra => rd_cnt_grey, - dpo => dout); - - - --* generate overflow - gen_of_proc: process(rst, wr_clk) - begin - if (rst = '1') then - overflow <= '0'; - elsif rising_edge(wr_clk) then - if (full_int = '1' and wr_en = '1') then - overflow <= '1'; - end if; - end if; - end process gen_of_proc; - - --* generate underflow - gen_uf_proc: process(rst, rd_clk) - begin - if (rst = '1') then - underflow <= '0'; - elsif rising_edge(rd_clk) then - if (empty_int = '1' and rd_en = '1') then - underflow <= '1'; - end if; - end if; - end process gen_uf_proc; - - -- generate empty - empty_int <= '1' when (wr_cnt_grey = rd_cnt_grey) else - '0'; - - -- generate full - full_int <= '1' when (wr_cnt_next_grey = rd_cnt_grey) else - '0'; - - --* select clock side for flags - u1 : if (C_SYNC_TO = "WR") generate - --* sync flags to write clock - fifo_prog_flags_1 : fifo_prog_flags - generic map ( - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => C_SYNC_TO) - port map ( - rst => rst, - clk => wr_clk, - cnt_grey => rd_cnt_grey, - cnt => wr_cnt, - prog_full_thresh => prog_full_thresh, - prog_empty_thresh => prog_empty_thresh, - prog_empty => prog_empty, - prog_full => prog_full); - end generate u1; - - u2 : if (C_SYNC_TO = "RD") generate - --* sync flags to read clock - fifo_prog_flags_1 : fifo_prog_flags - generic map ( - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => C_SYNC_TO) - port map ( - rst => rst, - clk => rd_clk, - cnt_grey => wr_cnt_grey, - cnt => rd_cnt, - prog_full_thresh => prog_full_thresh, - prog_empty_thresh => prog_empty_thresh, - prog_empty => prog_empty, - prog_full => prog_full); - end generate u2; -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (nonexistent) @@ -1,67 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -package opb_spi_slave_pack is - - constant C_ADR_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#0#, 6); - constant C_ADR_STATUS : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#1#, 6); - constant C_ADR_TX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#2#, 6); - constant C_ADR_RX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#3#, 6); - constant C_ADR_TX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#4#, 6); - constant C_ADR_RX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#5#, 6); - constant C_ADR_TX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#6#, 6); - constant C_ADR_TX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#7#, 6); - constant C_ADR_TX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#8#, 6); - constant C_ADR_RX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#9#, 6); - constant C_ADR_RX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#A#, 6); - constant C_ADR_RX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#B#, 6); - --- XIIF_V123B compatible - constant C_ADR_DGIE : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#10#, 6); - constant C_ADR_ISR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#11#, 6); - constant C_ADR_IER : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#12#, 6); - - constant C_NUM_FLG : integer := 15; - constant C_NUM_INT : integer := 10; - - --- CTL_Register - -- width - constant C_OPB_CTL_REG_WIDTH : integer := 4; - -- bits - constant C_OPB_CTL_REG_DGE : integer := 0; - constant C_OPB_CTL_REG_TX_EN : integer := 1; - constant C_OPB_CTL_REG_RX_EN : integer := 2; - constant C_OPB_CTL_REG_RST : integer := 3; - - - -- Status Register - constant SPI_SR_Bit_TX_Prog_Full : integer := 0; - constant SPI_SR_Bit_TX_Full : integer := 1; - constant SPI_SR_Bit_TX_Overflow : integer := 2; - constant SPI_SR_Bit_TX_Prog_empty : integer := 3; - constant SPI_SR_Bit_TX_Empty : integer := 4; - constant SPI_SR_Bit_TX_Underflow : integer := 5; - - constant SPI_SR_Bit_RX_Prog_Full : integer := 6; - constant SPI_SR_Bit_RX_Full : integer := 7; - constant SPI_SR_Bit_RX_Overflow : integer := 8; - constant SPI_SR_Bit_RX_Prog_empty : integer := 9; - constant SPI_SR_Bit_RX_Empty : integer := 10; - constant SPI_SR_Bit_RX_Underflow : integer := 11; - - constant SPI_SR_Bit_SS_n : integer := 12; - - -- Interrupt Status Register - constant SPI_ISR_Bit_TX_Prog_Empty : integer := 0; - constant SPI_ISR_Bit_TX_Empty : integer := 1; - constant SPI_ISR_Bit_TX_Underflow : integer := 2; - constant SPI_ISR_Bit_RX_Prog_Full : integer := 3; - constant SPI_ISR_Bit_RX_Full : integer := 4; - constant SPI_ISR_Bit_RX_Overflow : integer := 5; - constant SPI_ISR_Bit_SS_Fall : integer := 6; - constant SPI_ISR_Bit_SS_Rise : integer := 7; -end opb_spi_slave_pack; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (nonexistent) @@ -1,562 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Top entity of the project opi_spi_slave ---* ---* @generic C_FAMILY virtex-4 and generic supported ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - -library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.opb_spi_slave_pack.all; - - -entity opb_spi_slave is - - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 0; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - - C_FAMILY : string := "virtex4"; - -- user ports - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0; - C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32 - C_DMA_EN : boolean := false); - - port ( - -- OPB signals (Slave Side) - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - - -- OPB signals (Master Side) - -- Arbitration - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - -- - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - -- spi ports - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - -- irq output - opb_irq : out std_logic); - -end opb_spi_slave; - -architecture behavior of opb_spi_slave is - - component opb_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_DMA_EN : boolean); - port ( - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - opb_s_tx_en : out std_logic; - opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_s_rx_en : out std_logic; - opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); - opb_dgie : out std_logic; - opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_ctl : out std_logic_vector(0 downto 0); - opb_tx_dma_num : out std_logic_vector(15 downto 0); - opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_ctl : out std_logic_vector(0 downto 0); - opb_rx_dma_num : out std_logic_vector(15 downto 0)); - end component; - - - component opb_m_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1; - C_FIFO_SIZE_WIDTH : integer range 4 to 7); - port ( - OPB_Clk : in std_logic; - OPB_Rst : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - opb_m_tx_req : in std_logic; - opb_m_tx_en : out std_logic; - opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_tx_dma_ctl : in std_logic_vector(0 downto 0); - opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_num : in std_logic_vector(15 downto 0); - opb_tx_dma_done : out std_logic; - opb_m_rx_req : in std_logic; - opb_m_rx_en : out std_logic; - opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_dma_ctl : in std_logic_vector(0 downto 0); - opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_num : in std_logic_vector(15 downto 0); - opb_rx_dma_done : out std_logic); - end component; - - component shift_register - generic ( - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1); - port ( - rst : in std_logic; - opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - sr_tx_clk : out std_logic; - sr_tx_en : out std_logic; - sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - sr_rx_clk : out std_logic; - sr_rx_en : out std_logic; - sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - component fifo - generic ( - C_FIFO_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_SYNC_TO : string); - port ( - rst : in std_logic; - wr_clk : in std_logic; - wr_en : in std_logic; - din : in std_logic_vector(C_SR_WIDTH-1 downto 0); - rd_clk : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(C_SR_WIDTH-1 downto 0); - empty : out std_logic; - full : out std_logic; - overflow : out std_logic; - underflow : out std_logic; - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - end component; - - component irq_ctl - generic ( - C_ACTIVE_EDGE : std_logic); - port ( - rst : in std_logic; - clk : in std_logic; - opb_fifo_flg : in std_logic; - opb_ier : in std_logic; - opb_isr : out std_logic; - opb_isr_clr : in std_logic); - end component; - --- opb_if - signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - - signal opb_s_tx_en : std_logic; - signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_s_rx_en : std_logic; - signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - - signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_tx_dma_num : std_logic_vector(15 downto 0); - signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_rx_dma_num : std_logic_vector(15 downto 0); - - -- opb_m_if - signal opb_m_tx_en : std_logic; - signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_m_rx_en : std_logic; - signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - --- shift_register - signal sr_tx_clk : std_logic; - signal sr_tx_en : std_logic; - signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal sr_rx_clk : std_logic; - signal sr_rx_en : std_logic; - signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - signal sclk_ibuf : std_logic; - signal sclk_bufr : std_logic; - - signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); - signal opb_irq_flg : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0'); - signal rst : std_logic; - - - signal opb_dgie : std_logic; - signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); - - -- opb_spi_slave - signal fifo_tx_en : std_logic; - signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal fifo_rx_en : std_logic; - signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - -begin -- behavior - - --* - virtex4_slk_buf : if C_FAMILY = "virtex4" generate - --* If C_FAMILY=Virtex-4 use "IBUF" - IBUF_1 : IBUF - port map ( - I => sclk, - O => sclk_ibuf); - ---* If C_FAMILY=Virtex-4 use "BUFR" - BUFR_1 : BUFR - generic map ( - BUFR_DIVIDE => "BYPASS", - SIM_DEVICE => "VIRTEX4") - port map ( - O => sclk_bufr, - CE => '0', - CLR => '0', - I => sclk_ibuf); - end generate virtex4_slk_buf; - - generic_sclk_buf : if C_FAMILY /= "virtex4" generate - sclk_bufr <= sclk; - end generate generic_sclk_buf; - - --* OPB-Slave Interface(Register-Interface) - opb_if_2 : opb_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_DMA_EN => C_DMA_EN) - port map ( - OPB_ABus => OPB_ABus, - OPB_BE => OPB_BE, - OPB_Clk => OPB_Clk, - OPB_DBus => OPB_DBus, - OPB_RNW => OPB_RNW, - OPB_Rst => OPB_Rst, - OPB_select => OPB_select, - OPB_seqAddr => OPB_seqAddr, - Sln_DBus => Sln_DBus, - Sln_errAck => Sln_errAck, - Sln_retry => Sln_retry, - Sln_toutSup => Sln_toutSup, - Sln_xferAck => Sln_xferAck, - opb_s_tx_en => opb_s_tx_en, - opb_s_tx_data => opb_s_tx_data, - opb_s_rx_en => opb_s_rx_en, - opb_s_rx_data => opb_s_rx_data, - opb_ctl_reg => opb_ctl_reg, - tx_thresh => tx_thresh, - rx_thresh => rx_thresh, - opb_fifo_flg => opb_fifo_flg, - opb_dgie => opb_dgie, - opb_ier => opb_ier, - opb_isr => opb_isr, - opb_isr_clr => opb_isr_clr, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_num => opb_tx_dma_num, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_num => opb_rx_dma_num); - - --* OPB-Master-Interface - --* - --* (DMA Read/Write Transfers to TX/RX-FIFO) - - dma_enable : if (C_DMA_EN = true) generate - opb_m_if_1 : opb_m_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) - port map ( - OPB_Clk => OPB_Clk, - OPB_Rst => OPB_Rst, - OPB_DBus => OPB_DBus, - M_request => M_request, - MOPB_MGrant => MOPB_MGrant, - M_busLock => M_busLock, - M_ABus => M_ABus, - M_BE => M_BE, - M_DBus => M_DBus, - M_RNW => M_RNW, - M_select => M_select, - M_seqAddr => M_seqAddr, - MOPB_errAck => MOPB_errAck, - MOPB_retry => MOPB_retry, - MOPB_timeout => MOPB_timeout, - MOPB_xferAck => MOPB_xferAck, - opb_m_tx_req => opb_fifo_flg(3), - opb_m_tx_en => opb_m_tx_en, - opb_m_tx_data => opb_m_tx_data, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_num => opb_tx_dma_num, - opb_tx_dma_done => opb_fifo_flg(13), - opb_m_rx_req => opb_fifo_flg(6), - opb_m_rx_en => opb_m_rx_en, - opb_m_rx_data => opb_m_rx_data, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_num => opb_rx_dma_num, - opb_rx_dma_done => opb_fifo_flg(14)); - end generate dma_enable; - - dma_disable : if (C_DMA_EN = false) generate - M_request <= '0'; - M_busLock <= '0'; - M_ABus <= (others => '0'); - M_BE <= (others => '0'); - M_DBus <= (others => '0'); - M_RNW <= '0'; - M_select <= '0'; - M_seqAddr <= '0'; - opb_m_tx_en <= '0'; - opb_m_tx_data <= (others => '0'); - opb_fifo_flg(13) <= '0'; - opb_m_rx_en <= '0'; - opb_fifo_flg(14) <= '0'; - end generate dma_disable; - - --* Shift-Register - shift_register_1 : shift_register - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA) - port map ( - rst => rst, - opb_ctl_reg => opb_ctl_reg, - sclk => sclk_bufr, - ss_n => ss_n, - mosi => mosi, - miso_o => miso_o, - miso_i => miso_i, - miso_t => miso_t, - sr_tx_clk => sr_tx_clk, - sr_tx_en => sr_tx_en, - sr_tx_data => sr_tx_data, - sr_rx_clk => sr_rx_clk, - sr_rx_en => sr_rx_en, - sr_rx_data => sr_rx_data); - - --* Transmit FIFO - tx_fifo_1 : fifo - generic map ( - C_FIFO_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => "WR") - port map ( - -- global - rst => rst, - prog_full_thresh => tx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), - prog_empty_thresh => tx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), - -- write port - wr_clk => OPB_Clk, - wr_en => fifo_tx_en, - din => fifo_tx_data, - -- flags - prog_full => opb_fifo_flg(0), - full => opb_fifo_flg(1), - overflow => opb_fifo_flg(2), - -- read port - rd_clk => sr_tx_clk, - rd_en => sr_tx_en, - dout => sr_tx_data, - -- flags - prog_empty => opb_fifo_flg(3), - empty => opb_fifo_flg(4), - underflow => opb_fifo_flg(5)); - - fifo_tx_en <= opb_s_tx_en or opb_m_tx_en; - fifo_tx_data <= opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else - opb_s_tx_data; - - --* Receive FIFO - rx_fifo_1 : fifo - generic map ( - C_FIFO_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => "RD") - port map ( - -- global - rst => rst, - prog_full_thresh => rx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), - prog_empty_thresh => rx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), - -- write port - wr_clk => sr_rx_clk, - wr_en => sr_rx_en, - din => sr_rx_data, - -- flags - prog_full => opb_fifo_flg(6), - full => opb_fifo_flg(7), - overflow => opb_fifo_flg(8), - -- read port - rd_clk => opb_clk, - rd_en => fifo_rx_en, - dout => fifo_rx_data, - -- flags - prog_empty => opb_fifo_flg(9), - empty => opb_fifo_flg(10), - underflow => opb_fifo_flg(11)); - - fifo_rx_en <= opb_s_rx_en or opb_m_rx_en; - opb_s_rx_data <= fifo_rx_data; - opb_m_rx_data <= fifo_rx_data; - - rst <= OPB_Rst or opb_ctl_reg(C_OPB_CTL_REG_RST); - - opb_fifo_flg(12) <= ss_n; - - - - - -- Bit 0 : TX_PROG_EMPTY - opb_irq_flg(0) <= opb_fifo_flg(3); - -- Bit 1 : TX_EMPTY - opb_irq_flg(1) <= opb_fifo_flg(4); - -- Bit 2 : TX_Underflow - opb_irq_flg(2) <= opb_fifo_flg(5); - -- Bit 3 : RX_PROG_FULL - opb_irq_flg(3) <= opb_fifo_flg(6); - -- Bit 4 : RX_FULL - opb_irq_flg(4) <= opb_fifo_flg(7); - -- Bit 5 : RX_Overflow - opb_irq_flg(5) <= opb_fifo_flg(9); - -- Bit 6: CS_H_TO_L - opb_irq_flg(6) <= not opb_fifo_flg(12); - -- Bit 7: CS_L_TO_H - opb_irq_flg(7) <= opb_fifo_flg(12); - -- Bit 8: TX DMA Done - opb_irq_flg(8) <= opb_fifo_flg(13); - -- Bit 9: RX DMA Done - opb_irq_flg(9) <= opb_fifo_flg(14); - - --* IRQ Enable, Detection and Flags Control - irq_gen : for i in 0 to C_NUM_INT-1 generate - irq_ctl_1 : irq_ctl - generic map ( - C_ACTIVE_EDGE => '1') - port map ( - rst => rst, - clk => OPB_Clk, - opb_fifo_flg => opb_irq_flg(i), - opb_ier => opb_ier(i), - opb_isr => opb_isr(i), - opb_isr_clr => opb_isr_clr(i)); - end generate irq_gen; - - -- assert irq if one Interupt Status bit set - opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else - '0'; - - - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (nonexistent) @@ -1,96 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Generate fifo flags ---* ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* @generic C_SYNC_TO Sync FIFO Flags to read or write clock ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - -entity fifo_prog_flags is - generic ( - C_FIFO_SIZE_WIDTH : integer := 4; - C_SYNC_TO : string := "WR"); - port ( - rst : in std_logic; - clk : in std_logic; - cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - -end fifo_prog_flags; -architecture behavior of fifo_prog_flags is - - -- sync register for clock domain transfer - signal cnt_grey_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - type rom_t is array (0 to (2**C_FIFO_SIZE_WIDTH)-1) of std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - --* convert from gray to binary - component gray2bin - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); - end component; - - signal cnt_bin_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - -begin -- behavior - - --* Generate fifo flags - gen_flags_proc: process(rst, clk) - variable diff : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - begin - if (rst = '1') then - cnt_grey_reg <= (others => '0'); - prog_empty <= '1'; - prog_full <= '0'; - elsif rising_edge(clk) then - -- transfer to rd_clk domain - cnt_grey_reg <= cnt_grey; - -- fifo prog full/empty - if (C_SYNC_TO = "RD") then - -- diff := conv_grey_rom(conv_integer(cnt_grey_reg))- cnt; - diff := cnt_bin_reg - cnt; - else - -- diff := cnt - conv_grey_rom(conv_integer(cnt_grey_reg)); - diff := cnt - cnt_bin_reg; - end if; - - if (diff > prog_full_thresh) then - prog_full <= '1'; - else - prog_full <= '0'; - end if; - - if (diff < prog_empty_thresh) then - prog_empty <= '1'; - else - prog_empty <= '0'; - end if; - end if; - end process gen_flags_proc; - - --* convert gray to bin - gray2bin_1: gray2bin - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => cnt_grey_reg, - out_bin => cnt_bin_reg); - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (nonexistent) @@ -1,300 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short OPB-Master Interface ---* ---* Generics described in top entity. ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -entity opb_m_if is - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 0; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - C_FAMILY : string := "virtex-4"; - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0; - C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7); - - port ( - -- opb master interface - OPB_Clk : in std_logic; - OPB_Rst : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - --------------------------------------------------------------------------- - -- read transfer - -- read data from memory and fill fifo - opb_m_tx_req : in std_logic; - opb_m_tx_en : out std_logic; - opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - -- enable/disable dma transfer - opb_tx_dma_ctl : in std_logic_vector(0 downto 0); - -- base adress for transfer - opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_num : in std_logic_vector(15 downto 0); - opb_tx_dma_done : out std_logic; - --------------------------------------------------------------------------- - -- write transfer - -- read fifo an write to memory - opb_m_rx_req : in std_logic; - opb_m_rx_en : out std_logic; - opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- enable/disable dma transfer - opb_rx_dma_ctl : in std_logic_vector(0 downto 0); - -- base adress for transfer - opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_num : in std_logic_vector(15 downto 0); - opb_rx_dma_done : out std_logic); -end opb_m_if; - -architecture behavior of opb_m_if is - - type state_t is (idle, - wait_grant, - transfer_write, - transfer_read, - done); - - - signal state : state_t := idle; - - signal M_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal M_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - - signal M_select_int : std_logic; - signal read_transfer : boolean; - - -- read transfer - signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_en : std_logic; - signal opb_tx_dma_num_int : std_logic_vector(15 downto 0); - signal opb_tx_dma_done_int : std_logic; - - -- write transfer - signal opb_rx_dma_en : std_logic; - signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_num_int : std_logic_vector(15 downto 0); - signal opb_rx_dma_done_int : std_logic; - - - -begin -- behavior - - --* convert M_DBus_big_end to little endian - process(M_DBus_big_end) - begin - for i in 0 to 31 loop - M_DBus(31-i) <= M_DBus_big_end(i); - end loop; -- i - end process; - - --* convert M_ABus_big_end to little endian - process(M_ABus_big_end) - begin - for i in 0 to 31 loop - M_ABus(31-i) <= M_ABus_big_end(i); - end loop; -- i - end process; - - --* convert OPB_DBus to bi endian - process(OPB_DBus) - begin - for i in 0 to 31 loop - OPB_DBus_big_end(31-i) <= OPB_DBus(i); - end loop; -- i - end process; - - -- for both sides - M_ABus_big_end <= opb_tx_dma_addr_int when (M_select_int = '1' and (read_transfer = true)) else - opb_rx_dma_addr_int when (M_select_int = '1' and (read_transfer = false)) else - (others => '0'); - M_select <= M_select_int; - - - - -- write transfer - opb_m_rx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = false)) else - '0'; - - M_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_m_rx_data when (M_select_int = '1' and (read_transfer = false)) else - (others => '0'); - M_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); - - opb_tx_dma_done <= opb_tx_dma_done_int; - - -- read transfer - opb_m_tx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = true)) else - '0'; - opb_m_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); - - opb_rx_dma_done <= opb_rx_dma_done_int; - - - -------------------------------------------------------------------------------- - opb_masteer_proc: process(OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - M_BE <= (others => '0'); - M_busLock <= '0'; - M_request <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_seqAddr <= '0'; - opb_tx_dma_done_int <= '0'; - opb_rx_dma_done_int <= '0'; - elsif rising_edge(OPB_Clk) then - case state is - when idle => - opb_tx_dma_en <= opb_tx_dma_ctl(0); - opb_rx_dma_en <= opb_rx_dma_ctl(0); - - if (opb_tx_dma_ctl(0) = '1' and opb_tx_dma_en = '0') then - opb_tx_dma_addr_int <= opb_tx_dma_addr; - opb_tx_dma_num_int <= opb_tx_dma_num; - opb_tx_dma_done_int <= '0'; - - end if; - - if (opb_rx_dma_ctl(0) = '1' and opb_rx_dma_en = '0') then - opb_rx_dma_addr_int <= opb_rx_dma_addr; - opb_rx_dma_num_int <= opb_rx_dma_num; - opb_rx_dma_done_int <= '0'; - end if; - - if (opb_tx_dma_en = '1' and opb_m_tx_req = '1' and opb_tx_dma_done_int = '0') then - -- read from memory to fifo - M_request <= '1'; - read_transfer <= true; - state <= wait_grant; - elsif (opb_rx_dma_en = '1' and opb_m_rx_req = '1'and opb_rx_dma_done_int = '0') then - -- read from fifo and write memory - M_request <= '1'; - read_transfer <= false; - state <= wait_grant; - else - state <= idle; - end if; - - when wait_grant => - if (MOPB_MGrant = '1') then - M_request <= '0'; - M_busLock <= '1'; - M_select_int <= '1'; - M_seqAddr <= '1'; - M_BE <= "1111"; - if (read_transfer) then - -- read - M_RNW <= '1'; - state <= transfer_read; - else - -- write - M_RNW <= '0'; - state <= transfer_write; - end if; - else - state <= wait_grant; - end if; - - when transfer_read => - if (MOPB_xferAck = '1') then - opb_tx_dma_addr_int <= opb_tx_dma_addr_int +4; - if (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then - -- cycle 14 - -- deassert buslock and seq_address 1 cycle before transfer complete - M_busLock <= '0'; - M_seqAddr <= '0'; - elsif (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then - -- cycle 15 - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - if (conv_integer(opb_tx_dma_num_int) = 0) then - opb_tx_dma_done_int <= '1'; - else - opb_tx_dma_num_int <= opb_tx_dma_num_int-1; - end if; - state <= done; - end if; - elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then - -- cancel transfer - M_busLock <= '0'; - M_seqAddr <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - state <= done; - else - state <= transfer_read; - end if; - - when transfer_write => - if (MOPB_xferAck = '1') then - opb_rx_dma_addr_int <= opb_rx_dma_addr_int +4; - if (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then - -- cycle 14 - -- deassert buslock and seq_address 1 cycle before transfer complete - M_busLock <= '0'; - M_seqAddr <= '0'; - elsif (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then - -- cycle 15 - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - if (conv_integer(opb_rx_dma_num_int) = 0) then - opb_rx_dma_done_int <= '1'; - else - opb_rx_dma_num_int <= opb_rx_dma_num_int-1; - end if; - state <= done; - end if; - elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then - -- cancel transfer - M_busLock <= '0'; - M_seqAddr <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - state <= done; - else - state <= transfer_write; - end if; - - when done => - - state <= idle; - - when others => - state <= idle; - end case; - end if; - end process opb_masteer_proc; -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (nonexistent) @@ -1,45 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short convert binary input vector to gray ---* ---* @generic width with of input vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity bin2gray is - generic ( - width : integer := 4); - port ( - in_bin : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); -end bin2gray; - -architecture behavior of bin2gray is - -begin -- behavior - - -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 - --* convert binary input vector to gray - bin2gray_proc : process(in_bin) - begin - out_gray(width-1) <= in_bin(width-1); - -- out_gray(3) <= in_bin(3); - - for i in 1 to width-1 loop - out_gray(width-1-i) <= in_bin(width-i) xor in_bin(width-1-i); - end loop; -- i - end process bin2gray_proc; - - -- i=1 out_gray(2) <= in_bin(3) xor in_bin(2); - -- i=2 out_gray(1) <= in_bin(2) xor in_bin(1); - -- i=3 out_gray(0) <= in_bin(1) xor in_bin(0); - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (nonexistent) @@ -1,52 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Control Unit for IRQ detection, enable and clear ---* ---* @generic C_ACTIVE_EDGE Select active edge for IRQ-Source 0: H->L;1: L->H ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -entity irq_ctl is - generic ( - C_ACTIVE_EDGE : std_logic := '0'); - port ( - rst : in std_logic; - clk : in std_logic; - opb_fifo_flg : in std_logic; - opb_ier : in std_logic; - opb_isr : out std_logic; - opb_isr_clr : in std_logic); - -end irq_ctl; - -architecture behavior of irq_ctl is - - signal opb_fifo_flg_int : std_logic; - signal opb_fifo_flg_reg : std_logic; -begin -- behavior - - opb_fifo_flg_int <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else - not opb_fifo_flg; - - irq_ctl_proc: process(rst, clk) - begin - if (rst = '1') then - opb_isr <= '0'; - elsif rising_edge(clk) then - opb_fifo_flg_reg <= opb_fifo_flg_int; - if (opb_ier= '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then - opb_isr <= '1'; - elsif (opb_isr_clr = '1') then - opb_isr <= '0'; - end if; - end if; - end process irq_ctl_proc; - - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (nonexistent) @@ -1,45 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short convert gray input vector to binary ---* ---* @generic width with of input vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity gray2bin is - generic ( - width : integer := 4); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); -end gray2bin; - -architecture behavior of gray2bin is - - signal out_bin_int : std_logic_vector(width-1 downto 0); -begin -- behavior - - out_bin <= out_bin_int; - - -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 - --* convert gray input vector to binary - gray2bin_proc: process(in_gray, out_bin_int) - begin - out_bin_int(width-1) <= in_gray(width-1); - -- out_gray(3) <= in_gray(3); - for i in 1 to width-1 loop - out_bin_int(width-1-i) <= out_bin_int(width-i) xor in_gray(width-1-i); - end loop ; -- i - end process gray2bin_proc; - -- i=1 out_bin(2) <= out_bin_int(3) xor out_bin(2); - -- i=2 out_bin(1) <= out_bin_int(2) xor out_bin(1); - -- i=3 out_bin(0) <= out_bin_int(1) xor out_bin(0); -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (nonexistent) @@ -1,336 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short OPB-Slave Interface ---* ---* Generics described in top entity. ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -library work; -use work.opb_spi_slave_pack.all; - -entity opb_if is - - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 3; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - C_FAMILY : string := "virtex-4"; - C_SR_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4; - C_DMA_EN : boolean := true); - port ( - -- OPB-Bus Signals - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - -- fifo ports - opb_s_tx_en : out std_logic; - opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_s_rx_en : out std_logic; - opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- control register - opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - -- Fifo almost full/empty thresholds - tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); - -- interrupts - opb_dgie : out std_logic; - opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); - -- dma register - opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_ctl : out std_logic_vector(0 downto 0); - opb_tx_dma_num : out std_logic_vector(15 downto 0); - opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_ctl : out std_logic_vector(0 downto 0); - opb_rx_dma_num : out std_logic_vector(15 downto 0)); -end opb_if; - -architecture behavior of opb_if is - - - signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - - - type state_t is (idle, - done); - signal state : state_t := idle; - - -- internal signals to enable readback - - signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_dgie_int : std_logic; - - signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - - - -- only used if C_DMA_EN=true - signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0); - signal opb_tx_dma_num_int : std_logic_vector(15 downto 0); - signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0); - signal opb_rx_dma_num_int : std_logic_vector(15 downto 0); - -begin -- behavior - - tx_thresh <= tx_thresh_int; - rx_thresh <= rx_thresh_int; - opb_ier <= opb_ier_int; - opb_dgie <= opb_dgie_int; - - opb_ctl_reg <= opb_ctl_reg_int; - - --* Signals for DMA-Engine control - u1 : if C_DMA_EN generate - opb_tx_dma_ctl <= opb_tx_dma_ctl_int; - opb_tx_dma_addr <= opb_tx_dma_addr_int; - opb_tx_dma_num <= opb_tx_dma_num_int; - opb_rx_dma_ctl <= opb_rx_dma_ctl_int; - opb_rx_dma_addr <= opb_rx_dma_addr_int; - opb_rx_dma_num <= opb_rx_dma_num_int; - end generate u1; - - --- unused outputs - Sln_errAck <= '0'; - Sln_retry <= '0'; - Sln_toutSup <= '0'; - - --* convert Sln_DBus_big_end to little mode - conv_big_Sln_DBus_proc: process(Sln_DBus_big_end) - begin - for i in 0 to 31 loop - Sln_DBus(31-i) <= Sln_DBus_big_end(i); - end loop; -- i - end process conv_big_Sln_DBus_proc; - - --* convert OPB_ABus to big endian - conv_big_OPB_ABus_proc: process(OPB_ABus) - begin - for i in 0 to 31 loop - OPB_ABus_big_end(31-i) <= OPB_ABus(i); - end loop; -- i - end process conv_big_OPB_ABus_proc; - - --* convert OPB_DBus to little mode - conv_big_OPB_DBus_proc: process(OPB_DBus) - begin - for i in 0 to 31 loop - OPB_DBus_big_end(31-i) <= OPB_DBus(i); - end loop; -- i - end process conv_big_OPB_DBus_proc; - - --* control OPB requests - --* - --* handles OPB-read and -write request - opb_slave_proc: process (OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - -- OPB - Sln_xferAck <= '0'; - Sln_DBus_big_end <= (others => '0'); - -- FIFO - opb_s_rx_en <= '0'; - opb_s_tx_en <= '0'; - -- - state <= idle; - -- Register - tx_thresh_int <= (others => '0'); - rx_thresh_int <= (others => '0'); - opb_ier_int <= (others => '0'); - opb_dgie_int <= '0'; - opb_ctl_reg_int <= (others => '0'); - - if C_DMA_EN then - opb_tx_dma_ctl_int <= (others => '0'); - opb_tx_dma_addr_int <= (others => '0'); - opb_tx_dma_num_int <= (others => '0'); - opb_rx_dma_ctl_int <= (others => '0'); - opb_rx_dma_addr_int <= (others => '0'); - opb_rx_dma_num_int <= (others => '0'); - end if; - - - elsif (OPB_Clk'event and OPB_Clk = '1') then - case state is - when idle => - if (OPB_select = '1' and - ((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then - -- *device selected - Sln_xferAck <= '1'; - state <= done; - if (OPB_RNW = '1') then - -- read acess - case OPB_ABus_big_end(7 downto 2) is - when C_ADR_CTL => - Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int; - - when C_ADR_RX_DATA => - opb_s_rx_en <= '1'; - Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data; - - when C_ADR_STATUS => - Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg; - - when C_ADR_TX_THRESH => - Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); - Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); - - when C_ADR_RX_THRESH => - Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); - Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); - - when C_ADR_DGIE => - Sln_DBus_big_end(0) <= opb_dgie_int; - when C_ADR_IER => - Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int; - - when C_ADR_ISR => - Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr; - - when C_ADR_TX_DMA_CTL => - if C_DMA_EN then - Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int; - end if; - - when C_ADR_TX_DMA_ADDR => - if C_DMA_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int; - end if; - - when C_ADR_TX_DMA_NUM => - if C_DMA_EN then - Sln_DBus_big_end(15 downto 0) <= opb_tx_dma_num_int; - end if; - - - when C_ADR_RX_DMA_CTL => - if C_DMA_EN then - Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int; - end if; - - when C_ADR_RX_DMA_ADDR => - if C_DMA_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int; - end if; - - when C_ADR_RX_DMA_NUM => - if C_DMA_EN then - Sln_DBus_big_end(15 downto 0) <= opb_rx_dma_num_int; - end if; - - - - when others => - null; - end case; - else - -- write acess - case OPB_ABus_big_end(7 downto 2) is - when C_ADR_CTL => - opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0); - - when C_ADR_TX_DATA => - opb_s_tx_en <= '1'; - opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); - - when C_ADR_TX_THRESH => - tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); - tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); - - when C_ADR_RX_THRESH => - rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); - rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); - - when C_ADR_DGIE => - opb_dgie_int <= OPB_DBus_big_end(0); - - when C_ADR_IER => - opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); - - when C_ADR_ISR => - opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); - - when C_ADR_TX_DMA_CTL => - if C_DMA_EN then - opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); - end if; - - when C_ADR_TX_DMA_ADDR => - if C_DMA_EN then - opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); - end if; - - when C_ADR_TX_DMA_NUM => - if C_DMA_EN then - opb_tx_dma_num_int <= OPB_DBus_big_end(15 downto 0); - end if; - - when C_ADR_RX_DMA_CTL => - if C_DMA_EN then - opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); - end if; - - when C_ADR_RX_DMA_ADDR => - if C_DMA_EN then - opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); - end if; - - when C_ADR_RX_DMA_NUM => - if C_DMA_EN then - opb_rx_dma_num_int <= OPB_DBus_big_end(15 downto 0); - end if; - - when others => - null; - end case; - end if; -- OPB_RNW - else - -- not selected - state <= idle; - end if; - when done => - opb_ctl_reg_int(3) <= '0'; - opb_isr_clr <= (others => '0'); - opb_s_rx_en <= '0'; - opb_s_tx_en <= '0'; - Sln_xferAck <= '0'; - Sln_DBus_big_end <= (others => '0'); - state <= idle; - - when others => - state <= idle; - end case; - end if; - end process opb_slave_proc; -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (nonexistent) @@ -1,46 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short RAM Sync-Write, Async Read ---* ---* @generic C_FIFO_WIDTH RAM-With (1..xx) ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity ram is - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4); - - port (clk : in std_logic; - we : in std_logic; - a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); -end ram; - -architecture behavior of ram is - type ram_type is array (2**C_FIFO_SIZE_WIDTH-1 downto 0) of std_logic_vector (C_FIFO_WIDTH-1 downto 0); - signal RAM : ram_type; -begin - - process (clk) - begin - if (clk'event and clk = '1') then - if (we = '1') then - RAM(conv_integer(a)) <= di; - end if; - end if; - end process; - - dpo <= RAM(conv_integer(dpra)); - -end behavior; Index: tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (nonexistent) @@ -1,7 +0,0 @@ -NET "mosi" TNM = "_mosi"; -TIMEGRP "_mosi" OFFSET = IN 5 ns VALID 10 ns BEFORE "sclk" HIGH ; - -NET "miso_o" TNM = "_miso_o"; -TIMEGRP "_miso_o" OFFSET = OUT 10 ns AFTER "sclk" LOW ; - - Index: tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (nonexistent) @@ -1,18 +0,0 @@ -############################################################################## -## Filename: E:\Eigene_Dateien\Entwicklung\cpld\spi-core\edk\test_opb_spi_slave\pcores/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao -## Description: Peripheral Analysis Order -## Date: Mon Oct 29 20:54:19 2007 (by Create and Import Peripheral Wizard) -############################################################################## - -lib opb_spi_slave_v1_00_a opb_spi_slave_pack vhdl -lib opb_spi_slave_v1_00_a shift_register vhdl -lib opb_spi_slave_v1_00_a bin2gray vhdl -lib opb_spi_slave_v1_00_a gray2bin vhdl -lib opb_spi_slave_v1_00_a gray_adder vhdl -lib opb_spi_slave_v1_00_a fifo vhdl -lib opb_spi_slave_v1_00_a fifo_prog_flags vhdl -lib opb_spi_slave_v1_00_a irq_ctl vhdl -lib opb_spi_slave_v1_00_a opb_m_if vhdl -lib opb_spi_slave_v1_00_a opb_if vhdl -lib opb_spi_slave_v1_00_a opb_spi_slave vhdl -lib opb_spi_slave_v1_00_a ram vhdl Index: tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd =================================================================== --- tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (revision 34) +++ tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (nonexistent) @@ -1,72 +0,0 @@ -################################################################### -## -## Name : opb_spi_slave -## Desc : Microprocessor Peripheral Description -## : Automatically generated by PsfUtility -## -################################################################### - -BEGIN opb_spi_slave - -## Peripheral Options -OPTION IPTYPE = PERIPHERAL -OPTION IMP_NETLIST = TRUE -OPTION HDL = VHDL -OPTION CORE_STATE = ACTIVE -OPTION IP_GROUP = MICROBLAZE:PPC:USER - - -## Bus Interfaces -BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB - -## Generics for VHDL or Parameters for Verilog -PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR -PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR -PARAMETER C_USER_ID_CODE = 0, DT = INTEGER -PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB -PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB -PARAMETER C_FAMILY = virtex-4, DT = STRING -PARAMETER C_SR_WIDTH = 8, DT = INTEGER -PARAMETER C_MSB_FIRST = true, DT = BOOLEAN -PARAMETER C_CPOL = 0, DT = INTEGER -PARAMETER C_PHA = 0, DT = INTEGER -PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER -PARAMETER C_DMA_EN = true, DT = BOOLEAN - -## Ports -PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB -PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB -PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK -PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB -PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST -PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB -PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB -PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB -PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB -PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB -PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB -PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB -PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB -PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB -PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT M_request = M_request, DIR = O, BUS = MSOPB -PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB -PORT M_select = M_select, DIR = O, BUS = MSOPB -PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB -PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB -PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB -PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB -PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB -PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB -PORT sclk = "", DIR = I, SIGIS = CLK -PORT ss_n = "", DIR = I -PORT mosi = "", DIR = I -PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T -PORT miso_o = "", DIR = O -PORT miso_i = "", DIR = I -PORT miso_t = "", DIR = O -PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH - -END Index: trunk/doc/src/Grafik/block_diagramm.eps =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/Grafik/block_diagramm.eps =================================================================== --- trunk/doc/src/Grafik/block_diagramm.eps (revision 34) +++ trunk/doc/src/Grafik/block_diagramm.eps (nonexistent)

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trunk/doc/src/Grafik/block_diagramm.odg Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/src/opb_spi_slave.tex =================================================================== --- trunk/doc/src/opb_spi_slave.tex (revision 34) +++ trunk/doc/src/opb_spi_slave.tex (nonexistent) @@ -1,46 +0,0 @@ -\documentclass[11pt, a4paper, german, oneside]{scrbook} -\textheight240mm -\usepackage{hyperref} -\usepackage[latin1]{inputenc} -\usepackage{graphicx} -\usepackage{colortbl} -\usepackage{tabularx} -\usepackage{longtable} -\definecolor{yellow1}{rgb}{0.98, 1.0, 0.6} -\pagestyle{plain} -\pagenumbering{arabic} -\usepackage{verbatim} - -\title{Specification OPB-SPI Slave} -\author{Daniel Koethe} -\date{\today} - - -\begin{document} - \maketitle -\tableofcontents - -\input{content/spec} - - -% Anhang (Bibliographie darf im deutschen nicht in den Anhang!) -\bibliography{bib/BibtexDatabase} -\bibliographystyle{plain} -\clearpage -\listoffigures -\listoftables - - - - - - - -% Anhang -\appendix -\input{content/Z-Anhang} - - -%% Dokument ENDE %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\end{document} - Index: trunk/doc/src/content/Z-Anhang.tex =================================================================== --- trunk/doc/src/content/Z-Anhang.tex (revision 34) +++ trunk/doc/src/content/Z-Anhang.tex (nonexistent) @@ -1,3 +0,0 @@ -% \input{content/Z-Anhang-01-Herleitungen} - -\chapter*{} Index: trunk/doc/src/content/spec.tex =================================================================== --- trunk/doc/src/content/spec.tex (revision 34) +++ trunk/doc/src/content/spec.tex (nonexistent) @@ -1,374 +0,0 @@ -\chapter{Introduction} -This document describe a SPI Slave core designed for the Xilinx EDK. \cite{bib_xilinx_edk} - -\section{Features} -\begin{itemize} -\item OPB-Clock and SPI-Clock are complete independent -\item SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX-FIFO Overrunn occure. -\item variable transfer length 2..32 -\end{itemize} - - - - -\section{Limitations} -\begin{itemize} -\item designed only for Xilinx Spartan-3/Virtex-4 at the moment -\item only Slave Operation -\end{itemize} - -\chapter{Core configuration} -\begin{table} [h] - \centering - \begin{tabularx} {160mm} {|l|l|c|X|} \hline - Description & Parameter Name & Allowable Values & Default Value \\ \hline - \multicolumn{4} {|c|} {System Parameter} \\ \hline - Base address for OPB SPI& C\_BASEADDR & 0x00 & 0x00000000 \\ \hline - High address for OPB SPI& C\_HIGHADDR & BASEADDR+0x3F & BASEADDR+0x3f \\ \hline - OPB address bus width & C\_OPB\_AWIDTH & 32 & 32 \\ \hline - OPB data bus width & C\_OPB\_DWIDTH & 32 & 32 \\ \hline - Target FPGA Family & C\_FAMILY & spartan3,virtex4 & virtex4 \\ \hline - \multicolumn{4} {|c|} {User Parameter} \\ \hline - Shift register width & C\_SR\_WIDTH & 8-32 & 8 \\ \hline - Shift MSB First & C\_MSB\_FIRST & true, false & true \\ \hline - SPI Clock Polarity & C\_CPOL & 0,1 & 0 \\ \hline - SPI Clock Phase & C\_CPHA & 0,1 & 0 \\ \hline - FIFO Size Width(TX/RX)\footnotemark[1] & C\_FIFO\_DEPTH & 4-7 & 4 \\ \hline - DMA\_EN & C\_DMA\_EN & true, false & false \\ \hline - \end{tabularx} - \caption{Generics} - \label{tab:Generics} -\end{table} - -\footnotetext[1]{FIFO depth is $2^{Value}$ =(16,32,64,128)} - - - -\chapter{IO-Ports} -\begin{table} [h] - \centering - \begin{tabularx} {160mm}{|l|l|l|X|} \hline - \textbf{Port} & \textbf{width} & \textbf{direction} & \textbf{Description} \\ \hline - SPI\_SCLK & 1 & input & Serial clock input \\ - SPI\_MOSI & 1 & input & Master Out Slave in \\ - SPI\_MISO & 1 & output & Master in Slave out \\ - SPI\_SS & 1 & input & Slave select \\ \hline - opb\_irq & 1 & output & IRQ Output \\ \hline - \end{tabularx} - \caption{external ports} - \label{tab:externalPorts} -\end{table} - -\chapter{Registers} -\section{Adressmap} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm} {|l|c|c|X|} \hline - \textbf{Name} & \textbf{Adress} & \textbf{Acess} & \textbf{Description} \\ \hline - SPI\_CR & 0x00 & R/W & SPI Control Register \\ \hline - SPI\_SR & 0x04 & R/W & SPI Status Register \\ \hline - SPI\_TD & 0x08 & W & SPI Transmit Data Register \\ \hline - SPI\_RD & 0x0C & R & SPI Receive Data Register \\ \hline - TX\_THRESH & 0x10 & R/W & TX-Threshold Prog Full/Emty \\ \hline - RX\_THRESH & 0x14 & R/W & RX-Threshold Prog Full/Emty \\ \hline - TX\_DMA\_CTL & 0x18 & R/W & TX DMA Control \\ \hline - TX\_DMA\_ADDR & 0x1C & R/W & TX DMA Base Adress Offset \\ \hline - TX\_DMA\_NUM & 0x20 & R/W & TX DMA Number of Transfers \\ \hline - RX\_DMA\_CTL & 0x24 & R/W & RX DMA Control \\ \hline - RX\_DMA\_ADDR & 0x28 & R/W & RX DMA Base Adress Offset \\ \hline - RX\_DMA\_NUM & 0x2C & R/W & RX DMA Number of Transfers \\ \hline - - DGIE & 0x40 & R/W & Device global IRQ Enable Register \\ \hline - IPISR & 0x44 & R/W & IRQ Status Register \\ \hline - IPIER & 0x48 & R/W & IRQ Enable Register \\ \hline - \end{tabularx} - \caption{Address-Map} - \label{tab:registers} -\end{table} - -\section{SPI\_CR} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1.5cm}|p{3cm}|p{1.5cm}|p{1.5cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & DGE & R/W & 0 & Device Global Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 30 & TX\_EN & R/W & 0 & Transmit Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29 & RX\_EN & R/W & 0 & Receive Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29 & RESET & R/W & 0 & Reset Device(self cleared) \\ - & & & & 0: Normal Operation \\ - & & & & 1: Reset SPI-Core(SR/FIFO) \\ \hline - 28..0 & \multicolumn{4} {c|} {reserved} \\ \hline - \end{tabularx} - \caption{SPI\_CR Register} - \label{tab:SPI_CR} -\end{table} - - -\section{SPI\_SR} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX Prog Full & R & 0 & Prog Full Flag \\ - & & & & 1: FIFO Prog Full \\ \hline - 30 & TX Full & R & 0 & Full Flag \\ - & & & & 1: FIFO Full \\ \hline - 29 & TX Overflow & R & 0 & Overflow Flag \\ - & & & & 1: FIFO Overflow \\ - & & & & (Cleared only at Reset) \\ \hline - 28 & TX Prog Empty & R & 0 & Prog Empty Flag \\ - & & & & 1: FIFO Prog Empty \\ \hline - 27 & TX Empty & R & 0 & Full Flag \\ - & & & & 1: FIFO Empty \\ \hline - 26 & TX Underflow & R & 0 & Underflow Flag \\ - & & & & 1: FIFO Underflow \\ - & & & & (Cleared only at Reset) \\ \hline - 25 & RX Prog Full & R & 0 & Prog Full Flag \\ - & & & & 1: FIFO Prog Full \\ \hline - 24 & RX Full & R & 0 & Full Flag \\ - & & & & 1: FIFO Full \\ \hline - 23 & RX Overflow & R & 0 & Overflow Flag \\ - & & & & 1: FIFO Overflow \\ - & & & & (Cleared only at Reset) \\ \hline - 22 & RX Prog Empty & R & 0 & Prog Empty Flag \\ - & & & & 1: FIFO Prog Empty \\ \hline - 21 & RX Empty & R & 0 & Full Flag \\ - & & & & 1: FIFO Empty \\ \hline - 20 & RX Underflow & R & 0 & Underflow Flag \\ - & & & & 1: FIFO Underflow \\ - & & & & (Cleared only at Reset) \\ \hline - 19 & Chip Select & R & 0 & Chip Select Flag \\ - & & & & 0: CS\_N Low \\ - & & & & 1: CS\_N High \\ \hline - 18 & TX DMA Done & R & 0 & Transmit DMA done \\ - & & & & 0: TX DMA in progress \\ - & & & & 1: TX DMA all Transfers done\\ \hline - 17 & RX DMA Done & R & 0 & Receive DMA done \\ - & & & & 0: RX DMA in progress \\ - & & & & 1: RX DMA all Transfers done\\ \hline - 16:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} - \caption{SPI\_SR Register} - \label{tab:SPI_SR} -\end{table} - -\section{TX\_THRESH} -\begin{table}[!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ - & & & \textbf{Value} & \\ \hline - 31:16 & TX\_THRESH\_PROG\_FULL & R/W & 0 & Transmit Prog Full Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - 15:0 & TX\_THRESH\_PROG\_EMPTY & R/W & 0 & Transmit Prog Empty Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - \end{tabularx} - \caption{TX\_THRESH Register} - \label{tab:TX_THRESH} -\end{table} - -This Register sets the Almost Full and Empty Flag Thresholds for Transmit FIFO. IF the DMA-Engine is used, the TX\_THRESH\_PROG\_EMPTY is used to trigger the DMA-Transfer. If Transmit FIFO is Almost Empty the Engine fills the FIFO with 16 Words(4..32bit). If the OPB-Bus is at medium or full load, increase Almost Empty Threshold to ensure there are ''some bytes reserve'' in Fifo until the DMA-Engine has access to the bus and can start transfer. Under light load condition a value of 4 should sufficient. - - -\section{RX\_THRESH} -\begin{table}[!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ - & & & \textbf{Value} & \\ \hline - 31:16 & RX\_THRESH\_PROG\_FULL & R/W & 0 & Receive Prog Full Threshold \\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline - 15:0 & RX\_THRESH\_PROG\_EMPTY & R/W & 0 & Receive Prog Empty Threshold\\ - & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline \end{tabularx} - \caption{RX\_THRESH Register} - \label{tab:RX_THRESH} -\end{table} - -This Register sets the Almost Full and Empty Flag Thresholds for Receive FIFO. IF the DMA-Engine is used, the RX\_THRESH\_PROG\_FULL is used to trigger the DMA-Transfer. Normally set this Threshold to the block size of 16. If the OPB-Bus is at medium or full load, increase the FIFO Size(C\_FIFO\_WIDTH) to ensure there are 'some bytes free'' in FIFO until overflow occurs. - - -\section{TX\_DMA\_CTL} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} - \caption{TX\_DMA\_CTL Register} - \label{tab:tx_dma_ctl} -\end{table} -This Register is only available if C\_DMA\_EN is set. -Set the Bit TX\_DMA\_EN to 1 to enable the Transmit DMA Engine. With Engine Start the Register TX\_DMA\_ADDR and TX\_DMA\_NUM are copied to internal register. Do not change this Registers if DMA Enable set. - -\section{TX\_DMA\_ADDR} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31:0 & TX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline - \end{tabularx} - \caption{TX\_DMA\_ADDR Register} - \label{tab:tx_dma_addr} -\end{table} - -This Register is only available if C\_DMA\_EN is set. With this Register the Base-Adress of the TX-DMA is set. The Adress must 4 Byte aligned. Remark: For this memory area the Data-Chache of the Microblaze can be enabled, because the Cache is a Write-True type. Using a controller with write-back cache only the first write will written in memory, the second only in the internal cache. - -\section{TX\_DMA\_NUM} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31:8 & TX\_DMA\_LEN & R/W & 0 & TX DMA Number of Block Transfers \\ \hline - 7:0 & \multicolumn{4} {c|} {reserved} \\ \hline - \end{tabularx} - \caption{TX\_DMA\_NUM Register} - \label{tab:tx_dma_len} -\end{table} -This Register is only available if C\_DMA\_EN is set. The Register set the Number of Blocktransfers. If all transfers done, the IRQ TX DMA Done asserted. The block size of the DMA is 16. A system configured with C\_SR\_WIDTH = 8 transfers 16 Bytes, if C\_SR\_WIDTH=32 64 Bytes are written to or read from the memory in one DMA-Cycle. - -\section{RX\_DMA\_CTL} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & RX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\ - & & & & 0: Disable \\ - & & & & 1: Enable \\ \hline - 29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} - \caption{RX\_DMA\_CTL Register} - \label{tab:RX_dma_ctl} -\end{table} - -This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_CTL for Description. - - -\section{RX\_DMA\_ADDR} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31:0 & RX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline - \end{tabularx} - \caption{RX\_DMA\_ADDR Register} - \label{tab:RX_dma_addr} -\end{table} - -This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_ADDR for Description. -\newline -\fbox{\parbox{160mm} {Remark: Check RX\_DMA\_ADDR that is set to the right memory section. If wrong set, program-Code or date overwritten with SPI-Data!}} - -\section{RX\_DMA\_NUM} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31:8 & RX\_DMA\_LEN & R/W & 0 & RX DMA Number of Block Transfers \\ \hline - 7:0 & \multicolumn{4} {c|} {reserved} \\ \hline - \end{tabularx} - \caption{RX\_DMA\_NUM Register} - \label{tab:RX_dma_len} -\end{table} - -This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_NUM for Description. - -\section{IPISR} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX\_Prog\_Empty & R/ToW\footnotemark[1] & 0 & IRQ Prog Empty Flag \\ \hline - 29 & TX\_Empty & R/ToW & 0 & IRQ Full Flag \\ \hline - 28 & RX\_Prog\_Full& R/ToW & 0 & IRQ Prog Full Flag \\ \hline - 27 & RX\_Full & R/ToW & 0 & IRQ Full Flag \\ \hline - 26 & SS\_FALL & R/ToW & 0 & IRQ SS FALL Flag \\ \hline - 25 & SS\_RISE & R/ToW & 0 & IRQ SS RISE Flag \\ \hline - 24..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} - \caption{IPISR Register} - \label{tab:IPISR} -\end{table} - -\footnotetext[1]{Read and ToggleOnWrite (writing 1 clears the bit)} - -\section{IPISE} -\begin{table} [!h] - \centering - \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline - \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline - 31 & TX\_Prog\_Empty & R/W & 0 & IRQ Prog Empty Enable \\ \hline - 29 & TX\_Empty & R/W & 0 & IRQ Full Enable \\ \hline - 28 & RX\_Prog\_Full & R/W & 0 & IRQ Prog Full Enable \\ \hline - 27 & RX\_Full & R/W & 0 & IRQ Full Enable \\ \hline - 26 & SS\_FALL & R/W & 0 & IRQ SS FALL Enable \\ \hline - 25 & SS\_RISE & R/W & 0 & IRQ SS RISE Enable \\ \hline - 24 & TX\_DMA\_DONE & R/W & 0 & IRQ TX Transfer done Enable\\ \hline - 23 & TX\_DMA\_DONE & R/W & 0 & IRQ RX Transfer done Enable\\ \hline - 22..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} - \caption{IPISE Register} - \label{tab:IPISE} -\end{table} - - -\chapter{System Integration} -To integrate this IP-Core in your System, unzip the opb\_spi\_slave.zip to your project-directory. Then Rescan the user repository with \textit{Project $\rightarrow$ Rescan User Repositories}. This will take some seconds. After this you find the core in the \textit{IP Catalog $\rightarrow$ Project Repository}. - -\section{MPD-File} -\begin{verbatim} -BEGIN opb_spi_slave - PARAMETER INSTANCE = opb_spi_slave_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0x7d600000 - PARAMETER C_HIGHADDR = 0x7d60ffff - BUS_INTERFACE MSOPB = mb_opb - PORT sclk = opb_spi_slave_0_sclk - PORT ss_n = opb_spi_slave_0_ss_n - PORT mosi = opb_spi_slave_0_mosi - PORT miso = opb_spi_slave_0_miso - PORT opb_irq = opb_spi_slave_0_opb_irq -END -\end{verbatim} - -\section{UCF-File} -\begin{verbatim} -# assign I/O Pins -NET opb_spi_slave_0_sclk_pin LOC= AA24; # must CC capable IO in virtex-4 -NET opb_spi_slave_0_ss_n_pin LOC= V20; -NET opb_spi_slave_0_mosi_pin LOC= AC25; -NET opb_spi_slave_0_miso_pin LOC= AC24; -NET opb_spi_slave_0_miso_pin SLEW = FAST; - -#### Module OPB_SPI_Slave constraints -Net opb_spi_slave_0_sclk_pin TNM_NET = spi_clk; -TIMESPEC TS_spi_clk = PERIOD spi_clk 40 ns; - -NET "opb_spi_slave_0_mosi_pin" TNM = "spi_in"; -#NET "opb_spi_slave_0_cs_n_pin" TNM = "spi_in"; -TIMEGRP "spi_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "opb_spi_slave_0_sclk_pin" HIGH ; - -NET "opb_spi_slave_0_miso_pin" TNM = "spi_out"; -TIMEGRP "spi_out" OFFSET = OUT 14 ns AFTER "opb_spi_slave_0_sclk_pin" LOW ; -\end{verbatim} - -\section{Register Header} - -\verbatiminput{opb_spi_slave.h} - - -\chapter{Operations} - - -\chapter{Architecture} - -\begin{figure}[h] - \centering - \includegraphics[width=1.00\textwidth]{Grafik/block_diagramm} - \caption{Blockdiagramm} - \label{fig:blockdiagramm} -\end{figure} - Index: trunk/doc/src/content/Titel.tex =================================================================== --- trunk/doc/src/content/Titel.tex (revision 34) +++ trunk/doc/src/content/Titel.tex (nonexistent) @@ -1,13 +0,0 @@ -\begin{titlepage} - \mbox{}\vspace{5\baselineskip}\\ - \sffamily\huge - \centering - specification OPB-SPI-Slave - \vspace{2\baselineskip}\\ - \rmfamily\Large - Daniel Koethe - \vspace{1\baselineskip}\\ - \today -\end{titlepage} - - Index: trunk/doc/src/opb_spi_slave.tcp =================================================================== --- trunk/doc/src/opb_spi_slave.tcp (revision 34) +++ trunk/doc/src/opb_spi_slave.tcp (nonexistent) @@ -1,12 +0,0 @@ -[FormatInfo] -Type=TeXnicCenterProjectInformation -Version=4 - -[ProjectInfo] -MainFile=opb_spi_slave.tex -UseBibTeX=0 -UseMakeIndex=0 -ActiveProfile=LaTeX => PDF -ProjectLanguage=de -ProjectDialect=DE - Index: trunk/doc/src/opb_spi_slave.h =================================================================== --- trunk/doc/src/opb_spi_slave.h (revision 34) +++ trunk/doc/src/opb_spi_slave.h (nonexistent) @@ -1,67 +0,0 @@ -#include "xparameters.h" - -#define XSS_CR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x00)) -#define XSS_SR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x01)) -#define XSS_TD (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x02)) -#define XSS_RD (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x03)) -#define XSS_TX_THRESH (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x04)) -#define XSS_RX_THRESH (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x05)) -#define XSS_TX_DMA_CTL (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x06)) -#define XSS_TX_DMA_ADR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x07)) -#define XSS_TX_DMA_NUM (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x08)) -#define XSS_RX_DMA_CTL (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x09)) -#define XSS_RX_DMA_ADR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x0A)) -#define XSS_RX_DMA_NUM (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x0B)) - -#define XSS_DGIE (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x10)) -#define XSS_IPISR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x11)) -#define XSS_IPIER (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x12)) - -//XSS_SPI_CR -#define XSS_CR_SPE_MASK (0x01) -#define XSS_CR_TX_EN_MASK (0x02) -#define XSS_CR_RX_EN_MASK (0x04) -#define XSS_CR_RESET_MASK (0x08) - -//XSS_SPI -// Transmit -#define XSS_SR_TX_PROG_FULL_MASK 0x0001 -#define XSS_SR_TX_FULL_MASK 0x0002 -#define XSS_SR_TX_OVERFLOW_MASK 0x0004 -#define XSS_SR_TX_PROG_EMPTY_MASK 0x0008 -#define XSS_SR_TX_EMPTY_MASK 0x0010 -#define XSS_SR_TX_UNDERFLOW_MASK 0x0020 -// Receive -#define XSS_SR_RX_PROG_FULL_MASK 0x0040 -#define XSS_SR_RX_FULL_MASK 0x0080 -#define XSS_SR_RX_OVERFLOW_MASK 0x0100 -#define XSS_SR_RX_PROG_EMPTY_MASK 0x0200 -#define XSS_SR_RX_EMPTY_MASK 0x0400 -#define XSS_SR_RX_UNDERFLOW_MASK 0x0800 -// Chip Select -#define XSS_SR_CHIP_SELECT_MASK 0x1000 -// DMA -#define XSS_SR_TX_DMA_done 0x2000 -#define XSS_SR_RX_DMA_done 0x4000 - - -// Device Global Interrupt Enable -#define XSS_DGIE_Bit_Enable 0x0001 - -// Interrupt /Enable Status Register -#define XSS_ISR_Bit_TX_Prog_Empty 0x0001 -#define XSS_ISR_Bit_TX_Empty 0x0002 -#define XSS_ISR_Bit_TX_Underflow 0x0004 -#define XSS_ISR_Bit_RX_Prog_Full 0x0008 -#define XSS_ISR_Bit_RX_Full 0x0010 -#define XSS_ISR_Bit_RX_Overflow 0x0020 -#define XSS_ISR_Bit_SS_Fall 0x0040 -#define XSS_ISR_Bit_SS_Rise 0x0080 -#define XSS_ISR_Bit_TX_DMA_done 0x0100 -#define XSS_ISR_Bit_RX_DMA_done 0x0200 - -// TX DMA Control Register -#define XSS_TX_DMA_CTL_EN 0x0001 - -// RX DMA Control Register -#define XSS_RX_DMA_CTL_EN 0x0001 Index: trunk/doc/vhdldoc_2007-11-22.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/vhdldoc_2007-11-22.zip =================================================================== --- trunk/doc/vhdldoc_2007-11-22.zip (revision 34) +++ trunk/doc/vhdldoc_2007-11-22.zip (nonexistent)

trunk/doc/vhdldoc_2007-11-22.zip Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/opb_spi_slave.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/opb_spi_slave.pdf =================================================================== --- trunk/doc/opb_spi_slave.pdf (revision 34) +++ trunk/doc/opb_spi_slave.pdf (nonexistent)

trunk/doc/opb_spi_slave.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do (nonexistent) @@ -1,13 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../bench/vhdl/images-body.vhd -vcom -93 ../../../../../bench/vhdl/txt_util.vhd -# DUT -vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd -vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd -vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd -vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd -vcom -93 ../../../../../rtl/vhdl/ram.vhd -vcom -93 ../../../../../rtl/vhdl/fifo.vhd -# Testbench -vcom -93 ../../../../../bench/vhdl/fifo_tb.vhd \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps fifo_tb -view wave -do fifo_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do (nonexistent) @@ -1,35 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_empty_thresh -add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_full_thresh -add wave -noupdate -divider {write port} -add wave -noupdate -format Logic /fifo_tb/wr_clk -add wave -noupdate -format Logic /fifo_tb/wr_en -add wave -noupdate -format Literal /fifo_tb/din -add wave -noupdate -divider read_port -add wave -noupdate -format Logic /fifo_tb/rd_clk -add wave -noupdate -format Logic /fifo_tb/rd_en -add wave -noupdate -format Literal /fifo_tb/dout -add wave -noupdate -divider flags -add wave -noupdate -format Logic /fifo_tb/prog_empty -add wave -noupdate -format Logic /fifo_tb/empty -add wave -noupdate -format Logic /fifo_tb/underflow -add wave -noupdate -format Logic /fifo_tb/prog_full -add wave -noupdate -format Logic /fifo_tb/full -add wave -noupdate -format Logic /fifo_tb/overflow -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {387500 ps} 0} -configure wave -namecolwidth 192 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {1160250 ps} Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do (nonexistent) @@ -1,64 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider OPB-Bus -add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rst -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_abus -add wave -noupdate -format Literal /opb_spi_slave_tb/opb_be -add wave -noupdate -format Logic /opb_spi_slave_tb/opb_clk -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_dbus -add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rnw -add wave -noupdate -format Logic /opb_spi_slave_tb/opb_select -add wave -noupdate -format Logic /opb_spi_slave_tb/opb_seqaddr -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/sln_dbus -add wave -noupdate -format Logic /opb_spi_slave_tb/sln_xferack -add wave -noupdate -divider SPI -add wave -noupdate -format Logic /opb_spi_slave_tb/sclk -add wave -noupdate -format Logic /opb_spi_slave_tb/ss_n -add wave -noupdate -format Logic /opb_spi_slave_tb/mosi -add wave -noupdate -format Logic /opb_spi_slave_tb/miso -add wave -noupdate -divider Internal -add wave -noupdate -format Literal /opb_spi_slave_tb/opb_read_data -add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/dout -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_thresh -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/rx_thresh -add wave -noupdate -format Literal /opb_spi_slave_tb/spi_value_in -add wave -noupdate -divider TX_FIFO -add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_full_thresh -add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty_thresh -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_clk -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_en -add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_fifo_1/din -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/empty -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/underflow -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_full -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/full -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/overflow -add wave -noupdate -divider RX_FIFO -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_clk -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_en -add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/din -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/empty -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_empty -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/underflow -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_full -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/full -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/overflow -add wave -noupdate -divider Internal -add wave -noupdate -format Logic /opb_spi_slave_tb/dut/opb_abort_flg -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {525982512 ps} 0} -configure wave -namecolwidth 302 -configure wave -valuecolwidth 53 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {568438500 ps} Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do (nonexistent) @@ -1,24 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd - -# DUT -vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd -vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd -vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd -vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd -vcom -93 ../../../../../rtl/vhdl/ram.vhd -vcom -93 ../../../../../rtl/vhdl/fifo.vhd -vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd -vcom -93 ../../../../../rtl/vhdl/opb_if.vhd -vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd -vcom -93 ../../../../../rtl/vhdl/shift_register.vhd -vcom -93 ../../../../../rtl/vhdl/irq_ctl.vhd -vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd -vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd -vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd -vcom -93 ../../../../../rtl/vhdl/crc_core.vhd -vcom -93 ../../../../../rtl/vhdl/opb_spi_slave.vhd - -# Testbench -vcom -93 ../../../../../bench/vhdl/opb_spi_slave_tb.vhd \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps opb_spi_slave_tb -view wave -do opb_spi_slave_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (nonexistent) @@ -1,53 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider Internal -add wave -noupdate -format Logic /opb_m_if_tb/opb_clk -add wave -noupdate -format Logic /opb_m_if_tb/opb_rst -add wave -noupdate -format Logic /opb_m_if_tb/m_request -add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant -add wave -noupdate -format Logic /opb_m_if_tb/m_buslock -add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr -add wave -noupdate -format Logic /opb_m_if_tb/m_select -add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack -add wave -noupdate -format Literal /opb_m_if_tb/m_be -add wave -noupdate -format Logic /opb_m_if_tb/m_rnw -add wave -noupdate -format Literal /opb_m_if_tb/m_abus -add wave -noupdate -format Literal /opb_m_if_tb/m_dbus -add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus -add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry -add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout -add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack -add wave -noupdate -divider T-FIFIO -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data -add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl -add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr -add wave -noupdate -divider R-FIFO -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data -add wave -noupdate -divider Internal -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_if_2/read_transfer -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/state -add wave -noupdate -format Literal -radix hexadecimal /opb_m_if_tb/opb_m_if_2/opb_tx_dma_addr_int -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/opb_rx_dma_addr_int -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1332415 ps} 0} -configure wave -namecolwidth 276 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {1055780 ps} Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (nonexistent) @@ -1,7 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd -# DUT -vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd -# Testbench -vcom -93 ../../../../../bench/vhdl/opb_m_if_tb.vhd \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps opb_m_if_tb -view wave -do opb_m_if_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps opb_if_tb -view wave -do opb_if_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do (nonexistent) @@ -1,8 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd -# DUT -vcom -93 ../../../../../rtl/vhdl/opb_if.vhd -# Testbench -vcom -93 ../../../../../bench/vhdl/opb_if_tb.vhd - Index: trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do (nonexistent) @@ -1,49 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider Internal -add wave -noupdate -format Logic /opb_m_if_tb/opb_clk -add wave -noupdate -format Logic /opb_m_if_tb/opb_rst -add wave -noupdate -format Logic /opb_m_if_tb/m_request -add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant -add wave -noupdate -format Logic /opb_m_if_tb/m_buslock -add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr -add wave -noupdate -format Logic /opb_m_if_tb/m_select -add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack -add wave -noupdate -format Literal /opb_m_if_tb/m_be -add wave -noupdate -format Logic /opb_m_if_tb/m_rnw -add wave -noupdate -format Literal /opb_m_if_tb/m_abus -add wave -noupdate -format Literal /opb_m_if_tb/m_dbus -add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus -add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry -add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout -add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack -add wave -noupdate -divider T-FIFIO -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data -add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl -add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr -add wave -noupdate -divider R-FIFO -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req -add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en -add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr -add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data -add wave -noupdate -divider Internal -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1710000 ps} 0} -configure wave -namecolwidth 276 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {3370500 ps} Index: trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do (nonexistent) @@ -1,12 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../bench/vhdl/images-body.vhd -vcom -93 ../../../../../bench/vhdl/txt_util.vhd -# DUT -vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd -vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd -vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd -vcom -93 ../../../../../rtl/vhdl/crc_core.vhd - -# Testbench -vcom -93 ../../../../../bench/vhdl/crc_core_tb.vhd \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps crc_core_tb -view wave -do crc_core_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do (nonexistent) @@ -1,35 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /crc_core_tb/rst -add wave -noupdate -format Logic /crc_core_tb/opb_clk -add wave -noupdate -format Logic /crc_core_tb/crc_clr -add wave -noupdate -format Logic /crc_core_tb/opb_m_last_block -add wave -noupdate -divider RX -add wave -noupdate -format Logic /crc_core_tb/fifo_rx_en -add wave -noupdate -format Literal /crc_core_tb/fifo_rx_data -add wave -noupdate -format Literal /crc_core_tb/opb_rx_crc_value -add wave -noupdate -divider TX -add wave -noupdate -format Logic /crc_core_tb/fifo_tx_en -add wave -noupdate -format Literal /crc_core_tb/fifo_tx_data -add wave -noupdate -format Logic /crc_core_tb/tx_crc_insert -add wave -noupdate -format Literal /crc_core_tb/opb_tx_crc_value -add wave -noupdate -divider Internal -add wave -noupdate -format Literal /crc_core_tb/dut/state -add wave -noupdate -format Logic /crc_core_tb/dut/rx_crc_en -add wave -noupdate -format Logic /crc_core_tb/dut/tx_crc_en -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {493567 ps} 0} -configure wave -namecolwidth 211 -configure wave -valuecolwidth 169 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {582750 ps} Index: trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do (nonexistent) @@ -1,4 +0,0 @@ -vsim -t ps shift_register_tb -view wave -do shift_register_tb_w.do -run -all \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do (nonexistent) @@ -1,9 +0,0 @@ -vlib work -# packages -vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd -# DUT -vcom -93 ../../../../../rtl/vhdl/shift_register.vhd -# Testbench -vcom -93 ../../../../../bench/vhdl/tx_fifo_emu.vhd -vcom -93 ../../../../../bench/vhdl/rx_fifo_emu.vhd -vcom -93 ../../../../../bench/vhdl/shift_register_tb.vhd \ No newline at end of file Index: trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do =================================================================== --- trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do (revision 34) +++ trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do (nonexistent) @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal /shift_register_tb/test_num -add wave -noupdate -format Logic /shift_register_tb/s_rst -add wave -noupdate -divider External -add wave -noupdate -format Logic /shift_register_tb/s_sclk -add wave -noupdate -format Logic /shift_register_tb/s_cs_n -add wave -noupdate -format Logic /shift_register_tb/s_mosi -add wave -noupdate -format Logic /shift_register_tb/s_miso_o -add wave -noupdate -format Logic /shift_register_tb/s_miso_i -add wave -noupdate -format Logic /shift_register_tb/s_miso_t -add wave -noupdate -divider TX-FIFO -add wave -noupdate -format Logic /shift_register_tb/s_tx_clk -add wave -noupdate -format Logic /shift_register_tb/s_tx_en -add wave -noupdate -format Literal -radix unsigned /shift_register_tb/s_tx_data -add wave -noupdate -divider RX-FIFO -add wave -noupdate -format Logic /shift_register_tb/s_rx_clk -add wave -noupdate -format Logic /shift_register_tb/s_rx_en -add wave -noupdate -format Literal /shift_register_tb/s_rx_data -add wave -noupdate -divider Internal -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {62874 ps} 0} -configure wave -namecolwidth 281 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {3570 ns} Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (nonexistent) @@ -1,45 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short convert gray input vector to binary ---* ---* @generic width with of input vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity gray2bin is - generic ( - width : integer := 4); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); -end gray2bin; - -architecture behavior of gray2bin is - - signal out_bin_int : std_logic_vector(width-1 downto 0); -begin -- behavior - - out_bin <= out_bin_int; - - -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 - --* convert gray input vector to binary - gray2bin_proc: process(in_gray, out_bin_int) - begin - out_bin_int(width-1) <= in_gray(width-1); - -- out_gray(3) <= in_gray(3); - for i in 1 to width-1 loop - out_bin_int(width-1-i) <= out_bin_int(width-i) xor in_gray(width-1-i); - end loop ; -- i - end process gray2bin_proc; - -- i=1 out_bin(2) <= out_bin_int(3) xor out_bin(2); - -- i=2 out_bin(1) <= out_bin_int(2) xor out_bin(1); - -- i=3 out_bin(0) <= out_bin_int(1) xor out_bin(0); -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (nonexistent) @@ -1,45 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short convert binary input vector to gray ---* ---* @generic width with of input vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity bin2gray is - generic ( - width : integer := 4); - port ( - in_bin : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); -end bin2gray; - -architecture behavior of bin2gray is - -begin -- behavior - - -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 - --* convert binary input vector to gray - bin2gray_proc : process(in_bin) - begin - out_gray(width-1) <= in_bin(width-1); - -- out_gray(3) <= in_bin(3); - - for i in 1 to width-1 loop - out_gray(width-1-i) <= in_bin(width-i) xor in_bin(width-1-i); - end loop; -- i - end process bin2gray_proc; - - -- i=1 out_gray(2) <= in_bin(3) xor in_bin(2); - -- i=2 out_gray(1) <= in_bin(2) xor in_bin(1); - -- i=3 out_gray(0) <= in_bin(1) xor in_bin(0); - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd (nonexistent) @@ -1,127 +0,0 @@ - -library ieee; -use ieee.std_logic_1164.all; - -entity crc_core is - - generic ( - C_SR_WIDTH : integer := 32); - port ( - rst : in std_logic; - opb_clk : in std_logic; - crc_en : in std_logic; - crc_clr : in std_logic; - opb_m_last_block : in std_logic; - -- RX - fifo_rx_en : in std_logic; - fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); - -- TX - fifo_tx_en : in std_logic; - fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - tx_crc_insert : out std_logic; - opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); -end crc_core; - - -architecture behavior of crc_core is - component crc_gen - generic ( - C_SR_WIDTH : integer; - crc_start_value : std_logic_vector(31 downto 0)); - port ( - clk : in std_logic; - crc_clear : in std_logic; - crc_en : in std_logic; - crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0); - crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - signal rx_crc_en : std_logic; - signal tx_crc_en : std_logic; - - - type state_define is (idle, - tx_insert_crc, - wait_done); - signal state : state_define; - -begin -- behavior - - --* RX CRC_GEN - crc_gen_rx : crc_gen - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - crc_start_value => (others => '1')) - port map ( - clk => OPB_Clk, - crc_clear => crc_clr, - crc_en => rx_crc_en, - crc_data_in => fifo_rx_data, - crc_data_out => opb_rx_crc_value); - - -- disable crc_generation for last data block - rx_crc_en <= '1' when (crc_en = '1' and fifo_rx_en = '1' and opb_m_last_block = '0') else - '0'; - - ----------------------------------------------------------------------------- - --* TX CRC_GEN - crc_gen_tx : crc_gen - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - crc_start_value => (others => '1')) - port map ( - clk => OPB_Clk, - crc_clear => crc_clr, - crc_en => tx_crc_en, - crc_data_in => fifo_tx_data, - crc_data_out => opb_tx_crc_value); - - -- disable crc_generation for last data block - tx_crc_en <= '1' when (crc_en = '1' and fifo_tx_en = '1' and opb_m_last_block = '0') else - '0'; - - process(rst, OPB_Clk) - begin - if (rst = '1') then - tx_crc_insert <= '0'; - state <= idle; - elsif rising_edge(OPB_Clk) then - case state is - when idle => - if (opb_m_last_block = '1') then - tx_crc_insert <= '1'; - state <= tx_insert_crc; - else - tx_crc_insert <= '0'; - state <= idle; - end if; - - when tx_insert_crc => - if (opb_m_last_block = '0') then - -- abort - tx_crc_insert <= '0'; - state <= idle; - elsif (fifo_tx_en = '1') then - tx_crc_insert <= '0'; - state <= wait_done; - else - state <= tx_insert_crc; - end if; - - when wait_done => - if (opb_m_last_block = '0') then - tx_crc_insert <= '0'; - state <= idle; - - else - state <= wait_done; - end if; - - when others => - state <= idle; - end case; - - end if; - end process; -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (nonexistent) @@ -1,46 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short RAM Sync-Write, Async Read ---* ---* @generic C_FIFO_WIDTH RAM-With (1..xx) ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity ram is - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4); - - port (clk : in std_logic; - we : in std_logic; - a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); -end ram; - -architecture behavior of ram is - type ram_type is array (2**C_FIFO_SIZE_WIDTH-1 downto 0) of std_logic_vector (C_FIFO_WIDTH-1 downto 0); - signal RAM : ram_type; -begin - - process (clk) - begin - if (clk'event and clk = '1') then - if (we = '1') then - RAM(conv_integer(a)) <= di; - end if; - end if; - end process; - - dpo <= RAM(conv_integer(dpra)); - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd (nonexistent) @@ -1,229 +0,0 @@ ------------------------------------------------------------------------ --- File: PCK_CRC32_D32.vhd --- Date: Tue Mar 4 19:11:40 2008 --- --- Copyright (C) 1999-2003 Easics NV. --- This source file may be used and distributed without restriction --- provided that this copyright statement is not removed from the file --- and that any derivative work contains the original copyright notice --- and the associated disclaimer. --- --- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS --- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED --- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. --- --- Purpose: VHDL package containing a synthesizable CRC function --- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) --- * data width: 32 --- --- Info: tools@easics.be --- http://www.easics.com ------------------------------------------------------------------------ - - -library IEEE; -use IEEE.std_logic_1164.all; - -package PCK_CRC32_D32 is - - -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) - -- data width: 32 - -- convention: the first serial data bit is D(31) - function nextCRC32_D32 - ( Data: std_logic_vector(31 downto 0); - CRC: std_logic_vector(31 downto 0) ) - return std_logic_vector; - -end PCK_CRC32_D32; - -library IEEE; -use IEEE.std_logic_1164.all; - -package body PCK_CRC32_D32 is - - -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) - -- data width: 32 - -- convention: the first serial data bit is D(31) - function nextCRC32_D32 - ( Data: std_logic_vector(31 downto 0); - CRC: std_logic_vector(31 downto 0) ) - return std_logic_vector is - - variable D: std_logic_vector(31 downto 0); - variable C: std_logic_vector(31 downto 0); - variable NewCRC: std_logic_vector(31 downto 0); - - begin - - D := Data; - C := CRC; - - NewCRC(0) := D(31) xor D(30) xor D(29) xor D(28) xor D(26) xor D(25) xor - D(24) xor D(16) xor D(12) xor D(10) xor D(9) xor D(6) xor - D(0) xor C(0) xor C(6) xor C(9) xor C(10) xor C(12) xor - C(16) xor C(24) xor C(25) xor C(26) xor C(28) xor C(29) xor - C(30) xor C(31); - NewCRC(1) := D(28) xor D(27) xor D(24) xor D(17) xor D(16) xor D(13) xor - D(12) xor D(11) xor D(9) xor D(7) xor D(6) xor D(1) xor - D(0) xor C(0) xor C(1) xor C(6) xor C(7) xor C(9) xor - C(11) xor C(12) xor C(13) xor C(16) xor C(17) xor C(24) xor - C(27) xor C(28); - NewCRC(2) := D(31) xor D(30) xor D(26) xor D(24) xor D(18) xor D(17) xor - D(16) xor D(14) xor D(13) xor D(9) xor D(8) xor D(7) xor - D(6) xor D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor - C(2) xor C(6) xor C(7) xor C(8) xor C(9) xor C(13) xor - C(14) xor C(16) xor C(17) xor C(18) xor C(24) xor C(26) xor - C(30) xor C(31); - NewCRC(3) := D(31) xor D(27) xor D(25) xor D(19) xor D(18) xor D(17) xor - D(15) xor D(14) xor D(10) xor D(9) xor D(8) xor D(7) xor - D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor - C(7) xor C(8) xor C(9) xor C(10) xor C(14) xor C(15) xor - C(17) xor C(18) xor C(19) xor C(25) xor C(27) xor C(31); - NewCRC(4) := D(31) xor D(30) xor D(29) xor D(25) xor D(24) xor D(20) xor - D(19) xor D(18) xor D(15) xor D(12) xor D(11) xor D(8) xor - D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(0) xor - C(2) xor C(3) xor C(4) xor C(6) xor C(8) xor C(11) xor - C(12) xor C(15) xor C(18) xor C(19) xor C(20) xor C(24) xor - C(25) xor C(29) xor C(30) xor C(31); - NewCRC(5) := D(29) xor D(28) xor D(24) xor D(21) xor D(20) xor D(19) xor - D(13) xor D(10) xor D(7) xor D(6) xor D(5) xor D(4) xor - D(3) xor D(1) xor D(0) xor C(0) xor C(1) xor C(3) xor - C(4) xor C(5) xor C(6) xor C(7) xor C(10) xor C(13) xor - C(19) xor C(20) xor C(21) xor C(24) xor C(28) xor C(29); - NewCRC(6) := D(30) xor D(29) xor D(25) xor D(22) xor D(21) xor D(20) xor - D(14) xor D(11) xor D(8) xor D(7) xor D(6) xor D(5) xor - D(4) xor D(2) xor D(1) xor C(1) xor C(2) xor C(4) xor - C(5) xor C(6) xor C(7) xor C(8) xor C(11) xor C(14) xor - C(20) xor C(21) xor C(22) xor C(25) xor C(29) xor C(30); - NewCRC(7) := D(29) xor D(28) xor D(25) xor D(24) xor D(23) xor D(22) xor - D(21) xor D(16) xor D(15) xor D(10) xor D(8) xor D(7) xor - D(5) xor D(3) xor D(2) xor D(0) xor C(0) xor C(2) xor - C(3) xor C(5) xor C(7) xor C(8) xor C(10) xor C(15) xor - C(16) xor C(21) xor C(22) xor C(23) xor C(24) xor C(25) xor - C(28) xor C(29); - NewCRC(8) := D(31) xor D(28) xor D(23) xor D(22) xor D(17) xor D(12) xor - D(11) xor D(10) xor D(8) xor D(4) xor D(3) xor D(1) xor - D(0) xor C(0) xor C(1) xor C(3) xor C(4) xor C(8) xor - C(10) xor C(11) xor C(12) xor C(17) xor C(22) xor C(23) xor - C(28) xor C(31); - NewCRC(9) := D(29) xor D(24) xor D(23) xor D(18) xor D(13) xor D(12) xor - D(11) xor D(9) xor D(5) xor D(4) xor D(2) xor D(1) xor - C(1) xor C(2) xor C(4) xor C(5) xor C(9) xor C(11) xor - C(12) xor C(13) xor C(18) xor C(23) xor C(24) xor C(29); - NewCRC(10) := D(31) xor D(29) xor D(28) xor D(26) xor D(19) xor D(16) xor - D(14) xor D(13) xor D(9) xor D(5) xor D(3) xor D(2) xor - D(0) xor C(0) xor C(2) xor C(3) xor C(5) xor C(9) xor - C(13) xor C(14) xor C(16) xor C(19) xor C(26) xor C(28) xor - C(29) xor C(31); - NewCRC(11) := D(31) xor D(28) xor D(27) xor D(26) xor D(25) xor D(24) xor - D(20) xor D(17) xor D(16) xor D(15) xor D(14) xor D(12) xor - D(9) xor D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor - C(1) xor C(3) xor C(4) xor C(9) xor C(12) xor C(14) xor - C(15) xor C(16) xor C(17) xor C(20) xor C(24) xor C(25) xor - C(26) xor C(27) xor C(28) xor C(31); - NewCRC(12) := D(31) xor D(30) xor D(27) xor D(24) xor D(21) xor D(18) xor - D(17) xor D(15) xor D(13) xor D(12) xor D(9) xor D(6) xor - D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor C(0) xor - C(1) xor C(2) xor C(4) xor C(5) xor C(6) xor C(9) xor - C(12) xor C(13) xor C(15) xor C(17) xor C(18) xor C(21) xor - C(24) xor C(27) xor C(30) xor C(31); - NewCRC(13) := D(31) xor D(28) xor D(25) xor D(22) xor D(19) xor D(18) xor - D(16) xor D(14) xor D(13) xor D(10) xor D(7) xor D(6) xor - D(5) xor D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor - C(3) xor C(5) xor C(6) xor C(7) xor C(10) xor C(13) xor - C(14) xor C(16) xor C(18) xor C(19) xor C(22) xor C(25) xor - C(28) xor C(31); - NewCRC(14) := D(29) xor D(26) xor D(23) xor D(20) xor D(19) xor D(17) xor - D(15) xor D(14) xor D(11) xor D(8) xor D(7) xor D(6) xor - D(4) xor D(3) xor D(2) xor C(2) xor C(3) xor C(4) xor - C(6) xor C(7) xor C(8) xor C(11) xor C(14) xor C(15) xor - C(17) xor C(19) xor C(20) xor C(23) xor C(26) xor C(29); - NewCRC(15) := D(30) xor D(27) xor D(24) xor D(21) xor D(20) xor D(18) xor - D(16) xor D(15) xor D(12) xor D(9) xor D(8) xor D(7) xor - D(5) xor D(4) xor D(3) xor C(3) xor C(4) xor C(5) xor - C(7) xor C(8) xor C(9) xor C(12) xor C(15) xor C(16) xor - C(18) xor C(20) xor C(21) xor C(24) xor C(27) xor C(30); - NewCRC(16) := D(30) xor D(29) xor D(26) xor D(24) xor D(22) xor D(21) xor - D(19) xor D(17) xor D(13) xor D(12) xor D(8) xor D(5) xor - D(4) xor D(0) xor C(0) xor C(4) xor C(5) xor C(8) xor - C(12) xor C(13) xor C(17) xor C(19) xor C(21) xor C(22) xor - C(24) xor C(26) xor C(29) xor C(30); - NewCRC(17) := D(31) xor D(30) xor D(27) xor D(25) xor D(23) xor D(22) xor - D(20) xor D(18) xor D(14) xor D(13) xor D(9) xor D(6) xor - D(5) xor D(1) xor C(1) xor C(5) xor C(6) xor C(9) xor - C(13) xor C(14) xor C(18) xor C(20) xor C(22) xor C(23) xor - C(25) xor C(27) xor C(30) xor C(31); - NewCRC(18) := D(31) xor D(28) xor D(26) xor D(24) xor D(23) xor D(21) xor - D(19) xor D(15) xor D(14) xor D(10) xor D(7) xor D(6) xor - D(2) xor C(2) xor C(6) xor C(7) xor C(10) xor C(14) xor - C(15) xor C(19) xor C(21) xor C(23) xor C(24) xor C(26) xor - C(28) xor C(31); - NewCRC(19) := D(29) xor D(27) xor D(25) xor D(24) xor D(22) xor D(20) xor - D(16) xor D(15) xor D(11) xor D(8) xor D(7) xor D(3) xor - C(3) xor C(7) xor C(8) xor C(11) xor C(15) xor C(16) xor - C(20) xor C(22) xor C(24) xor C(25) xor C(27) xor C(29); - NewCRC(20) := D(30) xor D(28) xor D(26) xor D(25) xor D(23) xor D(21) xor - D(17) xor D(16) xor D(12) xor D(9) xor D(8) xor D(4) xor - C(4) xor C(8) xor C(9) xor C(12) xor C(16) xor C(17) xor - C(21) xor C(23) xor C(25) xor C(26) xor C(28) xor C(30); - NewCRC(21) := D(31) xor D(29) xor D(27) xor D(26) xor D(24) xor D(22) xor - D(18) xor D(17) xor D(13) xor D(10) xor D(9) xor D(5) xor - C(5) xor C(9) xor C(10) xor C(13) xor C(17) xor C(18) xor - C(22) xor C(24) xor C(26) xor C(27) xor C(29) xor C(31); - NewCRC(22) := D(31) xor D(29) xor D(27) xor D(26) xor D(24) xor D(23) xor - D(19) xor D(18) xor D(16) xor D(14) xor D(12) xor D(11) xor - D(9) xor D(0) xor C(0) xor C(9) xor C(11) xor C(12) xor - C(14) xor C(16) xor C(18) xor C(19) xor C(23) xor C(24) xor - C(26) xor C(27) xor C(29) xor C(31); - NewCRC(23) := D(31) xor D(29) xor D(27) xor D(26) xor D(20) xor D(19) xor - D(17) xor D(16) xor D(15) xor D(13) xor D(9) xor D(6) xor - D(1) xor D(0) xor C(0) xor C(1) xor C(6) xor C(9) xor - C(13) xor C(15) xor C(16) xor C(17) xor C(19) xor C(20) xor - C(26) xor C(27) xor C(29) xor C(31); - NewCRC(24) := D(30) xor D(28) xor D(27) xor D(21) xor D(20) xor D(18) xor - D(17) xor D(16) xor D(14) xor D(10) xor D(7) xor D(2) xor - D(1) xor C(1) xor C(2) xor C(7) xor C(10) xor C(14) xor - C(16) xor C(17) xor C(18) xor C(20) xor C(21) xor C(27) xor - C(28) xor C(30); - NewCRC(25) := D(31) xor D(29) xor D(28) xor D(22) xor D(21) xor D(19) xor - D(18) xor D(17) xor D(15) xor D(11) xor D(8) xor D(3) xor - D(2) xor C(2) xor C(3) xor C(8) xor C(11) xor C(15) xor - C(17) xor C(18) xor C(19) xor C(21) xor C(22) xor C(28) xor - C(29) xor C(31); - NewCRC(26) := D(31) xor D(28) xor D(26) xor D(25) xor D(24) xor D(23) xor - D(22) xor D(20) xor D(19) xor D(18) xor D(10) xor D(6) xor - D(4) xor D(3) xor D(0) xor C(0) xor C(3) xor C(4) xor - C(6) xor C(10) xor C(18) xor C(19) xor C(20) xor C(22) xor - C(23) xor C(24) xor C(25) xor C(26) xor C(28) xor C(31); - NewCRC(27) := D(29) xor D(27) xor D(26) xor D(25) xor D(24) xor D(23) xor - D(21) xor D(20) xor D(19) xor D(11) xor D(7) xor D(5) xor - D(4) xor D(1) xor C(1) xor C(4) xor C(5) xor C(7) xor - C(11) xor C(19) xor C(20) xor C(21) xor C(23) xor C(24) xor - C(25) xor C(26) xor C(27) xor C(29); - NewCRC(28) := D(30) xor D(28) xor D(27) xor D(26) xor D(25) xor D(24) xor - D(22) xor D(21) xor D(20) xor D(12) xor D(8) xor D(6) xor - D(5) xor D(2) xor C(2) xor C(5) xor C(6) xor C(8) xor - C(12) xor C(20) xor C(21) xor C(22) xor C(24) xor C(25) xor - C(26) xor C(27) xor C(28) xor C(30); - NewCRC(29) := D(31) xor D(29) xor D(28) xor D(27) xor D(26) xor D(25) xor - D(23) xor D(22) xor D(21) xor D(13) xor D(9) xor D(7) xor - D(6) xor D(3) xor C(3) xor C(6) xor C(7) xor C(9) xor - C(13) xor C(21) xor C(22) xor C(23) xor C(25) xor C(26) xor - C(27) xor C(28) xor C(29) xor C(31); - NewCRC(30) := D(30) xor D(29) xor D(28) xor D(27) xor D(26) xor D(24) xor - D(23) xor D(22) xor D(14) xor D(10) xor D(8) xor D(7) xor - D(4) xor C(4) xor C(7) xor C(8) xor C(10) xor C(14) xor - C(22) xor C(23) xor C(24) xor C(26) xor C(27) xor C(28) xor - C(29) xor C(30); - NewCRC(31) := D(31) xor D(30) xor D(29) xor D(28) xor D(27) xor D(25) xor - D(24) xor D(23) xor D(15) xor D(11) xor D(9) xor D(8) xor - D(5) xor C(5) xor C(8) xor C(9) xor C(11) xor C(15) xor - C(23) xor C(24) xor C(25) xor C(27) xor C(28) xor C(29) xor - C(30) xor C(31); - - return NewCRC; - - end nextCRC32_D32; - -end PCK_CRC32_D32; - Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (nonexistent) @@ -1,191 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Shift-Register ---* ---* Control Register Description: ---* @li Bit0: DGE : Global Device Enable ---* @li Bit1: TX_EN: Transmit enable ---* @li Bit2: RX_EN: Receive enable ---* ---* Generics described in top entity. ---* @port opb_ctl_reg Control Register ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.1 ---* @date: 2007-11-11 ---/ --- Version 1.0 Initial Release --- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH --- Version 1.2 removed delays for simulation -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; - -library work; -use work.opb_spi_slave_pack.all; - -entity shift_register is - - generic ( - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0); - - port ( - rst : in std_logic; - -- control register - opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - -- external - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - -- transmit fifo - sr_tx_clk : out std_logic; - sr_tx_en : out std_logic; - sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- receive fifo - sr_rx_clk : out std_logic; - sr_rx_en : out std_logic; - sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); -end shift_register; - - -architecture behavior of shift_register is - --* Global - signal sclk_int : std_logic; - signal sclk_int_inv : std_logic; - signal rx_cnt : integer range 0 to 31 := 0; - - -- RX - signal rx_sr_reg : std_logic_vector(C_SR_WIDTH-2 downto 0); - signal sr_rx_en_int : std_logic; - signal sr_rx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -- tx - signal miso_int : std_logic; - signal tx_cnt : integer range 0 to 31 := 0; - signal sr_tx_en_int : std_logic; - signal sr_tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -begin -- behavior - - miso_t <= ss_n; -- tristate - - - sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else - sclk when (C_PHA = 1 and C_CPOL = 1) else - not sclk; - - - sr_rx_en <= sr_rx_en_int; - sr_tx_en <= sr_tx_en_int; - - --* reorder received bits if not "MSB_First" - reorder_rx_bits : process(sr_rx_data_int) - begin - for i in 0 to C_SR_WIDTH-1 loop - if C_MSB_FIRST then - sr_rx_data(i) <= sr_rx_data_int(i); - else - sr_rx_data(C_SR_WIDTH-1-i) <= sr_rx_data_int(i); - end if; - end loop; -- i - end process reorder_rx_bits; - - --* reorder transmit bits if not "MSB_First" - reorder_tx_bits : process(sr_tx_data) - begin - for i in 0 to C_SR_WIDTH-1 loop - if C_MSB_FIRST then - sr_tx_data_int(i) <= sr_tx_data(i); - else - sr_tx_data_int(C_SR_WIDTH-1-i) <= sr_tx_data(i); - end if; - end loop; -- i - end process reorder_tx_bits; - - - ----------------------------------------------------------------------------- - - sr_rx_clk <= sclk_int; - - sr_rx_data_int <= rx_sr_reg & mosi; - - --* RX-Shift-Register - rx_shift_proc : process(rst, opb_ctl_reg, sclk_int) - begin - if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_RX_EN) = '0') then - rx_cnt <= 0; - sr_rx_en_int <= '0'; - rx_sr_reg <= (others => '0'); - - elsif rising_edge(sclk_int) then - if (ss_n = '0') then - rx_sr_reg <= rx_sr_reg(C_SR_WIDTH-3 downto 0) & mosi; - if (rx_cnt = C_SR_WIDTH-2) then - rx_cnt <= rx_cnt +1; - sr_rx_en_int <= '1'; - elsif (rx_cnt = C_SR_WIDTH-1) then - rx_cnt <= 0; - sr_rx_en_int <= '0'; - else - rx_cnt <= rx_cnt +1; - end if; - else - -- ss_n high - -- assert framing error if cnt != 0? - sr_rx_en_int <= '0'; - rx_cnt <= 0; - end if; - end if; - end process rx_shift_proc; - -------------------------------------------------------------------------------- - -- TX Shift Register - sr_tx_clk <= sclk_int_inv; - sclk_int_inv <= not sclk_int; - - miso_o <= sr_tx_data_int(C_SR_WIDTH-1) when (tx_cnt = 0) else - miso_int; - - - --* TX Shift-Register - tx_shift_proc : process(rst, opb_ctl_reg, sclk_int_inv) - begin - if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_TX_EN) = '0') then - tx_cnt <= 0; - sr_tx_en_int <= '0'; - miso_int <= '0'; - elsif rising_edge(sclk_int_inv) then - if (ss_n = '0') then - if (tx_cnt /= C_SR_WIDTH-1) then - miso_int <= sr_tx_data_int(C_SR_WIDTH-1-(tx_cnt+1)); - end if; - if (tx_cnt = C_SR_WIDTH-2) then - sr_tx_en_int <= '1'; - tx_cnt <= tx_cnt +1; - elsif (tx_cnt = C_SR_WIDTH-1) then - tx_cnt <= 0; - sr_tx_en_int <= '0'; - else - tx_cnt <= tx_cnt +1; - end if; - else - -- ss_n high - -- assert framing error if cnt != 0? - sr_tx_en_int <= '0'; - tx_cnt <= 0; - end if; - end if; - end process tx_shift_proc; -------------------------------------------------------------------------------- - - end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (nonexistent) @@ -1,262 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Configurable FIFO ---* ---* @generic C_FIFO_WIDTH RAM-With (1..xx) ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* @generic C_SYNC_TO Sync FIFO Flags to read or write clock ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - -entity fifo is - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4; - C_SYNC_TO : string := "RD"); - port ( - rst : in std_logic; - -- write port - wr_clk : in std_logic; - wr_en : in std_logic; - din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - -- read port - rd_clk : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); - -- flags - empty : out std_logic; - full : out std_logic; - overflow : out std_logic; - underflow : out std_logic; - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - -end fifo; - -architecture behavior of fifo is - --* ram with sync write and async read - component ram - generic ( - C_FIFO_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4); - port ( - clk : in std_logic; - we : in std_logic; - a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); - end component; - - --* component generates fifo flag - component fifo_prog_flags - generic ( - C_FIFO_SIZE_WIDTH : integer; - C_SYNC_TO : string); - port ( - rst : in std_logic; - clk : in std_logic; - cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - end component; - - --* logic coded gray counter - component gray_adder - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - signal wr_cnt_gray_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal wr_cnt_next_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal rd_cnt_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - attribute fsm_extract : string; - -- wr_clock domain - -- main wr grey code counter - signal wr_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of wr_cnt_grey : signal is "no"; - - -- main grey code counter for full - signal wr_cnt_next_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of wr_cnt_next_grey : signal is "no"; - - -- rd_clk domain - -- main rd grey code counter - signal rd_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - attribute fsm_extract of rd_cnt_grey : signal is "no"; - - -- binary counter for prog full/empty - signal rd_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal wr_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - signal empty_int : std_logic; - signal full_int : std_logic; - -begin -- behavior - - empty <= empty_int; - full <= full_int; - ---* write counter generation - fifo_write_proc: process(rst, wr_clk) - begin - if (rst = '1') then - wr_cnt_grey <= (others => '0'); - wr_cnt <= (others => '0'); - wr_cnt_next_grey(C_FIFO_SIZE_WIDTH-1 downto 1) <= (others => '0'); - wr_cnt_next_grey(0) <= '1'; - elsif rising_edge(wr_clk) then - if (wr_en = '1') then - wr_cnt <= wr_cnt+1; - - -- wr_cnt_grey <= add_grey_rom(conv_integer(wr_cnt_grey)); - wr_cnt_grey <= wr_cnt_gray_add_one; - - -- wr_cnt_next_grey <= add_grey_rom(conv_integer(wr_cnt_next_grey)); - wr_cnt_next_grey <= wr_cnt_next_grey_add_one; - - end if; - end if; - end process fifo_write_proc; - - --* add one to wr_cnt_gray - gray_adder_1 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => wr_cnt_grey, - out_gray => wr_cnt_gray_add_one); - - --* add one to wr_cnt_next_grey - gray_adder_2 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => wr_cnt_next_grey, - out_gray => wr_cnt_next_grey_add_one); - - ---* read counter generation - fifo_read_proc: process(rst, rd_clk) - begin - if (rst = '1') then - rd_cnt_grey <= (others => '0'); - rd_cnt <= (others => '0'); - elsif rising_edge(rd_clk) then - -- rd grey code counter - if (rd_en = '1') then - -- rd_cnt_grey <= add_grey_rom(conv_integer(rd_cnt_grey)); - rd_cnt_grey <= rd_cnt_grey_add_one; - rd_cnt <= rd_cnt+1; - end if; - end if; - end process fifo_read_proc; - - --* add one to rd_cnt_grey - gray_adder_3 : gray_adder - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => rd_cnt_grey, - out_gray => rd_cnt_grey_add_one); - - - --* FIFO Memory - ram_1 : ram - generic map ( - C_FIFO_WIDTH => C_FIFO_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) - port map ( - clk => wr_clk, - we => wr_en, - a => wr_cnt_grey, - di => din, - dpra => rd_cnt_grey, - dpo => dout); - - - --* generate overflow - gen_of_proc: process(rst, wr_clk) - begin - if (rst = '1') then - overflow <= '0'; - elsif rising_edge(wr_clk) then - if (full_int = '1' and wr_en = '1') then - overflow <= '1'; - end if; - end if; - end process gen_of_proc; - - --* generate underflow - gen_uf_proc: process(rst, rd_clk) - begin - if (rst = '1') then - underflow <= '0'; - elsif rising_edge(rd_clk) then - if (empty_int = '1' and rd_en = '1') then - underflow <= '1'; - end if; - end if; - end process gen_uf_proc; - - -- generate empty - empty_int <= '1' when (wr_cnt_grey = rd_cnt_grey) else - '0'; - - -- generate full - full_int <= '1' when (wr_cnt_next_grey = rd_cnt_grey) else - '0'; - - --* select clock side for flags - u1 : if (C_SYNC_TO = "WR") generate - --* sync flags to write clock - fifo_prog_flags_1 : fifo_prog_flags - generic map ( - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => C_SYNC_TO) - port map ( - rst => rst, - clk => wr_clk, - cnt_grey => rd_cnt_grey, - cnt => wr_cnt, - prog_full_thresh => prog_full_thresh, - prog_empty_thresh => prog_empty_thresh, - prog_empty => prog_empty, - prog_full => prog_full); - end generate u1; - - u2 : if (C_SYNC_TO = "RD") generate - --* sync flags to read clock - fifo_prog_flags_1 : fifo_prog_flags - generic map ( - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => C_SYNC_TO) - port map ( - rst => rst, - clk => rd_clk, - cnt_grey => wr_cnt_grey, - cnt => rd_cnt, - prog_full_thresh => prog_full_thresh, - prog_empty_thresh => prog_empty_thresh, - prog_empty => prog_empty, - prog_full => prog_full); - end generate u2; -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (nonexistent) @@ -1,73 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -package opb_spi_slave_pack is - - constant C_ADR_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#0#, 6); - constant C_ADR_STATUS : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#1#, 6); - constant C_ADR_TX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#2#, 6); - constant C_ADR_RX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#3#, 6); - constant C_ADR_TX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#4#, 6); - constant C_ADR_RX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#5#, 6); - constant C_ADR_TX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#6#, 6); - constant C_ADR_TX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#7#, 6); - constant C_ADR_TX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#8#, 6); - constant C_ADR_RX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#9#, 6); - constant C_ADR_RX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#A#, 6); - constant C_ADR_RX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#B#, 6); - constant C_ADR_RX_CRC : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#C#, 6); - constant C_ADR_TX_CRC : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#D#, 6); - --- XIIF_V123B compatible - constant C_ADR_DGIE : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#10#, 6); - constant C_ADR_ISR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#11#, 6); - constant C_ADR_IER : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#12#, 6); - - constant C_NUM_FLG : integer := 16; - constant C_NUM_INT : integer := 11; - constant C_WIDTH_DMA_NUM : integer := 24; - - --- CTL_Register - -- width - constant C_OPB_CTL_REG_WIDTH : integer := 6; - -- bits - constant C_OPB_CTL_REG_DGE : integer := 0; - constant C_OPB_CTL_REG_TX_EN : integer := 1; - constant C_OPB_CTL_REG_RX_EN : integer := 2; - constant C_OPB_CTL_REG_RST : integer := 3; - constant C_OPB_CTL_REG_CRC_EN : integer := 4; - constant C_OPB_CTL_REG_CRC_CLR : integer := 5; - - -- Status Register - constant SPI_SR_Bit_TX_Prog_Full : integer := 0; - constant SPI_SR_Bit_TX_Full : integer := 1; - constant SPI_SR_Bit_TX_Overflow : integer := 2; - constant SPI_SR_Bit_TX_Prog_empty : integer := 3; - constant SPI_SR_Bit_TX_Empty : integer := 4; - constant SPI_SR_Bit_TX_Underflow : integer := 5; - - constant SPI_SR_Bit_RX_Prog_Full : integer := 6; - constant SPI_SR_Bit_RX_Full : integer := 7; - constant SPI_SR_Bit_RX_Overflow : integer := 8; - constant SPI_SR_Bit_RX_Prog_empty : integer := 9; - constant SPI_SR_Bit_RX_Empty : integer := 10; - constant SPI_SR_Bit_RX_Underflow : integer := 11; - - constant SPI_SR_Bit_SS_n : integer := 12; - constant SPI_SR_Bit_TX_DMA_Done : integer := 13; - constant SPI_SR_Bit_RX_DMA_Done : integer := 14; - - -- Interrupt Status Register - constant SPI_ISR_Bit_TX_Prog_Empty : integer := 0; - constant SPI_ISR_Bit_TX_Empty : integer := 1; - constant SPI_ISR_Bit_TX_Underflow : integer := 2; - constant SPI_ISR_Bit_RX_Prog_Full : integer := 3; - constant SPI_ISR_Bit_RX_Full : integer := 4; - constant SPI_ISR_Bit_RX_Overflow : integer := 5; - constant SPI_ISR_Bit_SS_Fall : integer := 6; - constant SPI_ISR_Bit_SS_Rise : integer := 7; -end opb_spi_slave_pack; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (nonexistent) @@ -1,640 +0,0 @@ -------------------------------------------------------------------------------- -------------------------------------------------------- ---! @file ---! @brief 2:1 Mux using with-select -------------------------------------------------------- - ---* ---* @short Top entity of the project opi_spi_slave ---* ---* @generic C_FAMILY virtex-4 and generic supported ---* @author: Daniel Köthe ---* @version: 1.1 ---* @date: 2007-11-19 ---/ --- Version 1.1 --- Bugfix --- IRQ-Flag RX_Overflow shows prog_empty insteed rx_overflow --- opb_irq_flg(5) <= opb_fifo_flg(9); to opb_irq_flg(5) <= opb_fifo_flg(8); - -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - -library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.opb_spi_slave_pack.all; - - -entity opb_spi_slave is - - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 0; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - - C_FAMILY : string := "virtex4"; - -- user ports - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0; - C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32 - C_DMA_EN : boolean := false; - C_CRC_EN : boolean := false); - - port ( - -- OPB signals (Slave Side) - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - - -- OPB signals (Master Side) - -- Arbitration - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - -- - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - -- spi ports - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - -- irq output - opb_irq : out std_logic); - -end opb_spi_slave; - -architecture behavior of opb_spi_slave is - - component opb_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_DMA_EN : boolean; - C_CRC_EN : boolean); - port ( - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - opb_s_tx_en : out std_logic; - opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_s_rx_en : out std_logic; - opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); - opb_dgie : out std_logic; - opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_ctl : out std_logic_vector(0 downto 0); - opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_ctl : out std_logic_vector(0 downto 0); - opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0)); - - end component; - - - component opb_m_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1; - C_FIFO_SIZE_WIDTH : integer range 4 to 7); - port ( - OPB_Clk : in std_logic; - OPB_Rst : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - opb_m_tx_req : in std_logic; - opb_m_tx_en : out std_logic; - opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_tx_dma_ctl : in std_logic_vector(0 downto 0); - opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_tx_dma_done : out std_logic; - opb_m_rx_req : in std_logic; - opb_m_rx_en : out std_logic; - opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_dma_ctl : in std_logic_vector(0 downto 0); - opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_rx_dma_done : out std_logic; - opb_abort_flg : out std_logic; - opb_m_last_block : out std_logic); - end component; - - component shift_register - generic ( - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1); - port ( - rst : in std_logic; - opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - sr_tx_clk : out std_logic; - sr_tx_en : out std_logic; - sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - sr_rx_clk : out std_logic; - sr_rx_en : out std_logic; - sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - component fifo - generic ( - C_FIFO_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_SYNC_TO : string); - port ( - rst : in std_logic; - wr_clk : in std_logic; - wr_en : in std_logic; - din : in std_logic_vector(C_SR_WIDTH-1 downto 0); - rd_clk : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(C_SR_WIDTH-1 downto 0); - empty : out std_logic; - full : out std_logic; - overflow : out std_logic; - underflow : out std_logic; - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - end component; - - component irq_ctl - generic ( - C_ACTIVE_EDGE : std_logic); - port ( - rst : in std_logic; - clk : in std_logic; - opb_fifo_flg : in std_logic; - opb_ier : in std_logic; - opb_isr : out std_logic; - opb_isr_clr : in std_logic); - end component; - - component crc_core - generic ( - C_SR_WIDTH : integer); - port ( - rst : in std_logic; - opb_clk : in std_logic; - crc_en : in std_logic; - crc_clr : in std_logic; - opb_m_last_block : in std_logic; - fifo_rx_en : in std_logic; - fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); - fifo_tx_en : in std_logic; - fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - tx_crc_insert : out std_logic; - opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - --- opb_if - signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - - signal opb_s_tx_en : std_logic; - signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_s_rx_en : std_logic; - signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - - signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_tx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_rx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - - signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -- opb_m_if - signal opb_m_tx_en : std_logic; - signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_m_rx_en : std_logic; - signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_abort_flg : std_logic; - signal opb_m_last_block : std_logic; - --- shift_register - signal sr_tx_clk : std_logic; - signal sr_tx_en : std_logic; - signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal sr_rx_clk : std_logic; - signal sr_rx_en : std_logic; - signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - signal sclk_ibuf : std_logic; - signal sclk_bufr : std_logic; - - signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); - signal opb_irq_flg : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0'); - signal rst : std_logic; - - - signal opb_dgie : std_logic; - signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); - - -- opb_spi_slave - signal fifo_tx_en : std_logic; - signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal fifo_rx_en : std_logic; - signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -- rx crc_core - signal crc_clr : std_logic; - signal crc_en : std_logic; - signal tx_crc_insert : std_logic; - -begin -- behavior - - --* - virtex4_slk_buf : if C_FAMILY = "virtex4" generate - --* If C_FAMILY=Virtex-4 use "IBUF" - IBUF_1 : IBUF - port map ( - I => sclk, - O => sclk_ibuf); - ---* If C_FAMILY=Virtex-4 use "BUFR" - BUFR_1 : BUFR - generic map ( - BUFR_DIVIDE => "BYPASS", - SIM_DEVICE => "VIRTEX4") - port map ( - O => sclk_bufr, - CE => '0', - CLR => '0', - I => sclk_ibuf); - end generate virtex4_slk_buf; - - generic_sclk_buf : if C_FAMILY /= "virtex4" generate - sclk_bufr <= sclk; - end generate generic_sclk_buf; - - --* OPB-Slave Interface(Register-Interface) - opb_if_2 : opb_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_DMA_EN => C_DMA_EN, - C_CRC_EN => C_CRC_EN) - port map ( - OPB_ABus => OPB_ABus, - OPB_BE => OPB_BE, - OPB_Clk => OPB_Clk, - OPB_DBus => OPB_DBus, - OPB_RNW => OPB_RNW, - OPB_Rst => OPB_Rst, - OPB_select => OPB_select, - OPB_seqAddr => OPB_seqAddr, - Sln_DBus => Sln_DBus, - Sln_errAck => Sln_errAck, - Sln_retry => Sln_retry, - Sln_toutSup => Sln_toutSup, - Sln_xferAck => Sln_xferAck, - opb_s_tx_en => opb_s_tx_en, - opb_s_tx_data => opb_s_tx_data, - opb_s_rx_en => opb_s_rx_en, - opb_s_rx_data => opb_s_rx_data, - opb_ctl_reg => opb_ctl_reg, - tx_thresh => tx_thresh, - rx_thresh => rx_thresh, - opb_fifo_flg => opb_fifo_flg, - opb_dgie => opb_dgie, - opb_ier => opb_ier, - opb_isr => opb_isr, - opb_isr_clr => opb_isr_clr, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_num => opb_tx_dma_num, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_num => opb_rx_dma_num, - opb_rx_crc_value => opb_rx_crc_value, - opb_tx_crc_value => opb_tx_crc_value); - - --* OPB-Master-Interface - --* - --* (DMA Read/Write Transfers to TX/RX-FIFO) - - dma_enable : if (C_DMA_EN = true) generate - opb_m_if_1 : opb_m_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) - port map ( - OPB_Clk => OPB_Clk, - OPB_Rst => OPB_Rst, - OPB_DBus => OPB_DBus, - M_request => M_request, - MOPB_MGrant => MOPB_MGrant, - M_busLock => M_busLock, - M_ABus => M_ABus, - M_BE => M_BE, - M_DBus => M_DBus, - M_RNW => M_RNW, - M_select => M_select, - M_seqAddr => M_seqAddr, - MOPB_errAck => MOPB_errAck, - MOPB_retry => MOPB_retry, - MOPB_timeout => MOPB_timeout, - MOPB_xferAck => MOPB_xferAck, - opb_m_tx_req => opb_fifo_flg(3), - opb_m_tx_en => opb_m_tx_en, - opb_m_tx_data => opb_m_tx_data, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_num => opb_tx_dma_num, - opb_tx_dma_done => opb_fifo_flg(13), - opb_m_rx_req => opb_fifo_flg(6), - opb_m_rx_en => opb_m_rx_en, - opb_m_rx_data => opb_m_rx_data, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_num => opb_rx_dma_num, - opb_rx_dma_done => opb_fifo_flg(14), - opb_abort_flg => opb_abort_flg, - opb_m_last_block => opb_m_last_block); - end generate dma_enable; - - dma_disable : if (C_DMA_EN = false) generate - M_request <= '0'; - M_busLock <= '0'; - M_ABus <= (others => '0'); - M_BE <= (others => '0'); - M_DBus <= (others => '0'); - M_RNW <= '0'; - M_select <= '0'; - M_seqAddr <= '0'; - opb_m_tx_en <= '0'; - opb_m_tx_data <= (others => '0'); - opb_fifo_flg(13) <= '0'; - opb_m_rx_en <= '0'; - opb_fifo_flg(14) <= '0'; - end generate dma_disable; - - --* Shift-Register - shift_register_1 : shift_register - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA) - port map ( - rst => rst, - opb_ctl_reg => opb_ctl_reg, - sclk => sclk_bufr, - ss_n => ss_n, - mosi => mosi, - miso_o => miso_o, - miso_i => miso_i, - miso_t => miso_t, - sr_tx_clk => sr_tx_clk, - sr_tx_en => sr_tx_en, - sr_tx_data => sr_tx_data, - sr_rx_clk => sr_rx_clk, - sr_rx_en => sr_rx_en, - sr_rx_data => sr_rx_data); - - --* Transmit FIFO - tx_fifo_1 : fifo - generic map ( - C_FIFO_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => "WR") - port map ( - -- global - rst => rst, - prog_full_thresh => tx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), - prog_empty_thresh => tx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), - -- write port - wr_clk => OPB_Clk, - wr_en => fifo_tx_en, - din => fifo_tx_data, - -- flags - prog_full => opb_fifo_flg(0), - full => opb_fifo_flg(1), - overflow => opb_fifo_flg(2), - -- read port - rd_clk => sr_tx_clk, - rd_en => sr_tx_en, - dout => sr_tx_data, - -- flags - prog_empty => opb_fifo_flg(3), - empty => opb_fifo_flg(4), - underflow => opb_fifo_flg(5)); - - fifo_tx_en <= opb_s_tx_en or opb_m_tx_en; - fifo_tx_data <= opb_tx_crc_value when (C_CRC_EN and tx_crc_insert = '1') else - opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else - opb_s_tx_data; - - --* Receive FIFO - rx_fifo_1 : fifo - generic map ( - C_FIFO_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => "RD") - port map ( - -- global - rst => rst, - prog_full_thresh => rx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), - prog_empty_thresh => rx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), - -- write port - wr_clk => sr_rx_clk, - wr_en => sr_rx_en, - din => sr_rx_data, - -- flags - prog_full => opb_fifo_flg(6), - full => opb_fifo_flg(7), - overflow => opb_fifo_flg(8), - -- read port - rd_clk => opb_clk, - rd_en => fifo_rx_en, - dout => fifo_rx_data, - -- flags - prog_empty => opb_fifo_flg(9), - empty => opb_fifo_flg(10), - underflow => opb_fifo_flg(11)); - - fifo_rx_en <= opb_s_rx_en or opb_m_rx_en; - opb_s_rx_data <= fifo_rx_data; - opb_m_rx_data <= fifo_rx_data; - - rst <= OPB_Rst or opb_ctl_reg(C_OPB_CTL_REG_RST); - - opb_fifo_flg(12) <= ss_n; - opb_fifo_flg(15) <= opb_abort_flg; - - - - -- Bit 0 : TX_PROG_EMPTY - opb_irq_flg(0) <= opb_fifo_flg(3); - -- Bit 1 : TX_EMPTY - opb_irq_flg(1) <= opb_fifo_flg(4); - -- Bit 2 : TX_Underflow - opb_irq_flg(2) <= opb_fifo_flg(5); - -- Bit 3 : RX_PROG_FULL - opb_irq_flg(3) <= opb_fifo_flg(6); - -- Bit 4 : RX_FULL - opb_irq_flg(4) <= opb_fifo_flg(7); - -- Bit 5 : RX_Overflow - opb_irq_flg(5) <= opb_fifo_flg(8); - -- Bit 6: CS_H_TO_L - opb_irq_flg(6) <= not opb_fifo_flg(12); - -- Bit 7: CS_L_TO_H - opb_irq_flg(7) <= opb_fifo_flg(12); - -- Bit 8: TX DMA Done - opb_irq_flg(8) <= opb_fifo_flg(13); - -- Bit 9: RX DMA Done - opb_irq_flg(9) <= opb_fifo_flg(14); - -- Bit 10: DMA Transfer Abort - opb_irq_flg(10) <= opb_abort_flg; - - --* IRQ Enable, Detection and Flags Control - irq_gen : for i in 0 to C_NUM_INT-1 generate - irq_ctl_1 : irq_ctl - generic map ( - C_ACTIVE_EDGE => '1') - port map ( - rst => rst, - clk => OPB_Clk, - opb_fifo_flg => opb_irq_flg(i), - opb_ier => opb_ier(i), - opb_isr => opb_isr(i), - opb_isr_clr => opb_isr_clr(i)); - end generate irq_gen; - - -- assert irq if one Interupt Status bit set - opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else - '0'; - - - ----------------------------------------------------------------------------- - - -- clear start_value at power up and soft_reset - crc_en <= opb_ctl_reg(C_OPB_CTL_REG_CRC_EN); - crc_clr <= opb_ctl_reg(C_OPB_CTL_REG_CRC_CLR) or rst; - - crc_gen : if (C_CRC_EN) generate - crc_core_1 : crc_core - generic map ( - C_SR_WIDTH => C_SR_WIDTH) - port map ( - rst => rst, - opb_clk => opb_clk, - crc_en => crc_en, - crc_clr => crc_clr, - opb_m_last_block => opb_m_last_block, - fifo_rx_en => fifo_rx_en, - fifo_rx_data => fifo_rx_data, - opb_rx_crc_value => opb_rx_crc_value, - fifo_tx_en => fifo_tx_en, - fifo_tx_data => fifo_tx_data, - tx_crc_insert => tx_crc_insert, - opb_tx_crc_value => opb_tx_crc_value); - end generate crc_gen; - - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (nonexistent) @@ -1,96 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Generate fifo flags ---* ---* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH ---* @generic C_SYNC_TO Sync FIFO Flags to read or write clock ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - -entity fifo_prog_flags is - generic ( - C_FIFO_SIZE_WIDTH : integer := 4; - C_SYNC_TO : string := "WR"); - port ( - rst : in std_logic; - clk : in std_logic; - cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - -end fifo_prog_flags; -architecture behavior of fifo_prog_flags is - - -- sync register for clock domain transfer - signal cnt_grey_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - type rom_t is array (0 to (2**C_FIFO_SIZE_WIDTH)-1) of std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - - --* convert from gray to binary - component gray2bin - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); - end component; - - signal cnt_bin_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - -begin -- behavior - - --* Generate fifo flags - gen_flags_proc: process(rst, clk) - variable diff : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - begin - if (rst = '1') then - cnt_grey_reg <= (others => '0'); - prog_empty <= '1'; - prog_full <= '0'; - elsif rising_edge(clk) then - -- transfer to rd_clk domain - cnt_grey_reg <= cnt_grey; - -- fifo prog full/empty - if (C_SYNC_TO = "RD") then - -- diff := conv_grey_rom(conv_integer(cnt_grey_reg))- cnt; - diff := cnt_bin_reg - cnt; - else - -- diff := cnt - conv_grey_rom(conv_integer(cnt_grey_reg)); - diff := cnt - cnt_bin_reg; - end if; - - if (diff > prog_full_thresh) then - prog_full <= '1'; - else - prog_full <= '0'; - end if; - - if (diff < prog_empty_thresh) then - prog_empty <= '1'; - else - prog_empty <= '0'; - end if; - end if; - end process gen_flags_proc; - - --* convert gray to bin - gray2bin_1: gray2bin - generic map ( - width => C_FIFO_SIZE_WIDTH) - port map ( - in_gray => cnt_grey_reg, - out_bin => cnt_bin_reg); - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd (nonexistent) @@ -1,77 +0,0 @@ ------------------------------------------------------------------------ --- File: PCK_CRC8_D8.vhd --- Date: Fri Mar 21 22:28:05 2008 --- --- Copyright (C) 1999-2003 Easics NV. --- This source file may be used and distributed without restriction --- provided that this copyright statement is not removed from the file --- and that any derivative work contains the original copyright notice --- and the associated disclaimer. --- --- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS --- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED --- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. --- --- Purpose: VHDL package containing a synthesizable CRC function --- * polynomial: (0 1 2 8) --- * data width: 8 --- --- Info: tools@easics.be --- http://www.easics.com ------------------------------------------------------------------------ - - -library IEEE; -use IEEE.std_logic_1164.all; - -package PCK_CRC8_D8 is - - -- polynomial: (0 1 2 8) - -- data width: 8 - -- convention: the first serial data bit is D(7) - function nextCRC8_D8 - ( Data: std_logic_vector(7 downto 0); - CRC: std_logic_vector(7 downto 0) ) - return std_logic_vector; - -end PCK_CRC8_D8; - -library IEEE; -use IEEE.std_logic_1164.all; - -package body PCK_CRC8_D8 is - - -- polynomial: (0 1 2 8) - -- data width: 8 - -- convention: the first serial data bit is D(7) - function nextCRC8_D8 - ( Data: std_logic_vector(7 downto 0); - CRC: std_logic_vector(7 downto 0) ) - return std_logic_vector is - - variable D: std_logic_vector(7 downto 0); - variable C: std_logic_vector(7 downto 0); - variable NewCRC: std_logic_vector(7 downto 0); - - begin - - D := Data; - C := CRC; - - NewCRC(0) := D(7) xor D(6) xor D(0) xor C(0) xor C(6) xor C(7); - NewCRC(1) := D(6) xor D(1) xor D(0) xor C(0) xor C(1) xor C(6); - NewCRC(2) := D(6) xor D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor - C(2) xor C(6); - NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor - C(3) xor C(7); - NewCRC(4) := D(4) xor D(3) xor D(2) xor C(2) xor C(3) xor C(4); - NewCRC(5) := D(5) xor D(4) xor D(3) xor C(3) xor C(4) xor C(5); - NewCRC(6) := D(6) xor D(5) xor D(4) xor C(4) xor C(5) xor C(6); - NewCRC(7) := D(7) xor D(6) xor D(5) xor C(5) xor C(6) xor C(7); - - return NewCRC; - - end nextCRC8_D8; - -end PCK_CRC8_D8; - Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (nonexistent) @@ -1,65 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short Control Unit for IRQ detection, enable and clear ---* ---* @generic C_ACTIVE_EDGE Select active edge for IRQ-Source 0: H->L;1: L->H ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ --- Version 1.1 --- Bugfix --- added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent --- metastability -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -entity irq_ctl is - generic ( - C_ACTIVE_EDGE : std_logic := '0'); - port ( - rst : in std_logic; - clk : in std_logic; - opb_fifo_flg : in std_logic; - opb_ier : in std_logic; - opb_isr : out std_logic; - opb_isr_clr : in std_logic); - -end irq_ctl; - -architecture behavior of irq_ctl is - - signal opb_fifo_flg_int : std_logic; - -- Sync to clock domain register - signal opb_fifo_flg_int_r0 : std_logic; - signal opb_fifo_flg_int_r1 : std_logic; - - - signal opb_fifo_flg_reg : std_logic; -begin -- behavior - - opb_fifo_flg_int_r0 <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else - not opb_fifo_flg; - - irq_ctl_proc : process(rst, clk) - begin - if (rst = '1') then - opb_isr <= '0'; - elsif rising_edge(clk) then - -- sync to clock domain - opb_fifo_flg_int_r1 <= opb_fifo_flg_int_r0; - opb_fifo_flg_int <= opb_fifo_flg_int_r1; - - opb_fifo_flg_reg <= opb_fifo_flg_int; - if (opb_ier = '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then - opb_isr <= '1'; - elsif (opb_isr_clr = '1') then - opb_isr <= '0'; - end if; - end if; - end process irq_ctl_proc; - - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (nonexistent) @@ -1,349 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short OPB-Slave Interface ---* ---* Generics described in top entity. ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -library work; -use work.opb_spi_slave_pack.all; - -entity opb_if is - - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 3; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - C_FAMILY : string := "virtex-4"; - C_SR_WIDTH : integer := 8; - C_FIFO_SIZE_WIDTH : integer := 4; - C_DMA_EN : boolean := false; - C_CRC_EN : boolean := false); - port ( - -- OPB-Bus Signals - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - -- fifo ports - opb_s_tx_en : out std_logic; - opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_s_rx_en : out std_logic; - opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- control register - opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - -- Fifo almost full/empty thresholds - tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); - -- interrupts - opb_dgie : out std_logic; - opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); - -- dma register - opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_ctl : out std_logic_vector(0 downto 0); - opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_ctl : out std_logic_vector(0 downto 0); - opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - -- rx crc - opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0)); -end opb_if; - -architecture behavior of opb_if is - - - signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - - - type state_t is (idle, - done); - signal state : state_t := idle; - - -- internal signals to enable readback - - signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_dgie_int : std_logic; - - signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - - - -- only used if C_DMA_EN=true - signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0); - signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0); - signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - -begin -- behavior - - tx_thresh <= tx_thresh_int; - rx_thresh <= rx_thresh_int; - opb_ier <= opb_ier_int; - opb_dgie <= opb_dgie_int; - - opb_ctl_reg <= opb_ctl_reg_int; - - --* Signals for DMA-Engine control - u1 : if C_DMA_EN generate - opb_tx_dma_ctl <= opb_tx_dma_ctl_int; - opb_tx_dma_addr <= opb_tx_dma_addr_int; - opb_tx_dma_num <= opb_tx_dma_num_int; - opb_rx_dma_ctl <= opb_rx_dma_ctl_int; - opb_rx_dma_addr <= opb_rx_dma_addr_int; - opb_rx_dma_num <= opb_rx_dma_num_int; - end generate u1; - - --- unused outputs - Sln_errAck <= '0'; - Sln_retry <= '0'; - Sln_toutSup <= '0'; - - --* convert Sln_DBus_big_end to little mode - conv_big_Sln_DBus_proc : process(Sln_DBus_big_end) - begin - for i in 0 to 31 loop - Sln_DBus(31-i) <= Sln_DBus_big_end(i); - end loop; -- i - end process conv_big_Sln_DBus_proc; - - --* convert OPB_ABus to big endian - conv_big_OPB_ABus_proc : process(OPB_ABus) - begin - for i in 0 to 31 loop - OPB_ABus_big_end(31-i) <= OPB_ABus(i); - end loop; -- i - end process conv_big_OPB_ABus_proc; - - --* convert OPB_DBus to little mode - conv_big_OPB_DBus_proc : process(OPB_DBus) - begin - for i in 0 to 31 loop - OPB_DBus_big_end(31-i) <= OPB_DBus(i); - end loop; -- i - end process conv_big_OPB_DBus_proc; - - --* control OPB requests - --* - --* handles OPB-read and -write request - opb_slave_proc : process (OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - -- OPB - Sln_xferAck <= '0'; - Sln_DBus_big_end <= (others => '0'); - -- FIFO - opb_s_rx_en <= '0'; - opb_s_tx_en <= '0'; - -- - state <= idle; - -- Register - tx_thresh_int <= (others => '0'); - rx_thresh_int <= (others => '0'); - opb_ier_int <= (others => '0'); - opb_dgie_int <= '0'; - opb_ctl_reg_int <= (others => '0'); - - if C_DMA_EN then - opb_tx_dma_ctl_int <= (others => '0'); - opb_tx_dma_addr_int <= (others => '0'); - opb_tx_dma_num_int <= (others => '0'); - opb_rx_dma_ctl_int <= (others => '0'); - opb_rx_dma_addr_int <= (others => '0'); - opb_rx_dma_num_int <= (others => '0'); - end if; - - - elsif (OPB_Clk'event and OPB_Clk = '1') then - case state is - when idle => - if (OPB_select = '1' and - ((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then - -- *device selected - Sln_xferAck <= '1'; - state <= done; - if (OPB_RNW = '1') then - -- read acess - case OPB_ABus_big_end(7 downto 2) is - when C_ADR_CTL => - Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int; - - when C_ADR_RX_DATA => - opb_s_rx_en <= '1'; - Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data; - - when C_ADR_STATUS => - Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg; - - when C_ADR_TX_THRESH => - Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); - Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); - - when C_ADR_RX_THRESH => - Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); - Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); - - when C_ADR_DGIE => - Sln_DBus_big_end(0) <= opb_dgie_int; - when C_ADR_IER => - Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int; - - when C_ADR_ISR => - Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr; - - when C_ADR_TX_DMA_CTL => - if C_DMA_EN then - Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int; - end if; - - when C_ADR_TX_DMA_ADDR => - if C_DMA_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int; - end if; - - when C_ADR_TX_DMA_NUM => - if C_DMA_EN then - Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_tx_dma_num_int; - end if; - - - when C_ADR_RX_DMA_CTL => - if C_DMA_EN then - Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int; - end if; - - when C_ADR_RX_DMA_ADDR => - if C_DMA_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int; - end if; - - when C_ADR_RX_DMA_NUM => - if C_DMA_EN then - Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_rx_dma_num_int; - end if; - - when C_ADR_RX_CRC => - if C_CRC_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); - Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_rx_crc_value; - end if; - - when C_ADR_TX_CRC => - if C_CRC_EN then - Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); - Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_tx_crc_value; - end if; - when others => - null; - end case; - else - -- write acess - case OPB_ABus_big_end(7 downto 2) is - when C_ADR_CTL => - opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0); - - when C_ADR_TX_DATA => - opb_s_tx_en <= '1'; - opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); - - when C_ADR_TX_THRESH => - tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); - tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); - - when C_ADR_RX_THRESH => - rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); - rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); - - when C_ADR_DGIE => - opb_dgie_int <= OPB_DBus_big_end(0); - - when C_ADR_IER => - opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); - - when C_ADR_ISR => - opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); - - when C_ADR_TX_DMA_CTL => - if C_DMA_EN then - opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); - end if; - - when C_ADR_TX_DMA_ADDR => - if C_DMA_EN then - opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); - end if; - - when C_ADR_TX_DMA_NUM => - if C_DMA_EN then - opb_tx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0); - end if; - - when C_ADR_RX_DMA_CTL => - if C_DMA_EN then - opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); - end if; - - when C_ADR_RX_DMA_ADDR => - if C_DMA_EN then - opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); - end if; - - when C_ADR_RX_DMA_NUM => - if C_DMA_EN then - opb_rx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0); - end if; - - when others => - null; - end case; - end if; -- OPB_RNW - else - -- not selected - state <= idle; - end if; - when done => - opb_ctl_reg_int(3) <= '0'; - opb_isr_clr <= (others => '0'); - opb_s_rx_en <= '0'; - opb_s_tx_en <= '0'; - Sln_xferAck <= '0'; - Sln_DBus_big_end <= (others => '0'); - state <= idle; - - when others => - state <= idle; - end case; - end if; - end process opb_slave_proc; -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd (nonexistent) @@ -1,76 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -library work; -use work.PCK_CRC32_D32.all; --- java -jar jacksum.jar -a crc:32,04C11DB7,FFFFFFFF,false,false,00000000 --- -q 000000000000000100000002000000030000000400000005000000060000000700000008000000090000000A0000000B0000000C0000000D0000000E0000000F --- -x --- Result: eb99fa90 64 - -use work.PCK_CRC8_D8.all; --- java -jar jacksum.jar -a crc:8,07,FF,false,false,00 --- -q 000102030405060708090A0B0C0D0E0F --- -x --- Result: B8 16 - -entity crc_gen is - generic ( - C_SR_WIDTH : integer := 32; - crc_start_value : std_logic_vector(31 downto 0) := (others => '1')); - port ( - clk : in std_logic; - crc_clear : in std_logic; - crc_en : in std_logic; - crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0); - crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0)); -end crc_gen; - -architecture rtl of crc_gen is - signal crc_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal crc_data_in_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - -begin -- crc_gen - process(clk) - begin - if rising_edge(clk) then - if (crc_clear = '1') then - crc_data_int <= crc_start_value(C_SR_WIDTH-1 downto 0); - elsif (crc_en = '1') then - case C_SR_WIDTH is - when 32 => - crc_data_int <= nextCRC32_D32(crc_data_in_int, crc_data_int); - when 8 => - crc_data_int <= nextCRC8_D8(crc_data_in_int, crc_data_int); - when others => - -- no crc calculation - crc_data_int <= (others => '0'); - end case; - end if; - end if; - end process; - - process(crc_data_int) - begin - for i in 0 to 7 loop - crc_data_out(24+7-i) <= not crc_data_int(i); - crc_data_out(16+7-i) <= not crc_data_int(8+i); - crc_data_out(8+7-i) <= not crc_data_int(16+i); - crc_data_out(7-i) <= not crc_data_int(24+i); - end loop; -- i - end process; - - process(crc_data_in) - begin - for i in 0 to 7 loop - crc_data_in_int(7-i) <= crc_data_in(i); - crc_data_in_int(8+7-i) <= crc_data_in(8+i); - crc_data_in_int(16+7-i) <= crc_data_in(16+i); - crc_data_in_int(24+7-i) <= crc_data_in(24+i); - end loop; -- i - end process; - - -end rtl; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (nonexistent) @@ -1,68 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short gray Adder ---* ---* @generic width with of adder vector ---* ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -entity gray_adder is - generic ( - width : integer := 4); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); -end gray_adder; - -architecture behavior of gray_adder is - --* convert gray to bin - component gray2bin - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); - end component; - --* convert bin to gray - component bin2gray - generic ( - width : integer); - port ( - in_bin : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - signal out_bin : std_logic_vector(width-1 downto 0); - signal bin_add : std_logic_vector(width-1 downto 0); - -begin -- behavior - --* convert input gray signal to binary - gray2bin_1 : gray2bin - generic map ( - width => width) - port map ( - in_gray => in_gray, - out_bin => out_bin); - - --* add one to signal - bin_add <= out_bin + 1; - --* convert signal back to gray - bin2gray_1 : bin2gray - generic map ( - width => width) - port map ( - in_bin => bin_add, - out_gray => out_gray); - - - -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (nonexistent) @@ -1,320 +0,0 @@ -------------------------------------------------------------------------------- ---* ---* @short OPB-Master Interface ---* ---* Generics described in top entity. ---* ---* @see opb_spi_slave ---* @author: Daniel Köthe ---* @version: 1.0 ---* @date: 2007-11-11 ---/ -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -library work; -use work.opb_spi_slave_pack.all; - -entity opb_m_if is - generic ( - C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - C_USER_ID_CODE : integer := 0; - C_OPB_AWIDTH : integer := 32; - C_OPB_DWIDTH : integer := 32; - C_FAMILY : string := "virtex-4"; - C_SR_WIDTH : integer := 8; - C_MSB_FIRST : boolean := true; - C_CPOL : integer range 0 to 1 := 0; - C_PHA : integer range 0 to 1 := 0; - C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7); - - port ( - -- opb master interface - OPB_Clk : in std_logic; - OPB_Rst : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - --------------------------------------------------------------------------- - -- read transfer - -- read data from memory and fill fifo - opb_m_tx_req : in std_logic; - opb_m_tx_en : out std_logic; - opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - -- enable/disable dma transfer - opb_tx_dma_ctl : in std_logic_vector(0 downto 0); - -- base adress for transfer - opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_tx_dma_done : out std_logic; - --------------------------------------------------------------------------- - -- write transfer - -- read fifo an write to memory - opb_m_rx_req : in std_logic; - opb_m_rx_en : out std_logic; - opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - -- enable/disable dma transfer - opb_rx_dma_ctl : in std_logic_vector(0 downto 0); - -- base adress for transfer - opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - opb_rx_dma_done : out std_logic; - --------------------------------------------------------------------------- - opb_abort_flg : out std_logic; - opb_m_last_block : out std_logic); -end opb_m_if; - -architecture behavior of opb_m_if is - - type state_t is (idle, - wait_grant, - transfer_write, - transfer_read, - done); - - - signal state : state_t := idle; - - signal M_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal M_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - - signal M_select_int : std_logic; - signal read_transfer : boolean; - - -- read transfer - signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_en : std_logic; - signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - signal opb_tx_dma_done_int : std_logic; - - -- write transfer - signal opb_rx_dma_en : std_logic; - signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); - signal opb_rx_dma_done_int : std_logic; - - -begin -- behavior - - --* convert M_DBus_big_end to little endian - process(M_DBus_big_end) - begin - for i in 0 to 31 loop - M_DBus(31-i) <= M_DBus_big_end(i); - end loop; -- i - end process; - - --* convert M_ABus_big_end to little endian - process(M_ABus_big_end) - begin - for i in 0 to 31 loop - M_ABus(31-i) <= M_ABus_big_end(i); - end loop; -- i - end process; - - --* convert OPB_DBus to bi endian - process(OPB_DBus) - begin - for i in 0 to 31 loop - OPB_DBus_big_end(31-i) <= OPB_DBus(i); - end loop; -- i - end process; - - -- for both sides - M_ABus_big_end <= opb_tx_dma_addr_int when (M_select_int = '1' and (read_transfer = true)) else - opb_rx_dma_addr_int when (M_select_int = '1' and (read_transfer = false)) else - (others => '0'); - M_select <= M_select_int; - - - - -- write transfer - opb_m_rx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = false)) else - '0'; - - M_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_m_rx_data when (M_select_int = '1' and (read_transfer = false)) else - (others => '0'); - M_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); - - opb_tx_dma_done <= opb_tx_dma_done_int; - - -- read transfer - opb_m_tx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = true)) else - '0'; - opb_m_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); - - opb_rx_dma_done <= opb_rx_dma_done_int; - - - -------------------------------------------------------------------------------- - opb_masteer_proc : process(OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - M_BE <= (others => '0'); - M_busLock <= '0'; - M_request <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_seqAddr <= '0'; - opb_tx_dma_done_int <= '0'; - opb_rx_dma_done_int <= '0'; - opb_abort_flg <= '0'; - opb_m_last_block <= '0'; - opb_tx_dma_num_int <= (others => '0'); - opb_rx_dma_num_int <= (others => '0'); - elsif rising_edge(OPB_Clk) then - case state is - when idle => - opb_abort_flg <= '0'; - opb_tx_dma_en <= opb_tx_dma_ctl(0); - opb_rx_dma_en <= opb_rx_dma_ctl(0); - - if (opb_tx_dma_ctl(0) = '1' and opb_tx_dma_en = '0') then - opb_tx_dma_addr_int <= opb_tx_dma_addr; - opb_tx_dma_num_int <= opb_tx_dma_num; - opb_tx_dma_done_int <= '0'; - - end if; - - if (opb_rx_dma_ctl(0) = '1' and opb_rx_dma_en = '0') then - opb_rx_dma_addr_int <= opb_rx_dma_addr; - opb_rx_dma_num_int <= opb_rx_dma_num; - opb_rx_dma_done_int <= '0'; - end if; - - if (opb_tx_dma_en = '1' and opb_m_tx_req = '1' and opb_tx_dma_done_int = '0') then - -- read from memory to fifo - M_request <= '1'; - read_transfer <= true; - state <= wait_grant; - elsif (opb_rx_dma_en = '1' and opb_m_rx_req = '1'and opb_rx_dma_done_int = '0') then - -- read from fifo and write memory - M_request <= '1'; - read_transfer <= false; - state <= wait_grant; - else - state <= idle; - end if; - - when wait_grant => - if (MOPB_MGrant = '1') then - M_request <= '0'; - M_busLock <= '1'; - M_select_int <= '1'; - M_seqAddr <= '1'; - M_BE <= "1111"; - if (read_transfer) then - -- read - M_RNW <= '1'; - if (conv_integer(opb_tx_dma_num_int) = 0) then - opb_m_last_block <= '1'; - end if; - state <= transfer_read; - else - -- write - M_RNW <= '0'; - if (conv_integer(opb_rx_dma_num_int) = 0) then - opb_m_last_block <= '1'; - end if; - state <= transfer_write; - end if; - else - state <= wait_grant; - end if; - - when transfer_read => - if (MOPB_xferAck = '1') then - opb_tx_dma_addr_int <= opb_tx_dma_addr_int +4; - if (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then - -- cycle 14 - -- deassert buslock and seq_address 1 cycle before transfer complete - M_busLock <= '0'; - M_seqAddr <= '0'; - elsif (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then - -- cycle 15 - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - if (conv_integer(opb_tx_dma_num_int) = 0) then - opb_tx_dma_done_int <= '1'; - opb_m_last_block <= '0'; - else - opb_tx_dma_num_int <= opb_tx_dma_num_int-1; - end if; - state <= done; - end if; - elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then - -- cancel transfer - M_busLock <= '0'; - M_seqAddr <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - opb_abort_flg <= '1'; - state <= done; - else - state <= transfer_read; - end if; - - when transfer_write => - if (MOPB_xferAck = '1') then - opb_rx_dma_addr_int <= opb_rx_dma_addr_int +4; - if (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then - -- cycle 14 - -- deassert buslock and seq_address 1 cycle before transfer complete - M_busLock <= '0'; - M_seqAddr <= '0'; - elsif (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then - -- cycle 15 - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - if (conv_integer(opb_rx_dma_num_int) = 0) then - opb_rx_dma_done_int <= '1'; - opb_m_last_block <= '0'; - else - opb_rx_dma_num_int <= opb_rx_dma_num_int-1; - end if; - state <= done; - end if; - elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then - -- cancel transfer - M_busLock <= '0'; - M_seqAddr <= '0'; - M_RNW <= '0'; - M_select_int <= '0'; - M_BE <= (others => '0'); - opb_abort_flg <= '1'; - state <= done; - else - state <= transfer_write; - end if; - - when done => - - state <= idle; - - when others => - state <= idle; - end case; - end if; - end process opb_masteer_proc; -end behavior; Index: trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (nonexistent) @@ -1,21 +0,0 @@ -############################################################################## -## Filename: E:\Eigene_Dateien\Entwicklung\cpld\spi-core\edk\test_opb_spi_slave\pcores/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao -## Description: Peripheral Analysis Order -## Date: Mon Oct 29 20:54:19 2007 (by Create and Import Peripheral Wizard) -############################################################################## - -lib opb_spi_slave_v1_00_a opb_spi_slave_pack vhdl -lib opb_spi_slave_v1_00_a shift_register vhdl -lib opb_spi_slave_v1_00_a bin2gray vhdl -lib opb_spi_slave_v1_00_a gray2bin vhdl -lib opb_spi_slave_v1_00_a gray_adder vhdl -lib opb_spi_slave_v1_00_a fifo vhdl -lib opb_spi_slave_v1_00_a fifo_prog_flags vhdl -lib opb_spi_slave_v1_00_a irq_ctl vhdl -lib opb_spi_slave_v1_00_a opb_m_if vhdl -lib opb_spi_slave_v1_00_a opb_if vhdl -lib opb_spi_slave_v1_00_a PCK_CRC32_D32.vhd vhdl -lib opb_spi_slave_v1_00_a crc_gen.vhd vhdl -lib opb_spi_slave_v1_00_a ram vhdl -lib opb_spi_slave_v1_00_a opb_spi_slave vhdl - Index: trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (nonexistent) @@ -1,73 +0,0 @@ -################################################################### -## -## Name : opb_spi_slave -## Desc : Microprocessor Peripheral Description -## : Automatically generated by PsfUtility -## -################################################################### - -BEGIN opb_spi_slave - -## Peripheral Options -OPTION IPTYPE = PERIPHERAL -OPTION IMP_NETLIST = TRUE -OPTION HDL = VHDL -OPTION CORE_STATE = ACTIVE -OPTION IP_GROUP = MICROBLAZE:PPC:USER - - -## Bus Interfaces -BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB - -## Generics for VHDL or Parameters for Verilog -PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80 -PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR -PARAMETER C_USER_ID_CODE = 0, DT = INTEGER -PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB -PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB -PARAMETER C_FAMILY = virtex-4, DT = STRING -PARAMETER C_SR_WIDTH = 8, DT = INTEGER -PARAMETER C_MSB_FIRST = true, DT = BOOLEAN -PARAMETER C_CPOL = 0, DT = INTEGER -PARAMETER C_PHA = 0, DT = INTEGER -PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER -PARAMETER C_DMA_EN = true, DT = BOOLEAN -PARAMETER C_CRC_EN = true, DT = BOOLEAN - -## Ports -PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB -PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB -PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK -PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB -PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST -PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB -PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB -PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB -PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB -PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB -PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB -PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB -PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB -PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB -PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB -PORT M_request = M_request, DIR = O, BUS = MSOPB -PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB -PORT M_select = M_select, DIR = O, BUS = MSOPB -PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB -PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB -PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB -PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB -PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB -PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB -PORT sclk = "", DIR = I, SIGIS = CLK -PORT ss_n = "", DIR = I -PORT mosi = "", DIR = I -PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T -PORT miso_o = "", DIR = O -PORT miso_i = "", DIR = I -PORT miso_t = "", DIR = O -PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH - -END Index: trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf =================================================================== --- trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (revision 34) +++ trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (nonexistent) @@ -1,7 +0,0 @@ -NET "mosi" TNM = "_mosi"; -TIMEGRP "_mosi" OFFSET = IN 5 ns VALID 10 ns BEFORE "sclk" HIGH ; - -NET "miso_o" TNM = "_miso_o"; -TIMEGRP "_miso_o" OFFSET = OUT 10 ns AFTER "sclk" LOW ; - - Index: trunk/bench/vhdl/txt_util.vhd =================================================================== --- trunk/bench/vhdl/txt_util.vhd (revision 34) +++ trunk/bench/vhdl/txt_util.vhd (nonexistent) @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - Index: trunk/bench/vhdl/opb_m_if_tb.vhd =================================================================== --- trunk/bench/vhdl/opb_m_if_tb.vhd (revision 34) +++ trunk/bench/vhdl/opb_m_if_tb.vhd (nonexistent) @@ -1,313 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "opb_m_if" --- Project : -------------------------------------------------------------------------------- --- File : opb_m_if_tb.vhd --- Author : --- Company : --- Created : 2007-10-29 --- Last update: 2007-11-12 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-10-29 1.0 d.koethe Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() -------------------------------------------------------------------------------- - -entity opb_m_if_tb is - -end opb_m_if_tb; - -------------------------------------------------------------------------------- - -architecture behavior of opb_m_if_tb is - - component opb_m_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1; - C_FIFO_SIZE_WIDTH : integer range 4 to 7); - port ( - OPB_Clk : in std_logic; - OPB_Rst : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - opb_m_tx_req : in std_logic; - opb_m_tx_en : out std_logic; - opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_tx_dma_ctl : in std_logic_vector(0 downto 0); - opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_num : in std_logic_vector(15 downto 0); - opb_tx_dma_done : out std_logic; - opb_m_rx_req : in std_logic; - opb_m_rx_en : out std_logic; - opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_dma_ctl : in std_logic_vector(0 downto 0); - opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_num : in std_logic_vector(15 downto 0); - opb_rx_dma_done : out std_logic); - end component; - - - - -- component generics - constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - constant C_USER_ID_CODE : integer := 0; - constant C_OPB_AWIDTH : integer := 32; - constant C_OPB_DWIDTH : integer := 32; - constant C_FAMILY : string := "virtex-4"; - constant C_SR_WIDTH : integer := 8; - constant C_MSB_FIRST : boolean := true; - constant C_CPOL : integer range 0 to 1 := 0; - constant C_PHA : integer range 0 to 1 := 0; - constant C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7; - - -- component ports - signal OPB_Clk : std_logic; - signal OPB_Rst : std_logic; - signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal M_request : std_logic; - signal MOPB_MGrant : std_logic; - signal M_busLock : std_logic; - signal M_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); - signal M_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); - signal M_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal M_RNW : std_logic; - signal M_select : std_logic; - signal M_seqAddr : std_logic; - signal MOPB_errAck : std_logic; - signal MOPB_retry : std_logic; - signal MOPB_timeout : std_logic; - signal MOPB_xferAck : std_logic; - signal opb_m_tx_req : std_logic; - signal opb_m_tx_en : std_logic; - signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_num : std_logic_vector(15 downto 0); - signal opb_tx_dma_done : std_logic; - signal opb_m_rx_req : std_logic; - signal opb_m_rx_en : std_logic; - signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_num : std_logic_vector(15 downto 0); - signal opb_rx_dma_done : std_logic; - - signal opb_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_tx_data : std_logic_vector(0 to C_SR_WIDTH-1); - -begin -- behavior - - -- component instantiation - opb_m_if_1: opb_m_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) - port map ( - OPB_Clk => OPB_Clk, - OPB_Rst => OPB_Rst, - OPB_DBus => OPB_DBus, - M_request => M_request, - MOPB_MGrant => MOPB_MGrant, - M_busLock => M_busLock, - M_ABus => M_ABus, - M_BE => M_BE, - M_DBus => M_DBus, - M_RNW => M_RNW, - M_select => M_select, - M_seqAddr => M_seqAddr, - MOPB_errAck => MOPB_errAck, - MOPB_retry => MOPB_retry, - MOPB_timeout => MOPB_timeout, - MOPB_xferAck => MOPB_xferAck, - opb_m_tx_req => opb_m_tx_req, - opb_m_tx_en => opb_m_tx_en, - opb_m_tx_data => opb_m_tx_data, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_num => opb_tx_dma_num, - opb_tx_dma_done => opb_tx_dma_done, - opb_m_rx_req => opb_m_rx_req, - opb_m_rx_en => opb_m_rx_en, - opb_m_rx_data => opb_m_rx_data, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_num => opb_rx_dma_num, - opb_rx_dma_done => opb_rx_dma_done); - - - -- clock generation - process - begin - OPB_Clk <= '0'; - wait for 10 ns; - OPB_Clk <= '1'; - wait for 10 ns; - end process; - - - -- arbiter/xferack - process(OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - MOPB_MGrant <= '0'; - MOPB_xferAck <= '0'; - opb_tx_data <= (others => '0'); - elsif rising_edge(OPB_Clk) then - -- arbiter - if (M_request = '1') then - MOPB_MGrant <= '1'; - else - MOPB_MGrant <= '0'; - end if; - - -- xfer_Ack - if (M_select = '1') then - if (M_RNW = '1' and MOPB_xferAck = '1') then - opb_tx_data <= opb_tx_data+1; - end if; - MOPB_xferAck <= not MOPB_xferAck; - else - opb_tx_data <= (others => '0'); - MOPB_xferAck <= '0'; - end if; - end if; - end process; - - OPB_DBus( 0 to C_OPB_DWIDTH-C_SR_WIDTH-1) <= (others => '0'); - OPB_DBus(C_OPB_DWIDTH-C_SR_WIDTH to C_OPB_DWIDTH-1) <= opb_tx_data; - - -- rx fifo emulation - process(OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - opb_rx_data <= (others => '0'); - elsif rising_edge(OPB_Clk) then - if (opb_m_rx_en = '1') then - opb_rx_data <= opb_rx_data+1; - end if; - end if; - end process; - - opb_m_rx_data <= opb_rx_data; - - - -- waveform generation - WaveGen_Proc : process - begin - -- reset active - OPB_Rst <= '1'; - - MOPB_errAck <= '0'; - MOPB_retry <= '0'; - MOPB_timeout <= '0'; - - opb_m_tx_req <= '0'; - opb_tx_dma_ctl <= (others => '0'); - opb_tx_dma_addr <= (others => '0'); - opb_m_rx_req <= '0'; - opb_rx_dma_ctl <= (others => '0'); - opb_rx_dma_addr <= (others => '0'); - - - - - wait for 100 ns; - -- remove rst - OPB_Rst <= '0'; - --------------------------------------------------------------------------- - -- write transfer - opb_tx_dma_addr <= conv_std_logic_vector(16#24000000#, 32); - - wait until rising_edge(OPB_Clk); - opb_tx_dma_ctl(0) <= '1'; - - - wait until rising_edge(OPB_Clk); - opb_m_tx_req <= '1'; -- asssert almost full flag - wait until rising_edge(OPB_Clk); - opb_m_tx_req <= '0'; -- deassert almost full flag - - wait for 1 us; - - --------------------------------------------------------------------------- - -- read transfer - opb_rx_dma_addr <= conv_std_logic_vector(16#25000000#, 32); - - wait until rising_edge(OPB_Clk); - opb_rx_dma_ctl(0) <= '1'; - - -- first transfer - wait until rising_edge(OPB_Clk); - opb_m_rx_req <= '1'; -- asssert almost full flag - wait until rising_edge(OPB_Clk); - opb_m_rx_req <= '0'; -- deassert almost full flag - wait for 1 us; - - -- second transfer - wait until rising_edge(OPB_Clk); - opb_m_rx_req <= '1'; -- asssert almost full flag - wait until rising_edge(OPB_Clk); - opb_m_rx_req <= '0'; -- deassert almost full flag - wait for 1 us; - --------------------------------------------------------------------------- - - - assert false report "Simulation Sucessful" severity failure; - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration opb_m_if_tb_behavior_cfg of opb_m_if_tb is - for behavior - end for; -end opb_m_if_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/images-body.vhd =================================================================== --- trunk/bench/vhdl/images-body.vhd (revision 34) +++ trunk/bench/vhdl/images-body.vhd (nonexistent) @@ -1,200 +0,0 @@ --------------------------------------------------------------------------- --- --- Copyright (C) 1993, Peter J. Ashenden --- Mail: Dept. Computer Science --- University of Adelaide, SA 5005, Australia --- e-mail: petera@cs.adelaide.edu.au --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 1, or (at your option) --- any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. --- --------------------------------------------------------------------------- --- --- $RCSfile: images-body.vhd,v $ $Revision: 1.1 $ $Date: 2007-11-30 20:22:01 $ --- --------------------------------------------------------------------------- --- --- Images package body. --- --- Functions that return the string image of values. --- Each image is a correctly formed literal according to the --- rules of VHDL-93. --- --------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -package images is - function image ( - constant bv : std_logic_vector) - return string; -end images; - -package body images is - - - -- Image of bit vector as binary bit string literal - -- (in the format B"...") - -- Length of result is bv'length + 3 - - function image (bv : in bit_vector) return string is - - alias bv_norm : bit_vector(1 to bv'length) is bv; - variable result : string(1 to bv'length + 3); - - begin - result(1) := 'B'; - result(2) := '"'; - for index in bv_norm'range loop - if bv_norm(index) = '0' then - result(index + 2) := '0'; - else - result(index + 2) := '1'; - end if; - end loop; - result(bv'length + 3) := '"'; - return result; - end image; -------------------------------------------------------------------------------- - -- Image of bit vector as binary bit string literal - -- (in the format B"...") - -- Length of result is bv'length + 3 - - function image (bv : in std_logic_vector) return string is - - alias bv_norm : std_logic_vector(1 to bv'length) is bv; - variable result : string(1 to bv'length + 3); - - begin - result(1) := 'B'; - result(2) := '"'; - for index in bv_norm'range loop - if bv_norm(index) = '0' then - result(index + 2) := '0'; - else - result(index + 2) := '1'; - end if; - end loop; - result(bv'length + 3) := '"'; - return result; - end image; - - - - ---------------------------------------------------------------- - - -- Image of bit vector as octal bit string literal - -- (in the format O"...") - -- Length of result is (bv'length+2)/3 + 3 - - function image_octal (bv : in bit_vector) return string is - - constant nr_digits : natural := (bv'length + 2) / 3; - variable result : string(1 to nr_digits + 3); - variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0'); - variable three_bits : bit_vector(0 to 2); - variable digit : character; - - begin - result(1) := 'O'; - result(2) := '"'; - bits(bits'right - bv'length + 1 to bits'right) := bv; - for index in 0 to nr_digits - 1 loop - three_bits := bits(3*index to 3*index + 2); - case three_bits is - when b"000" => - digit := '0'; - when b"001" => - digit := '1'; - when b"010" => - digit := '2'; - when b"011" => - digit := '3'; - when b"100" => - digit := '4'; - when b"101" => - digit := '5'; - when b"110" => - digit := '6'; - when b"111" => - digit := '7'; - end case; - result(index + 3) := digit; - end loop; - result(nr_digits + 3) := '"'; - return result; - end image_octal; - - ---------------------------------------------------------------- - - -- Image of bit vector as hex bit string literal - -- (in the format X"...") - -- Length of result is (bv'length+3)/4 + 3 - - function image_hex (bv : in bit_vector) return string is - - constant nr_digits : natural := (bv'length + 3) / 4; - variable result : string(1 to nr_digits + 3); - variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0'); - variable four_bits : bit_vector(0 to 3); - variable digit : character; - - begin - result(1) := 'X'; - result(2) := '"'; - bits(bits'right - bv'length + 1 to bits'right) := bv; - for index in 0 to nr_digits - 1 loop - four_bits := bits(4*index to 4*index + 3); - case four_bits is - when b"0000" => - digit := '0'; - when b"0001" => - digit := '1'; - when b"0010" => - digit := '2'; - when b"0011" => - digit := '3'; - when b"0100" => - digit := '4'; - when b"0101" => - digit := '5'; - when b"0110" => - digit := '6'; - when b"0111" => - digit := '7'; - when b"1000" => - digit := '8'; - when b"1001" => - digit := '9'; - when b"1010" => - digit := 'A'; - when b"1011" => - digit := 'B'; - when b"1100" => - digit := 'C'; - when b"1101" => - digit := 'D'; - when b"1110" => - digit := 'E'; - when b"1111" => - digit := 'F'; - end case; - result(index + 3) := digit; - end loop; - result(nr_digits + 3) := '"'; - return result; - end image_hex; - - -end images; Index: trunk/bench/vhdl/bin2gray_tb.vhd =================================================================== --- trunk/bench/vhdl/bin2gray_tb.vhd (revision 34) +++ trunk/bench/vhdl/bin2gray_tb.vhd (nonexistent) @@ -1,118 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "bin2grey" --- Project : -------------------------------------------------------------------------------- --- File : bin2gray_tb.vhd --- Author : --- Company : --- Created : 2007-10-22 --- Last update: 2007-10-22 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-10-22 1.0 d.koethe Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -------------------------------------------------------------------------------- - -entity bin2gray_tb is - -end bin2gray_tb; - -------------------------------------------------------------------------------- - -architecture behavior of bin2gray_tb is - - component gray2bin - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_bin : out std_logic_vector(width-1 downto 0)); - end component; - - component bin2gray - generic ( - width : integer); - port ( - in_bin : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - component gray_adder - generic ( - width : integer); - port ( - in_gray : in std_logic_vector(width-1 downto 0); - out_gray : out std_logic_vector(width-1 downto 0)); - end component; - - -- component generics - constant width : integer := 4; - - -- component ports - signal in_bin : std_logic_vector(width-1 downto 0); - signal out_gray : std_logic_vector(width-1 downto 0); - signal out_bin : std_logic_vector(width-1 downto 0); - signal out_gray_add_one : std_logic_vector(width-1 downto 0); - -begin -- behavior - - -- component instantiation - bin2gray_1 : bin2gray - generic map ( - width => width) - port map ( - in_bin => in_bin, - out_gray => out_gray); - - - gray2bin_1 : gray2bin - generic map ( - width => width) - port map ( - in_gray => out_gray, - out_bin => out_bin); - - - gray_adder_1 : gray_adder - generic map ( - width => width) - port map ( - in_gray => out_gray, - out_gray => out_gray_add_one); - - - -- waveform generation - WaveGen_Proc : process - begin - for i in 0 to 2**width-1 loop - in_bin <= conv_std_logic_vector(i, width); - wait for 10 ns; - - end loop; -- i - assert false report "Simulation Sucessful" severity failure; - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration bin2gray_tb_behavior_cfg of bin2gray_tb is - for behavior - end for; -end bin2gray_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/rx_fifo_emu.vhd =================================================================== --- trunk/bench/vhdl/rx_fifo_emu.vhd (revision 34) +++ trunk/bench/vhdl/rx_fifo_emu.vhd (nonexistent) @@ -1,37 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - -entity rx_fifo_emu is - - generic ( - C_SR_WIDTH : integer; - C_RX_CMP_VALUE : integer); - - port ( - rst : in std_logic; - rx_clk : in std_logic; - rx_en : in std_logic; - rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0)); - -end rx_fifo_emu; - - -architecture behavior of rx_fifo_emu is - - signal rx_data_cmp : std_logic_vector(C_SR_WIDTH-1 downto 0) := conv_std_logic_vector(C_RX_CMP_VALUE,C_SR_WIDTH); - -begin -- behavior - process(rst, rx_clk) - begin - if (rst = '1') then - elsif rising_edge(rx_clk) then - if (rx_en = '1') then - assert (rx_data = rx_data_cmp) report "RX-FIFO Compare Error" severity warning; - rx_data_cmp <= rx_data_cmp+1; - end if; - end if; - end process; -end behavior; Index: trunk/bench/vhdl/opb_if_tb.vhd =================================================================== --- trunk/bench/vhdl/opb_if_tb.vhd (revision 34) +++ trunk/bench/vhdl/opb_if_tb.vhd (nonexistent) @@ -1,252 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "opb_if" --- Project : -------------------------------------------------------------------------------- --- File : opb_if_tb.vhd --- Author : --- Company : --- Created : 2007-09-01 --- Last update: 2007-11-12 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-09-01 1.0 d.koethe Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library work; -use work.opb_spi_slave_pack.all; - -------------------------------------------------------------------------------- - -entity opb_if_tb is - -end opb_if_tb; - -------------------------------------------------------------------------------- - -architecture behavior of opb_if_tb is - - component opb_if - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_DMA_EN : boolean); - port ( - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - opb_s_tx_en : out std_logic; - opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_s_rx_en : out std_logic; - opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); - opb_dgie : out std_logic; - opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); - opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); - opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_tx_dma_ctl : out std_logic_vector(0 downto 0); - opb_tx_dma_num : out std_logic_vector(15 downto 0); - opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); - opb_rx_dma_ctl : out std_logic_vector(0 downto 0); - opb_rx_dma_num : out std_logic_vector(15 downto 0)); - end component; - - constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - constant C_USER_ID_CODE : integer := 3; - constant C_OPB_AWIDTH : integer := 32; - constant C_OPB_DWIDTH : integer := 32; - constant C_FAMILY : string := "virtex-4"; - constant C_SR_WIDTH : integer := 8; - constant C_FIFO_SIZE_WIDTH : integer := 4; - constant C_DMA_EN : boolean := true; - - - signal OPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); - signal OPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); - signal OPB_Clk : std_logic; - signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal OPB_RNW : std_logic; - signal OPB_Rst : std_logic; - signal OPB_select : std_logic; - signal OPB_seqAddr : std_logic; - signal Sln_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal Sln_errAck : std_logic; - signal Sln_retry : std_logic; - signal Sln_toutSup : std_logic; - signal Sln_xferAck : std_logic; - signal opb_s_tx_en : std_logic; - signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_s_rx_en : std_logic; - signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); - signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); - signal opb_dgie : std_logic; - signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); - signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_tx_dma_num : std_logic_vector(15 downto 0); - signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); - signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); - signal opb_rx_dma_num : std_logic_vector(15 downto 0); - - constant clk_period : time := 25 ns; - -begin -- behavior - - -- component instantiation - DUT: opb_if - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_DMA_EN => C_DMA_EN) - port map ( - OPB_ABus => OPB_ABus, - OPB_BE => OPB_BE, - OPB_Clk => OPB_Clk, - OPB_DBus => OPB_DBus, - OPB_RNW => OPB_RNW, - OPB_Rst => OPB_Rst, - OPB_select => OPB_select, - OPB_seqAddr => OPB_seqAddr, - Sln_DBus => Sln_DBus, - Sln_errAck => Sln_errAck, - Sln_retry => Sln_retry, - Sln_toutSup => Sln_toutSup, - Sln_xferAck => Sln_xferAck, - opb_s_tx_en => opb_s_tx_en, - opb_s_tx_data => opb_s_tx_data, - opb_s_rx_en => opb_s_rx_en, - opb_s_rx_data => opb_s_rx_data, - opb_ctl_reg => opb_ctl_reg, - tx_thresh => tx_thresh, - rx_thresh => rx_thresh, - opb_fifo_flg => opb_fifo_flg, - opb_dgie => opb_dgie, - opb_ier => opb_ier, - opb_isr => opb_isr, - opb_isr_clr => opb_isr_clr, - opb_tx_dma_addr => opb_tx_dma_addr, - opb_tx_dma_ctl => opb_tx_dma_ctl, - opb_tx_dma_num => opb_tx_dma_num, - opb_rx_dma_addr => opb_rx_dma_addr, - opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_num => opb_rx_dma_num); - - -- clock generation - process - begin - OPB_Clk <= '0'; - wait for clk_period; - OPB_Clk <= '1'; - wait for clk_period; - end process; - - -- waveform generation - WaveGen_Proc : process - begin - OPB_ABus <= (others => '0'); - OPB_BE <= (others => '0'); - OPB_DBus <= (others => '0'); - OPB_RNW <= '0'; - OPB_select <= '0'; - OPB_seqAddr <= '0'; - -- reset active - OPB_Rst <= '1'; - wait for 100 ns; - -- reset inactive - OPB_Rst <= '0'; - - - -- write acess - wait until rising_edge(OPB_Clk); - OPB_ABus <= X"10000000"; - OPB_select <= '1'; - OPB_RNW <= '0'; - OPB_DBus <= X"12345678"; - - for i in 0 to 3 loop - wait until rising_edge(OPB_Clk); - if (Sln_xferAck = '1') then - exit; - end if; - end loop; -- i - OPB_DBus <= X"00000000"; - OPB_ABus <= X"00000000"; - OPB_select <= '0'; - - - -- read acess - wait until rising_edge(OPB_Clk); - OPB_ABus <= X"10000000"; - OPB_select <= '1'; - OPB_RNW <= '1'; - - for i in 0 to 3 loop - wait until rising_edge(OPB_Clk); - if (Sln_xferAck = '1') then - exit; - end if; - end loop; -- i - OPB_ABus <= X"00000000"; - OPB_select <= '0'; - - - - wait for 100 ns; - assert false report "Simulation sucessful" severity failure; - - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration opb_if_tb_behavior_cfg of opb_if_tb is - for behavior - end for; -end opb_if_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/crc_core_tb.vhd =================================================================== --- trunk/bench/vhdl/crc_core_tb.vhd (revision 34) +++ trunk/bench/vhdl/crc_core_tb.vhd (nonexistent) @@ -1,191 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "crc_core" --- Project : -------------------------------------------------------------------------------- --- File : crc_core_tb.vhd --- Author : --- Company : --- Created : 2008-03-23 --- Last update: 2008-03-23 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2008 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2008-03-23 1.0 d.koethe Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -------------------------------------------------------------------------------- - -entity crc_core_tb is - generic ( - C_SR_WIDTH : integer := 32); - -end crc_core_tb; - -------------------------------------------------------------------------------- - -architecture behavior of crc_core_tb is - component crc_core - generic ( - C_SR_WIDTH : integer); - port ( - rst : in std_logic; - opb_clk : in std_logic; - crc_en : in std_logic; - crc_clr : in std_logic; - opb_m_last_block : in std_logic; - fifo_rx_en : in std_logic; - fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); - fifo_tx_en : in std_logic; - fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - tx_crc_insert : out std_logic; - opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - signal rst : std_logic; - signal opb_clk : std_logic; - signal crc_en : std_logic; - signal crc_clr : std_logic; - signal opb_m_last_block : std_logic; - signal fifo_rx_en : std_logic; - signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal fifo_tx_en : std_logic; - signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal tx_crc_insert : std_logic; - signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); - - constant C_CLK_PERIOD : time := 10 ns; - -begin -- behavior - - -- component instantiation - DUT : crc_core - generic map ( - C_SR_WIDTH => C_SR_WIDTH) - port map ( - rst => rst, - opb_clk => opb_clk, - crc_en => crc_en, - crc_clr => crc_clr, - opb_m_last_block => opb_m_last_block, - fifo_rx_en => fifo_rx_en, - fifo_rx_data => fifo_rx_data, - opb_rx_crc_value => opb_rx_crc_value, - fifo_tx_en => fifo_tx_en, - fifo_tx_data => fifo_tx_data, - tx_crc_insert => tx_crc_insert, - opb_tx_crc_value => opb_tx_crc_value); - - -- clock generation - process - begin - opb_clk <= '0'; - wait for C_CLK_PERIOD/2; - opb_clk <= '1'; - wait for C_CLK_PERIOD/2; - end process; - - -- waveform generation - WaveGen_Proc : process - begin - rst <= '1'; - crc_en <= '0'; - crc_clr <= '0'; - opb_m_last_block <= '0'; - fifo_rx_en <= '0'; - fifo_rx_data <= (others => '0'); - fifo_tx_en <= '0'; - fifo_tx_data <= (others => '0'); - wait for 100 ns; - rst <= '0'; - - -- clear crc - wait until rising_edge(opb_clk); - crc_clr <= '1'; - wait until rising_edge(opb_clk); - crc_clr <= '0'; - crc_en <= '1'; - - - - -- generate data block - opb_m_last_block <= '0'; - - for i in 0 to 15 loop - wait until rising_edge(opb_clk); - -- RX - fifo_rx_en <= '1'; - fifo_rx_data <= conv_std_logic_vector(i, fifo_rx_data'length); - -- TX - fifo_tx_en <= '1'; - fifo_tx_data <= conv_std_logic_vector(i, fifo_tx_data'length); - end loop; -- i - wait until rising_edge(opb_clk); - fifo_rx_en <= '0'; - fifo_rx_data <= (others => '0'); - fifo_tx_en <= '0'; - fifo_tx_data <= (others => '0'); - wait until rising_edge(opb_clk); - - if (C_SR_WIDTH = 32) then - assert (conv_integer(opb_rx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; - assert (conv_integer(opb_tx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; - end if; - - - -- generate crc_block - opb_m_last_block <= '1'; - - for i in 0 to 15 loop - wait until rising_edge(opb_clk); - -- RX - fifo_rx_en <= '1'; - fifo_rx_data <= (others => '1'); - -- TX - fifo_tx_en <= '1'; - fifo_tx_data <= (others => '1'); - end loop; -- i - wait until rising_edge(opb_clk); - fifo_rx_en <= '0'; - fifo_rx_data <= (others => '0'); - fifo_tx_en <= '0'; - fifo_tx_data <= (others => '0'); - wait until rising_edge(opb_clk); - -- same value, no changes in last block - if (C_SR_WIDTH = 32) then - assert (conv_integer(opb_rx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; - assert (conv_integer(opb_tx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; - end if; - opb_m_last_block <= '0'; - - - wait for 100 ns; - - - - assert false report "Simulation Sucessful" severity failure; - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration crc_core_tb_behavior_cfg of crc_core_tb is - for behavior - end for; -end crc_core_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/tx_fifo_emu.vhd =================================================================== --- trunk/bench/vhdl/tx_fifo_emu.vhd (revision 34) +++ trunk/bench/vhdl/tx_fifo_emu.vhd (nonexistent) @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - -entity tx_fifo_emu is - generic ( - C_SR_WIDTH : integer := 8; - C_TX_CMP_VALUE : integer); - port ( - rst : in std_logic; - tx_clk : in std_logic; - tx_en : in std_logic; - tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - -end tx_fifo_emu; - -architecture behavior of tx_fifo_emu is - - signal tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -begin -- behavior - - tx_data <= tx_data_int; - - process(rst, tx_clk) - begin - if (rst = '1') then - tx_data_int <= conv_std_logic_vector(C_TX_CMP_VALUE,C_SR_WIDTH); - elsif rising_edge(tx_clk) then - if (tx_en = '1') then - tx_data_int <= tx_data_int + 1; - end if; - end if; - end process; - -end behavior; Index: trunk/bench/vhdl/shift_register_tb.vhd =================================================================== --- trunk/bench/vhdl/shift_register_tb.vhd (revision 34) +++ trunk/bench/vhdl/shift_register_tb.vhd (nonexistent) @@ -1,411 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "shift_register" --- Project : -------------------------------------------------------------------------------- --- File : shift_register_tb.vhd --- Author : --- Company : --- Created : 2007-08-24 --- Last update: 2007-11-12 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-08-24 1.0 d.koethe Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - -library work; -use work.opb_spi_slave_pack.all; - -------------------------------------------------------------------------------- - -entity shift_register_tb is - -end shift_register_tb; - -------------------------------------------------------------------------------- - -architecture behavior of shift_register_tb is - - component shift_register - generic ( - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1); - port ( - rst : in std_logic; - opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - sr_tx_clk : out std_logic; - sr_tx_en : out std_logic; - sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); - sr_rx_clk : out std_logic; - sr_rx_en : out std_logic; - sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - - component tx_fifo_emu - generic ( - C_SR_WIDTH : integer; - C_TX_CMP_VALUE : integer); - port ( - rst : in std_logic; - tx_clk : in std_logic; - tx_en : in std_logic; - tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - component rx_fifo_emu - generic ( - C_SR_WIDTH : integer; - C_RX_CMP_VALUE : integer); - port ( - rst : in std_logic; - rx_clk : in std_logic; - rx_en : in std_logic; - rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0)); - end component; - - - constant C_NUM_TESTS : integer := 3; - - -- component generics - constant C_SR_WIDTH : integer := 8; - type C_MSB_FIRST_t is array (0 to C_NUM_TESTS) of boolean; - constant C_MSB_FIRST : C_MSB_FIRST_t := (true, false, true, false); - type C_CPOL_t is array (0 to C_NUM_TESTS) of integer range 0 to 1; - constant C_CPOL : C_CPOL_t := (0, 0, 1, 1); - type C_PHA_t is array (0 to C_NUM_TESTS) of integer range 0 to 1; - constant C_PHA : C_PHA_t := (0, 0, 0, 0); - - constant clk_period : time := 40 ns; - - type sig_std_logic_t is array (0 to C_NUM_TESTS) of std_logic; - type sig_std_logic_vector_t is array (0 to C_NUM_TESTS) of std_logic_vector(C_SR_WIDTH-1 downto 0); - - type C_SCLK_INIT_t is array (0 to C_NUM_TESTS) of std_logic; - constant C_SCLK_INIT : C_SCLK_INIT_t := ('0', '0', '1', '1'); - - signal TEST_NUM : integer := 0; - - -- component ports - signal rst : sig_std_logic_t; - signal sclk : sig_std_logic_t; - signal cs_n : sig_std_logic_t; - signal mosi : sig_std_logic_t; - signal miso_o : sig_std_logic_t; - signal miso_i : sig_std_logic_t; - signal miso_t : sig_std_logic_t; - signal tx_clk : sig_std_logic_t; - signal tx_en : sig_std_logic_t; - signal tx_data : sig_std_logic_vector_t; - signal rx_clk : sig_std_logic_t; - signal rx_en : sig_std_logic_t; - signal rx_data : sig_std_logic_vector_t; - - -- component ports - signal s_rst : std_logic; - signal s_sclk : std_logic; - signal s_cs_n : std_logic; - signal s_mosi : std_logic; - signal s_miso_o : std_logic; - signal s_miso_i : std_logic; - signal s_miso_t : std_logic; - signal s_tx_clk : std_logic; - signal s_tx_en : std_logic; - signal s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - signal s_rx_clk : std_logic; - signal s_rx_en : std_logic; - signal s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); - - -- testbench - constant C_TX_CMP_VALUE : integer := 130; - constant C_RX_CMP_VALUE : integer := 129; - - signal rx_master : std_logic_vector(7 downto 0); - - signal opb_ctl_reg: std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); - -begin -- behavior - - opb_ctl_reg <= "0111"; -- enable all - - s_rst <= rst(TEST_NUM); - s_sclk <= sclk(TEST_NUM); - s_cs_n <= cs_n(TEST_NUM); - s_mosi <= mosi(TEST_NUM); - s_miso_o <= miso_o(TEST_NUM); - s_miso_i <= miso_i(TEST_NUM); - s_miso_t <= miso_t(TEST_NUM); - s_tx_clk <= tx_clk(TEST_NUM); - s_tx_en <= tx_en(TEST_NUM); - s_tx_data <= tx_data(TEST_NUM); - s_rx_clk <= rx_clk(TEST_NUM); - s_rx_en <= rx_en(TEST_NUM); - s_rx_data <= rx_data(TEST_NUM); - - - -- component instantiation - - i : for i in 0 to 3 generate - DUT : shift_register - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST(i), - C_CPOL => C_CPOL(i), - C_PHA => C_PHA(i)) - port map ( - rst => rst(i), - opb_ctl_reg => opb_ctl_reg, - sclk => sclk(i), - ss_n => cs_n(i), - mosi => mosi(i), - miso_o => miso_o(i), - miso_i => miso_i(i), - miso_t => miso_t(i), - sr_tx_clk => tx_clk(i), - sr_tx_en => tx_en(i), - sr_tx_data => tx_data(i), - sr_rx_clk => rx_clk(i), - sr_rx_en => rx_en(i), - sr_rx_data => rx_data(i)); - - - - tx_fifo_emu_1 : tx_fifo_emu - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - C_TX_CMP_VALUE => C_TX_CMP_VALUE) - port map ( - rst => rst(i), - tx_clk => tx_clk(i), - tx_en => tx_en(i), - tx_data => tx_data(i)); - - - rx_fifo_emu_1 : rx_fifo_emu - generic map ( - C_SR_WIDTH => C_SR_WIDTH, - C_RX_CMP_VALUE => C_RX_CMP_VALUE) - port map ( - rst => rst(i), - rx_clk => rx_clk(i), - rx_en => rx_en(i), - rx_data => rx_data(i)); - end generate i; - - - -- waveform generation - WaveGen_Proc : process - variable rx_value : std_logic_vector(7 downto 0); - variable tx_value : std_logic_vector(7 downto 0); - begin - for i in 0 to C_NUM_TESTS loop - sclk(i) <= C_SCLK_INIT(i); - cs_n(i) <= '1'; - mosi(i) <= 'Z'; - miso_i(i) <= 'Z'; - -- rst_active - rst(i) <= '1'; - end loop; -- i -------------------------------------------------------------------------------- - -- Actual Tests - TEST_NUM <= 0; - rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); - tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); - wait for 100 ns; - rst(TEST_NUM) <= '0'; - - -- CPHA=0 CPOL=0 C_MSB_FIRST=TRUE - cs_n(TEST_NUM) <= '0'; - for i in 7 downto 0 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - rx_master(i) <= miso_o(TEST_NUM); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - end loop; -- i - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - wait for 100 ns; - assert (rx_master = tx_value) report "Master Receive Failure" severity warning; - - - -- write 2 byte - cs_n(TEST_NUM) <= '0'; - for n in 1 to 2 loop - rx_value := rx_value +1; - tx_value := tx_value +1; - for i in 7 downto 0 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - rx_master(i) <= miso_o(TEST_NUM); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - end loop; -- i - assert (rx_master = tx_value) report "Master Receive Failure" severity warning; - end loop; -- n - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; ---------------------------------------------------------------------------- - -- Actual Tests - TEST_NUM <= 1; - rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); - tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); - wait for 100 ns; - rst(TEST_NUM) <= '0'; - - -- CPHA=0 CPOL=0 C_MSB_FIRST=FALSE - cs_n(TEST_NUM) <= '0'; - for i in 0 to 7 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - rx_master(i) <= miso_o(TEST_NUM); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - end loop; -- i - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - wait for 100 ns; - assert (rx_master = tx_value) report "Master Receive Failure" severity warning; - - - -- write 2 byte - cs_n(TEST_NUM) <= '0'; - for n in 1 to 2 loop - rx_value := rx_value +1; - tx_value := tx_value +1; - for i in 0 to 7 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - rx_master(i) <= miso_o(TEST_NUM); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - end loop; -- i - assert (rx_master = tx_value) report "Master Receive Failure" severity warning; - end loop; -- n - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - -------------------------------------------------------------------------------- - TEST_NUM <= 2; - rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); - tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); - wait for 100 ns; - rst(TEST_NUM) <= '0'; - - -- CPHA=0 CPOL=1 C_MSB_FIRST=TRUE - cs_n(TEST_NUM) <= '0'; - for i in 7 downto 0 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - end loop; -- i - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - wait for 100 ns; - - -- write 2 byte - cs_n(TEST_NUM) <= '0'; - for n in 1 to 2 loop - rx_value := rx_value +1; - for i in 7 downto 0 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - end loop; -- i - end loop; -- n - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - -------------------------------------------------------------------------------- - TEST_NUM <= 3; - rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); - tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); - wait for 100 ns; - rst(TEST_NUM) <= '0'; - - -- CPHA=0 CPOL=1 C_MSB_FIRST=FALSE - cs_n(TEST_NUM) <= '0'; - for i in 0 to 7 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - end loop; -- i - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - wait for 100 ns; - - -- write 2 byte - cs_n(TEST_NUM) <= '0'; - for n in 1 to 2 loop - rx_value := rx_value +1; - for i in 0 to 7 loop - mosi(TEST_NUM) <= rx_value(i); - wait for clk_period/2; - sclk(TEST_NUM) <= '0'; - wait for clk_period/2; - sclk(TEST_NUM) <= '1'; - end loop; -- i - end loop; -- n - mosi(TEST_NUM) <= 'Z'; - wait for clk_period/2; - cs_n(TEST_NUM) <= '1'; - -------------------------------------------------------------------------------- - - - wait for 1 us; - - assert false report "Simulation sucessful" severity failure; - - - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration shift_register_tb_behavior_cfg of shift_register_tb is - for behavior - end for; -end shift_register_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/fifo_tb.vhd =================================================================== --- trunk/bench/vhdl/fifo_tb.vhd (revision 34) +++ trunk/bench/vhdl/fifo_tb.vhd (nonexistent) @@ -1,308 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "fifo_8bitx16" --- Project : -------------------------------------------------------------------------------- --- File : fifo_8bitx16_tb.vhd --- Author : --- Company : --- Created : 2007-09-04 --- Last update: 2007-11-12 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-09-04 1.0 d.koethe Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use IEEE.STD_LOGIC_ARITH.all; - - -library work; -use work.txt_util.all; -------------------------------------------------------------------------------- - -entity fifo_tb is - -end fifo_tb; - -------------------------------------------------------------------------------- - -architecture behavior of fifo_tb is - component fifo - generic ( - C_FIFO_WIDTH : integer; - C_FIFO_SIZE_WIDTH : integer; - C_SYNC_TO : string); - port ( - rst : in std_logic; - wr_clk : in std_logic; - wr_en : in std_logic; - din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); - rd_clk : in std_logic; - rd_en : in std_logic; - dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); - empty : out std_logic; - full : out std_logic; - overflow : out std_logic; - underflow : out std_logic; - prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - prog_empty : out std_logic; - prog_full : out std_logic); - end component; - --- Testbench - constant C_FIFO_SIZE : integer := 15; - constant C_FIFO_WIDTH : integer := 8; - constant C_FIFO_SIZE_WIDTH : integer := 4; - - -- sync to RD --- constant C_SYNC_TO : string := "RD"; --- constant wr_clk_period : time := 100 ns; --- constant rd_clk_period : time := 25 ns; - - -- sync to WR - constant C_SYNC_TO : string := "WR"; - constant wr_clk_period : time := 25 ns; - constant rd_clk_period : time := 100 ns; - - signal rst : std_logic; - signal wr_clk : std_logic; - signal wr_en : std_logic; - signal din : std_logic_vector(C_FIFO_WIDTH-1 downto 0); - signal rd_clk : std_logic; - signal rd_en : std_logic; - signal dout : std_logic_vector(C_FIFO_WIDTH-1 downto 0); - signal empty : std_logic; - signal full : std_logic; - signal overflow : std_logic; - signal underflow : std_logic; - signal prog_empty_thresh : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal prog_full_thresh : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); - signal prog_empty : std_logic; - signal prog_full : std_logic; - - - - - - signal flags : std_logic_vector(5 downto 0); - signal wr_clk_int : std_logic; - signal wr_clk_en : boolean := false; - - signal rd_clk_int : std_logic; - signal rd_clk_en : boolean := false; - - - signal wr_off : boolean := false; - signal rd_off : boolean := false; - -begin -- behavior - - process - begin - rd_clk_int <= '0'; - wait for rd_clk_period/2; - rd_clk_int <= '1'; - wait for rd_clk_period/2; - end process; - - process - begin - wr_clk_int <= '0'; - wait for wr_clk_period/2; - wr_clk_int <= '1'; - wait for wr_clk_period/2; - end process; - - -- component instantiation - - - DUT : fifo - generic map ( - C_FIFO_WIDTH => C_FIFO_WIDTH, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_SYNC_TO => C_SYNC_TO) - port map ( - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - dout => dout, - empty => empty, - full => full, - overflow => overflow, - underflow => underflow, - prog_empty_thresh => prog_empty_thresh, - prog_full_thresh => prog_full_thresh, - prog_empty => prog_empty, - prog_full => prog_full); - - flags <= prog_empty & - empty & - underflow & - prog_full & - full & - overflow; - - - wr_off <= false when (C_SYNC_TO = "RD") else true; - rd_off <= false when (C_SYNC_TO = "WR") else true; - - wr_clk <= wr_clk_int when wr_clk_en else '0'; - rd_clk <= rd_clk_int when rd_clk_en else '0'; - - -- waveform generation - WaveGen_Proc : process - variable first : std_logic_vector(7 downto 0) := (others => '0'); - begin - wr_en <= '0'; - din <= (others => 'Z'); - rd_en <= '0'; - -- prog_empty assert 2 cycle delay - -- prog_empty deassert 1 cycle delay - prog_empty_thresh <= X"4"; - -- prog_full assert 2 cycle delay - -- prog_full deassert 1 cycle delay - prog_full_thresh <= X"B"; - -- rst active - rst <= '1'; - wait for 100 ns; - rst <= '0'; - - -- check reset value - -- 1: empty/prog_empty - assert (flags = "110000") report "Flag Reset Value wrong " & str(flags) severity warning; - - -- write - - wait until falling_edge(wr_clk_int); - wr_clk_en <= true; - wr_en <= '1'; - din <= X"A5"; - wait until falling_edge(wr_clk_int); - wr_clk_en <= wr_off; - wr_en <= '0'; - din <= (others => 'Z'); - -- check after 1 write - -- 1: empty - assert (flags = "100000") report "Flag after one write wrong " & str(flags) severity warning; - - wait for 100 ns; - - -- read - wait until falling_edge(rd_clk_int); - rd_clk_en <= true; - rd_en <= '1'; - wait until falling_edge(rd_clk_int); - rd_en <= '0'; - rd_clk_en <= rd_off; - wait for 100 ns; - - -- check reset value - -- 1: empty/prog_empty - assert (flags = "110000") report "Flag after one read wrong " & str(flags) severity warning; - - -- write 16 byte - wait until falling_edge(wr_clk_int); - for i in 1 to 255 loop - wr_clk_en <= true; - wr_en <= '1'; - din <= conv_std_logic_vector(i, din'length); - wait until falling_edge(wr_clk_int); - wr_en <= '0'; - din <= (others => 'Z'); - wr_clk_en <= wr_off; - -- report threshold for prog_empty - if (prog_empty = '0' and first(0) = '0') then - assert (i = conv_integer(prog_empty_thresh)) - report "prog_emtpy deassert after " & integer'image(i) & " writes." severity warning; - first(0) := '1'; - end if; - -- report threshold for prog_full - if (prog_full = '1' and first(1) = '0') then - assert (i = conv_integer(prog_full_thresh)+1) - report "prog_full assert after " & integer'image(i) & " writes." severity warning; - first(1) := '1'; - end if; - -- report threshold for full - if (full = '1') then - assert (i = C_FIFO_SIZE) report "full assert after " & integer'image(i) & " writes." severity warning; - exit; - end if; - end loop; -- i - - -- read - wait until falling_edge(rd_clk_int); - for i in 1 to 255 loop - rd_clk_en <= true; - rd_en <= '1'; - if (empty = '0' and underflow = '0') then - assert (conv_integer(dout) = i) report "Read failure at " & integer'image(i) severity warning; - end if; - wait until falling_edge(rd_clk_int); - wait for 1 ps; - rd_clk_en <= rd_off; - rd_en <= '0'; - - - - -- report threshold for prog_full - if (prog_full = '0' and first(2) = '0') then - assert (C_FIFO_SIZE-i = conv_integer(prog_full_thresh)-1) - report "prog_full deassert after " & integer'image(i) & " reads." severity warning; - first(2) := '1'; - end if; - -- report threshold for prog_empty - - if (prog_empty = '1' and first(3) = '0') then - assert (C_FIFO_SIZE-i = conv_integer(prog_empty_thresh)-2) - report "prog_empty assert after " & integer'image(i) & " reads." severity warning; - first(3) := '1'; - end if; - -- report threshold for empty - if (empty = '1' and first(4) = '0') then - assert (i = C_FIFO_SIZE) - report "empty assert after " & integer'image(i) & " reads." severity warning; - first(4) := '1'; - end if; - -- report threshold for underflow - if (underflow = '1') then - assert (i = C_FIFO_SIZE+1) - report "underflow assert after " & integer'image(i) & " reads." severity warning; - exit; - end if; - - end loop; -- i - - wait for 100 ns; - - assert false report "Simulation Sucessful" severity failure; - - - - - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration fifo_tb_behavior_cfg of fifo_tb is - for behavior - end for; -end fifo_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: trunk/bench/vhdl/opb_spi_slave_tb.vhd =================================================================== --- trunk/bench/vhdl/opb_spi_slave_tb.vhd (revision 34) +++ trunk/bench/vhdl/opb_spi_slave_tb.vhd (nonexistent) @@ -1,805 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Testbench for design "opb_spi_slave" --- Project : -------------------------------------------------------------------------------- --- File : opb_spi_slave_tb.vhd --- Author : --- Company : --- Created : 2007-09-02 --- Last update: 2008-05-15 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2007 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2007-09-02 1.0 d.koethe Created -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; -use IEEE.numeric_std.all; -- conv_integer() - -library work; -use work.opb_spi_slave_pack.all; -------------------------------------------------------------------------------- - -entity opb_spi_slave_tb is - generic ( - -- 0: simple transfer 1 byte transmit/receive - -- 1: transfer 4 bytes and check flags - -- 2: write until TX-FIFO asserts full, read until RX-FIFO asserts full, read - -- and compare data - -- 3: check FIFO Reset form underflow condition - -- 4: check FIFO Flags IRQ Generation - -- 5: check Slave select IRQ Generation - -- 6: test opb Master Transfer - test : std_logic_vector(7 downto 0) := "01000000"); -end opb_spi_slave_tb; - -------------------------------------------------------------------------------- - -architecture behavior of opb_spi_slave_tb is - constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; - constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; - constant C_USER_ID_CODE : integer := 0; - constant C_OPB_AWIDTH : integer := 32; - constant C_OPB_DWIDTH : integer := 32; - constant C_FAMILY : string := "virtex-4"; - -- - -- constant C_SR_WIDTH : integer := 8; - constant C_SR_WIDTH : integer := 32; - -- - constant C_MSB_FIRST : boolean := true; - constant C_CPOL : integer range 0 to 1 := 0; - constant C_PHA : integer range 0 to 1 := 0; - constant C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7; - constant C_DMA_EN : boolean := true; - constant C_CRC_EN : boolean := true; - - component opb_spi_slave - generic ( - C_BASEADDR : std_logic_vector(0 to 31); - C_HIGHADDR : std_logic_vector(0 to 31); - C_USER_ID_CODE : integer; - C_OPB_AWIDTH : integer; - C_OPB_DWIDTH : integer; - C_FAMILY : string; - C_SR_WIDTH : integer; - C_MSB_FIRST : boolean; - C_CPOL : integer range 0 to 1; - C_PHA : integer range 0 to 1; - C_FIFO_SIZE_WIDTH : integer range 4 to 7; - C_DMA_EN : boolean; - C_CRC_EN : boolean); - port ( - OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); - OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); - OPB_Clk : in std_logic; - OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); - OPB_RNW : in std_logic; - OPB_Rst : in std_logic; - OPB_select : in std_logic; - OPB_seqAddr : in std_logic; - Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - Sln_errAck : out std_logic; - Sln_retry : out std_logic; - Sln_toutSup : out std_logic; - Sln_xferAck : out std_logic; - M_request : out std_logic; - MOPB_MGrant : in std_logic; - M_busLock : out std_logic; - M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); - M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); - M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); - M_RNW : out std_logic; - M_select : out std_logic; - M_seqAddr : out std_logic; - MOPB_errAck : in std_logic; - MOPB_retry : in std_logic; - MOPB_timeout : in std_logic; - MOPB_xferAck : in std_logic; - sclk : in std_logic; - ss_n : in std_logic; - mosi : in std_logic; - miso_o : out std_logic; - miso_i : in std_logic; - miso_t : out std_logic; - opb_irq : out std_logic); - end component; - - signal OPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); - signal OPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); - signal OPB_Clk : std_logic; - signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal OPB_RNW : std_logic; - signal OPB_Rst : std_logic; - signal OPB_select : std_logic; - signal OPB_seqAddr : std_logic; - signal Sln_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal Sln_errAck : std_logic; - signal Sln_retry : std_logic; - signal Sln_toutSup : std_logic; - signal Sln_xferAck : std_logic; - signal M_request : std_logic; - signal MOPB_MGrant : std_logic; - signal M_busLock : std_logic; - signal M_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); - signal M_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); - signal M_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal M_RNW : std_logic; - signal M_select : std_logic; - signal M_seqAddr : std_logic; - signal MOPB_errAck : std_logic; - signal MOPB_retry : std_logic; - signal MOPB_timeout : std_logic; - signal MOPB_xferAck : std_logic; - signal sclk : std_logic; - signal ss_n : std_logic; - signal mosi : std_logic; - signal miso_o : std_logic; - signal miso_i : std_logic; - signal miso_t : std_logic; - signal opb_irq : std_logic; - --- testbench - constant clk_period : time := 10 ns; - constant spi_clk_period : time := 50 ns; - - signal miso : std_logic; - - signal opb_read_data : std_logic_vector(31 downto 0); - signal spi_value_in : std_logic_vector(C_SR_WIDTH-1 downto 0); - - signal OPB_Transfer_Abort : boolean; - signal OPB_DBus0 : std_logic_vector(0 to C_OPB_DWIDTH-1); - signal OPB_DBus1 : std_logic_vector(0 to C_OPB_DWIDTH-1); - -begin -- behavior - - -- component instantiation - DUT : opb_spi_slave - generic map ( - C_BASEADDR => C_BASEADDR, - C_HIGHADDR => C_HIGHADDR, - C_USER_ID_CODE => C_USER_ID_CODE, - C_OPB_AWIDTH => C_OPB_AWIDTH, - C_OPB_DWIDTH => C_OPB_DWIDTH, - C_FAMILY => C_FAMILY, - C_SR_WIDTH => C_SR_WIDTH, - C_MSB_FIRST => C_MSB_FIRST, - C_CPOL => C_CPOL, - C_PHA => C_PHA, - C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_DMA_EN => C_DMA_EN, - C_CRC_EN => C_CRC_EN) - port map ( - OPB_ABus => OPB_ABus, - OPB_BE => OPB_BE, - OPB_Clk => OPB_Clk, - OPB_DBus => OPB_DBus, - OPB_RNW => OPB_RNW, - OPB_Rst => OPB_Rst, - OPB_select => OPB_select, - OPB_seqAddr => OPB_seqAddr, - Sln_DBus => Sln_DBus, - Sln_errAck => Sln_errAck, - Sln_retry => Sln_retry, - Sln_toutSup => Sln_toutSup, - Sln_xferAck => Sln_xferAck, - M_request => M_request, - MOPB_MGrant => MOPB_MGrant, - M_busLock => M_busLock, - M_ABus => M_ABus, - M_BE => M_BE, - M_DBus => M_DBus, - M_RNW => M_RNW, - M_select => M_select, - M_seqAddr => M_seqAddr, - MOPB_errAck => MOPB_errAck, - MOPB_retry => MOPB_retry, - MOPB_timeout => MOPB_timeout, - MOPB_xferAck => MOPB_xferAck, - sclk => sclk, - ss_n => ss_n, - mosi => mosi, - miso_o => miso_o, - miso_i => miso_i, - miso_t => miso_t, - opb_irq => opb_irq); - - - - -- clock generation - process - begin - OPB_Clk <= '0'; - wait for clk_period; - OPB_Clk <= '1'; - wait for clk_period; - end process; - - -- IOB-Buffer - miso <= miso_o when (miso_t = '0') else - 'Z'; - miso_i <= miso; - - -- OPB-Master arbiter/xferack generation - process(OPB_Rst, OPB_Clk) - begin - if (OPB_Rst = '1') then - MOPB_MGrant <= '0'; - MOPB_xferAck <= '0'; - MOPB_errAck <= '0'; - elsif rising_edge(OPB_Clk) then - -- arbiter - if (M_request = '1') then - MOPB_MGrant <= '1'; - else - MOPB_MGrant <= '0'; - end if; - - -- xfer_Ack - if (M_select = '1') then - if (OPB_Transfer_Abort) then - MOPB_errAck <= '1'; - else - if (conv_integer(M_ABus) >= 16#24000000#) then - if (M_RNW = '1') then - -- read - OPB_DBus0(C_OPB_DWIDTH-C_SR_WIDTH to C_OPB_DWIDTH-1) <= "0000000000000000" & "00" & M_ABus(16 to C_OPB_DWIDTH-3); - end if; - MOPB_xferAck <= not MOPB_xferAck; - end if; - - end if; - - - else - OPB_DBus0 <= (others => '0'); - MOPB_errAck <= '0'; - MOPB_xferAck <= '0'; - end if; - - end if; - end process; - ------------------------------------------------------------------------------- - u1 : for i in 0 to 31 generate - OPB_DBus(i) <= OPB_DBus0(i) or OPB_DBus1(i); - end generate u1; - - ------------------------------------------------------------------------------ - -- waveform generation - WaveGen_Proc : process - variable temp : std_logic_vector(31 downto 0); - variable first : std_logic_vector(7 downto 0) := (others => '0'); - - --------------------------------------------------------------------------- - procedure opb_write ( - constant adr : in std_logic_vector(7 downto 2); - constant data : in integer) is - begin - -- write transmit data - wait until rising_edge(OPB_Clk); - OPB_ABus <= transport conv_std_logic_vector(conv_integer(adr & "00"), 32) after 2 ns; - OPB_select <= transport '1' after 2 ns; - OPB_RNW <= transport '0' after 2 ns; - OPB_DBus1 <= transport conv_std_logic_vector(data, 32) after 2 ns; - - for i in 0 to 3 loop - wait until rising_edge(OPB_Clk); - if (Sln_xferAck = '1') then - exit; - end if; - end loop; -- i - OPB_DBus1 <= transport X"00000000" after 2 ns; - OPB_ABus <= transport X"00000000" after 2 ns; - OPB_select <= '0'; - end procedure opb_write; - ------------------------------------------------------------------------------- - procedure opb_read ( - constant adr : in std_logic_vector(7 downto 2)) is - begin - wait until rising_edge(OPB_Clk); - OPB_ABus <= transport conv_std_logic_vector(conv_integer(adr & "00"), 32) after 2 ns; - OPB_select <= transport '1' after 2 ns; - OPB_RNW <= transport '1' after 2 ns; - OPB_DBus1 <= transport conv_std_logic_vector(0, 32) after 2 ns; - - for i in 0 to 3 loop - wait until rising_edge(OPB_Clk); - if (Sln_xferAck = '1') then - opb_read_data <= Sln_DBus; - exit; - end if; - end loop; -- i - OPB_ABus <= transport X"00000000" after 2 ns; - OPB_select <= transport '0' after 2 ns; - wait until rising_edge(OPB_Clk); - end procedure opb_read; - ------------------------------------------------------------------------------- - procedure spi_transfer( - constant spi_value_out : in std_logic_vector(C_SR_WIDTH-1 downto 0)) is - begin - -- CPHA=0 CPOL=0 C_MSB_FIRST=TRUE - ss_n <= '0'; - for i in C_SR_WIDTH-1 downto 0 loop - mosi <= spi_value_out(i); - wait for spi_clk_period/2; - sclk <= '1'; - spi_value_in(i) <= miso; - wait for spi_clk_period/2; - sclk <= '0'; - end loop; -- i - mosi <= 'Z'; - wait for clk_period/2; - ss_n <= '1'; - wait for clk_period/2; - end procedure spi_transfer; - ------------------------------------------------------------------------------- - - begin - sclk <= '0'; - ss_n <= '1'; - mosi <= 'Z'; - miso_i <= '0'; - - -- init OPB-Slave - OPB_ABus <= (others => '0'); - OPB_BE <= (others => '0'); - OPB_RNW <= '0'; - OPB_select <= '0'; - OPB_seqAddr <= '0'; - - -- int opb_master - MOPB_retry <= '0'; - MOPB_timeout <= '0'; - - OPB_Transfer_Abort <= false; - - -- reset active - OPB_Rst <= '1'; - wait for 100 ns; - -- reset inactive - OPB_Rst <= '0'; - - - for i in 0 to 7 loop - wait until rising_edge(OPB_Clk); - end loop; -- i - - -- write TX Threshold - -- Bit [15:00] Prog Full Threshold - -- Bit [31:16] Prog Empty Threshold - opb_write(C_ADR_TX_THRESH, 16#0005000B#); - - -- write RX Threshold - -- Bit [15:00] Prog Full Threshold - -- Bit [31:16] Prog Empty Threshold - opb_write(C_ADR_RX_THRESH, 16#0006000C#); - - - --------------------------------------------------------------------------- - -- simple transfer 1 byte transmit/receive - if (test(0) = '1') then - -- write transmit data - opb_write(C_ADR_TX_DATA, 16#78#); - - -- enable GDE and TX_EN and RX_EN - opb_write(C_ADR_CTL, 16#7#); - - -- send/receive 8bit - spi_transfer(conv_std_logic_vector(16#B5#, C_SR_WIDTH)); - - -- compare transmit data - assert (spi_value_in = conv_std_logic_vector(16#78#, C_SR_WIDTH)) report "Master Receive Failure" severity failure; - - -- read RX-Data Value - opb_read(C_ADR_RX_DATA); - - -- compare receive data - assert (opb_read_data = conv_std_logic_vector(16#B5#, C_SR_WIDTH)) report "Master Transfer Failure" severity failure; - - end if; - --------------------------------------------------------------------------- - -- transfer 4 bytes and check flags - if (test(1) = '1') then - opb_read(C_ADR_STATUS); - -- only empty Bit and prog_empty set - - temp := (others => '0'); - temp(SPI_SR_Bit_TX_Prog_empty) := '1'; - temp(SPI_SR_Bit_TX_Empty) := '1'; - temp(SPI_SR_Bit_RX_Prog_empty) := '1'; - temp(SPI_SR_Bit_RX_Empty) := '1'; - temp(SPI_SR_Bit_SS_n) := '1'; - - assert (opb_read_data = temp) report "Check Status Bits: TX: 0, RX: 0" severity failure; - - -- write transmit data - opb_write(C_ADR_TX_DATA, 16#01#); - - - opb_read(C_ADR_STATUS); - temp := (others => '0'); - temp(SPI_SR_Bit_TX_Prog_empty) := '1'; - temp(SPI_SR_Bit_RX_Prog_empty) := '1'; - temp(SPI_SR_Bit_RX_Empty) := '1'; - temp(SPI_SR_Bit_SS_n) := '1'; - - assert (opb_read_data = temp) report "Check Status Bits: TX: 1, RX:0" severity failure; - end if; ---------------------------------------------------------------------------- --- write until TX-FIFO asserts full, read until RX-FIFO asserts full, read an --- compare data - if (test(2) = '1') then - for i in 2 to 255 loop - opb_write(C_ADR_TX_DATA, i); - opb_read(C_ADR_STATUS); - -- check TX prog_empty deassert - if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '0') and first(0) = '0') then - assert (false) report "TX prog_emtpy deassert after " & integer'image(i) & " writes." severity warning; - first(0) := '1'; - end if; - - -- check TX prog_full assert - if ((opb_read_data(SPI_SR_Bit_TX_Prog_Full) = '1') and first(1) = '0') then - assert (false) report "TX prog_full assert after " & integer'image(i) & " writes." severity warning; - first(1) := '1'; - end if; - - -- check TX full assert - if ((opb_read_data(SPI_SR_Bit_TX_Full) = '1') and first(2) = '0') then - assert (false) report "TX full assert after " & integer'image(i) & " writes." severity warning; - first(2) := '1'; - exit; - end if; - - end loop; -- i - - --------------------------------------------------------------------------- - first := (others => '0'); - - -- 16 spi transfer - for i in 1 to 255 loop - spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); - opb_read(C_ADR_STATUS); - - ------------------------------------------------------------------------- - -- check TX FIFO flags - -- check TX full deassert - if ((opb_read_data(SPI_SR_Bit_TX_Full) = '0') and first(0) = '0') then - assert (false) report "TX full deassert after " & integer'image(i) & " transfers." severity warning; - first(0) := '1'; - end if; - - -- check TX prog_full deassert - if ((opb_read_data(SPI_SR_Bit_TX_Prog_Full) = '0') and first(1) = '0') then - assert (false) report "TX prog_full deassert after " & integer'image(i) & " transfers." severity warning; - first(1) := '1'; - end if; - - -- check TX prog_emtpy assert - if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '1') and first(2) = '0') then - assert (false) report "TX prog_empty assert after " & integer'image(i) & " transfers." severity warning; - first(2) := '1'; - end if; - - -- check TX emtpy assert - if ((opb_read_data(SPI_SR_Bit_TX_Empty) = '1') and first(3) = '0') then - assert (false) report "TX empty assert after " & integer'image(i) & " transfers." severity warning; - first(3) := '1'; - end if; - - ------------------------------------------------------------------------- - -- check RX FIFO flags - -- check RX empty deassert - if ((opb_read_data(SPI_SR_Bit_RX_Empty) = '0') and first(4) = '0') then - assert (false) report "RX empty deassert after " & integer'image(i) & " transfers." severity warning; - first(4) := '1'; - end if; - - -- check RX prog_empty deassert - if ((opb_read_data(SPI_SR_Bit_RX_Prog_empty) = '0') and first(5) = '0') then - assert (false) report "RX prog_empty deassert after " & integer'image(i) & " transfers." severity warning; - first(5) := '1'; - end if; - - -- check RX prog_full deassert - if ((opb_read_data(SPI_SR_Bit_RX_Prog_Full) = '1') and first(6) = '0') then - assert (false) report "RX prog_full assert after " & integer'image(i) & " transfers." severity warning; - first(6) := '1'; - end if; - - -- check RX full deassert - if ((opb_read_data(SPI_SR_Bit_RX_Full) = '1') and first(7) = '0') then - assert (false) report "RX full assert after " & integer'image(i) & " transfers." severity warning; - first(7) := '1'; - exit; - end if; - end loop; -- i - - - --------------------------------------------------------------------------- - -- read data from fifo - first := (others => '0'); - - for i in 1 to 255 loop - opb_read(C_ADR_RX_DATA); - - -- check data - assert (i = conv_integer(opb_read_data)) report "Read data failure at " & integer'image(i) severity failure; - - opb_read(C_ADR_STATUS); - -- check RX FIFO flags - - -- check RX full deassert - if ((opb_read_data(SPI_SR_Bit_RX_Full) = '0') and first(0) = '0') then - assert (false) report "RX full deassert after " & integer'image(i) & " transfers." severity warning; - first(0) := '1'; - end if; - - -- check RX prog_full deassert - if ((opb_read_data(SPI_SR_Bit_RX_Prog_Full) = '0') and first(1) = '0') then - assert (false) report "RX prog_full deassert after " & integer'image(i) & " transfers." severity warning; - first(1) := '1'; - end if; - - -- check RX prog_empty assert - if ((opb_read_data(SPI_SR_Bit_RX_Prog_empty) = '1') and first(2) = '0') then - assert (false) report "RX prog_empty assert after " & integer'image(i) & " transfers." severity warning; - first(2) := '1'; - end if; - - - -- check RX empty assert - if ((opb_read_data(SPI_SR_Bit_RX_Empty) = '1') and first(3) = '0') then - assert (false) report "RX empty assert after " & integer'image(i) & " transfers." severity warning; - first(3) := '1'; - exit; - end if; - end loop; -- i - end if; - ---------------------------------------------------------------------------- --- check FIFO Reset form underflow condition - if (test(3) = '1') then - -- add transfer to go in underflow condition - spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH)); - - -- reset core (Bit 4) - opb_write(C_ADR_CTL, 16#F#); - - --Check flags - temp := (others => '0'); - temp(SPI_SR_Bit_TX_Prog_empty) := '1'; - temp(SPI_SR_Bit_TX_Empty) := '1'; - temp(SPI_SR_Bit_RX_Prog_empty) := '1'; - temp(SPI_SR_Bit_RX_Empty) := '1'; - temp(SPI_SR_Bit_SS_n) := '1'; - - assert (opb_read_data = temp) report "Status Bits after Reset failure" severity failure; - end if; -------------------------------------------------------------------------------- --- check FIFO Flags IRQ Generation - if (test(4) = '1') then - -- enable all IRQ except Chip select - opb_write(C_ADR_IER, 16#3F#); - -- global irq enable - opb_write(C_ADR_DGIE, 16#1#); - - -- fill transmit buffer - for i in 1 to 255 loop - opb_write(C_ADR_TX_DATA, i); - opb_read(C_ADR_STATUS); - -- check TX full assert - if ((opb_read_data(SPI_SR_Bit_TX_Full) = '1')) then - assert (false) report "TX full assert after " & integer'image(i) & " writes." severity warning; - exit; - end if; - end loop; -- i - - -- SPI-Data Transfers an Check TX Prog_Empty and TX Empty IRQ Generation - for i in 1 to 255 loop - spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH)); - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - if (opb_irq = '1') then - opb_read(C_ADR_ISR); - -- TX Prog Empty - if ((opb_read_data(SPI_ISR_Bit_TX_Prog_Empty) = '1')) then - report "TX prog empty irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 16#1#); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "TX Prog Empty not cleared" severity warning; - end if; - - -- TX EMPTY - if ((opb_read_data(SPI_ISR_Bit_TX_Empty) = '1')) then - report "TX empty irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 16#2#); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "IRQ TX Empty not cleared" severity warning; - end if; - - -- TX Underflow - if ((opb_read_data(SPI_ISR_Bit_TX_Underflow) = '1')) then - report "TX underflow irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 16#4#); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "IRQ TX underflow not cleared" severity warning; - end if; - - -- RX Prog Full - if ((opb_read_data(SPI_ISR_Bit_RX_Prog_Full) = '1')) then - report "RX prog full irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 16#8#); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "RX Prog Full not cleared" severity warning; - end if; - - -- RX Full - if ((opb_read_data(SPI_ISR_Bit_RX_Full) = '1')) then - report "RX full irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 16#10#); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "RX Full not cleared" severity warning; - end if; - - -- RX Overflow - if ((opb_read_data(SPI_ISR_Bit_RX_Overflow) = '1')) then - report "RX overflow irq after " & integer'image(i) & " transfers."; - -- clear_irq - opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_RX_Overflow); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "RX Overflow not cleared" severity warning; - exit; - end if; - - end if; - - end loop; -- i - end if; ---------------------------------------------------------------------------- - -- check slave select irq - if (test(5) = '1') then - -- reset core - opb_write(C_ADR_CTL, 16#F#); - - -- eable Chip select fall/rise IRQ - opb_write(C_ADR_IER, 16#C0#); - - ss_n <= '0'; - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - if (opb_irq = '1') then - opb_read(C_ADR_ISR); - if ((opb_read_data(SPI_ISR_Bit_SS_Fall) = '1')) then - report "SS Fall irq found"; - -- clear_irq - opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Fall); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "SS_Fall IRQ not cleared" severity warning; - end if; - end if; - - ss_n <= '1'; - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - wait until rising_edge(OPB_Clk); - if (opb_irq = '1') then - opb_read(C_ADR_ISR); - if ((opb_read_data(SPI_ISR_Bit_SS_Rise) = '1')) then - report "SS Rise irq found"; - -- clear_irq - opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Rise); - wait until rising_edge(OPB_Clk); - assert (opb_irq = '0') report "SS_Rise IRQ not cleared" severity warning; - end if; - end if; - end if; -------------------------------------------------------------------------------- - -- test opb Master Transfer - if (test(6) = '1') then - - -- enable SPI and CRC - opb_write(C_ADR_CTL, 2**C_OPB_CTL_REG_DGE+2**C_OPB_CTL_REG_TX_EN+2**C_OPB_CTL_REG_RX_EN+2**C_OPB_CTL_REG_CRC_EN); - -- write TX Threshold - -- Bit [15:00] Prog Full Threshold - -- Bit [31:16] Prog Empty Threshold - opb_write(C_ADR_TX_THRESH, 16#0005000B#); - - -- write RX Threshold - -- Bit [15:00] Prog Full Threshold - -- Bit [31:16] Prog Empty Threshold - - -- Pog full must greater or equal than 16(Block Transfer Size)! - opb_write(C_ADR_RX_THRESH, 16#0006000F#); - - -- set transmit buffer Base Adress - opb_write(C_ADR_TX_DMA_ADDR, 16#24000000#); - -- set block number - opb_write(C_ADR_TX_DMA_NUM, 1); - - -- set RX-Buffer base adress - opb_write(C_ADR_RX_DMA_ADDR, 16#25000000#); - -- set block number - opb_write(C_ADR_RX_DMA_NUM, 1); - - -- enable dma write transfer - opb_write(C_ADR_RX_DMA_CTL, 1); - - -- enable dma read transfer - opb_write(C_ADR_TX_DMA_CTL, 1); - - -- time to fill fifo from ram - for i in 0 to 15 loop - wait until rising_edge(OPB_Clk); - end loop; -- i - - -- transfer 16 bytes - -- data block - for i in 0 to 15 loop - spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); - assert (conv_integer(spi_value_in) = i) report "DMA Transfer 1 read data failure" severity failure; - end loop; -- i - - -- crc_block - for i in 16 to 31 loop - spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); - if (i = 16) then - assert (conv_integer(spi_value_in) = 16#e4ea78bf#) report "DMA-block CRC failure" severity failure; - else - assert (conv_integer(spi_value_in) = i) report "DMA Transfer 1 read data failure" severity failure; - end if; - end loop; -- i - - -- wait until RX transfer done - for i in 0 to 15 loop - opb_read(C_ADR_STATUS); - if (opb_read_data(SPI_SR_Bit_RX_DMA_Done) = '1') then - exit; - end if; - wait for 1 us; - end loop; -- i - - -- check TX CRC Register - opb_read(C_ADR_TX_CRC); - assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "TX Register CRC Failure" severity failure; - - -- check RX CRC Register - opb_read(C_ADR_RX_CRC); - assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "RX Register CRC Failure" severity failure; - - wait for 1 us; - end if; ---------------------------------------------------------------------------- - - - - assert false report "Simulation sucessful" severity failure; - end process WaveGen_Proc; - - - -end behavior; - -------------------------------------------------------------------------------- - -configuration opb_spi_slave_tb_behavior_cfg of opb_spi_slave_tb is - for behavior - end for; -end opb_spi_slave_tb_behavior_cfg; - -------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/opb_spi_slave_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/opb_spi_slave_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/opb_spi_slave_tb.vhd (revision 35) @@ -0,0 +1,805 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "opb_spi_slave" +-- Project : +------------------------------------------------------------------------------- +-- File : opb_spi_slave_tb.vhd +-- Author : +-- Company : +-- Created : 2007-09-02 +-- Last update: 2008-05-15 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-09-02 1.0 d.koethe Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +library work; +use work.opb_spi_slave_pack.all; +------------------------------------------------------------------------------- + +entity opb_spi_slave_tb is + generic ( + -- 0: simple transfer 1 byte transmit/receive + -- 1: transfer 4 bytes and check flags + -- 2: write until TX-FIFO asserts full, read until RX-FIFO asserts full, read + -- and compare data + -- 3: check FIFO Reset form underflow condition + -- 4: check FIFO Flags IRQ Generation + -- 5: check Slave select IRQ Generation + -- 6: test opb Master Transfer + test : std_logic_vector(7 downto 0) := "01000000"); +end opb_spi_slave_tb; + +------------------------------------------------------------------------------- + +architecture behavior of opb_spi_slave_tb is + constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + constant C_USER_ID_CODE : integer := 0; + constant C_OPB_AWIDTH : integer := 32; + constant C_OPB_DWIDTH : integer := 32; + constant C_FAMILY : string := "virtex-4"; + -- + -- constant C_SR_WIDTH : integer := 8; + constant C_SR_WIDTH : integer := 32; + -- + constant C_MSB_FIRST : boolean := true; + constant C_CPOL : integer range 0 to 1 := 0; + constant C_PHA : integer range 0 to 1 := 0; + constant C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7; + constant C_DMA_EN : boolean := true; + constant C_CRC_EN : boolean := true; + + component opb_spi_slave + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1; + C_FIFO_SIZE_WIDTH : integer range 4 to 7; + C_DMA_EN : boolean; + C_CRC_EN : boolean); + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + opb_irq : out std_logic); + end component; + + signal OPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); + signal OPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); + signal OPB_Clk : std_logic; + signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal OPB_RNW : std_logic; + signal OPB_Rst : std_logic; + signal OPB_select : std_logic; + signal OPB_seqAddr : std_logic; + signal Sln_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal Sln_errAck : std_logic; + signal Sln_retry : std_logic; + signal Sln_toutSup : std_logic; + signal Sln_xferAck : std_logic; + signal M_request : std_logic; + signal MOPB_MGrant : std_logic; + signal M_busLock : std_logic; + signal M_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); + signal M_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); + signal M_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal M_RNW : std_logic; + signal M_select : std_logic; + signal M_seqAddr : std_logic; + signal MOPB_errAck : std_logic; + signal MOPB_retry : std_logic; + signal MOPB_timeout : std_logic; + signal MOPB_xferAck : std_logic; + signal sclk : std_logic; + signal ss_n : std_logic; + signal mosi : std_logic; + signal miso_o : std_logic; + signal miso_i : std_logic; + signal miso_t : std_logic; + signal opb_irq : std_logic; + +-- testbench + constant clk_period : time := 10 ns; + constant spi_clk_period : time := 50 ns; + + signal miso : std_logic; + + signal opb_read_data : std_logic_vector(31 downto 0); + signal spi_value_in : std_logic_vector(C_SR_WIDTH-1 downto 0); + + signal OPB_Transfer_Abort : boolean; + signal OPB_DBus0 : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal OPB_DBus1 : std_logic_vector(0 to C_OPB_DWIDTH-1); + +begin -- behavior + + -- component instantiation + DUT : opb_spi_slave + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_DMA_EN => C_DMA_EN, + C_CRC_EN => C_CRC_EN) + port map ( + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_Clk => OPB_Clk, + OPB_DBus => OPB_DBus, + OPB_RNW => OPB_RNW, + OPB_Rst => OPB_Rst, + OPB_select => OPB_select, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sln_DBus, + Sln_errAck => Sln_errAck, + Sln_retry => Sln_retry, + Sln_toutSup => Sln_toutSup, + Sln_xferAck => Sln_xferAck, + M_request => M_request, + MOPB_MGrant => MOPB_MGrant, + M_busLock => M_busLock, + M_ABus => M_ABus, + M_BE => M_BE, + M_DBus => M_DBus, + M_RNW => M_RNW, + M_select => M_select, + M_seqAddr => M_seqAddr, + MOPB_errAck => MOPB_errAck, + MOPB_retry => MOPB_retry, + MOPB_timeout => MOPB_timeout, + MOPB_xferAck => MOPB_xferAck, + sclk => sclk, + ss_n => ss_n, + mosi => mosi, + miso_o => miso_o, + miso_i => miso_i, + miso_t => miso_t, + opb_irq => opb_irq); + + + + -- clock generation + process + begin + OPB_Clk <= '0'; + wait for clk_period; + OPB_Clk <= '1'; + wait for clk_period; + end process; + + -- IOB-Buffer + miso <= miso_o when (miso_t = '0') else + 'Z'; + miso_i <= miso; + + -- OPB-Master arbiter/xferack generation + process(OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + MOPB_MGrant <= '0'; + MOPB_xferAck <= '0'; + MOPB_errAck <= '0'; + elsif rising_edge(OPB_Clk) then + -- arbiter + if (M_request = '1') then + MOPB_MGrant <= '1'; + else + MOPB_MGrant <= '0'; + end if; + + -- xfer_Ack + if (M_select = '1') then + if (OPB_Transfer_Abort) then + MOPB_errAck <= '1'; + else + if (conv_integer(M_ABus) >= 16#24000000#) then + if (M_RNW = '1') then + -- read + OPB_DBus0(C_OPB_DWIDTH-C_SR_WIDTH to C_OPB_DWIDTH-1) <= "0000000000000000" & "00" & M_ABus(16 to C_OPB_DWIDTH-3); + end if; + MOPB_xferAck <= not MOPB_xferAck; + end if; + + end if; + + + else + OPB_DBus0 <= (others => '0'); + MOPB_errAck <= '0'; + MOPB_xferAck <= '0'; + end if; + + end if; + end process; + ------------------------------------------------------------------------------- + u1 : for i in 0 to 31 generate + OPB_DBus(i) <= OPB_DBus0(i) or OPB_DBus1(i); + end generate u1; + + ------------------------------------------------------------------------------ + -- waveform generation + WaveGen_Proc : process + variable temp : std_logic_vector(31 downto 0); + variable first : std_logic_vector(7 downto 0) := (others => '0'); + + --------------------------------------------------------------------------- + procedure opb_write ( + constant adr : in std_logic_vector(7 downto 2); + constant data : in integer) is + begin + -- write transmit data + wait until rising_edge(OPB_Clk); + OPB_ABus <= transport conv_std_logic_vector(conv_integer(adr & "00"), 32) after 2 ns; + OPB_select <= transport '1' after 2 ns; + OPB_RNW <= transport '0' after 2 ns; + OPB_DBus1 <= transport conv_std_logic_vector(data, 32) after 2 ns; + + for i in 0 to 3 loop + wait until rising_edge(OPB_Clk); + if (Sln_xferAck = '1') then + exit; + end if; + end loop; -- i + OPB_DBus1 <= transport X"00000000" after 2 ns; + OPB_ABus <= transport X"00000000" after 2 ns; + OPB_select <= '0'; + end procedure opb_write; + ------------------------------------------------------------------------------- + procedure opb_read ( + constant adr : in std_logic_vector(7 downto 2)) is + begin + wait until rising_edge(OPB_Clk); + OPB_ABus <= transport conv_std_logic_vector(conv_integer(adr & "00"), 32) after 2 ns; + OPB_select <= transport '1' after 2 ns; + OPB_RNW <= transport '1' after 2 ns; + OPB_DBus1 <= transport conv_std_logic_vector(0, 32) after 2 ns; + + for i in 0 to 3 loop + wait until rising_edge(OPB_Clk); + if (Sln_xferAck = '1') then + opb_read_data <= Sln_DBus; + exit; + end if; + end loop; -- i + OPB_ABus <= transport X"00000000" after 2 ns; + OPB_select <= transport '0' after 2 ns; + wait until rising_edge(OPB_Clk); + end procedure opb_read; + ------------------------------------------------------------------------------- + procedure spi_transfer( + constant spi_value_out : in std_logic_vector(C_SR_WIDTH-1 downto 0)) is + begin + -- CPHA=0 CPOL=0 C_MSB_FIRST=TRUE + ss_n <= '0'; + for i in C_SR_WIDTH-1 downto 0 loop + mosi <= spi_value_out(i); + wait for spi_clk_period/2; + sclk <= '1'; + spi_value_in(i) <= miso; + wait for spi_clk_period/2; + sclk <= '0'; + end loop; -- i + mosi <= 'Z'; + wait for clk_period/2; + ss_n <= '1'; + wait for clk_period/2; + end procedure spi_transfer; + ------------------------------------------------------------------------------- + + begin + sclk <= '0'; + ss_n <= '1'; + mosi <= 'Z'; + miso_i <= '0'; + + -- init OPB-Slave + OPB_ABus <= (others => '0'); + OPB_BE <= (others => '0'); + OPB_RNW <= '0'; + OPB_select <= '0'; + OPB_seqAddr <= '0'; + + -- int opb_master + MOPB_retry <= '0'; + MOPB_timeout <= '0'; + + OPB_Transfer_Abort <= false; + + -- reset active + OPB_Rst <= '1'; + wait for 100 ns; + -- reset inactive + OPB_Rst <= '0'; + + + for i in 0 to 7 loop + wait until rising_edge(OPB_Clk); + end loop; -- i + + -- write TX Threshold + -- Bit [15:00] Prog Full Threshold + -- Bit [31:16] Prog Empty Threshold + opb_write(C_ADR_TX_THRESH, 16#0005000B#); + + -- write RX Threshold + -- Bit [15:00] Prog Full Threshold + -- Bit [31:16] Prog Empty Threshold + opb_write(C_ADR_RX_THRESH, 16#0006000C#); + + + --------------------------------------------------------------------------- + -- simple transfer 1 byte transmit/receive + if (test(0) = '1') then + -- write transmit data + opb_write(C_ADR_TX_DATA, 16#78#); + + -- enable GDE and TX_EN and RX_EN + opb_write(C_ADR_CTL, 16#7#); + + -- send/receive 8bit + spi_transfer(conv_std_logic_vector(16#B5#, C_SR_WIDTH)); + + -- compare transmit data + assert (spi_value_in = conv_std_logic_vector(16#78#, C_SR_WIDTH)) report "Master Receive Failure" severity failure; + + -- read RX-Data Value + opb_read(C_ADR_RX_DATA); + + -- compare receive data + assert (opb_read_data = conv_std_logic_vector(16#B5#, C_SR_WIDTH)) report "Master Transfer Failure" severity failure; + + end if; + --------------------------------------------------------------------------- + -- transfer 4 bytes and check flags + if (test(1) = '1') then + opb_read(C_ADR_STATUS); + -- only empty Bit and prog_empty set + + temp := (others => '0'); + temp(SPI_SR_Bit_TX_Prog_empty) := '1'; + temp(SPI_SR_Bit_TX_Empty) := '1'; + temp(SPI_SR_Bit_RX_Prog_empty) := '1'; + temp(SPI_SR_Bit_RX_Empty) := '1'; + temp(SPI_SR_Bit_SS_n) := '1'; + + assert (opb_read_data = temp) report "Check Status Bits: TX: 0, RX: 0" severity failure; + + -- write transmit data + opb_write(C_ADR_TX_DATA, 16#01#); + + + opb_read(C_ADR_STATUS); + temp := (others => '0'); + temp(SPI_SR_Bit_TX_Prog_empty) := '1'; + temp(SPI_SR_Bit_RX_Prog_empty) := '1'; + temp(SPI_SR_Bit_RX_Empty) := '1'; + temp(SPI_SR_Bit_SS_n) := '1'; + + assert (opb_read_data = temp) report "Check Status Bits: TX: 1, RX:0" severity failure; + end if; +--------------------------------------------------------------------------- +-- write until TX-FIFO asserts full, read until RX-FIFO asserts full, read an +-- compare data + if (test(2) = '1') then + for i in 2 to 255 loop + opb_write(C_ADR_TX_DATA, i); + opb_read(C_ADR_STATUS); + -- check TX prog_empty deassert + if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '0') and first(0) = '0') then + assert (false) report "TX prog_emtpy deassert after " & integer'image(i) & " writes." severity warning; + first(0) := '1'; + end if; + + -- check TX prog_full assert + if ((opb_read_data(SPI_SR_Bit_TX_Prog_Full) = '1') and first(1) = '0') then + assert (false) report "TX prog_full assert after " & integer'image(i) & " writes." severity warning; + first(1) := '1'; + end if; + + -- check TX full assert + if ((opb_read_data(SPI_SR_Bit_TX_Full) = '1') and first(2) = '0') then + assert (false) report "TX full assert after " & integer'image(i) & " writes." severity warning; + first(2) := '1'; + exit; + end if; + + end loop; -- i + + --------------------------------------------------------------------------- + first := (others => '0'); + + -- 16 spi transfer + for i in 1 to 255 loop + spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); + opb_read(C_ADR_STATUS); + + ------------------------------------------------------------------------- + -- check TX FIFO flags + -- check TX full deassert + if ((opb_read_data(SPI_SR_Bit_TX_Full) = '0') and first(0) = '0') then + assert (false) report "TX full deassert after " & integer'image(i) & " transfers." severity warning; + first(0) := '1'; + end if; + + -- check TX prog_full deassert + if ((opb_read_data(SPI_SR_Bit_TX_Prog_Full) = '0') and first(1) = '0') then + assert (false) report "TX prog_full deassert after " & integer'image(i) & " transfers." severity warning; + first(1) := '1'; + end if; + + -- check TX prog_emtpy assert + if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '1') and first(2) = '0') then + assert (false) report "TX prog_empty assert after " & integer'image(i) & " transfers." severity warning; + first(2) := '1'; + end if; + + -- check TX emtpy assert + if ((opb_read_data(SPI_SR_Bit_TX_Empty) = '1') and first(3) = '0') then + assert (false) report "TX empty assert after " & integer'image(i) & " transfers." severity warning; + first(3) := '1'; + end if; + + ------------------------------------------------------------------------- + -- check RX FIFO flags + -- check RX empty deassert + if ((opb_read_data(SPI_SR_Bit_RX_Empty) = '0') and first(4) = '0') then + assert (false) report "RX empty deassert after " & integer'image(i) & " transfers." severity warning; + first(4) := '1'; + end if; + + -- check RX prog_empty deassert + if ((opb_read_data(SPI_SR_Bit_RX_Prog_empty) = '0') and first(5) = '0') then + assert (false) report "RX prog_empty deassert after " & integer'image(i) & " transfers." severity warning; + first(5) := '1'; + end if; + + -- check RX prog_full deassert + if ((opb_read_data(SPI_SR_Bit_RX_Prog_Full) = '1') and first(6) = '0') then + assert (false) report "RX prog_full assert after " & integer'image(i) & " transfers." severity warning; + first(6) := '1'; + end if; + + -- check RX full deassert + if ((opb_read_data(SPI_SR_Bit_RX_Full) = '1') and first(7) = '0') then + assert (false) report "RX full assert after " & integer'image(i) & " transfers." severity warning; + first(7) := '1'; + exit; + end if; + end loop; -- i + + + --------------------------------------------------------------------------- + -- read data from fifo + first := (others => '0'); + + for i in 1 to 255 loop + opb_read(C_ADR_RX_DATA); + + -- check data + assert (i = conv_integer(opb_read_data)) report "Read data failure at " & integer'image(i) severity failure; + + opb_read(C_ADR_STATUS); + -- check RX FIFO flags + + -- check RX full deassert + if ((opb_read_data(SPI_SR_Bit_RX_Full) = '0') and first(0) = '0') then + assert (false) report "RX full deassert after " & integer'image(i) & " transfers." severity warning; + first(0) := '1'; + end if; + + -- check RX prog_full deassert + if ((opb_read_data(SPI_SR_Bit_RX_Prog_Full) = '0') and first(1) = '0') then + assert (false) report "RX prog_full deassert after " & integer'image(i) & " transfers." severity warning; + first(1) := '1'; + end if; + + -- check RX prog_empty assert + if ((opb_read_data(SPI_SR_Bit_RX_Prog_empty) = '1') and first(2) = '0') then + assert (false) report "RX prog_empty assert after " & integer'image(i) & " transfers." severity warning; + first(2) := '1'; + end if; + + + -- check RX empty assert + if ((opb_read_data(SPI_SR_Bit_RX_Empty) = '1') and first(3) = '0') then + assert (false) report "RX empty assert after " & integer'image(i) & " transfers." severity warning; + first(3) := '1'; + exit; + end if; + end loop; -- i + end if; + +--------------------------------------------------------------------------- +-- check FIFO Reset form underflow condition + if (test(3) = '1') then + -- add transfer to go in underflow condition + spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH)); + + -- reset core (Bit 4) + opb_write(C_ADR_CTL, 16#F#); + + --Check flags + temp := (others => '0'); + temp(SPI_SR_Bit_TX_Prog_empty) := '1'; + temp(SPI_SR_Bit_TX_Empty) := '1'; + temp(SPI_SR_Bit_RX_Prog_empty) := '1'; + temp(SPI_SR_Bit_RX_Empty) := '1'; + temp(SPI_SR_Bit_SS_n) := '1'; + + assert (opb_read_data = temp) report "Status Bits after Reset failure" severity failure; + end if; +------------------------------------------------------------------------------- +-- check FIFO Flags IRQ Generation + if (test(4) = '1') then + -- enable all IRQ except Chip select + opb_write(C_ADR_IER, 16#3F#); + -- global irq enable + opb_write(C_ADR_DGIE, 16#1#); + + -- fill transmit buffer + for i in 1 to 255 loop + opb_write(C_ADR_TX_DATA, i); + opb_read(C_ADR_STATUS); + -- check TX full assert + if ((opb_read_data(SPI_SR_Bit_TX_Full) = '1')) then + assert (false) report "TX full assert after " & integer'image(i) & " writes." severity warning; + exit; + end if; + end loop; -- i + + -- SPI-Data Transfers an Check TX Prog_Empty and TX Empty IRQ Generation + for i in 1 to 255 loop + spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH)); + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + if (opb_irq = '1') then + opb_read(C_ADR_ISR); + -- TX Prog Empty + if ((opb_read_data(SPI_ISR_Bit_TX_Prog_Empty) = '1')) then + report "TX prog empty irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 16#1#); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "TX Prog Empty not cleared" severity warning; + end if; + + -- TX EMPTY + if ((opb_read_data(SPI_ISR_Bit_TX_Empty) = '1')) then + report "TX empty irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 16#2#); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "IRQ TX Empty not cleared" severity warning; + end if; + + -- TX Underflow + if ((opb_read_data(SPI_ISR_Bit_TX_Underflow) = '1')) then + report "TX underflow irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 16#4#); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "IRQ TX underflow not cleared" severity warning; + end if; + + -- RX Prog Full + if ((opb_read_data(SPI_ISR_Bit_RX_Prog_Full) = '1')) then + report "RX prog full irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 16#8#); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "RX Prog Full not cleared" severity warning; + end if; + + -- RX Full + if ((opb_read_data(SPI_ISR_Bit_RX_Full) = '1')) then + report "RX full irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 16#10#); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "RX Full not cleared" severity warning; + end if; + + -- RX Overflow + if ((opb_read_data(SPI_ISR_Bit_RX_Overflow) = '1')) then + report "RX overflow irq after " & integer'image(i) & " transfers."; + -- clear_irq + opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_RX_Overflow); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "RX Overflow not cleared" severity warning; + exit; + end if; + + end if; + + end loop; -- i + end if; +--------------------------------------------------------------------------- + -- check slave select irq + if (test(5) = '1') then + -- reset core + opb_write(C_ADR_CTL, 16#F#); + + -- eable Chip select fall/rise IRQ + opb_write(C_ADR_IER, 16#C0#); + + ss_n <= '0'; + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + if (opb_irq = '1') then + opb_read(C_ADR_ISR); + if ((opb_read_data(SPI_ISR_Bit_SS_Fall) = '1')) then + report "SS Fall irq found"; + -- clear_irq + opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Fall); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "SS_Fall IRQ not cleared" severity warning; + end if; + end if; + + ss_n <= '1'; + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + wait until rising_edge(OPB_Clk); + if (opb_irq = '1') then + opb_read(C_ADR_ISR); + if ((opb_read_data(SPI_ISR_Bit_SS_Rise) = '1')) then + report "SS Rise irq found"; + -- clear_irq + opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Rise); + wait until rising_edge(OPB_Clk); + assert (opb_irq = '0') report "SS_Rise IRQ not cleared" severity warning; + end if; + end if; + end if; +------------------------------------------------------------------------------- + -- test opb Master Transfer + if (test(6) = '1') then + + -- enable SPI and CRC + opb_write(C_ADR_CTL, 2**C_OPB_CTL_REG_DGE+2**C_OPB_CTL_REG_TX_EN+2**C_OPB_CTL_REG_RX_EN+2**C_OPB_CTL_REG_CRC_EN); + -- write TX Threshold + -- Bit [15:00] Prog Full Threshold + -- Bit [31:16] Prog Empty Threshold + opb_write(C_ADR_TX_THRESH, 16#0005000B#); + + -- write RX Threshold + -- Bit [15:00] Prog Full Threshold + -- Bit [31:16] Prog Empty Threshold + + -- Pog full must greater or equal than 16(Block Transfer Size)! + opb_write(C_ADR_RX_THRESH, 16#0006000F#); + + -- set transmit buffer Base Adress + opb_write(C_ADR_TX_DMA_ADDR, 16#24000000#); + -- set block number + opb_write(C_ADR_TX_DMA_NUM, 1); + + -- set RX-Buffer base adress + opb_write(C_ADR_RX_DMA_ADDR, 16#25000000#); + -- set block number + opb_write(C_ADR_RX_DMA_NUM, 1); + + -- enable dma write transfer + opb_write(C_ADR_RX_DMA_CTL, 1); + + -- enable dma read transfer + opb_write(C_ADR_TX_DMA_CTL, 1); + + -- time to fill fifo from ram + for i in 0 to 15 loop + wait until rising_edge(OPB_Clk); + end loop; -- i + + -- transfer 16 bytes + -- data block + for i in 0 to 15 loop + spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); + assert (conv_integer(spi_value_in) = i) report "DMA Transfer 1 read data failure" severity failure; + end loop; -- i + + -- crc_block + for i in 16 to 31 loop + spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH)); + if (i = 16) then + assert (conv_integer(spi_value_in) = 16#e4ea78bf#) report "DMA-block CRC failure" severity failure; + else + assert (conv_integer(spi_value_in) = i) report "DMA Transfer 1 read data failure" severity failure; + end if; + end loop; -- i + + -- wait until RX transfer done + for i in 0 to 15 loop + opb_read(C_ADR_STATUS); + if (opb_read_data(SPI_SR_Bit_RX_DMA_Done) = '1') then + exit; + end if; + wait for 1 us; + end loop; -- i + + -- check TX CRC Register + opb_read(C_ADR_TX_CRC); + assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "TX Register CRC Failure" severity failure; + + -- check RX CRC Register + opb_read(C_ADR_RX_CRC); + assert (conv_integer(opb_read_data) = 16#e4ea78bf#) report "RX Register CRC Failure" severity failure; + + wait for 1 us; + end if; +--------------------------------------------------------------------------- + + + + assert false report "Simulation sucessful" severity failure; + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration opb_spi_slave_tb_behavior_cfg of opb_spi_slave_tb is + for behavior + end for; +end opb_spi_slave_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/crc_core_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/crc_core_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/crc_core_tb.vhd (revision 35) @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "crc_core" +-- Project : +------------------------------------------------------------------------------- +-- File : crc_core_tb.vhd +-- Author : +-- Company : +-- Created : 2008-03-23 +-- Last update: 2008-03-23 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2008 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2008-03-23 1.0 d.koethe Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +------------------------------------------------------------------------------- + +entity crc_core_tb is + generic ( + C_SR_WIDTH : integer := 32); + +end crc_core_tb; + +------------------------------------------------------------------------------- + +architecture behavior of crc_core_tb is + component crc_core + generic ( + C_SR_WIDTH : integer); + port ( + rst : in std_logic; + opb_clk : in std_logic; + crc_en : in std_logic; + crc_clr : in std_logic; + opb_m_last_block : in std_logic; + fifo_rx_en : in std_logic; + fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); + fifo_tx_en : in std_logic; + fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + tx_crc_insert : out std_logic; + opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + signal rst : std_logic; + signal opb_clk : std_logic; + signal crc_en : std_logic; + signal crc_clr : std_logic; + signal opb_m_last_block : std_logic; + signal fifo_rx_en : std_logic; + signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal fifo_tx_en : std_logic; + signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal tx_crc_insert : std_logic; + signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); + + constant C_CLK_PERIOD : time := 10 ns; + +begin -- behavior + + -- component instantiation + DUT : crc_core + generic map ( + C_SR_WIDTH => C_SR_WIDTH) + port map ( + rst => rst, + opb_clk => opb_clk, + crc_en => crc_en, + crc_clr => crc_clr, + opb_m_last_block => opb_m_last_block, + fifo_rx_en => fifo_rx_en, + fifo_rx_data => fifo_rx_data, + opb_rx_crc_value => opb_rx_crc_value, + fifo_tx_en => fifo_tx_en, + fifo_tx_data => fifo_tx_data, + tx_crc_insert => tx_crc_insert, + opb_tx_crc_value => opb_tx_crc_value); + + -- clock generation + process + begin + opb_clk <= '0'; + wait for C_CLK_PERIOD/2; + opb_clk <= '1'; + wait for C_CLK_PERIOD/2; + end process; + + -- waveform generation + WaveGen_Proc : process + begin + rst <= '1'; + crc_en <= '0'; + crc_clr <= '0'; + opb_m_last_block <= '0'; + fifo_rx_en <= '0'; + fifo_rx_data <= (others => '0'); + fifo_tx_en <= '0'; + fifo_tx_data <= (others => '0'); + wait for 100 ns; + rst <= '0'; + + -- clear crc + wait until rising_edge(opb_clk); + crc_clr <= '1'; + wait until rising_edge(opb_clk); + crc_clr <= '0'; + crc_en <= '1'; + + + + -- generate data block + opb_m_last_block <= '0'; + + for i in 0 to 15 loop + wait until rising_edge(opb_clk); + -- RX + fifo_rx_en <= '1'; + fifo_rx_data <= conv_std_logic_vector(i, fifo_rx_data'length); + -- TX + fifo_tx_en <= '1'; + fifo_tx_data <= conv_std_logic_vector(i, fifo_tx_data'length); + end loop; -- i + wait until rising_edge(opb_clk); + fifo_rx_en <= '0'; + fifo_rx_data <= (others => '0'); + fifo_tx_en <= '0'; + fifo_tx_data <= (others => '0'); + wait until rising_edge(opb_clk); + + if (C_SR_WIDTH = 32) then + assert (conv_integer(opb_rx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; + assert (conv_integer(opb_tx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; + end if; + + + -- generate crc_block + opb_m_last_block <= '1'; + + for i in 0 to 15 loop + wait until rising_edge(opb_clk); + -- RX + fifo_rx_en <= '1'; + fifo_rx_data <= (others => '1'); + -- TX + fifo_tx_en <= '1'; + fifo_tx_data <= (others => '1'); + end loop; -- i + wait until rising_edge(opb_clk); + fifo_rx_en <= '0'; + fifo_rx_data <= (others => '0'); + fifo_tx_en <= '0'; + fifo_tx_data <= (others => '0'); + wait until rising_edge(opb_clk); + -- same value, no changes in last block + if (C_SR_WIDTH = 32) then + assert (conv_integer(opb_rx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; + assert (conv_integer(opb_tx_crc_value) = 16#eb99fa90#) report"RX_CRC_Failure" severity failure; + end if; + opb_m_last_block <= '0'; + + + wait for 100 ns; + + + + assert false report "Simulation Sucessful" severity failure; + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration crc_core_tb_behavior_cfg of crc_core_tb is + for behavior + end for; +end crc_core_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/opb_m_if_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/opb_m_if_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/opb_m_if_tb.vhd (revision 35) @@ -0,0 +1,313 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "opb_m_if" +-- Project : +------------------------------------------------------------------------------- +-- File : opb_m_if_tb.vhd +-- Author : +-- Company : +-- Created : 2007-10-29 +-- Last update: 2007-11-12 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-10-29 1.0 d.koethe Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() +------------------------------------------------------------------------------- + +entity opb_m_if_tb is + +end opb_m_if_tb; + +------------------------------------------------------------------------------- + +architecture behavior of opb_m_if_tb is + + component opb_m_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1; + C_FIFO_SIZE_WIDTH : integer range 4 to 7); + port ( + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + opb_m_tx_req : in std_logic; + opb_m_tx_en : out std_logic; + opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_tx_dma_ctl : in std_logic_vector(0 downto 0); + opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_num : in std_logic_vector(15 downto 0); + opb_tx_dma_done : out std_logic; + opb_m_rx_req : in std_logic; + opb_m_rx_en : out std_logic; + opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_dma_ctl : in std_logic_vector(0 downto 0); + opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_num : in std_logic_vector(15 downto 0); + opb_rx_dma_done : out std_logic); + end component; + + + + -- component generics + constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + constant C_USER_ID_CODE : integer := 0; + constant C_OPB_AWIDTH : integer := 32; + constant C_OPB_DWIDTH : integer := 32; + constant C_FAMILY : string := "virtex-4"; + constant C_SR_WIDTH : integer := 8; + constant C_MSB_FIRST : boolean := true; + constant C_CPOL : integer range 0 to 1 := 0; + constant C_PHA : integer range 0 to 1 := 0; + constant C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7; + + -- component ports + signal OPB_Clk : std_logic; + signal OPB_Rst : std_logic; + signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal M_request : std_logic; + signal MOPB_MGrant : std_logic; + signal M_busLock : std_logic; + signal M_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); + signal M_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); + signal M_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal M_RNW : std_logic; + signal M_select : std_logic; + signal M_seqAddr : std_logic; + signal MOPB_errAck : std_logic; + signal MOPB_retry : std_logic; + signal MOPB_timeout : std_logic; + signal MOPB_xferAck : std_logic; + signal opb_m_tx_req : std_logic; + signal opb_m_tx_en : std_logic; + signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_num : std_logic_vector(15 downto 0); + signal opb_tx_dma_done : std_logic; + signal opb_m_rx_req : std_logic; + signal opb_m_rx_en : std_logic; + signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_num : std_logic_vector(15 downto 0); + signal opb_rx_dma_done : std_logic; + + signal opb_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_tx_data : std_logic_vector(0 to C_SR_WIDTH-1); + +begin -- behavior + + -- component instantiation + opb_m_if_1: opb_m_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) + port map ( + OPB_Clk => OPB_Clk, + OPB_Rst => OPB_Rst, + OPB_DBus => OPB_DBus, + M_request => M_request, + MOPB_MGrant => MOPB_MGrant, + M_busLock => M_busLock, + M_ABus => M_ABus, + M_BE => M_BE, + M_DBus => M_DBus, + M_RNW => M_RNW, + M_select => M_select, + M_seqAddr => M_seqAddr, + MOPB_errAck => MOPB_errAck, + MOPB_retry => MOPB_retry, + MOPB_timeout => MOPB_timeout, + MOPB_xferAck => MOPB_xferAck, + opb_m_tx_req => opb_m_tx_req, + opb_m_tx_en => opb_m_tx_en, + opb_m_tx_data => opb_m_tx_data, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_num => opb_tx_dma_num, + opb_tx_dma_done => opb_tx_dma_done, + opb_m_rx_req => opb_m_rx_req, + opb_m_rx_en => opb_m_rx_en, + opb_m_rx_data => opb_m_rx_data, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_num => opb_rx_dma_num, + opb_rx_dma_done => opb_rx_dma_done); + + + -- clock generation + process + begin + OPB_Clk <= '0'; + wait for 10 ns; + OPB_Clk <= '1'; + wait for 10 ns; + end process; + + + -- arbiter/xferack + process(OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + MOPB_MGrant <= '0'; + MOPB_xferAck <= '0'; + opb_tx_data <= (others => '0'); + elsif rising_edge(OPB_Clk) then + -- arbiter + if (M_request = '1') then + MOPB_MGrant <= '1'; + else + MOPB_MGrant <= '0'; + end if; + + -- xfer_Ack + if (M_select = '1') then + if (M_RNW = '1' and MOPB_xferAck = '1') then + opb_tx_data <= opb_tx_data+1; + end if; + MOPB_xferAck <= not MOPB_xferAck; + else + opb_tx_data <= (others => '0'); + MOPB_xferAck <= '0'; + end if; + end if; + end process; + + OPB_DBus( 0 to C_OPB_DWIDTH-C_SR_WIDTH-1) <= (others => '0'); + OPB_DBus(C_OPB_DWIDTH-C_SR_WIDTH to C_OPB_DWIDTH-1) <= opb_tx_data; + + -- rx fifo emulation + process(OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + opb_rx_data <= (others => '0'); + elsif rising_edge(OPB_Clk) then + if (opb_m_rx_en = '1') then + opb_rx_data <= opb_rx_data+1; + end if; + end if; + end process; + + opb_m_rx_data <= opb_rx_data; + + + -- waveform generation + WaveGen_Proc : process + begin + -- reset active + OPB_Rst <= '1'; + + MOPB_errAck <= '0'; + MOPB_retry <= '0'; + MOPB_timeout <= '0'; + + opb_m_tx_req <= '0'; + opb_tx_dma_ctl <= (others => '0'); + opb_tx_dma_addr <= (others => '0'); + opb_m_rx_req <= '0'; + opb_rx_dma_ctl <= (others => '0'); + opb_rx_dma_addr <= (others => '0'); + + + + + wait for 100 ns; + -- remove rst + OPB_Rst <= '0'; + --------------------------------------------------------------------------- + -- write transfer + opb_tx_dma_addr <= conv_std_logic_vector(16#24000000#, 32); + + wait until rising_edge(OPB_Clk); + opb_tx_dma_ctl(0) <= '1'; + + + wait until rising_edge(OPB_Clk); + opb_m_tx_req <= '1'; -- asssert almost full flag + wait until rising_edge(OPB_Clk); + opb_m_tx_req <= '0'; -- deassert almost full flag + + wait for 1 us; + + --------------------------------------------------------------------------- + -- read transfer + opb_rx_dma_addr <= conv_std_logic_vector(16#25000000#, 32); + + wait until rising_edge(OPB_Clk); + opb_rx_dma_ctl(0) <= '1'; + + -- first transfer + wait until rising_edge(OPB_Clk); + opb_m_rx_req <= '1'; -- asssert almost full flag + wait until rising_edge(OPB_Clk); + opb_m_rx_req <= '0'; -- deassert almost full flag + wait for 1 us; + + -- second transfer + wait until rising_edge(OPB_Clk); + opb_m_rx_req <= '1'; -- asssert almost full flag + wait until rising_edge(OPB_Clk); + opb_m_rx_req <= '0'; -- deassert almost full flag + wait for 1 us; + --------------------------------------------------------------------------- + + + assert false report "Simulation Sucessful" severity failure; + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration opb_m_if_tb_behavior_cfg of opb_m_if_tb is + for behavior + end for; +end opb_m_if_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/images-body.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/images-body.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/images-body.vhd (revision 35) @@ -0,0 +1,200 @@ +-------------------------------------------------------------------------- +-- +-- Copyright (C) 1993, Peter J. Ashenden +-- Mail: Dept. Computer Science +-- University of Adelaide, SA 5005, Australia +-- e-mail: petera@cs.adelaide.edu.au +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 1, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +-- +-------------------------------------------------------------------------- +-- +-- $RCSfile: images-body.vhd,v $ $Revision: 1.1 $ $Date: 2007-11-30 20:22:01 $ +-- +-------------------------------------------------------------------------- +-- +-- Images package body. +-- +-- Functions that return the string image of values. +-- Each image is a correctly formed literal according to the +-- rules of VHDL-93. +-- +-------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package images is + function image ( + constant bv : std_logic_vector) + return string; +end images; + +package body images is + + + -- Image of bit vector as binary bit string literal + -- (in the format B"...") + -- Length of result is bv'length + 3 + + function image (bv : in bit_vector) return string is + + alias bv_norm : bit_vector(1 to bv'length) is bv; + variable result : string(1 to bv'length + 3); + + begin + result(1) := 'B'; + result(2) := '"'; + for index in bv_norm'range loop + if bv_norm(index) = '0' then + result(index + 2) := '0'; + else + result(index + 2) := '1'; + end if; + end loop; + result(bv'length + 3) := '"'; + return result; + end image; +------------------------------------------------------------------------------- + -- Image of bit vector as binary bit string literal + -- (in the format B"...") + -- Length of result is bv'length + 3 + + function image (bv : in std_logic_vector) return string is + + alias bv_norm : std_logic_vector(1 to bv'length) is bv; + variable result : string(1 to bv'length + 3); + + begin + result(1) := 'B'; + result(2) := '"'; + for index in bv_norm'range loop + if bv_norm(index) = '0' then + result(index + 2) := '0'; + else + result(index + 2) := '1'; + end if; + end loop; + result(bv'length + 3) := '"'; + return result; + end image; + + + + ---------------------------------------------------------------- + + -- Image of bit vector as octal bit string literal + -- (in the format O"...") + -- Length of result is (bv'length+2)/3 + 3 + + function image_octal (bv : in bit_vector) return string is + + constant nr_digits : natural := (bv'length + 2) / 3; + variable result : string(1 to nr_digits + 3); + variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0'); + variable three_bits : bit_vector(0 to 2); + variable digit : character; + + begin + result(1) := 'O'; + result(2) := '"'; + bits(bits'right - bv'length + 1 to bits'right) := bv; + for index in 0 to nr_digits - 1 loop + three_bits := bits(3*index to 3*index + 2); + case three_bits is + when b"000" => + digit := '0'; + when b"001" => + digit := '1'; + when b"010" => + digit := '2'; + when b"011" => + digit := '3'; + when b"100" => + digit := '4'; + when b"101" => + digit := '5'; + when b"110" => + digit := '6'; + when b"111" => + digit := '7'; + end case; + result(index + 3) := digit; + end loop; + result(nr_digits + 3) := '"'; + return result; + end image_octal; + + ---------------------------------------------------------------- + + -- Image of bit vector as hex bit string literal + -- (in the format X"...") + -- Length of result is (bv'length+3)/4 + 3 + + function image_hex (bv : in bit_vector) return string is + + constant nr_digits : natural := (bv'length + 3) / 4; + variable result : string(1 to nr_digits + 3); + variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0'); + variable four_bits : bit_vector(0 to 3); + variable digit : character; + + begin + result(1) := 'X'; + result(2) := '"'; + bits(bits'right - bv'length + 1 to bits'right) := bv; + for index in 0 to nr_digits - 1 loop + four_bits := bits(4*index to 4*index + 3); + case four_bits is + when b"0000" => + digit := '0'; + when b"0001" => + digit := '1'; + when b"0010" => + digit := '2'; + when b"0011" => + digit := '3'; + when b"0100" => + digit := '4'; + when b"0101" => + digit := '5'; + when b"0110" => + digit := '6'; + when b"0111" => + digit := '7'; + when b"1000" => + digit := '8'; + when b"1001" => + digit := '9'; + when b"1010" => + digit := 'A'; + when b"1011" => + digit := 'B'; + when b"1100" => + digit := 'C'; + when b"1101" => + digit := 'D'; + when b"1110" => + digit := 'E'; + when b"1111" => + digit := 'F'; + end case; + result(index + 3) := digit; + end loop; + result(nr_digits + 3) := '"'; + return result; + end image_hex; + + +end images; Index: spi_slave/trunk/bench/vhdl/bin2gray_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/bin2gray_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/bin2gray_tb.vhd (revision 35) @@ -0,0 +1,118 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "bin2grey" +-- Project : +------------------------------------------------------------------------------- +-- File : bin2gray_tb.vhd +-- Author : +-- Company : +-- Created : 2007-10-22 +-- Last update: 2007-10-22 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-10-22 1.0 d.koethe Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +------------------------------------------------------------------------------- + +entity bin2gray_tb is + +end bin2gray_tb; + +------------------------------------------------------------------------------- + +architecture behavior of bin2gray_tb is + + component gray2bin + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); + end component; + + component bin2gray + generic ( + width : integer); + port ( + in_bin : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + component gray_adder + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + -- component generics + constant width : integer := 4; + + -- component ports + signal in_bin : std_logic_vector(width-1 downto 0); + signal out_gray : std_logic_vector(width-1 downto 0); + signal out_bin : std_logic_vector(width-1 downto 0); + signal out_gray_add_one : std_logic_vector(width-1 downto 0); + +begin -- behavior + + -- component instantiation + bin2gray_1 : bin2gray + generic map ( + width => width) + port map ( + in_bin => in_bin, + out_gray => out_gray); + + + gray2bin_1 : gray2bin + generic map ( + width => width) + port map ( + in_gray => out_gray, + out_bin => out_bin); + + + gray_adder_1 : gray_adder + generic map ( + width => width) + port map ( + in_gray => out_gray, + out_gray => out_gray_add_one); + + + -- waveform generation + WaveGen_Proc : process + begin + for i in 0 to 2**width-1 loop + in_bin <= conv_std_logic_vector(i, width); + wait for 10 ns; + + end loop; -- i + assert false report "Simulation Sucessful" severity failure; + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration bin2gray_tb_behavior_cfg of bin2gray_tb is + for behavior + end for; +end bin2gray_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/rx_fifo_emu.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/rx_fifo_emu.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/rx_fifo_emu.vhd (revision 35) @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity rx_fifo_emu is + + generic ( + C_SR_WIDTH : integer; + C_RX_CMP_VALUE : integer); + + port ( + rst : in std_logic; + rx_clk : in std_logic; + rx_en : in std_logic; + rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0)); + +end rx_fifo_emu; + + +architecture behavior of rx_fifo_emu is + + signal rx_data_cmp : std_logic_vector(C_SR_WIDTH-1 downto 0) := conv_std_logic_vector(C_RX_CMP_VALUE,C_SR_WIDTH); + +begin -- behavior + process(rst, rx_clk) + begin + if (rst = '1') then + elsif rising_edge(rx_clk) then + if (rx_en = '1') then + assert (rx_data = rx_data_cmp) report "RX-FIFO Compare Error" severity warning; + rx_data_cmp <= rx_data_cmp+1; + end if; + end if; + end process; +end behavior; Index: spi_slave/trunk/bench/vhdl/opb_if_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/opb_if_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/opb_if_tb.vhd (revision 35) @@ -0,0 +1,252 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "opb_if" +-- Project : +------------------------------------------------------------------------------- +-- File : opb_if_tb.vhd +-- Author : +-- Company : +-- Created : 2007-09-01 +-- Last update: 2007-11-12 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-09-01 1.0 d.koethe Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.opb_spi_slave_pack.all; + +------------------------------------------------------------------------------- + +entity opb_if_tb is + +end opb_if_tb; + +------------------------------------------------------------------------------- + +architecture behavior of opb_if_tb is + + component opb_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_DMA_EN : boolean); + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + opb_s_tx_en : out std_logic; + opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_s_rx_en : out std_logic; + opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); + opb_dgie : out std_logic; + opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_ctl : out std_logic_vector(0 downto 0); + opb_tx_dma_num : out std_logic_vector(15 downto 0); + opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_ctl : out std_logic_vector(0 downto 0); + opb_rx_dma_num : out std_logic_vector(15 downto 0)); + end component; + + constant C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + constant C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + constant C_USER_ID_CODE : integer := 3; + constant C_OPB_AWIDTH : integer := 32; + constant C_OPB_DWIDTH : integer := 32; + constant C_FAMILY : string := "virtex-4"; + constant C_SR_WIDTH : integer := 8; + constant C_FIFO_SIZE_WIDTH : integer := 4; + constant C_DMA_EN : boolean := true; + + + signal OPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1); + signal OPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1); + signal OPB_Clk : std_logic; + signal OPB_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal OPB_RNW : std_logic; + signal OPB_Rst : std_logic; + signal OPB_select : std_logic; + signal OPB_seqAddr : std_logic; + signal Sln_DBus : std_logic_vector(0 to C_OPB_DWIDTH-1); + signal Sln_errAck : std_logic; + signal Sln_retry : std_logic; + signal Sln_toutSup : std_logic; + signal Sln_xferAck : std_logic; + signal opb_s_tx_en : std_logic; + signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_s_rx_en : std_logic; + signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); + signal opb_dgie : std_logic; + signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_tx_dma_num : std_logic_vector(15 downto 0); + signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_rx_dma_num : std_logic_vector(15 downto 0); + + constant clk_period : time := 25 ns; + +begin -- behavior + + -- component instantiation + DUT: opb_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_DMA_EN => C_DMA_EN) + port map ( + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_Clk => OPB_Clk, + OPB_DBus => OPB_DBus, + OPB_RNW => OPB_RNW, + OPB_Rst => OPB_Rst, + OPB_select => OPB_select, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sln_DBus, + Sln_errAck => Sln_errAck, + Sln_retry => Sln_retry, + Sln_toutSup => Sln_toutSup, + Sln_xferAck => Sln_xferAck, + opb_s_tx_en => opb_s_tx_en, + opb_s_tx_data => opb_s_tx_data, + opb_s_rx_en => opb_s_rx_en, + opb_s_rx_data => opb_s_rx_data, + opb_ctl_reg => opb_ctl_reg, + tx_thresh => tx_thresh, + rx_thresh => rx_thresh, + opb_fifo_flg => opb_fifo_flg, + opb_dgie => opb_dgie, + opb_ier => opb_ier, + opb_isr => opb_isr, + opb_isr_clr => opb_isr_clr, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_num => opb_tx_dma_num, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_num => opb_rx_dma_num); + + -- clock generation + process + begin + OPB_Clk <= '0'; + wait for clk_period; + OPB_Clk <= '1'; + wait for clk_period; + end process; + + -- waveform generation + WaveGen_Proc : process + begin + OPB_ABus <= (others => '0'); + OPB_BE <= (others => '0'); + OPB_DBus <= (others => '0'); + OPB_RNW <= '0'; + OPB_select <= '0'; + OPB_seqAddr <= '0'; + -- reset active + OPB_Rst <= '1'; + wait for 100 ns; + -- reset inactive + OPB_Rst <= '0'; + + + -- write acess + wait until rising_edge(OPB_Clk); + OPB_ABus <= X"10000000"; + OPB_select <= '1'; + OPB_RNW <= '0'; + OPB_DBus <= X"12345678"; + + for i in 0 to 3 loop + wait until rising_edge(OPB_Clk); + if (Sln_xferAck = '1') then + exit; + end if; + end loop; -- i + OPB_DBus <= X"00000000"; + OPB_ABus <= X"00000000"; + OPB_select <= '0'; + + + -- read acess + wait until rising_edge(OPB_Clk); + OPB_ABus <= X"10000000"; + OPB_select <= '1'; + OPB_RNW <= '1'; + + for i in 0 to 3 loop + wait until rising_edge(OPB_Clk); + if (Sln_xferAck = '1') then + exit; + end if; + end loop; -- i + OPB_ABus <= X"00000000"; + OPB_select <= '0'; + + + + wait for 100 ns; + assert false report "Simulation sucessful" severity failure; + + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration opb_if_tb_behavior_cfg of opb_if_tb is + for behavior + end for; +end opb_if_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/tx_fifo_emu.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/tx_fifo_emu.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/tx_fifo_emu.vhd (revision 35) @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity tx_fifo_emu is + generic ( + C_SR_WIDTH : integer := 8; + C_TX_CMP_VALUE : integer); + port ( + rst : in std_logic; + tx_clk : in std_logic; + tx_en : in std_logic; + tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + +end tx_fifo_emu; + +architecture behavior of tx_fifo_emu is + + signal tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + + +begin -- behavior + + tx_data <= tx_data_int; + + process(rst, tx_clk) + begin + if (rst = '1') then + tx_data_int <= conv_std_logic_vector(C_TX_CMP_VALUE,C_SR_WIDTH); + elsif rising_edge(tx_clk) then + if (tx_en = '1') then + tx_data_int <= tx_data_int + 1; + end if; + end if; + end process; + +end behavior; Index: spi_slave/trunk/bench/vhdl/shift_register_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/shift_register_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/shift_register_tb.vhd (revision 35) @@ -0,0 +1,411 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "shift_register" +-- Project : +------------------------------------------------------------------------------- +-- File : shift_register_tb.vhd +-- Author : +-- Company : +-- Created : 2007-08-24 +-- Last update: 2007-11-12 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-08-24 1.0 d.koethe Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +library work; +use work.opb_spi_slave_pack.all; + +------------------------------------------------------------------------------- + +entity shift_register_tb is + +end shift_register_tb; + +------------------------------------------------------------------------------- + +architecture behavior of shift_register_tb is + + component shift_register + generic ( + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1); + port ( + rst : in std_logic; + opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + sr_tx_clk : out std_logic; + sr_tx_en : out std_logic; + sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + sr_rx_clk : out std_logic; + sr_rx_en : out std_logic; + sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + + component tx_fifo_emu + generic ( + C_SR_WIDTH : integer; + C_TX_CMP_VALUE : integer); + port ( + rst : in std_logic; + tx_clk : in std_logic; + tx_en : in std_logic; + tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + component rx_fifo_emu + generic ( + C_SR_WIDTH : integer; + C_RX_CMP_VALUE : integer); + port ( + rst : in std_logic; + rx_clk : in std_logic; + rx_en : in std_logic; + rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + + constant C_NUM_TESTS : integer := 3; + + -- component generics + constant C_SR_WIDTH : integer := 8; + type C_MSB_FIRST_t is array (0 to C_NUM_TESTS) of boolean; + constant C_MSB_FIRST : C_MSB_FIRST_t := (true, false, true, false); + type C_CPOL_t is array (0 to C_NUM_TESTS) of integer range 0 to 1; + constant C_CPOL : C_CPOL_t := (0, 0, 1, 1); + type C_PHA_t is array (0 to C_NUM_TESTS) of integer range 0 to 1; + constant C_PHA : C_PHA_t := (0, 0, 0, 0); + + constant clk_period : time := 40 ns; + + type sig_std_logic_t is array (0 to C_NUM_TESTS) of std_logic; + type sig_std_logic_vector_t is array (0 to C_NUM_TESTS) of std_logic_vector(C_SR_WIDTH-1 downto 0); + + type C_SCLK_INIT_t is array (0 to C_NUM_TESTS) of std_logic; + constant C_SCLK_INIT : C_SCLK_INIT_t := ('0', '0', '1', '1'); + + signal TEST_NUM : integer := 0; + + -- component ports + signal rst : sig_std_logic_t; + signal sclk : sig_std_logic_t; + signal cs_n : sig_std_logic_t; + signal mosi : sig_std_logic_t; + signal miso_o : sig_std_logic_t; + signal miso_i : sig_std_logic_t; + signal miso_t : sig_std_logic_t; + signal tx_clk : sig_std_logic_t; + signal tx_en : sig_std_logic_t; + signal tx_data : sig_std_logic_vector_t; + signal rx_clk : sig_std_logic_t; + signal rx_en : sig_std_logic_t; + signal rx_data : sig_std_logic_vector_t; + + -- component ports + signal s_rst : std_logic; + signal s_sclk : std_logic; + signal s_cs_n : std_logic; + signal s_mosi : std_logic; + signal s_miso_o : std_logic; + signal s_miso_i : std_logic; + signal s_miso_t : std_logic; + signal s_tx_clk : std_logic; + signal s_tx_en : std_logic; + signal s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal s_rx_clk : std_logic; + signal s_rx_en : std_logic; + signal s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + -- testbench + constant C_TX_CMP_VALUE : integer := 130; + constant C_RX_CMP_VALUE : integer := 129; + + signal rx_master : std_logic_vector(7 downto 0); + + signal opb_ctl_reg: std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + +begin -- behavior + + opb_ctl_reg <= "0111"; -- enable all + + s_rst <= rst(TEST_NUM); + s_sclk <= sclk(TEST_NUM); + s_cs_n <= cs_n(TEST_NUM); + s_mosi <= mosi(TEST_NUM); + s_miso_o <= miso_o(TEST_NUM); + s_miso_i <= miso_i(TEST_NUM); + s_miso_t <= miso_t(TEST_NUM); + s_tx_clk <= tx_clk(TEST_NUM); + s_tx_en <= tx_en(TEST_NUM); + s_tx_data <= tx_data(TEST_NUM); + s_rx_clk <= rx_clk(TEST_NUM); + s_rx_en <= rx_en(TEST_NUM); + s_rx_data <= rx_data(TEST_NUM); + + + -- component instantiation + + i : for i in 0 to 3 generate + DUT : shift_register + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST(i), + C_CPOL => C_CPOL(i), + C_PHA => C_PHA(i)) + port map ( + rst => rst(i), + opb_ctl_reg => opb_ctl_reg, + sclk => sclk(i), + ss_n => cs_n(i), + mosi => mosi(i), + miso_o => miso_o(i), + miso_i => miso_i(i), + miso_t => miso_t(i), + sr_tx_clk => tx_clk(i), + sr_tx_en => tx_en(i), + sr_tx_data => tx_data(i), + sr_rx_clk => rx_clk(i), + sr_rx_en => rx_en(i), + sr_rx_data => rx_data(i)); + + + + tx_fifo_emu_1 : tx_fifo_emu + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + C_TX_CMP_VALUE => C_TX_CMP_VALUE) + port map ( + rst => rst(i), + tx_clk => tx_clk(i), + tx_en => tx_en(i), + tx_data => tx_data(i)); + + + rx_fifo_emu_1 : rx_fifo_emu + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + C_RX_CMP_VALUE => C_RX_CMP_VALUE) + port map ( + rst => rst(i), + rx_clk => rx_clk(i), + rx_en => rx_en(i), + rx_data => rx_data(i)); + end generate i; + + + -- waveform generation + WaveGen_Proc : process + variable rx_value : std_logic_vector(7 downto 0); + variable tx_value : std_logic_vector(7 downto 0); + begin + for i in 0 to C_NUM_TESTS loop + sclk(i) <= C_SCLK_INIT(i); + cs_n(i) <= '1'; + mosi(i) <= 'Z'; + miso_i(i) <= 'Z'; + -- rst_active + rst(i) <= '1'; + end loop; -- i +------------------------------------------------------------------------------- + -- Actual Tests + TEST_NUM <= 0; + rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); + tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); + wait for 100 ns; + rst(TEST_NUM) <= '0'; + + -- CPHA=0 CPOL=0 C_MSB_FIRST=TRUE + cs_n(TEST_NUM) <= '0'; + for i in 7 downto 0 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + rx_master(i) <= miso_o(TEST_NUM); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + end loop; -- i + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + wait for 100 ns; + assert (rx_master = tx_value) report "Master Receive Failure" severity warning; + + + -- write 2 byte + cs_n(TEST_NUM) <= '0'; + for n in 1 to 2 loop + rx_value := rx_value +1; + tx_value := tx_value +1; + for i in 7 downto 0 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + rx_master(i) <= miso_o(TEST_NUM); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + end loop; -- i + assert (rx_master = tx_value) report "Master Receive Failure" severity warning; + end loop; -- n + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; +--------------------------------------------------------------------------- + -- Actual Tests + TEST_NUM <= 1; + rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); + tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); + wait for 100 ns; + rst(TEST_NUM) <= '0'; + + -- CPHA=0 CPOL=0 C_MSB_FIRST=FALSE + cs_n(TEST_NUM) <= '0'; + for i in 0 to 7 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + rx_master(i) <= miso_o(TEST_NUM); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + end loop; -- i + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + wait for 100 ns; + assert (rx_master = tx_value) report "Master Receive Failure" severity warning; + + + -- write 2 byte + cs_n(TEST_NUM) <= '0'; + for n in 1 to 2 loop + rx_value := rx_value +1; + tx_value := tx_value +1; + for i in 0 to 7 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + rx_master(i) <= miso_o(TEST_NUM); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + end loop; -- i + assert (rx_master = tx_value) report "Master Receive Failure" severity warning; + end loop; -- n + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + +------------------------------------------------------------------------------- + TEST_NUM <= 2; + rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); + tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); + wait for 100 ns; + rst(TEST_NUM) <= '0'; + + -- CPHA=0 CPOL=1 C_MSB_FIRST=TRUE + cs_n(TEST_NUM) <= '0'; + for i in 7 downto 0 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + end loop; -- i + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + wait for 100 ns; + + -- write 2 byte + cs_n(TEST_NUM) <= '0'; + for n in 1 to 2 loop + rx_value := rx_value +1; + for i in 7 downto 0 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + end loop; -- i + end loop; -- n + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + +------------------------------------------------------------------------------- + TEST_NUM <= 3; + rx_value := conv_std_logic_vector(C_RX_CMP_VALUE, 8); + tx_value := conv_std_logic_vector(C_TX_CMP_VALUE, 8); + wait for 100 ns; + rst(TEST_NUM) <= '0'; + + -- CPHA=0 CPOL=1 C_MSB_FIRST=FALSE + cs_n(TEST_NUM) <= '0'; + for i in 0 to 7 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + end loop; -- i + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + wait for 100 ns; + + -- write 2 byte + cs_n(TEST_NUM) <= '0'; + for n in 1 to 2 loop + rx_value := rx_value +1; + for i in 0 to 7 loop + mosi(TEST_NUM) <= rx_value(i); + wait for clk_period/2; + sclk(TEST_NUM) <= '0'; + wait for clk_period/2; + sclk(TEST_NUM) <= '1'; + end loop; -- i + end loop; -- n + mosi(TEST_NUM) <= 'Z'; + wait for clk_period/2; + cs_n(TEST_NUM) <= '1'; + +------------------------------------------------------------------------------- + + + wait for 1 us; + + assert false report "Simulation sucessful" severity failure; + + + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration shift_register_tb_behavior_cfg of shift_register_tb is + for behavior + end for; +end shift_register_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/fifo_tb.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/fifo_tb.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/fifo_tb.vhd (revision 35) @@ -0,0 +1,308 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "fifo_8bitx16" +-- Project : +------------------------------------------------------------------------------- +-- File : fifo_8bitx16_tb.vhd +-- Author : +-- Company : +-- Created : 2007-09-04 +-- Last update: 2007-11-12 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2007 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2007-09-04 1.0 d.koethe Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use IEEE.STD_LOGIC_ARITH.all; + + +library work; +use work.txt_util.all; +------------------------------------------------------------------------------- + +entity fifo_tb is + +end fifo_tb; + +------------------------------------------------------------------------------- + +architecture behavior of fifo_tb is + component fifo + generic ( + C_FIFO_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_SYNC_TO : string); + port ( + rst : in std_logic; + wr_clk : in std_logic; + wr_en : in std_logic; + din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + rd_clk : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); + empty : out std_logic; + full : out std_logic; + overflow : out std_logic; + underflow : out std_logic; + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + end component; + +-- Testbench + constant C_FIFO_SIZE : integer := 15; + constant C_FIFO_WIDTH : integer := 8; + constant C_FIFO_SIZE_WIDTH : integer := 4; + + -- sync to RD +-- constant C_SYNC_TO : string := "RD"; +-- constant wr_clk_period : time := 100 ns; +-- constant rd_clk_period : time := 25 ns; + + -- sync to WR + constant C_SYNC_TO : string := "WR"; + constant wr_clk_period : time := 25 ns; + constant rd_clk_period : time := 100 ns; + + signal rst : std_logic; + signal wr_clk : std_logic; + signal wr_en : std_logic; + signal din : std_logic_vector(C_FIFO_WIDTH-1 downto 0); + signal rd_clk : std_logic; + signal rd_en : std_logic; + signal dout : std_logic_vector(C_FIFO_WIDTH-1 downto 0); + signal empty : std_logic; + signal full : std_logic; + signal overflow : std_logic; + signal underflow : std_logic; + signal prog_empty_thresh : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal prog_full_thresh : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal prog_empty : std_logic; + signal prog_full : std_logic; + + + + + + signal flags : std_logic_vector(5 downto 0); + signal wr_clk_int : std_logic; + signal wr_clk_en : boolean := false; + + signal rd_clk_int : std_logic; + signal rd_clk_en : boolean := false; + + + signal wr_off : boolean := false; + signal rd_off : boolean := false; + +begin -- behavior + + process + begin + rd_clk_int <= '0'; + wait for rd_clk_period/2; + rd_clk_int <= '1'; + wait for rd_clk_period/2; + end process; + + process + begin + wr_clk_int <= '0'; + wait for wr_clk_period/2; + wr_clk_int <= '1'; + wait for wr_clk_period/2; + end process; + + -- component instantiation + + + DUT : fifo + generic map ( + C_FIFO_WIDTH => C_FIFO_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => C_SYNC_TO) + port map ( + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + dout => dout, + empty => empty, + full => full, + overflow => overflow, + underflow => underflow, + prog_empty_thresh => prog_empty_thresh, + prog_full_thresh => prog_full_thresh, + prog_empty => prog_empty, + prog_full => prog_full); + + flags <= prog_empty & + empty & + underflow & + prog_full & + full & + overflow; + + + wr_off <= false when (C_SYNC_TO = "RD") else true; + rd_off <= false when (C_SYNC_TO = "WR") else true; + + wr_clk <= wr_clk_int when wr_clk_en else '0'; + rd_clk <= rd_clk_int when rd_clk_en else '0'; + + -- waveform generation + WaveGen_Proc : process + variable first : std_logic_vector(7 downto 0) := (others => '0'); + begin + wr_en <= '0'; + din <= (others => 'Z'); + rd_en <= '0'; + -- prog_empty assert 2 cycle delay + -- prog_empty deassert 1 cycle delay + prog_empty_thresh <= X"4"; + -- prog_full assert 2 cycle delay + -- prog_full deassert 1 cycle delay + prog_full_thresh <= X"B"; + -- rst active + rst <= '1'; + wait for 100 ns; + rst <= '0'; + + -- check reset value + -- 1: empty/prog_empty + assert (flags = "110000") report "Flag Reset Value wrong " & str(flags) severity warning; + + -- write + + wait until falling_edge(wr_clk_int); + wr_clk_en <= true; + wr_en <= '1'; + din <= X"A5"; + wait until falling_edge(wr_clk_int); + wr_clk_en <= wr_off; + wr_en <= '0'; + din <= (others => 'Z'); + -- check after 1 write + -- 1: empty + assert (flags = "100000") report "Flag after one write wrong " & str(flags) severity warning; + + wait for 100 ns; + + -- read + wait until falling_edge(rd_clk_int); + rd_clk_en <= true; + rd_en <= '1'; + wait until falling_edge(rd_clk_int); + rd_en <= '0'; + rd_clk_en <= rd_off; + wait for 100 ns; + + -- check reset value + -- 1: empty/prog_empty + assert (flags = "110000") report "Flag after one read wrong " & str(flags) severity warning; + + -- write 16 byte + wait until falling_edge(wr_clk_int); + for i in 1 to 255 loop + wr_clk_en <= true; + wr_en <= '1'; + din <= conv_std_logic_vector(i, din'length); + wait until falling_edge(wr_clk_int); + wr_en <= '0'; + din <= (others => 'Z'); + wr_clk_en <= wr_off; + -- report threshold for prog_empty + if (prog_empty = '0' and first(0) = '0') then + assert (i = conv_integer(prog_empty_thresh)) + report "prog_emtpy deassert after " & integer'image(i) & " writes." severity warning; + first(0) := '1'; + end if; + -- report threshold for prog_full + if (prog_full = '1' and first(1) = '0') then + assert (i = conv_integer(prog_full_thresh)+1) + report "prog_full assert after " & integer'image(i) & " writes." severity warning; + first(1) := '1'; + end if; + -- report threshold for full + if (full = '1') then + assert (i = C_FIFO_SIZE) report "full assert after " & integer'image(i) & " writes." severity warning; + exit; + end if; + end loop; -- i + + -- read + wait until falling_edge(rd_clk_int); + for i in 1 to 255 loop + rd_clk_en <= true; + rd_en <= '1'; + if (empty = '0' and underflow = '0') then + assert (conv_integer(dout) = i) report "Read failure at " & integer'image(i) severity warning; + end if; + wait until falling_edge(rd_clk_int); + wait for 1 ps; + rd_clk_en <= rd_off; + rd_en <= '0'; + + + + -- report threshold for prog_full + if (prog_full = '0' and first(2) = '0') then + assert (C_FIFO_SIZE-i = conv_integer(prog_full_thresh)-1) + report "prog_full deassert after " & integer'image(i) & " reads." severity warning; + first(2) := '1'; + end if; + -- report threshold for prog_empty + + if (prog_empty = '1' and first(3) = '0') then + assert (C_FIFO_SIZE-i = conv_integer(prog_empty_thresh)-2) + report "prog_empty assert after " & integer'image(i) & " reads." severity warning; + first(3) := '1'; + end if; + -- report threshold for empty + if (empty = '1' and first(4) = '0') then + assert (i = C_FIFO_SIZE) + report "empty assert after " & integer'image(i) & " reads." severity warning; + first(4) := '1'; + end if; + -- report threshold for underflow + if (underflow = '1') then + assert (i = C_FIFO_SIZE+1) + report "underflow assert after " & integer'image(i) & " reads." severity warning; + exit; + end if; + + end loop; -- i + + wait for 100 ns; + + assert false report "Simulation Sucessful" severity failure; + + + + + end process WaveGen_Proc; + + + +end behavior; + +------------------------------------------------------------------------------- + +configuration fifo_tb_behavior_cfg of fifo_tb is + for behavior + end for; +end fifo_tb_behavior_cfg; + +------------------------------------------------------------------------------- Index: spi_slave/trunk/bench/vhdl/txt_util.vhd =================================================================== --- spi_slave/trunk/bench/vhdl/txt_util.vhd (nonexistent) +++ spi_slave/trunk/bench/vhdl/txt_util.vhd (revision 35) @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_core.vhd (revision 35) @@ -0,0 +1,127 @@ + +library ieee; +use ieee.std_logic_1164.all; + +entity crc_core is + + generic ( + C_SR_WIDTH : integer := 32); + port ( + rst : in std_logic; + opb_clk : in std_logic; + crc_en : in std_logic; + crc_clr : in std_logic; + opb_m_last_block : in std_logic; + -- RX + fifo_rx_en : in std_logic; + fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); + -- TX + fifo_tx_en : in std_logic; + fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + tx_crc_insert : out std_logic; + opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); +end crc_core; + + +architecture behavior of crc_core is + component crc_gen + generic ( + C_SR_WIDTH : integer; + crc_start_value : std_logic_vector(31 downto 0)); + port ( + clk : in std_logic; + crc_clear : in std_logic; + crc_en : in std_logic; + crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0); + crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + signal rx_crc_en : std_logic; + signal tx_crc_en : std_logic; + + + type state_define is (idle, + tx_insert_crc, + wait_done); + signal state : state_define; + +begin -- behavior + + --* RX CRC_GEN + crc_gen_rx : crc_gen + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + crc_start_value => (others => '1')) + port map ( + clk => OPB_Clk, + crc_clear => crc_clr, + crc_en => rx_crc_en, + crc_data_in => fifo_rx_data, + crc_data_out => opb_rx_crc_value); + + -- disable crc_generation for last data block + rx_crc_en <= '1' when (crc_en = '1' and fifo_rx_en = '1' and opb_m_last_block = '0') else + '0'; + + ----------------------------------------------------------------------------- + --* TX CRC_GEN + crc_gen_tx : crc_gen + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + crc_start_value => (others => '1')) + port map ( + clk => OPB_Clk, + crc_clear => crc_clr, + crc_en => tx_crc_en, + crc_data_in => fifo_tx_data, + crc_data_out => opb_tx_crc_value); + + -- disable crc_generation for last data block + tx_crc_en <= '1' when (crc_en = '1' and fifo_tx_en = '1' and opb_m_last_block = '0') else + '0'; + + process(rst, OPB_Clk) + begin + if (rst = '1') then + tx_crc_insert <= '0'; + state <= idle; + elsif rising_edge(OPB_Clk) then + case state is + when idle => + if (opb_m_last_block = '1') then + tx_crc_insert <= '1'; + state <= tx_insert_crc; + else + tx_crc_insert <= '0'; + state <= idle; + end if; + + when tx_insert_crc => + if (opb_m_last_block = '0') then + -- abort + tx_crc_insert <= '0'; + state <= idle; + elsif (fifo_tx_en = '1') then + tx_crc_insert <= '0'; + state <= wait_done; + else + state <= tx_insert_crc; + end if; + + when wait_done => + if (opb_m_last_block = '0') then + tx_crc_insert <= '0'; + state <= idle; + + else + state <= wait_done; + end if; + + when others => + state <= idle; + end case; + + end if; + end process; +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (revision 35) @@ -0,0 +1,640 @@ +------------------------------------------------------------------------------- +------------------------------------------------------- +--! @file +--! @brief 2:1 Mux using with-select +------------------------------------------------------- + +--* +--* @short Top entity of the project opi_spi_slave +--* +--* @generic C_FAMILY virtex-4 and generic supported +--* @author: Daniel Köthe +--* @version: 1.1 +--* @date: 2007-11-19 +--/ +-- Version 1.1 +-- Bugfix +-- IRQ-Flag RX_Overflow shows prog_empty insteed rx_overflow +-- opb_irq_flg(5) <= opb_fifo_flg(9); to opb_irq_flg(5) <= opb_fifo_flg(8); + +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +library UNISIM; +use UNISIM.vcomponents.all; + +library work; +use work.opb_spi_slave_pack.all; + + +entity opb_spi_slave is + + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 0; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + + C_FAMILY : string := "virtex4"; + -- user ports + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0; + C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32 + C_DMA_EN : boolean := false; + C_CRC_EN : boolean := false); + + port ( + -- OPB signals (Slave Side) + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + + -- OPB signals (Master Side) + -- Arbitration + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + -- + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + -- spi ports + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + -- irq output + opb_irq : out std_logic); + +end opb_spi_slave; + +architecture behavior of opb_spi_slave is + + component opb_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_DMA_EN : boolean; + C_CRC_EN : boolean); + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + opb_s_tx_en : out std_logic; + opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_s_rx_en : out std_logic; + opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); + opb_dgie : out std_logic; + opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_ctl : out std_logic_vector(0 downto 0); + opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_ctl : out std_logic_vector(0 downto 0); + opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0)); + + end component; + + + component opb_m_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1; + C_FIFO_SIZE_WIDTH : integer range 4 to 7); + port ( + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + opb_m_tx_req : in std_logic; + opb_m_tx_en : out std_logic; + opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_tx_dma_ctl : in std_logic_vector(0 downto 0); + opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_tx_dma_done : out std_logic; + opb_m_rx_req : in std_logic; + opb_m_rx_en : out std_logic; + opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_dma_ctl : in std_logic_vector(0 downto 0); + opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_rx_dma_done : out std_logic; + opb_abort_flg : out std_logic; + opb_m_last_block : out std_logic); + end component; + + component shift_register + generic ( + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1); + port ( + rst : in std_logic; + opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + sr_tx_clk : out std_logic; + sr_tx_en : out std_logic; + sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + sr_rx_clk : out std_logic; + sr_rx_en : out std_logic; + sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + component fifo + generic ( + C_FIFO_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_SYNC_TO : string); + port ( + rst : in std_logic; + wr_clk : in std_logic; + wr_en : in std_logic; + din : in std_logic_vector(C_SR_WIDTH-1 downto 0); + rd_clk : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(C_SR_WIDTH-1 downto 0); + empty : out std_logic; + full : out std_logic; + overflow : out std_logic; + underflow : out std_logic; + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + end component; + + component irq_ctl + generic ( + C_ACTIVE_EDGE : std_logic); + port ( + rst : in std_logic; + clk : in std_logic; + opb_fifo_flg : in std_logic; + opb_ier : in std_logic; + opb_isr : out std_logic; + opb_isr_clr : in std_logic); + end component; + + component crc_core + generic ( + C_SR_WIDTH : integer); + port ( + rst : in std_logic; + opb_clk : in std_logic; + crc_en : in std_logic; + crc_clr : in std_logic; + opb_m_last_block : in std_logic; + fifo_rx_en : in std_logic; + fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0); + fifo_tx_en : in std_logic; + fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + tx_crc_insert : out std_logic; + opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + +-- opb_if + signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + + signal opb_s_tx_en : std_logic; + signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_s_rx_en : std_logic; + signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + + signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_tx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_rx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + + signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0); + + -- opb_m_if + signal opb_m_tx_en : std_logic; + signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_m_rx_en : std_logic; + signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_abort_flg : std_logic; + signal opb_m_last_block : std_logic; + +-- shift_register + signal sr_tx_clk : std_logic; + signal sr_tx_en : std_logic; + signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal sr_rx_clk : std_logic; + signal sr_rx_en : std_logic; + signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + signal sclk_ibuf : std_logic; + signal sclk_bufr : std_logic; + + signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); + signal opb_irq_flg : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0'); + signal rst : std_logic; + + + signal opb_dgie : std_logic; + signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); + + -- opb_spi_slave + signal fifo_tx_en : std_logic; + signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal fifo_rx_en : std_logic; + signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + -- rx crc_core + signal crc_clr : std_logic; + signal crc_en : std_logic; + signal tx_crc_insert : std_logic; + +begin -- behavior + + --* + virtex4_slk_buf : if C_FAMILY = "virtex4" generate + --* If C_FAMILY=Virtex-4 use "IBUF" + IBUF_1 : IBUF + port map ( + I => sclk, + O => sclk_ibuf); + +--* If C_FAMILY=Virtex-4 use "BUFR" + BUFR_1 : BUFR + generic map ( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "VIRTEX4") + port map ( + O => sclk_bufr, + CE => '0', + CLR => '0', + I => sclk_ibuf); + end generate virtex4_slk_buf; + + generic_sclk_buf : if C_FAMILY /= "virtex4" generate + sclk_bufr <= sclk; + end generate generic_sclk_buf; + + --* OPB-Slave Interface(Register-Interface) + opb_if_2 : opb_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_DMA_EN => C_DMA_EN, + C_CRC_EN => C_CRC_EN) + port map ( + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_Clk => OPB_Clk, + OPB_DBus => OPB_DBus, + OPB_RNW => OPB_RNW, + OPB_Rst => OPB_Rst, + OPB_select => OPB_select, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sln_DBus, + Sln_errAck => Sln_errAck, + Sln_retry => Sln_retry, + Sln_toutSup => Sln_toutSup, + Sln_xferAck => Sln_xferAck, + opb_s_tx_en => opb_s_tx_en, + opb_s_tx_data => opb_s_tx_data, + opb_s_rx_en => opb_s_rx_en, + opb_s_rx_data => opb_s_rx_data, + opb_ctl_reg => opb_ctl_reg, + tx_thresh => tx_thresh, + rx_thresh => rx_thresh, + opb_fifo_flg => opb_fifo_flg, + opb_dgie => opb_dgie, + opb_ier => opb_ier, + opb_isr => opb_isr, + opb_isr_clr => opb_isr_clr, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_num => opb_tx_dma_num, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_num => opb_rx_dma_num, + opb_rx_crc_value => opb_rx_crc_value, + opb_tx_crc_value => opb_tx_crc_value); + + --* OPB-Master-Interface + --* + --* (DMA Read/Write Transfers to TX/RX-FIFO) + + dma_enable : if (C_DMA_EN = true) generate + opb_m_if_1 : opb_m_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) + port map ( + OPB_Clk => OPB_Clk, + OPB_Rst => OPB_Rst, + OPB_DBus => OPB_DBus, + M_request => M_request, + MOPB_MGrant => MOPB_MGrant, + M_busLock => M_busLock, + M_ABus => M_ABus, + M_BE => M_BE, + M_DBus => M_DBus, + M_RNW => M_RNW, + M_select => M_select, + M_seqAddr => M_seqAddr, + MOPB_errAck => MOPB_errAck, + MOPB_retry => MOPB_retry, + MOPB_timeout => MOPB_timeout, + MOPB_xferAck => MOPB_xferAck, + opb_m_tx_req => opb_fifo_flg(3), + opb_m_tx_en => opb_m_tx_en, + opb_m_tx_data => opb_m_tx_data, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_num => opb_tx_dma_num, + opb_tx_dma_done => opb_fifo_flg(13), + opb_m_rx_req => opb_fifo_flg(6), + opb_m_rx_en => opb_m_rx_en, + opb_m_rx_data => opb_m_rx_data, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_num => opb_rx_dma_num, + opb_rx_dma_done => opb_fifo_flg(14), + opb_abort_flg => opb_abort_flg, + opb_m_last_block => opb_m_last_block); + end generate dma_enable; + + dma_disable : if (C_DMA_EN = false) generate + M_request <= '0'; + M_busLock <= '0'; + M_ABus <= (others => '0'); + M_BE <= (others => '0'); + M_DBus <= (others => '0'); + M_RNW <= '0'; + M_select <= '0'; + M_seqAddr <= '0'; + opb_m_tx_en <= '0'; + opb_m_tx_data <= (others => '0'); + opb_fifo_flg(13) <= '0'; + opb_m_rx_en <= '0'; + opb_fifo_flg(14) <= '0'; + end generate dma_disable; + + --* Shift-Register + shift_register_1 : shift_register + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA) + port map ( + rst => rst, + opb_ctl_reg => opb_ctl_reg, + sclk => sclk_bufr, + ss_n => ss_n, + mosi => mosi, + miso_o => miso_o, + miso_i => miso_i, + miso_t => miso_t, + sr_tx_clk => sr_tx_clk, + sr_tx_en => sr_tx_en, + sr_tx_data => sr_tx_data, + sr_rx_clk => sr_rx_clk, + sr_rx_en => sr_rx_en, + sr_rx_data => sr_rx_data); + + --* Transmit FIFO + tx_fifo_1 : fifo + generic map ( + C_FIFO_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => "WR") + port map ( + -- global + rst => rst, + prog_full_thresh => tx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), + prog_empty_thresh => tx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), + -- write port + wr_clk => OPB_Clk, + wr_en => fifo_tx_en, + din => fifo_tx_data, + -- flags + prog_full => opb_fifo_flg(0), + full => opb_fifo_flg(1), + overflow => opb_fifo_flg(2), + -- read port + rd_clk => sr_tx_clk, + rd_en => sr_tx_en, + dout => sr_tx_data, + -- flags + prog_empty => opb_fifo_flg(3), + empty => opb_fifo_flg(4), + underflow => opb_fifo_flg(5)); + + fifo_tx_en <= opb_s_tx_en or opb_m_tx_en; + fifo_tx_data <= opb_tx_crc_value when (C_CRC_EN and tx_crc_insert = '1') else + opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else + opb_s_tx_data; + + --* Receive FIFO + rx_fifo_1 : fifo + generic map ( + C_FIFO_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => "RD") + port map ( + -- global + rst => rst, + prog_full_thresh => rx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), + prog_empty_thresh => rx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), + -- write port + wr_clk => sr_rx_clk, + wr_en => sr_rx_en, + din => sr_rx_data, + -- flags + prog_full => opb_fifo_flg(6), + full => opb_fifo_flg(7), + overflow => opb_fifo_flg(8), + -- read port + rd_clk => opb_clk, + rd_en => fifo_rx_en, + dout => fifo_rx_data, + -- flags + prog_empty => opb_fifo_flg(9), + empty => opb_fifo_flg(10), + underflow => opb_fifo_flg(11)); + + fifo_rx_en <= opb_s_rx_en or opb_m_rx_en; + opb_s_rx_data <= fifo_rx_data; + opb_m_rx_data <= fifo_rx_data; + + rst <= OPB_Rst or opb_ctl_reg(C_OPB_CTL_REG_RST); + + opb_fifo_flg(12) <= ss_n; + opb_fifo_flg(15) <= opb_abort_flg; + + + + -- Bit 0 : TX_PROG_EMPTY + opb_irq_flg(0) <= opb_fifo_flg(3); + -- Bit 1 : TX_EMPTY + opb_irq_flg(1) <= opb_fifo_flg(4); + -- Bit 2 : TX_Underflow + opb_irq_flg(2) <= opb_fifo_flg(5); + -- Bit 3 : RX_PROG_FULL + opb_irq_flg(3) <= opb_fifo_flg(6); + -- Bit 4 : RX_FULL + opb_irq_flg(4) <= opb_fifo_flg(7); + -- Bit 5 : RX_Overflow + opb_irq_flg(5) <= opb_fifo_flg(8); + -- Bit 6: CS_H_TO_L + opb_irq_flg(6) <= not opb_fifo_flg(12); + -- Bit 7: CS_L_TO_H + opb_irq_flg(7) <= opb_fifo_flg(12); + -- Bit 8: TX DMA Done + opb_irq_flg(8) <= opb_fifo_flg(13); + -- Bit 9: RX DMA Done + opb_irq_flg(9) <= opb_fifo_flg(14); + -- Bit 10: DMA Transfer Abort + opb_irq_flg(10) <= opb_abort_flg; + + --* IRQ Enable, Detection and Flags Control + irq_gen : for i in 0 to C_NUM_INT-1 generate + irq_ctl_1 : irq_ctl + generic map ( + C_ACTIVE_EDGE => '1') + port map ( + rst => rst, + clk => OPB_Clk, + opb_fifo_flg => opb_irq_flg(i), + opb_ier => opb_ier(i), + opb_isr => opb_isr(i), + opb_isr_clr => opb_isr_clr(i)); + end generate irq_gen; + + -- assert irq if one Interupt Status bit set + opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else + '0'; + + + ----------------------------------------------------------------------------- + + -- clear start_value at power up and soft_reset + crc_en <= opb_ctl_reg(C_OPB_CTL_REG_CRC_EN); + crc_clr <= opb_ctl_reg(C_OPB_CTL_REG_CRC_CLR) or rst; + + crc_gen : if (C_CRC_EN) generate + crc_core_1 : crc_core + generic map ( + C_SR_WIDTH => C_SR_WIDTH) + port map ( + rst => rst, + opb_clk => opb_clk, + crc_en => crc_en, + crc_clr => crc_clr, + opb_m_last_block => opb_m_last_block, + fifo_rx_en => fifo_rx_en, + fifo_rx_data => fifo_rx_data, + opb_rx_crc_value => opb_rx_crc_value, + fifo_tx_en => fifo_tx_en, + fifo_tx_data => fifo_tx_data, + tx_crc_insert => tx_crc_insert, + opb_tx_crc_value => opb_tx_crc_value); + end generate crc_gen; + + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/crc_gen.vhd (revision 35) @@ -0,0 +1,76 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library work; +use work.PCK_CRC32_D32.all; +-- java -jar jacksum.jar -a crc:32,04C11DB7,FFFFFFFF,false,false,00000000 +-- -q 000000000000000100000002000000030000000400000005000000060000000700000008000000090000000A0000000B0000000C0000000D0000000E0000000F +-- -x +-- Result: eb99fa90 64 + +use work.PCK_CRC8_D8.all; +-- java -jar jacksum.jar -a crc:8,07,FF,false,false,00 +-- -q 000102030405060708090A0B0C0D0E0F +-- -x +-- Result: B8 16 + +entity crc_gen is + generic ( + C_SR_WIDTH : integer := 32; + crc_start_value : std_logic_vector(31 downto 0) := (others => '1')); + port ( + clk : in std_logic; + crc_clear : in std_logic; + crc_en : in std_logic; + crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0); + crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0)); +end crc_gen; + +architecture rtl of crc_gen is + signal crc_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal crc_data_in_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + +begin -- crc_gen + process(clk) + begin + if rising_edge(clk) then + if (crc_clear = '1') then + crc_data_int <= crc_start_value(C_SR_WIDTH-1 downto 0); + elsif (crc_en = '1') then + case C_SR_WIDTH is + when 32 => + crc_data_int <= nextCRC32_D32(crc_data_in_int, crc_data_int); + when 8 => + crc_data_int <= nextCRC8_D8(crc_data_in_int, crc_data_int); + when others => + -- no crc calculation + crc_data_int <= (others => '0'); + end case; + end if; + end if; + end process; + + process(crc_data_int) + begin + for i in 0 to 7 loop + crc_data_out(24+7-i) <= not crc_data_int(i); + crc_data_out(16+7-i) <= not crc_data_int(8+i); + crc_data_out(8+7-i) <= not crc_data_int(16+i); + crc_data_out(7-i) <= not crc_data_int(24+i); + end loop; -- i + end process; + + process(crc_data_in) + begin + for i in 0 to 7 loop + crc_data_in_int(7-i) <= crc_data_in(i); + crc_data_in_int(8+7-i) <= crc_data_in(8+i); + crc_data_in_int(16+7-i) <= crc_data_in(16+i); + crc_data_in_int(24+7-i) <= crc_data_in(24+i); + end loop; -- i + end process; + + +end rtl; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (revision 35) @@ -0,0 +1,349 @@ +------------------------------------------------------------------------------- +--* +--* @short OPB-Slave Interface +--* +--* Generics described in top entity. +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +library work; +use work.opb_spi_slave_pack.all; + +entity opb_if is + + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 3; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "virtex-4"; + C_SR_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4; + C_DMA_EN : boolean := false; + C_CRC_EN : boolean := false); + port ( + -- OPB-Bus Signals + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + -- fifo ports + opb_s_tx_en : out std_logic; + opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_s_rx_en : out std_logic; + opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- control register + opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + -- Fifo almost full/empty thresholds + tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); + -- interrupts + opb_dgie : out std_logic; + opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); + -- dma register + opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_ctl : out std_logic_vector(0 downto 0); + opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_ctl : out std_logic_vector(0 downto 0); + opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + -- rx crc + opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0)); +end opb_if; + +architecture behavior of opb_if is + + + signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + + + type state_t is (idle, + done); + signal state : state_t := idle; + + -- internal signals to enable readback + + signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_dgie_int : std_logic; + + signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + + + -- only used if C_DMA_EN=true + signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0); + signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0); + signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + +begin -- behavior + + tx_thresh <= tx_thresh_int; + rx_thresh <= rx_thresh_int; + opb_ier <= opb_ier_int; + opb_dgie <= opb_dgie_int; + + opb_ctl_reg <= opb_ctl_reg_int; + + --* Signals for DMA-Engine control + u1 : if C_DMA_EN generate + opb_tx_dma_ctl <= opb_tx_dma_ctl_int; + opb_tx_dma_addr <= opb_tx_dma_addr_int; + opb_tx_dma_num <= opb_tx_dma_num_int; + opb_rx_dma_ctl <= opb_rx_dma_ctl_int; + opb_rx_dma_addr <= opb_rx_dma_addr_int; + opb_rx_dma_num <= opb_rx_dma_num_int; + end generate u1; + + +-- unused outputs + Sln_errAck <= '0'; + Sln_retry <= '0'; + Sln_toutSup <= '0'; + + --* convert Sln_DBus_big_end to little mode + conv_big_Sln_DBus_proc : process(Sln_DBus_big_end) + begin + for i in 0 to 31 loop + Sln_DBus(31-i) <= Sln_DBus_big_end(i); + end loop; -- i + end process conv_big_Sln_DBus_proc; + + --* convert OPB_ABus to big endian + conv_big_OPB_ABus_proc : process(OPB_ABus) + begin + for i in 0 to 31 loop + OPB_ABus_big_end(31-i) <= OPB_ABus(i); + end loop; -- i + end process conv_big_OPB_ABus_proc; + + --* convert OPB_DBus to little mode + conv_big_OPB_DBus_proc : process(OPB_DBus) + begin + for i in 0 to 31 loop + OPB_DBus_big_end(31-i) <= OPB_DBus(i); + end loop; -- i + end process conv_big_OPB_DBus_proc; + + --* control OPB requests + --* + --* handles OPB-read and -write request + opb_slave_proc : process (OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + -- OPB + Sln_xferAck <= '0'; + Sln_DBus_big_end <= (others => '0'); + -- FIFO + opb_s_rx_en <= '0'; + opb_s_tx_en <= '0'; + -- + state <= idle; + -- Register + tx_thresh_int <= (others => '0'); + rx_thresh_int <= (others => '0'); + opb_ier_int <= (others => '0'); + opb_dgie_int <= '0'; + opb_ctl_reg_int <= (others => '0'); + + if C_DMA_EN then + opb_tx_dma_ctl_int <= (others => '0'); + opb_tx_dma_addr_int <= (others => '0'); + opb_tx_dma_num_int <= (others => '0'); + opb_rx_dma_ctl_int <= (others => '0'); + opb_rx_dma_addr_int <= (others => '0'); + opb_rx_dma_num_int <= (others => '0'); + end if; + + + elsif (OPB_Clk'event and OPB_Clk = '1') then + case state is + when idle => + if (OPB_select = '1' and + ((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then + -- *device selected + Sln_xferAck <= '1'; + state <= done; + if (OPB_RNW = '1') then + -- read acess + case OPB_ABus_big_end(7 downto 2) is + when C_ADR_CTL => + Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int; + + when C_ADR_RX_DATA => + opb_s_rx_en <= '1'; + Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data; + + when C_ADR_STATUS => + Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg; + + when C_ADR_TX_THRESH => + Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); + Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); + + when C_ADR_RX_THRESH => + Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); + Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); + + when C_ADR_DGIE => + Sln_DBus_big_end(0) <= opb_dgie_int; + when C_ADR_IER => + Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int; + + when C_ADR_ISR => + Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr; + + when C_ADR_TX_DMA_CTL => + if C_DMA_EN then + Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int; + end if; + + when C_ADR_TX_DMA_ADDR => + if C_DMA_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int; + end if; + + when C_ADR_TX_DMA_NUM => + if C_DMA_EN then + Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_tx_dma_num_int; + end if; + + + when C_ADR_RX_DMA_CTL => + if C_DMA_EN then + Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int; + end if; + + when C_ADR_RX_DMA_ADDR => + if C_DMA_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int; + end if; + + when C_ADR_RX_DMA_NUM => + if C_DMA_EN then + Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_rx_dma_num_int; + end if; + + when C_ADR_RX_CRC => + if C_CRC_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); + Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_rx_crc_value; + end if; + + when C_ADR_TX_CRC => + if C_CRC_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); + Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_tx_crc_value; + end if; + when others => + null; + end case; + else + -- write acess + case OPB_ABus_big_end(7 downto 2) is + when C_ADR_CTL => + opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0); + + when C_ADR_TX_DATA => + opb_s_tx_en <= '1'; + opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); + + when C_ADR_TX_THRESH => + tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); + tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); + + when C_ADR_RX_THRESH => + rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); + rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); + + when C_ADR_DGIE => + opb_dgie_int <= OPB_DBus_big_end(0); + + when C_ADR_IER => + opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); + + when C_ADR_ISR => + opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); + + when C_ADR_TX_DMA_CTL => + if C_DMA_EN then + opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); + end if; + + when C_ADR_TX_DMA_ADDR => + if C_DMA_EN then + opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); + end if; + + when C_ADR_TX_DMA_NUM => + if C_DMA_EN then + opb_tx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0); + end if; + + when C_ADR_RX_DMA_CTL => + if C_DMA_EN then + opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); + end if; + + when C_ADR_RX_DMA_ADDR => + if C_DMA_EN then + opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); + end if; + + when C_ADR_RX_DMA_NUM => + if C_DMA_EN then + opb_rx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0); + end if; + + when others => + null; + end case; + end if; -- OPB_RNW + else + -- not selected + state <= idle; + end if; + when done => + opb_ctl_reg_int(3) <= '0'; + opb_isr_clr <= (others => '0'); + opb_s_rx_en <= '0'; + opb_s_tx_en <= '0'; + Sln_xferAck <= '0'; + Sln_DBus_big_end <= (others => '0'); + state <= idle; + + when others => + state <= idle; + end case; + end if; + end process opb_slave_proc; +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (revision 35) @@ -0,0 +1,320 @@ +------------------------------------------------------------------------------- +--* +--* @short OPB-Master Interface +--* +--* Generics described in top entity. +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +library work; +use work.opb_spi_slave_pack.all; + +entity opb_m_if is + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 0; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "virtex-4"; + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0; + C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7); + + port ( + -- opb master interface + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + --------------------------------------------------------------------------- + -- read transfer + -- read data from memory and fill fifo + opb_m_tx_req : in std_logic; + opb_m_tx_en : out std_logic; + opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + -- enable/disable dma transfer + opb_tx_dma_ctl : in std_logic_vector(0 downto 0); + -- base adress for transfer + opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_tx_dma_done : out std_logic; + --------------------------------------------------------------------------- + -- write transfer + -- read fifo an write to memory + opb_m_rx_req : in std_logic; + opb_m_rx_en : out std_logic; + opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- enable/disable dma transfer + opb_rx_dma_ctl : in std_logic_vector(0 downto 0); + -- base adress for transfer + opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + opb_rx_dma_done : out std_logic; + --------------------------------------------------------------------------- + opb_abort_flg : out std_logic; + opb_m_last_block : out std_logic); +end opb_m_if; + +architecture behavior of opb_m_if is + + type state_t is (idle, + wait_grant, + transfer_write, + transfer_read, + done); + + + signal state : state_t := idle; + + signal M_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal M_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + + signal M_select_int : std_logic; + signal read_transfer : boolean; + + -- read transfer + signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_en : std_logic; + signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + signal opb_tx_dma_done_int : std_logic; + + -- write transfer + signal opb_rx_dma_en : std_logic; + signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0); + signal opb_rx_dma_done_int : std_logic; + + +begin -- behavior + + --* convert M_DBus_big_end to little endian + process(M_DBus_big_end) + begin + for i in 0 to 31 loop + M_DBus(31-i) <= M_DBus_big_end(i); + end loop; -- i + end process; + + --* convert M_ABus_big_end to little endian + process(M_ABus_big_end) + begin + for i in 0 to 31 loop + M_ABus(31-i) <= M_ABus_big_end(i); + end loop; -- i + end process; + + --* convert OPB_DBus to bi endian + process(OPB_DBus) + begin + for i in 0 to 31 loop + OPB_DBus_big_end(31-i) <= OPB_DBus(i); + end loop; -- i + end process; + + -- for both sides + M_ABus_big_end <= opb_tx_dma_addr_int when (M_select_int = '1' and (read_transfer = true)) else + opb_rx_dma_addr_int when (M_select_int = '1' and (read_transfer = false)) else + (others => '0'); + M_select <= M_select_int; + + + + -- write transfer + opb_m_rx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = false)) else + '0'; + + M_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_m_rx_data when (M_select_int = '1' and (read_transfer = false)) else + (others => '0'); + M_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); + + opb_tx_dma_done <= opb_tx_dma_done_int; + + -- read transfer + opb_m_tx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = true)) else + '0'; + opb_m_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); + + opb_rx_dma_done <= opb_rx_dma_done_int; + + + +------------------------------------------------------------------------------- + opb_masteer_proc : process(OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + M_BE <= (others => '0'); + M_busLock <= '0'; + M_request <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_seqAddr <= '0'; + opb_tx_dma_done_int <= '0'; + opb_rx_dma_done_int <= '0'; + opb_abort_flg <= '0'; + opb_m_last_block <= '0'; + opb_tx_dma_num_int <= (others => '0'); + opb_rx_dma_num_int <= (others => '0'); + elsif rising_edge(OPB_Clk) then + case state is + when idle => + opb_abort_flg <= '0'; + opb_tx_dma_en <= opb_tx_dma_ctl(0); + opb_rx_dma_en <= opb_rx_dma_ctl(0); + + if (opb_tx_dma_ctl(0) = '1' and opb_tx_dma_en = '0') then + opb_tx_dma_addr_int <= opb_tx_dma_addr; + opb_tx_dma_num_int <= opb_tx_dma_num; + opb_tx_dma_done_int <= '0'; + + end if; + + if (opb_rx_dma_ctl(0) = '1' and opb_rx_dma_en = '0') then + opb_rx_dma_addr_int <= opb_rx_dma_addr; + opb_rx_dma_num_int <= opb_rx_dma_num; + opb_rx_dma_done_int <= '0'; + end if; + + if (opb_tx_dma_en = '1' and opb_m_tx_req = '1' and opb_tx_dma_done_int = '0') then + -- read from memory to fifo + M_request <= '1'; + read_transfer <= true; + state <= wait_grant; + elsif (opb_rx_dma_en = '1' and opb_m_rx_req = '1'and opb_rx_dma_done_int = '0') then + -- read from fifo and write memory + M_request <= '1'; + read_transfer <= false; + state <= wait_grant; + else + state <= idle; + end if; + + when wait_grant => + if (MOPB_MGrant = '1') then + M_request <= '0'; + M_busLock <= '1'; + M_select_int <= '1'; + M_seqAddr <= '1'; + M_BE <= "1111"; + if (read_transfer) then + -- read + M_RNW <= '1'; + if (conv_integer(opb_tx_dma_num_int) = 0) then + opb_m_last_block <= '1'; + end if; + state <= transfer_read; + else + -- write + M_RNW <= '0'; + if (conv_integer(opb_rx_dma_num_int) = 0) then + opb_m_last_block <= '1'; + end if; + state <= transfer_write; + end if; + else + state <= wait_grant; + end if; + + when transfer_read => + if (MOPB_xferAck = '1') then + opb_tx_dma_addr_int <= opb_tx_dma_addr_int +4; + if (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then + -- cycle 14 + -- deassert buslock and seq_address 1 cycle before transfer complete + M_busLock <= '0'; + M_seqAddr <= '0'; + elsif (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then + -- cycle 15 + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + if (conv_integer(opb_tx_dma_num_int) = 0) then + opb_tx_dma_done_int <= '1'; + opb_m_last_block <= '0'; + else + opb_tx_dma_num_int <= opb_tx_dma_num_int-1; + end if; + state <= done; + end if; + elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then + -- cancel transfer + M_busLock <= '0'; + M_seqAddr <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + opb_abort_flg <= '1'; + state <= done; + else + state <= transfer_read; + end if; + + when transfer_write => + if (MOPB_xferAck = '1') then + opb_rx_dma_addr_int <= opb_rx_dma_addr_int +4; + if (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then + -- cycle 14 + -- deassert buslock and seq_address 1 cycle before transfer complete + M_busLock <= '0'; + M_seqAddr <= '0'; + elsif (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then + -- cycle 15 + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + if (conv_integer(opb_rx_dma_num_int) = 0) then + opb_rx_dma_done_int <= '1'; + opb_m_last_block <= '0'; + else + opb_rx_dma_num_int <= opb_rx_dma_num_int-1; + end if; + state <= done; + end if; + elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then + -- cancel transfer + M_busLock <= '0'; + M_seqAddr <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + opb_abort_flg <= '1'; + state <= done; + else + state <= transfer_write; + end if; + + when done => + + state <= idle; + + when others => + state <= idle; + end case; + end if; + end process opb_masteer_proc; +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (revision 35) @@ -0,0 +1,73 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +package opb_spi_slave_pack is + + constant C_ADR_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#0#, 6); + constant C_ADR_STATUS : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#1#, 6); + constant C_ADR_TX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#2#, 6); + constant C_ADR_RX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#3#, 6); + constant C_ADR_TX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#4#, 6); + constant C_ADR_RX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#5#, 6); + constant C_ADR_TX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#6#, 6); + constant C_ADR_TX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#7#, 6); + constant C_ADR_TX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#8#, 6); + constant C_ADR_RX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#9#, 6); + constant C_ADR_RX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#A#, 6); + constant C_ADR_RX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#B#, 6); + constant C_ADR_RX_CRC : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#C#, 6); + constant C_ADR_TX_CRC : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#D#, 6); + +-- XIIF_V123B compatible + constant C_ADR_DGIE : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#10#, 6); + constant C_ADR_ISR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#11#, 6); + constant C_ADR_IER : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#12#, 6); + + constant C_NUM_FLG : integer := 16; + constant C_NUM_INT : integer := 11; + constant C_WIDTH_DMA_NUM : integer := 24; + + +-- CTL_Register + -- width + constant C_OPB_CTL_REG_WIDTH : integer := 6; + -- bits + constant C_OPB_CTL_REG_DGE : integer := 0; + constant C_OPB_CTL_REG_TX_EN : integer := 1; + constant C_OPB_CTL_REG_RX_EN : integer := 2; + constant C_OPB_CTL_REG_RST : integer := 3; + constant C_OPB_CTL_REG_CRC_EN : integer := 4; + constant C_OPB_CTL_REG_CRC_CLR : integer := 5; + + -- Status Register + constant SPI_SR_Bit_TX_Prog_Full : integer := 0; + constant SPI_SR_Bit_TX_Full : integer := 1; + constant SPI_SR_Bit_TX_Overflow : integer := 2; + constant SPI_SR_Bit_TX_Prog_empty : integer := 3; + constant SPI_SR_Bit_TX_Empty : integer := 4; + constant SPI_SR_Bit_TX_Underflow : integer := 5; + + constant SPI_SR_Bit_RX_Prog_Full : integer := 6; + constant SPI_SR_Bit_RX_Full : integer := 7; + constant SPI_SR_Bit_RX_Overflow : integer := 8; + constant SPI_SR_Bit_RX_Prog_empty : integer := 9; + constant SPI_SR_Bit_RX_Empty : integer := 10; + constant SPI_SR_Bit_RX_Underflow : integer := 11; + + constant SPI_SR_Bit_SS_n : integer := 12; + constant SPI_SR_Bit_TX_DMA_Done : integer := 13; + constant SPI_SR_Bit_RX_DMA_Done : integer := 14; + + -- Interrupt Status Register + constant SPI_ISR_Bit_TX_Prog_Empty : integer := 0; + constant SPI_ISR_Bit_TX_Empty : integer := 1; + constant SPI_ISR_Bit_TX_Underflow : integer := 2; + constant SPI_ISR_Bit_RX_Prog_Full : integer := 3; + constant SPI_ISR_Bit_RX_Full : integer := 4; + constant SPI_ISR_Bit_RX_Overflow : integer := 5; + constant SPI_ISR_Bit_SS_Fall : integer := 6; + constant SPI_ISR_Bit_SS_Rise : integer := 7; +end opb_spi_slave_pack; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC32_D32.vhd (revision 35) @@ -0,0 +1,229 @@ +----------------------------------------------------------------------- +-- File: PCK_CRC32_D32.vhd +-- Date: Tue Mar 4 19:11:40 2008 +-- +-- Copyright (C) 1999-2003 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose: VHDL package containing a synthesizable CRC function +-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +-- * data width: 32 +-- +-- Info: tools@easics.be +-- http://www.easics.com +----------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; + +package PCK_CRC32_D32 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 32 + -- convention: the first serial data bit is D(31) + function nextCRC32_D32 + ( Data: std_logic_vector(31 downto 0); + CRC: std_logic_vector(31 downto 0) ) + return std_logic_vector; + +end PCK_CRC32_D32; + +library IEEE; +use IEEE.std_logic_1164.all; + +package body PCK_CRC32_D32 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 32 + -- convention: the first serial data bit is D(31) + function nextCRC32_D32 + ( Data: std_logic_vector(31 downto 0); + CRC: std_logic_vector(31 downto 0) ) + return std_logic_vector is + + variable D: std_logic_vector(31 downto 0); + variable C: std_logic_vector(31 downto 0); + variable NewCRC: std_logic_vector(31 downto 0); + + begin + + D := Data; + C := CRC; + + NewCRC(0) := D(31) xor D(30) xor D(29) xor D(28) xor D(26) xor D(25) xor + D(24) xor D(16) xor D(12) xor D(10) xor D(9) xor D(6) xor + D(0) xor C(0) xor C(6) xor C(9) xor C(10) xor C(12) xor + C(16) xor C(24) xor C(25) xor C(26) xor C(28) xor C(29) xor + C(30) xor C(31); + NewCRC(1) := D(28) xor D(27) xor D(24) xor D(17) xor D(16) xor D(13) xor + D(12) xor D(11) xor D(9) xor D(7) xor D(6) xor D(1) xor + D(0) xor C(0) xor C(1) xor C(6) xor C(7) xor C(9) xor + C(11) xor C(12) xor C(13) xor C(16) xor C(17) xor C(24) xor + C(27) xor C(28); + NewCRC(2) := D(31) xor D(30) xor D(26) xor D(24) xor D(18) xor D(17) xor + D(16) xor D(14) xor D(13) xor D(9) xor D(8) xor D(7) xor + D(6) xor D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor + C(2) xor C(6) xor C(7) xor C(8) xor C(9) xor C(13) xor + C(14) xor C(16) xor C(17) xor C(18) xor C(24) xor C(26) xor + C(30) xor C(31); + NewCRC(3) := D(31) xor D(27) xor D(25) xor D(19) xor D(18) xor D(17) xor + D(15) xor D(14) xor D(10) xor D(9) xor D(8) xor D(7) xor + D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor + C(7) xor C(8) xor C(9) xor C(10) xor C(14) xor C(15) xor + C(17) xor C(18) xor C(19) xor C(25) xor C(27) xor C(31); + NewCRC(4) := D(31) xor D(30) xor D(29) xor D(25) xor D(24) xor D(20) xor + D(19) xor D(18) xor D(15) xor D(12) xor D(11) xor D(8) xor + D(6) xor D(4) xor D(3) xor D(2) xor D(0) xor C(0) xor + C(2) xor C(3) xor C(4) xor C(6) xor C(8) xor C(11) xor + C(12) xor C(15) xor C(18) xor C(19) xor C(20) xor C(24) xor + C(25) xor C(29) xor C(30) xor C(31); + NewCRC(5) := D(29) xor D(28) xor D(24) xor D(21) xor D(20) xor D(19) xor + D(13) xor D(10) xor D(7) xor D(6) xor D(5) xor D(4) xor + D(3) xor D(1) xor D(0) xor C(0) xor C(1) xor C(3) xor + C(4) xor C(5) xor C(6) xor C(7) xor C(10) xor C(13) xor + C(19) xor C(20) xor C(21) xor C(24) xor C(28) xor C(29); + NewCRC(6) := D(30) xor D(29) xor D(25) xor D(22) xor D(21) xor D(20) xor + D(14) xor D(11) xor D(8) xor D(7) xor D(6) xor D(5) xor + D(4) xor D(2) xor D(1) xor C(1) xor C(2) xor C(4) xor + C(5) xor C(6) xor C(7) xor C(8) xor C(11) xor C(14) xor + C(20) xor C(21) xor C(22) xor C(25) xor C(29) xor C(30); + NewCRC(7) := D(29) xor D(28) xor D(25) xor D(24) xor D(23) xor D(22) xor + D(21) xor D(16) xor D(15) xor D(10) xor D(8) xor D(7) xor + D(5) xor D(3) xor D(2) xor D(0) xor C(0) xor C(2) xor + C(3) xor C(5) xor C(7) xor C(8) xor C(10) xor C(15) xor + C(16) xor C(21) xor C(22) xor C(23) xor C(24) xor C(25) xor + C(28) xor C(29); + NewCRC(8) := D(31) xor D(28) xor D(23) xor D(22) xor D(17) xor D(12) xor + D(11) xor D(10) xor D(8) xor D(4) xor D(3) xor D(1) xor + D(0) xor C(0) xor C(1) xor C(3) xor C(4) xor C(8) xor + C(10) xor C(11) xor C(12) xor C(17) xor C(22) xor C(23) xor + C(28) xor C(31); + NewCRC(9) := D(29) xor D(24) xor D(23) xor D(18) xor D(13) xor D(12) xor + D(11) xor D(9) xor D(5) xor D(4) xor D(2) xor D(1) xor + C(1) xor C(2) xor C(4) xor C(5) xor C(9) xor C(11) xor + C(12) xor C(13) xor C(18) xor C(23) xor C(24) xor C(29); + NewCRC(10) := D(31) xor D(29) xor D(28) xor D(26) xor D(19) xor D(16) xor + D(14) xor D(13) xor D(9) xor D(5) xor D(3) xor D(2) xor + D(0) xor C(0) xor C(2) xor C(3) xor C(5) xor C(9) xor + C(13) xor C(14) xor C(16) xor C(19) xor C(26) xor C(28) xor + C(29) xor C(31); + NewCRC(11) := D(31) xor D(28) xor D(27) xor D(26) xor D(25) xor D(24) xor + D(20) xor D(17) xor D(16) xor D(15) xor D(14) xor D(12) xor + D(9) xor D(4) xor D(3) xor D(1) xor D(0) xor C(0) xor + C(1) xor C(3) xor C(4) xor C(9) xor C(12) xor C(14) xor + C(15) xor C(16) xor C(17) xor C(20) xor C(24) xor C(25) xor + C(26) xor C(27) xor C(28) xor C(31); + NewCRC(12) := D(31) xor D(30) xor D(27) xor D(24) xor D(21) xor D(18) xor + D(17) xor D(15) xor D(13) xor D(12) xor D(9) xor D(6) xor + D(5) xor D(4) xor D(2) xor D(1) xor D(0) xor C(0) xor + C(1) xor C(2) xor C(4) xor C(5) xor C(6) xor C(9) xor + C(12) xor C(13) xor C(15) xor C(17) xor C(18) xor C(21) xor + C(24) xor C(27) xor C(30) xor C(31); + NewCRC(13) := D(31) xor D(28) xor D(25) xor D(22) xor D(19) xor D(18) xor + D(16) xor D(14) xor D(13) xor D(10) xor D(7) xor D(6) xor + D(5) xor D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor + C(3) xor C(5) xor C(6) xor C(7) xor C(10) xor C(13) xor + C(14) xor C(16) xor C(18) xor C(19) xor C(22) xor C(25) xor + C(28) xor C(31); + NewCRC(14) := D(29) xor D(26) xor D(23) xor D(20) xor D(19) xor D(17) xor + D(15) xor D(14) xor D(11) xor D(8) xor D(7) xor D(6) xor + D(4) xor D(3) xor D(2) xor C(2) xor C(3) xor C(4) xor + C(6) xor C(7) xor C(8) xor C(11) xor C(14) xor C(15) xor + C(17) xor C(19) xor C(20) xor C(23) xor C(26) xor C(29); + NewCRC(15) := D(30) xor D(27) xor D(24) xor D(21) xor D(20) xor D(18) xor + D(16) xor D(15) xor D(12) xor D(9) xor D(8) xor D(7) xor + D(5) xor D(4) xor D(3) xor C(3) xor C(4) xor C(5) xor + C(7) xor C(8) xor C(9) xor C(12) xor C(15) xor C(16) xor + C(18) xor C(20) xor C(21) xor C(24) xor C(27) xor C(30); + NewCRC(16) := D(30) xor D(29) xor D(26) xor D(24) xor D(22) xor D(21) xor + D(19) xor D(17) xor D(13) xor D(12) xor D(8) xor D(5) xor + D(4) xor D(0) xor C(0) xor C(4) xor C(5) xor C(8) xor + C(12) xor C(13) xor C(17) xor C(19) xor C(21) xor C(22) xor + C(24) xor C(26) xor C(29) xor C(30); + NewCRC(17) := D(31) xor D(30) xor D(27) xor D(25) xor D(23) xor D(22) xor + D(20) xor D(18) xor D(14) xor D(13) xor D(9) xor D(6) xor + D(5) xor D(1) xor C(1) xor C(5) xor C(6) xor C(9) xor + C(13) xor C(14) xor C(18) xor C(20) xor C(22) xor C(23) xor + C(25) xor C(27) xor C(30) xor C(31); + NewCRC(18) := D(31) xor D(28) xor D(26) xor D(24) xor D(23) xor D(21) xor + D(19) xor D(15) xor D(14) xor D(10) xor D(7) xor D(6) xor + D(2) xor C(2) xor C(6) xor C(7) xor C(10) xor C(14) xor + C(15) xor C(19) xor C(21) xor C(23) xor C(24) xor C(26) xor + C(28) xor C(31); + NewCRC(19) := D(29) xor D(27) xor D(25) xor D(24) xor D(22) xor D(20) xor + D(16) xor D(15) xor D(11) xor D(8) xor D(7) xor D(3) xor + C(3) xor C(7) xor C(8) xor C(11) xor C(15) xor C(16) xor + C(20) xor C(22) xor C(24) xor C(25) xor C(27) xor C(29); + NewCRC(20) := D(30) xor D(28) xor D(26) xor D(25) xor D(23) xor D(21) xor + D(17) xor D(16) xor D(12) xor D(9) xor D(8) xor D(4) xor + C(4) xor C(8) xor C(9) xor C(12) xor C(16) xor C(17) xor + C(21) xor C(23) xor C(25) xor C(26) xor C(28) xor C(30); + NewCRC(21) := D(31) xor D(29) xor D(27) xor D(26) xor D(24) xor D(22) xor + D(18) xor D(17) xor D(13) xor D(10) xor D(9) xor D(5) xor + C(5) xor C(9) xor C(10) xor C(13) xor C(17) xor C(18) xor + C(22) xor C(24) xor C(26) xor C(27) xor C(29) xor C(31); + NewCRC(22) := D(31) xor D(29) xor D(27) xor D(26) xor D(24) xor D(23) xor + D(19) xor D(18) xor D(16) xor D(14) xor D(12) xor D(11) xor + D(9) xor D(0) xor C(0) xor C(9) xor C(11) xor C(12) xor + C(14) xor C(16) xor C(18) xor C(19) xor C(23) xor C(24) xor + C(26) xor C(27) xor C(29) xor C(31); + NewCRC(23) := D(31) xor D(29) xor D(27) xor D(26) xor D(20) xor D(19) xor + D(17) xor D(16) xor D(15) xor D(13) xor D(9) xor D(6) xor + D(1) xor D(0) xor C(0) xor C(1) xor C(6) xor C(9) xor + C(13) xor C(15) xor C(16) xor C(17) xor C(19) xor C(20) xor + C(26) xor C(27) xor C(29) xor C(31); + NewCRC(24) := D(30) xor D(28) xor D(27) xor D(21) xor D(20) xor D(18) xor + D(17) xor D(16) xor D(14) xor D(10) xor D(7) xor D(2) xor + D(1) xor C(1) xor C(2) xor C(7) xor C(10) xor C(14) xor + C(16) xor C(17) xor C(18) xor C(20) xor C(21) xor C(27) xor + C(28) xor C(30); + NewCRC(25) := D(31) xor D(29) xor D(28) xor D(22) xor D(21) xor D(19) xor + D(18) xor D(17) xor D(15) xor D(11) xor D(8) xor D(3) xor + D(2) xor C(2) xor C(3) xor C(8) xor C(11) xor C(15) xor + C(17) xor C(18) xor C(19) xor C(21) xor C(22) xor C(28) xor + C(29) xor C(31); + NewCRC(26) := D(31) xor D(28) xor D(26) xor D(25) xor D(24) xor D(23) xor + D(22) xor D(20) xor D(19) xor D(18) xor D(10) xor D(6) xor + D(4) xor D(3) xor D(0) xor C(0) xor C(3) xor C(4) xor + C(6) xor C(10) xor C(18) xor C(19) xor C(20) xor C(22) xor + C(23) xor C(24) xor C(25) xor C(26) xor C(28) xor C(31); + NewCRC(27) := D(29) xor D(27) xor D(26) xor D(25) xor D(24) xor D(23) xor + D(21) xor D(20) xor D(19) xor D(11) xor D(7) xor D(5) xor + D(4) xor D(1) xor C(1) xor C(4) xor C(5) xor C(7) xor + C(11) xor C(19) xor C(20) xor C(21) xor C(23) xor C(24) xor + C(25) xor C(26) xor C(27) xor C(29); + NewCRC(28) := D(30) xor D(28) xor D(27) xor D(26) xor D(25) xor D(24) xor + D(22) xor D(21) xor D(20) xor D(12) xor D(8) xor D(6) xor + D(5) xor D(2) xor C(2) xor C(5) xor C(6) xor C(8) xor + C(12) xor C(20) xor C(21) xor C(22) xor C(24) xor C(25) xor + C(26) xor C(27) xor C(28) xor C(30); + NewCRC(29) := D(31) xor D(29) xor D(28) xor D(27) xor D(26) xor D(25) xor + D(23) xor D(22) xor D(21) xor D(13) xor D(9) xor D(7) xor + D(6) xor D(3) xor C(3) xor C(6) xor C(7) xor C(9) xor + C(13) xor C(21) xor C(22) xor C(23) xor C(25) xor C(26) xor + C(27) xor C(28) xor C(29) xor C(31); + NewCRC(30) := D(30) xor D(29) xor D(28) xor D(27) xor D(26) xor D(24) xor + D(23) xor D(22) xor D(14) xor D(10) xor D(8) xor D(7) xor + D(4) xor C(4) xor C(7) xor C(8) xor C(10) xor C(14) xor + C(22) xor C(23) xor C(24) xor C(26) xor C(27) xor C(28) xor + C(29) xor C(30); + NewCRC(31) := D(31) xor D(30) xor D(29) xor D(28) xor D(27) xor D(25) xor + D(24) xor D(23) xor D(15) xor D(11) xor D(9) xor D(8) xor + D(5) xor C(5) xor C(8) xor C(9) xor C(11) xor C(15) xor + C(23) xor C(24) xor C(25) xor C(27) xor C(28) xor C(29) xor + C(30) xor C(31); + + return NewCRC; + + end nextCRC32_D32; + +end PCK_CRC32_D32; + Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/PCK_CRC8_D8.vhd (revision 35) @@ -0,0 +1,77 @@ +----------------------------------------------------------------------- +-- File: PCK_CRC8_D8.vhd +-- Date: Fri Mar 21 22:28:05 2008 +-- +-- Copyright (C) 1999-2003 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose: VHDL package containing a synthesizable CRC function +-- * polynomial: (0 1 2 8) +-- * data width: 8 +-- +-- Info: tools@easics.be +-- http://www.easics.com +----------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; + +package PCK_CRC8_D8 is + + -- polynomial: (0 1 2 8) + -- data width: 8 + -- convention: the first serial data bit is D(7) + function nextCRC8_D8 + ( Data: std_logic_vector(7 downto 0); + CRC: std_logic_vector(7 downto 0) ) + return std_logic_vector; + +end PCK_CRC8_D8; + +library IEEE; +use IEEE.std_logic_1164.all; + +package body PCK_CRC8_D8 is + + -- polynomial: (0 1 2 8) + -- data width: 8 + -- convention: the first serial data bit is D(7) + function nextCRC8_D8 + ( Data: std_logic_vector(7 downto 0); + CRC: std_logic_vector(7 downto 0) ) + return std_logic_vector is + + variable D: std_logic_vector(7 downto 0); + variable C: std_logic_vector(7 downto 0); + variable NewCRC: std_logic_vector(7 downto 0); + + begin + + D := Data; + C := CRC; + + NewCRC(0) := D(7) xor D(6) xor D(0) xor C(0) xor C(6) xor C(7); + NewCRC(1) := D(6) xor D(1) xor D(0) xor C(0) xor C(1) xor C(6); + NewCRC(2) := D(6) xor D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor + C(2) xor C(6); + NewCRC(3) := D(7) xor D(3) xor D(2) xor D(1) xor C(1) xor C(2) xor + C(3) xor C(7); + NewCRC(4) := D(4) xor D(3) xor D(2) xor C(2) xor C(3) xor C(4); + NewCRC(5) := D(5) xor D(4) xor D(3) xor C(3) xor C(4) xor C(5); + NewCRC(6) := D(6) xor D(5) xor D(4) xor C(4) xor C(5) xor C(6); + NewCRC(7) := D(7) xor D(6) xor D(5) xor C(5) xor C(6) xor C(7); + + return NewCRC; + + end nextCRC8_D8; + +end PCK_CRC8_D8; + Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (revision 35) @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +--* +--* @short Shift-Register +--* +--* Control Register Description: +--* @li Bit0: DGE : Global Device Enable +--* @li Bit1: TX_EN: Transmit enable +--* @li Bit2: RX_EN: Receive enable +--* +--* Generics described in top entity. +--* @port opb_ctl_reg Control Register +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.1 +--* @date: 2007-11-11 +--/ +-- Version 1.0 Initial Release +-- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH +-- Version 1.2 removed delays for simulation +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.opb_spi_slave_pack.all; + +entity shift_register is + + generic ( + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0); + + port ( + rst : in std_logic; + -- control register + opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + -- external + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + -- transmit fifo + sr_tx_clk : out std_logic; + sr_tx_en : out std_logic; + sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- receive fifo + sr_rx_clk : out std_logic; + sr_rx_en : out std_logic; + sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); +end shift_register; + + +architecture behavior of shift_register is + --* Global + signal sclk_int : std_logic; + signal sclk_int_inv : std_logic; + signal rx_cnt : integer range 0 to 31 := 0; + + -- RX + signal rx_sr_reg : std_logic_vector(C_SR_WIDTH-2 downto 0); + signal sr_rx_en_int : std_logic; + signal sr_rx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + + -- tx + signal miso_int : std_logic; + signal tx_cnt : integer range 0 to 31 := 0; + signal sr_tx_en_int : std_logic; + signal sr_tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + + +begin -- behavior + + miso_t <= ss_n; -- tristate + + + sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else + sclk when (C_PHA = 1 and C_CPOL = 1) else + not sclk; + + + sr_rx_en <= sr_rx_en_int; + sr_tx_en <= sr_tx_en_int; + + --* reorder received bits if not "MSB_First" + reorder_rx_bits : process(sr_rx_data_int) + begin + for i in 0 to C_SR_WIDTH-1 loop + if C_MSB_FIRST then + sr_rx_data(i) <= sr_rx_data_int(i); + else + sr_rx_data(C_SR_WIDTH-1-i) <= sr_rx_data_int(i); + end if; + end loop; -- i + end process reorder_rx_bits; + + --* reorder transmit bits if not "MSB_First" + reorder_tx_bits : process(sr_tx_data) + begin + for i in 0 to C_SR_WIDTH-1 loop + if C_MSB_FIRST then + sr_tx_data_int(i) <= sr_tx_data(i); + else + sr_tx_data_int(C_SR_WIDTH-1-i) <= sr_tx_data(i); + end if; + end loop; -- i + end process reorder_tx_bits; + + + ----------------------------------------------------------------------------- + + sr_rx_clk <= sclk_int; + + sr_rx_data_int <= rx_sr_reg & mosi; + + --* RX-Shift-Register + rx_shift_proc : process(rst, opb_ctl_reg, sclk_int) + begin + if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_RX_EN) = '0') then + rx_cnt <= 0; + sr_rx_en_int <= '0'; + rx_sr_reg <= (others => '0'); + + elsif rising_edge(sclk_int) then + if (ss_n = '0') then + rx_sr_reg <= rx_sr_reg(C_SR_WIDTH-3 downto 0) & mosi; + if (rx_cnt = C_SR_WIDTH-2) then + rx_cnt <= rx_cnt +1; + sr_rx_en_int <= '1'; + elsif (rx_cnt = C_SR_WIDTH-1) then + rx_cnt <= 0; + sr_rx_en_int <= '0'; + else + rx_cnt <= rx_cnt +1; + end if; + else + -- ss_n high + -- assert framing error if cnt != 0? + sr_rx_en_int <= '0'; + rx_cnt <= 0; + end if; + end if; + end process rx_shift_proc; + +------------------------------------------------------------------------------- + -- TX Shift Register + sr_tx_clk <= sclk_int_inv; + sclk_int_inv <= not sclk_int; + + miso_o <= sr_tx_data_int(C_SR_WIDTH-1) when (tx_cnt = 0) else + miso_int; + + + --* TX Shift-Register + tx_shift_proc : process(rst, opb_ctl_reg, sclk_int_inv) + begin + if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_TX_EN) = '0') then + tx_cnt <= 0; + sr_tx_en_int <= '0'; + miso_int <= '0'; + elsif rising_edge(sclk_int_inv) then + if (ss_n = '0') then + if (tx_cnt /= C_SR_WIDTH-1) then + miso_int <= sr_tx_data_int(C_SR_WIDTH-1-(tx_cnt+1)); + end if; + if (tx_cnt = C_SR_WIDTH-2) then + sr_tx_en_int <= '1'; + tx_cnt <= tx_cnt +1; + elsif (tx_cnt = C_SR_WIDTH-1) then + tx_cnt <= 0; + sr_tx_en_int <= '0'; + else + tx_cnt <= tx_cnt +1; + end if; + else + -- ss_n high + -- assert framing error if cnt != 0? + sr_tx_en_int <= '0'; + tx_cnt <= 0; + end if; + end if; + end process tx_shift_proc; +------------------------------------------------------------------------------- + + end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (revision 35) @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------- +--* +--* @short Control Unit for IRQ detection, enable and clear +--* +--* @generic C_ACTIVE_EDGE Select active edge for IRQ-Source 0: H->L;1: L->H +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +-- Version 1.1 +-- Bugfix +-- added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent +-- metastability +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +entity irq_ctl is + generic ( + C_ACTIVE_EDGE : std_logic := '0'); + port ( + rst : in std_logic; + clk : in std_logic; + opb_fifo_flg : in std_logic; + opb_ier : in std_logic; + opb_isr : out std_logic; + opb_isr_clr : in std_logic); + +end irq_ctl; + +architecture behavior of irq_ctl is + + signal opb_fifo_flg_int : std_logic; + -- Sync to clock domain register + signal opb_fifo_flg_int_r0 : std_logic; + signal opb_fifo_flg_int_r1 : std_logic; + + + signal opb_fifo_flg_reg : std_logic; +begin -- behavior + + opb_fifo_flg_int_r0 <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else + not opb_fifo_flg; + + irq_ctl_proc : process(rst, clk) + begin + if (rst = '1') then + opb_isr <= '0'; + elsif rising_edge(clk) then + -- sync to clock domain + opb_fifo_flg_int_r1 <= opb_fifo_flg_int_r0; + opb_fifo_flg_int <= opb_fifo_flg_int_r1; + + opb_fifo_flg_reg <= opb_fifo_flg_int; + if (opb_ier = '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then + opb_isr <= '1'; + elsif (opb_isr_clr = '1') then + opb_isr <= '0'; + end if; + end if; + end process irq_ctl_proc; + + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (revision 35) @@ -0,0 +1,46 @@ +------------------------------------------------------------------------------- +--* +--* @short RAM Sync-Write, Async Read +--* +--* @generic C_FIFO_WIDTH RAM-With (1..xx) +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity ram is + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4); + + port (clk : in std_logic; + we : in std_logic; + a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); +end ram; + +architecture behavior of ram is + type ram_type is array (2**C_FIFO_SIZE_WIDTH-1 downto 0) of std_logic_vector (C_FIFO_WIDTH-1 downto 0); + signal RAM : ram_type; +begin + + process (clk) + begin + if (clk'event and clk = '1') then + if (we = '1') then + RAM(conv_integer(a)) <= di; + end if; + end if; + end process; + + dpo <= RAM(conv_integer(dpra)); + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (revision 35) @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------- +--* +--* @short gray Adder +--* +--* @generic width with of adder vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity gray_adder is + generic ( + width : integer := 4); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); +end gray_adder; + +architecture behavior of gray_adder is + --* convert gray to bin + component gray2bin + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); + end component; + --* convert bin to gray + component bin2gray + generic ( + width : integer); + port ( + in_bin : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + signal out_bin : std_logic_vector(width-1 downto 0); + signal bin_add : std_logic_vector(width-1 downto 0); + +begin -- behavior + --* convert input gray signal to binary + gray2bin_1 : gray2bin + generic map ( + width => width) + port map ( + in_gray => in_gray, + out_bin => out_bin); + + --* add one to signal + bin_add <= out_bin + 1; + --* convert signal back to gray + bin2gray_1 : bin2gray + generic map ( + width => width) + port map ( + in_bin => bin_add, + out_gray => out_gray); + + + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (revision 35) @@ -0,0 +1,262 @@ +------------------------------------------------------------------------------- +--* +--* @short Configurable FIFO +--* +--* @generic C_FIFO_WIDTH RAM-With (1..xx) +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* @generic C_SYNC_TO Sync FIFO Flags to read or write clock +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +entity fifo is + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4; + C_SYNC_TO : string := "RD"); + port ( + rst : in std_logic; + -- write port + wr_clk : in std_logic; + wr_en : in std_logic; + din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + -- read port + rd_clk : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); + -- flags + empty : out std_logic; + full : out std_logic; + overflow : out std_logic; + underflow : out std_logic; + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + +end fifo; + +architecture behavior of fifo is + --* ram with sync write and async read + component ram + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4); + port ( + clk : in std_logic; + we : in std_logic; + a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); + end component; + + --* component generates fifo flag + component fifo_prog_flags + generic ( + C_FIFO_SIZE_WIDTH : integer; + C_SYNC_TO : string); + port ( + rst : in std_logic; + clk : in std_logic; + cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + end component; + + --* logic coded gray counter + component gray_adder + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + signal wr_cnt_gray_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal wr_cnt_next_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal rd_cnt_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + attribute fsm_extract : string; + -- wr_clock domain + -- main wr grey code counter + signal wr_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of wr_cnt_grey : signal is "no"; + + -- main grey code counter for full + signal wr_cnt_next_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of wr_cnt_next_grey : signal is "no"; + + -- rd_clk domain + -- main rd grey code counter + signal rd_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of rd_cnt_grey : signal is "no"; + + -- binary counter for prog full/empty + signal rd_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal wr_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + signal empty_int : std_logic; + signal full_int : std_logic; + +begin -- behavior + + empty <= empty_int; + full <= full_int; + +--* write counter generation + fifo_write_proc: process(rst, wr_clk) + begin + if (rst = '1') then + wr_cnt_grey <= (others => '0'); + wr_cnt <= (others => '0'); + wr_cnt_next_grey(C_FIFO_SIZE_WIDTH-1 downto 1) <= (others => '0'); + wr_cnt_next_grey(0) <= '1'; + elsif rising_edge(wr_clk) then + if (wr_en = '1') then + wr_cnt <= wr_cnt+1; + + -- wr_cnt_grey <= add_grey_rom(conv_integer(wr_cnt_grey)); + wr_cnt_grey <= wr_cnt_gray_add_one; + + -- wr_cnt_next_grey <= add_grey_rom(conv_integer(wr_cnt_next_grey)); + wr_cnt_next_grey <= wr_cnt_next_grey_add_one; + + end if; + end if; + end process fifo_write_proc; + + --* add one to wr_cnt_gray + gray_adder_1 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => wr_cnt_grey, + out_gray => wr_cnt_gray_add_one); + + --* add one to wr_cnt_next_grey + gray_adder_2 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => wr_cnt_next_grey, + out_gray => wr_cnt_next_grey_add_one); + + +--* read counter generation + fifo_read_proc: process(rst, rd_clk) + begin + if (rst = '1') then + rd_cnt_grey <= (others => '0'); + rd_cnt <= (others => '0'); + elsif rising_edge(rd_clk) then + -- rd grey code counter + if (rd_en = '1') then + -- rd_cnt_grey <= add_grey_rom(conv_integer(rd_cnt_grey)); + rd_cnt_grey <= rd_cnt_grey_add_one; + rd_cnt <= rd_cnt+1; + end if; + end if; + end process fifo_read_proc; + + --* add one to rd_cnt_grey + gray_adder_3 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => rd_cnt_grey, + out_gray => rd_cnt_grey_add_one); + + + --* FIFO Memory + ram_1 : ram + generic map ( + C_FIFO_WIDTH => C_FIFO_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) + port map ( + clk => wr_clk, + we => wr_en, + a => wr_cnt_grey, + di => din, + dpra => rd_cnt_grey, + dpo => dout); + + + --* generate overflow + gen_of_proc: process(rst, wr_clk) + begin + if (rst = '1') then + overflow <= '0'; + elsif rising_edge(wr_clk) then + if (full_int = '1' and wr_en = '1') then + overflow <= '1'; + end if; + end if; + end process gen_of_proc; + + --* generate underflow + gen_uf_proc: process(rst, rd_clk) + begin + if (rst = '1') then + underflow <= '0'; + elsif rising_edge(rd_clk) then + if (empty_int = '1' and rd_en = '1') then + underflow <= '1'; + end if; + end if; + end process gen_uf_proc; + + -- generate empty + empty_int <= '1' when (wr_cnt_grey = rd_cnt_grey) else + '0'; + + -- generate full + full_int <= '1' when (wr_cnt_next_grey = rd_cnt_grey) else + '0'; + + --* select clock side for flags + u1 : if (C_SYNC_TO = "WR") generate + --* sync flags to write clock + fifo_prog_flags_1 : fifo_prog_flags + generic map ( + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => C_SYNC_TO) + port map ( + rst => rst, + clk => wr_clk, + cnt_grey => rd_cnt_grey, + cnt => wr_cnt, + prog_full_thresh => prog_full_thresh, + prog_empty_thresh => prog_empty_thresh, + prog_empty => prog_empty, + prog_full => prog_full); + end generate u1; + + u2 : if (C_SYNC_TO = "RD") generate + --* sync flags to read clock + fifo_prog_flags_1 : fifo_prog_flags + generic map ( + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => C_SYNC_TO) + port map ( + rst => rst, + clk => rd_clk, + cnt_grey => wr_cnt_grey, + cnt => rd_cnt, + prog_full_thresh => prog_full_thresh, + prog_empty_thresh => prog_empty_thresh, + prog_empty => prog_empty, + prog_full => prog_full); + end generate u2; +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (revision 35) @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +--* +--* @short Generate fifo flags +--* +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* @generic C_SYNC_TO Sync FIFO Flags to read or write clock +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +entity fifo_prog_flags is + generic ( + C_FIFO_SIZE_WIDTH : integer := 4; + C_SYNC_TO : string := "WR"); + port ( + rst : in std_logic; + clk : in std_logic; + cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + +end fifo_prog_flags; +architecture behavior of fifo_prog_flags is + + -- sync register for clock domain transfer + signal cnt_grey_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + type rom_t is array (0 to (2**C_FIFO_SIZE_WIDTH)-1) of std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + --* convert from gray to binary + component gray2bin + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); + end component; + + signal cnt_bin_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + +begin -- behavior + + --* Generate fifo flags + gen_flags_proc: process(rst, clk) + variable diff : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + begin + if (rst = '1') then + cnt_grey_reg <= (others => '0'); + prog_empty <= '1'; + prog_full <= '0'; + elsif rising_edge(clk) then + -- transfer to rd_clk domain + cnt_grey_reg <= cnt_grey; + -- fifo prog full/empty + if (C_SYNC_TO = "RD") then + -- diff := conv_grey_rom(conv_integer(cnt_grey_reg))- cnt; + diff := cnt_bin_reg - cnt; + else + -- diff := cnt - conv_grey_rom(conv_integer(cnt_grey_reg)); + diff := cnt - cnt_bin_reg; + end if; + + if (diff > prog_full_thresh) then + prog_full <= '1'; + else + prog_full <= '0'; + end if; + + if (diff < prog_empty_thresh) then + prog_empty <= '1'; + else + prog_empty <= '0'; + end if; + end if; + end process gen_flags_proc; + + --* convert gray to bin + gray2bin_1: gray2bin + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => cnt_grey_reg, + out_bin => cnt_bin_reg); + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (revision 35) @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------- +--* +--* @short convert binary input vector to gray +--* +--* @generic width with of input vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity bin2gray is + generic ( + width : integer := 4); + port ( + in_bin : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); +end bin2gray; + +architecture behavior of bin2gray is + +begin -- behavior + + -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 + --* convert binary input vector to gray + bin2gray_proc : process(in_bin) + begin + out_gray(width-1) <= in_bin(width-1); + -- out_gray(3) <= in_bin(3); + + for i in 1 to width-1 loop + out_gray(width-1-i) <= in_bin(width-i) xor in_bin(width-1-i); + end loop; -- i + end process bin2gray_proc; + + -- i=1 out_gray(2) <= in_bin(3) xor in_bin(2); + -- i=2 out_gray(1) <= in_bin(2) xor in_bin(1); + -- i=3 out_gray(0) <= in_bin(1) xor in_bin(0); + +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (revision 35) @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------- +--* +--* @short convert gray input vector to binary +--* +--* @generic width with of input vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity gray2bin is + generic ( + width : integer := 4); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); +end gray2bin; + +architecture behavior of gray2bin is + + signal out_bin_int : std_logic_vector(width-1 downto 0); +begin -- behavior + + out_bin <= out_bin_int; + + -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 + --* convert gray input vector to binary + gray2bin_proc: process(in_gray, out_bin_int) + begin + out_bin_int(width-1) <= in_gray(width-1); + -- out_gray(3) <= in_gray(3); + for i in 1 to width-1 loop + out_bin_int(width-1-i) <= out_bin_int(width-i) xor in_gray(width-1-i); + end loop ; -- i + end process gray2bin_proc; + -- i=1 out_bin(2) <= out_bin_int(3) xor out_bin(2); + -- i=2 out_bin(1) <= out_bin_int(2) xor out_bin(1); + -- i=3 out_bin(0) <= out_bin_int(1) xor out_bin(0); +end behavior; Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (revision 35) @@ -0,0 +1,21 @@ +############################################################################## +## Filename: E:\Eigene_Dateien\Entwicklung\cpld\spi-core\edk\test_opb_spi_slave\pcores/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Mon Oct 29 20:54:19 2007 (by Create and Import Peripheral Wizard) +############################################################################## + +lib opb_spi_slave_v1_00_a opb_spi_slave_pack vhdl +lib opb_spi_slave_v1_00_a shift_register vhdl +lib opb_spi_slave_v1_00_a bin2gray vhdl +lib opb_spi_slave_v1_00_a gray2bin vhdl +lib opb_spi_slave_v1_00_a gray_adder vhdl +lib opb_spi_slave_v1_00_a fifo vhdl +lib opb_spi_slave_v1_00_a fifo_prog_flags vhdl +lib opb_spi_slave_v1_00_a irq_ctl vhdl +lib opb_spi_slave_v1_00_a opb_m_if vhdl +lib opb_spi_slave_v1_00_a opb_if vhdl +lib opb_spi_slave_v1_00_a PCK_CRC32_D32.vhd vhdl +lib opb_spi_slave_v1_00_a crc_gen.vhd vhdl +lib opb_spi_slave_v1_00_a ram vhdl +lib opb_spi_slave_v1_00_a opb_spi_slave vhdl + Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (revision 35) @@ -0,0 +1,73 @@ +################################################################### +## +## Name : opb_spi_slave +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN opb_spi_slave + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VHDL +OPTION CORE_STATE = ACTIVE +OPTION IP_GROUP = MICROBLAZE:PPC:USER + + +## Bus Interfaces +BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80 +PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR +PARAMETER C_USER_ID_CODE = 0, DT = INTEGER +PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB +PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB +PARAMETER C_FAMILY = virtex-4, DT = STRING +PARAMETER C_SR_WIDTH = 8, DT = INTEGER +PARAMETER C_MSB_FIRST = true, DT = BOOLEAN +PARAMETER C_CPOL = 0, DT = INTEGER +PARAMETER C_PHA = 0, DT = INTEGER +PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER +PARAMETER C_DMA_EN = true, DT = BOOLEAN +PARAMETER C_CRC_EN = true, DT = BOOLEAN + +## Ports +PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB +PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB +PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK +PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB +PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST +PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB +PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB +PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB +PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB +PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB +PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB +PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB +PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB +PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB +PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT M_request = M_request, DIR = O, BUS = MSOPB +PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB +PORT M_select = M_select, DIR = O, BUS = MSOPB +PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB +PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB +PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB +PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB +PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB +PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB +PORT sclk = "", DIR = I, SIGIS = CLK +PORT ss_n = "", DIR = I +PORT mosi = "", DIR = I +PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T +PORT miso_o = "", DIR = O +PORT miso_i = "", DIR = I +PORT miso_t = "", DIR = O +PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH + +END Index: spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf =================================================================== --- spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (nonexistent) +++ spi_slave/trunk/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (revision 35) @@ -0,0 +1,7 @@ +NET "mosi" TNM = "_mosi"; +TIMEGRP "_mosi" OFFSET = IN 5 ns VALID 10 ns BEFORE "sclk" HIGH ; + +NET "miso_o" TNM = "_miso_o"; +TIMEGRP "_miso_o" OFFSET = OUT 10 ns AFTER "sclk" LOW ; + + Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_c.do (revision 35) @@ -0,0 +1,12 @@ +vlib work +# packages +vcom -93 ../../../../../bench/vhdl/images-body.vhd +vcom -93 ../../../../../bench/vhdl/txt_util.vhd +# DUT +vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd +vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd +vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd +vcom -93 ../../../../../rtl/vhdl/crc_core.vhd + +# Testbench +vcom -93 ../../../../../bench/vhdl/crc_core_tb.vhd \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps crc_core_tb +view wave +do crc_core_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/crc_core/crc_core_tb_w.do (revision 35) @@ -0,0 +1,35 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /crc_core_tb/rst +add wave -noupdate -format Logic /crc_core_tb/opb_clk +add wave -noupdate -format Logic /crc_core_tb/crc_clr +add wave -noupdate -format Logic /crc_core_tb/opb_m_last_block +add wave -noupdate -divider RX +add wave -noupdate -format Logic /crc_core_tb/fifo_rx_en +add wave -noupdate -format Literal /crc_core_tb/fifo_rx_data +add wave -noupdate -format Literal /crc_core_tb/opb_rx_crc_value +add wave -noupdate -divider TX +add wave -noupdate -format Logic /crc_core_tb/fifo_tx_en +add wave -noupdate -format Literal /crc_core_tb/fifo_tx_data +add wave -noupdate -format Logic /crc_core_tb/tx_crc_insert +add wave -noupdate -format Literal /crc_core_tb/opb_tx_crc_value +add wave -noupdate -divider Internal +add wave -noupdate -format Literal /crc_core_tb/dut/state +add wave -noupdate -format Logic /crc_core_tb/dut/rx_crc_en +add wave -noupdate -format Logic /crc_core_tb/dut/tx_crc_en +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {493567 ps} 0} +configure wave -namecolwidth 211 +configure wave -valuecolwidth 169 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {582750 ps} Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do (revision 35) @@ -0,0 +1,24 @@ +vlib work +# packages +vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd + +# DUT +vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd +vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd +vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd +vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd +vcom -93 ../../../../../rtl/vhdl/ram.vhd +vcom -93 ../../../../../rtl/vhdl/fifo.vhd +vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd +vcom -93 ../../../../../rtl/vhdl/opb_if.vhd +vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd +vcom -93 ../../../../../rtl/vhdl/shift_register.vhd +vcom -93 ../../../../../rtl/vhdl/irq_ctl.vhd +vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd +vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd +vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd +vcom -93 ../../../../../rtl/vhdl/crc_core.vhd +vcom -93 ../../../../../rtl/vhdl/opb_spi_slave.vhd + +# Testbench +vcom -93 ../../../../../bench/vhdl/opb_spi_slave_tb.vhd \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do (revision 35) @@ -0,0 +1,64 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider OPB-Bus +add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rst +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_abus +add wave -noupdate -format Literal /opb_spi_slave_tb/opb_be +add wave -noupdate -format Logic /opb_spi_slave_tb/opb_clk +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_dbus +add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rnw +add wave -noupdate -format Logic /opb_spi_slave_tb/opb_select +add wave -noupdate -format Logic /opb_spi_slave_tb/opb_seqaddr +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/sln_dbus +add wave -noupdate -format Logic /opb_spi_slave_tb/sln_xferack +add wave -noupdate -divider SPI +add wave -noupdate -format Logic /opb_spi_slave_tb/sclk +add wave -noupdate -format Logic /opb_spi_slave_tb/ss_n +add wave -noupdate -format Logic /opb_spi_slave_tb/mosi +add wave -noupdate -format Logic /opb_spi_slave_tb/miso +add wave -noupdate -divider Internal +add wave -noupdate -format Literal /opb_spi_slave_tb/opb_read_data +add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/dout +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_thresh +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/rx_thresh +add wave -noupdate -format Literal /opb_spi_slave_tb/spi_value_in +add wave -noupdate -divider TX_FIFO +add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_full_thresh +add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty_thresh +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_clk +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_en +add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_fifo_1/din +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/empty +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/underflow +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_full +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/full +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/overflow +add wave -noupdate -divider RX_FIFO +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_clk +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_en +add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/din +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/empty +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_empty +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/underflow +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_full +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/full +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/overflow +add wave -noupdate -divider Internal +add wave -noupdate -format Logic /opb_spi_slave_tb/dut/opb_abort_flg +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {525982512 ps} 0} +configure wave -namecolwidth 302 +configure wave -valuecolwidth 53 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {568438500 ps} Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps opb_spi_slave_tb +view wave +do opb_spi_slave_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_c.do (revision 35) @@ -0,0 +1,9 @@ +vlib work +# packages +vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd +# DUT +vcom -93 ../../../../../rtl/vhdl/shift_register.vhd +# Testbench +vcom -93 ../../../../../bench/vhdl/tx_fifo_emu.vhd +vcom -93 ../../../../../bench/vhdl/rx_fifo_emu.vhd +vcom -93 ../../../../../bench/vhdl/shift_register_tb.vhd \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps shift_register_tb +view wave +do shift_register_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/shift_register/shift_register_tb_w.do (revision 35) @@ -0,0 +1,36 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Literal /shift_register_tb/test_num +add wave -noupdate -format Logic /shift_register_tb/s_rst +add wave -noupdate -divider External +add wave -noupdate -format Logic /shift_register_tb/s_sclk +add wave -noupdate -format Logic /shift_register_tb/s_cs_n +add wave -noupdate -format Logic /shift_register_tb/s_mosi +add wave -noupdate -format Logic /shift_register_tb/s_miso_o +add wave -noupdate -format Logic /shift_register_tb/s_miso_i +add wave -noupdate -format Logic /shift_register_tb/s_miso_t +add wave -noupdate -divider TX-FIFO +add wave -noupdate -format Logic /shift_register_tb/s_tx_clk +add wave -noupdate -format Logic /shift_register_tb/s_tx_en +add wave -noupdate -format Literal -radix unsigned /shift_register_tb/s_tx_data +add wave -noupdate -divider RX-FIFO +add wave -noupdate -format Logic /shift_register_tb/s_rx_clk +add wave -noupdate -format Logic /shift_register_tb/s_rx_en +add wave -noupdate -format Literal /shift_register_tb/s_rx_data +add wave -noupdate -divider Internal +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {62874 ps} 0} +configure wave -namecolwidth 281 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {3570 ns} Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_w.do (revision 35) @@ -0,0 +1,35 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_empty_thresh +add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_full_thresh +add wave -noupdate -divider {write port} +add wave -noupdate -format Logic /fifo_tb/wr_clk +add wave -noupdate -format Logic /fifo_tb/wr_en +add wave -noupdate -format Literal /fifo_tb/din +add wave -noupdate -divider read_port +add wave -noupdate -format Logic /fifo_tb/rd_clk +add wave -noupdate -format Logic /fifo_tb/rd_en +add wave -noupdate -format Literal /fifo_tb/dout +add wave -noupdate -divider flags +add wave -noupdate -format Logic /fifo_tb/prog_empty +add wave -noupdate -format Logic /fifo_tb/empty +add wave -noupdate -format Logic /fifo_tb/underflow +add wave -noupdate -format Logic /fifo_tb/prog_full +add wave -noupdate -format Logic /fifo_tb/full +add wave -noupdate -format Logic /fifo_tb/overflow +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {387500 ps} 0} +configure wave -namecolwidth 192 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {1160250 ps} Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_c.do (revision 35) @@ -0,0 +1,13 @@ +vlib work +# packages +vcom -93 ../../../../../bench/vhdl/images-body.vhd +vcom -93 ../../../../../bench/vhdl/txt_util.vhd +# DUT +vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd +vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd +vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd +vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd +vcom -93 ../../../../../rtl/vhdl/ram.vhd +vcom -93 ../../../../../rtl/vhdl/fifo.vhd +# Testbench +vcom -93 ../../../../../bench/vhdl/fifo_tb.vhd \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/fifo/fifo_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps fifo_tb +view wave +do fifo_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/grey_adder/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (revision 35) @@ -0,0 +1,7 @@ +vlib work +# packages +vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd +# DUT +vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd +# Testbench +vcom -93 ../../../../../bench/vhdl/opb_m_if_tb.vhd \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps opb_m_if_tb +view wave +do opb_m_if_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (revision 35) @@ -0,0 +1,53 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider Internal +add wave -noupdate -format Logic /opb_m_if_tb/opb_clk +add wave -noupdate -format Logic /opb_m_if_tb/opb_rst +add wave -noupdate -format Logic /opb_m_if_tb/m_request +add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant +add wave -noupdate -format Logic /opb_m_if_tb/m_buslock +add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr +add wave -noupdate -format Logic /opb_m_if_tb/m_select +add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack +add wave -noupdate -format Literal /opb_m_if_tb/m_be +add wave -noupdate -format Logic /opb_m_if_tb/m_rnw +add wave -noupdate -format Literal /opb_m_if_tb/m_abus +add wave -noupdate -format Literal /opb_m_if_tb/m_dbus +add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus +add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry +add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout +add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack +add wave -noupdate -divider T-FIFIO +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data +add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl +add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr +add wave -noupdate -divider R-FIFO +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data +add wave -noupdate -divider Internal +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_if_2/read_transfer +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/state +add wave -noupdate -format Literal -radix hexadecimal /opb_m_if_tb/opb_m_if_2/opb_tx_dma_addr_int +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/opb_rx_dma_addr_int +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1332415 ps} 0} +configure wave -namecolwidth 276 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {1055780 ps} Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/irq_ctl/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/work/.keepdir =================================================================== Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_c.do (revision 35) @@ -0,0 +1,8 @@ +vlib work +# packages +vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd +# DUT +vcom -93 ../../../../../rtl/vhdl/opb_if.vhd +# Testbench +vcom -93 ../../../../../bench/vhdl/opb_if_tb.vhd + Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_s.do (revision 35) @@ -0,0 +1,4 @@ +vsim -t ps opb_if_tb +view wave +do opb_if_tb_w.do +run -all \ No newline at end of file Index: spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do =================================================================== --- spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do (nonexistent) +++ spi_slave/trunk/sim/rtl_sim/modelsim_sim/run/opb_if/opb_if_tb_w.do (revision 35) @@ -0,0 +1,49 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider Internal +add wave -noupdate -format Logic /opb_m_if_tb/opb_clk +add wave -noupdate -format Logic /opb_m_if_tb/opb_rst +add wave -noupdate -format Logic /opb_m_if_tb/m_request +add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant +add wave -noupdate -format Logic /opb_m_if_tb/m_buslock +add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr +add wave -noupdate -format Logic /opb_m_if_tb/m_select +add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack +add wave -noupdate -format Literal /opb_m_if_tb/m_be +add wave -noupdate -format Logic /opb_m_if_tb/m_rnw +add wave -noupdate -format Literal /opb_m_if_tb/m_abus +add wave -noupdate -format Literal /opb_m_if_tb/m_dbus +add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus +add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry +add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout +add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack +add wave -noupdate -divider T-FIFIO +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data +add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl +add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr +add wave -noupdate -divider R-FIFO +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req +add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en +add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr +add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data +add wave -noupdate -divider Internal +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1710000 ps} 0} +configure wave -namecolwidth 276 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {3370500 ps} Index: spi_slave/trunk/doc/src/content/spec.tex =================================================================== --- spi_slave/trunk/doc/src/content/spec.tex (nonexistent) +++ spi_slave/trunk/doc/src/content/spec.tex (revision 35) @@ -0,0 +1,374 @@ +\chapter{Introduction} +This document describe a SPI Slave core designed for the Xilinx EDK. \cite{bib_xilinx_edk} + +\section{Features} +\begin{itemize} +\item OPB-Clock and SPI-Clock are complete independent +\item SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX-FIFO Overrunn occure. +\item variable transfer length 2..32 +\end{itemize} + + + + +\section{Limitations} +\begin{itemize} +\item designed only for Xilinx Spartan-3/Virtex-4 at the moment +\item only Slave Operation +\end{itemize} + +\chapter{Core configuration} +\begin{table} [h] + \centering + \begin{tabularx} {160mm} {|l|l|c|X|} \hline + Description & Parameter Name & Allowable Values & Default Value \\ \hline + \multicolumn{4} {|c|} {System Parameter} \\ \hline + Base address for OPB SPI& C\_BASEADDR & 0x00 & 0x00000000 \\ \hline + High address for OPB SPI& C\_HIGHADDR & BASEADDR+0x3F & BASEADDR+0x3f \\ \hline + OPB address bus width & C\_OPB\_AWIDTH & 32 & 32 \\ \hline + OPB data bus width & C\_OPB\_DWIDTH & 32 & 32 \\ \hline + Target FPGA Family & C\_FAMILY & spartan3,virtex4 & virtex4 \\ \hline + \multicolumn{4} {|c|} {User Parameter} \\ \hline + Shift register width & C\_SR\_WIDTH & 8-32 & 8 \\ \hline + Shift MSB First & C\_MSB\_FIRST & true, false & true \\ \hline + SPI Clock Polarity & C\_CPOL & 0,1 & 0 \\ \hline + SPI Clock Phase & C\_CPHA & 0,1 & 0 \\ \hline + FIFO Size Width(TX/RX)\footnotemark[1] & C\_FIFO\_DEPTH & 4-7 & 4 \\ \hline + DMA\_EN & C\_DMA\_EN & true, false & false \\ \hline + \end{tabularx} + \caption{Generics} + \label{tab:Generics} +\end{table} + +\footnotetext[1]{FIFO depth is $2^{Value}$ =(16,32,64,128)} + + + +\chapter{IO-Ports} +\begin{table} [h] + \centering + \begin{tabularx} {160mm}{|l|l|l|X|} \hline + \textbf{Port} & \textbf{width} & \textbf{direction} & \textbf{Description} \\ \hline + SPI\_SCLK & 1 & input & Serial clock input \\ + SPI\_MOSI & 1 & input & Master Out Slave in \\ + SPI\_MISO & 1 & output & Master in Slave out \\ + SPI\_SS & 1 & input & Slave select \\ \hline + opb\_irq & 1 & output & IRQ Output \\ \hline + \end{tabularx} + \caption{external ports} + \label{tab:externalPorts} +\end{table} + +\chapter{Registers} +\section{Adressmap} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm} {|l|c|c|X|} \hline + \textbf{Name} & \textbf{Adress} & \textbf{Acess} & \textbf{Description} \\ \hline + SPI\_CR & 0x00 & R/W & SPI Control Register \\ \hline + SPI\_SR & 0x04 & R/W & SPI Status Register \\ \hline + SPI\_TD & 0x08 & W & SPI Transmit Data Register \\ \hline + SPI\_RD & 0x0C & R & SPI Receive Data Register \\ \hline + TX\_THRESH & 0x10 & R/W & TX-Threshold Prog Full/Emty \\ \hline + RX\_THRESH & 0x14 & R/W & RX-Threshold Prog Full/Emty \\ \hline + TX\_DMA\_CTL & 0x18 & R/W & TX DMA Control \\ \hline + TX\_DMA\_ADDR & 0x1C & R/W & TX DMA Base Adress Offset \\ \hline + TX\_DMA\_NUM & 0x20 & R/W & TX DMA Number of Transfers \\ \hline + RX\_DMA\_CTL & 0x24 & R/W & RX DMA Control \\ \hline + RX\_DMA\_ADDR & 0x28 & R/W & RX DMA Base Adress Offset \\ \hline + RX\_DMA\_NUM & 0x2C & R/W & RX DMA Number of Transfers \\ \hline + + DGIE & 0x40 & R/W & Device global IRQ Enable Register \\ \hline + IPISR & 0x44 & R/W & IRQ Status Register \\ \hline + IPIER & 0x48 & R/W & IRQ Enable Register \\ \hline + \end{tabularx} + \caption{Address-Map} + \label{tab:registers} +\end{table} + +\section{SPI\_CR} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1.5cm}|p{3cm}|p{1.5cm}|p{1.5cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & DGE & R/W & 0 & Device Global Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 30 & TX\_EN & R/W & 0 & Transmit Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29 & RX\_EN & R/W & 0 & Receive Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29 & RESET & R/W & 0 & Reset Device(self cleared) \\ + & & & & 0: Normal Operation \\ + & & & & 1: Reset SPI-Core(SR/FIFO) \\ \hline + 28..0 & \multicolumn{4} {c|} {reserved} \\ \hline + \end{tabularx} + \caption{SPI\_CR Register} + \label{tab:SPI_CR} +\end{table} + + +\section{SPI\_SR} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX Prog Full & R & 0 & Prog Full Flag \\ + & & & & 1: FIFO Prog Full \\ \hline + 30 & TX Full & R & 0 & Full Flag \\ + & & & & 1: FIFO Full \\ \hline + 29 & TX Overflow & R & 0 & Overflow Flag \\ + & & & & 1: FIFO Overflow \\ + & & & & (Cleared only at Reset) \\ \hline + 28 & TX Prog Empty & R & 0 & Prog Empty Flag \\ + & & & & 1: FIFO Prog Empty \\ \hline + 27 & TX Empty & R & 0 & Full Flag \\ + & & & & 1: FIFO Empty \\ \hline + 26 & TX Underflow & R & 0 & Underflow Flag \\ + & & & & 1: FIFO Underflow \\ + & & & & (Cleared only at Reset) \\ \hline + 25 & RX Prog Full & R & 0 & Prog Full Flag \\ + & & & & 1: FIFO Prog Full \\ \hline + 24 & RX Full & R & 0 & Full Flag \\ + & & & & 1: FIFO Full \\ \hline + 23 & RX Overflow & R & 0 & Overflow Flag \\ + & & & & 1: FIFO Overflow \\ + & & & & (Cleared only at Reset) \\ \hline + 22 & RX Prog Empty & R & 0 & Prog Empty Flag \\ + & & & & 1: FIFO Prog Empty \\ \hline + 21 & RX Empty & R & 0 & Full Flag \\ + & & & & 1: FIFO Empty \\ \hline + 20 & RX Underflow & R & 0 & Underflow Flag \\ + & & & & 1: FIFO Underflow \\ + & & & & (Cleared only at Reset) \\ \hline + 19 & Chip Select & R & 0 & Chip Select Flag \\ + & & & & 0: CS\_N Low \\ + & & & & 1: CS\_N High \\ \hline + 18 & TX DMA Done & R & 0 & Transmit DMA done \\ + & & & & 0: TX DMA in progress \\ + & & & & 1: TX DMA all Transfers done\\ \hline + 17 & RX DMA Done & R & 0 & Receive DMA done \\ + & & & & 0: RX DMA in progress \\ + & & & & 1: RX DMA all Transfers done\\ \hline + 16:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} + \caption{SPI\_SR Register} + \label{tab:SPI_SR} +\end{table} + +\section{TX\_THRESH} +\begin{table}[!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ + & & & \textbf{Value} & \\ \hline + 31:16 & TX\_THRESH\_PROG\_FULL & R/W & 0 & Transmit Prog Full Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + 15:0 & TX\_THRESH\_PROG\_EMPTY & R/W & 0 & Transmit Prog Empty Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + \end{tabularx} + \caption{TX\_THRESH Register} + \label{tab:TX_THRESH} +\end{table} + +This Register sets the Almost Full and Empty Flag Thresholds for Transmit FIFO. IF the DMA-Engine is used, the TX\_THRESH\_PROG\_EMPTY is used to trigger the DMA-Transfer. If Transmit FIFO is Almost Empty the Engine fills the FIFO with 16 Words(4..32bit). If the OPB-Bus is at medium or full load, increase Almost Empty Threshold to ensure there are ''some bytes reserve'' in Fifo until the DMA-Engine has access to the bus and can start transfer. Under light load condition a value of 4 should sufficient. + + +\section{RX\_THRESH} +\begin{table}[!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ + & & & \textbf{Value} & \\ \hline + 31:16 & RX\_THRESH\_PROG\_FULL & R/W & 0 & Receive Prog Full Threshold \\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + 15:0 & RX\_THRESH\_PROG\_EMPTY & R/W & 0 & Receive Prog Empty Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline \end{tabularx} + \caption{RX\_THRESH Register} + \label{tab:RX_THRESH} +\end{table} + +This Register sets the Almost Full and Empty Flag Thresholds for Receive FIFO. IF the DMA-Engine is used, the RX\_THRESH\_PROG\_FULL is used to trigger the DMA-Transfer. Normally set this Threshold to the block size of 16. If the OPB-Bus is at medium or full load, increase the FIFO Size(C\_FIFO\_WIDTH) to ensure there are 'some bytes free'' in FIFO until overflow occurs. + + +\section{TX\_DMA\_CTL} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} + \caption{TX\_DMA\_CTL Register} + \label{tab:tx_dma_ctl} +\end{table} +This Register is only available if C\_DMA\_EN is set. +Set the Bit TX\_DMA\_EN to 1 to enable the Transmit DMA Engine. With Engine Start the Register TX\_DMA\_ADDR and TX\_DMA\_NUM are copied to internal register. Do not change this Registers if DMA Enable set. + +\section{TX\_DMA\_ADDR} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31:0 & TX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline + \end{tabularx} + \caption{TX\_DMA\_ADDR Register} + \label{tab:tx_dma_addr} +\end{table} + +This Register is only available if C\_DMA\_EN is set. With this Register the Base-Adress of the TX-DMA is set. The Adress must 4 Byte aligned. Remark: For this memory area the Data-Chache of the Microblaze can be enabled, because the Cache is a Write-True type. Using a controller with write-back cache only the first write will written in memory, the second only in the internal cache. + +\section{TX\_DMA\_NUM} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31:8 & TX\_DMA\_LEN & R/W & 0 & TX DMA Number of Block Transfers \\ \hline + 7:0 & \multicolumn{4} {c|} {reserved} \\ \hline + \end{tabularx} + \caption{TX\_DMA\_NUM Register} + \label{tab:tx_dma_len} +\end{table} +This Register is only available if C\_DMA\_EN is set. The Register set the Number of Blocktransfers. If all transfers done, the IRQ TX DMA Done asserted. The block size of the DMA is 16. A system configured with C\_SR\_WIDTH = 8 transfers 16 Bytes, if C\_SR\_WIDTH=32 64 Bytes are written to or read from the memory in one DMA-Cycle. + +\section{RX\_DMA\_CTL} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & RX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} + \caption{RX\_DMA\_CTL Register} + \label{tab:RX_dma_ctl} +\end{table} + +This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_CTL for Description. + + +\section{RX\_DMA\_ADDR} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31:0 & RX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline + \end{tabularx} + \caption{RX\_DMA\_ADDR Register} + \label{tab:RX_dma_addr} +\end{table} + +This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_ADDR for Description. +\newline +\fbox{\parbox{160mm} {Remark: Check RX\_DMA\_ADDR that is set to the right memory section. If wrong set, program-Code or date overwritten with SPI-Data!}} + +\section{RX\_DMA\_NUM} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31:8 & RX\_DMA\_LEN & R/W & 0 & RX DMA Number of Block Transfers \\ \hline + 7:0 & \multicolumn{4} {c|} {reserved} \\ \hline + \end{tabularx} + \caption{RX\_DMA\_NUM Register} + \label{tab:RX_dma_len} +\end{table} + +This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_NUM for Description. + +\section{IPISR} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX\_Prog\_Empty & R/ToW\footnotemark[1] & 0 & IRQ Prog Empty Flag \\ \hline + 29 & TX\_Empty & R/ToW & 0 & IRQ Full Flag \\ \hline + 28 & RX\_Prog\_Full& R/ToW & 0 & IRQ Prog Full Flag \\ \hline + 27 & RX\_Full & R/ToW & 0 & IRQ Full Flag \\ \hline + 26 & SS\_FALL & R/ToW & 0 & IRQ SS FALL Flag \\ \hline + 25 & SS\_RISE & R/ToW & 0 & IRQ SS RISE Flag \\ \hline + 24..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} + \caption{IPISR Register} + \label{tab:IPISR} +\end{table} + +\footnotetext[1]{Read and ToggleOnWrite (writing 1 clears the bit)} + +\section{IPISE} +\begin{table} [!h] + \centering + \begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX\_Prog\_Empty & R/W & 0 & IRQ Prog Empty Enable \\ \hline + 29 & TX\_Empty & R/W & 0 & IRQ Full Enable \\ \hline + 28 & RX\_Prog\_Full & R/W & 0 & IRQ Prog Full Enable \\ \hline + 27 & RX\_Full & R/W & 0 & IRQ Full Enable \\ \hline + 26 & SS\_FALL & R/W & 0 & IRQ SS FALL Enable \\ \hline + 25 & SS\_RISE & R/W & 0 & IRQ SS RISE Enable \\ \hline + 24 & TX\_DMA\_DONE & R/W & 0 & IRQ TX Transfer done Enable\\ \hline + 23 & TX\_DMA\_DONE & R/W & 0 & IRQ RX Transfer done Enable\\ \hline + 22..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx} + \caption{IPISE Register} + \label{tab:IPISE} +\end{table} + + +\chapter{System Integration} +To integrate this IP-Core in your System, unzip the opb\_spi\_slave.zip to your project-directory. Then Rescan the user repository with \textit{Project $\rightarrow$ Rescan User Repositories}. This will take some seconds. After this you find the core in the \textit{IP Catalog $\rightarrow$ Project Repository}. + +\section{MPD-File} +\begin{verbatim} +BEGIN opb_spi_slave + PARAMETER INSTANCE = opb_spi_slave_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x7d600000 + PARAMETER C_HIGHADDR = 0x7d60ffff + BUS_INTERFACE MSOPB = mb_opb + PORT sclk = opb_spi_slave_0_sclk + PORT ss_n = opb_spi_slave_0_ss_n + PORT mosi = opb_spi_slave_0_mosi + PORT miso = opb_spi_slave_0_miso + PORT opb_irq = opb_spi_slave_0_opb_irq +END +\end{verbatim} + +\section{UCF-File} +\begin{verbatim} +# assign I/O Pins +NET opb_spi_slave_0_sclk_pin LOC= AA24; # must CC capable IO in virtex-4 +NET opb_spi_slave_0_ss_n_pin LOC= V20; +NET opb_spi_slave_0_mosi_pin LOC= AC25; +NET opb_spi_slave_0_miso_pin LOC= AC24; +NET opb_spi_slave_0_miso_pin SLEW = FAST; + +#### Module OPB_SPI_Slave constraints +Net opb_spi_slave_0_sclk_pin TNM_NET = spi_clk; +TIMESPEC TS_spi_clk = PERIOD spi_clk 40 ns; + +NET "opb_spi_slave_0_mosi_pin" TNM = "spi_in"; +#NET "opb_spi_slave_0_cs_n_pin" TNM = "spi_in"; +TIMEGRP "spi_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "opb_spi_slave_0_sclk_pin" HIGH ; + +NET "opb_spi_slave_0_miso_pin" TNM = "spi_out"; +TIMEGRP "spi_out" OFFSET = OUT 14 ns AFTER "opb_spi_slave_0_sclk_pin" LOW ; +\end{verbatim} + +\section{Register Header} + +\verbatiminput{opb_spi_slave.h} + + +\chapter{Operations} + + +\chapter{Architecture} + +\begin{figure}[h] + \centering + \includegraphics[width=1.00\textwidth]{Grafik/block_diagramm} + \caption{Blockdiagramm} + \label{fig:blockdiagramm} +\end{figure} + Index: spi_slave/trunk/doc/src/content/Titel.tex =================================================================== --- spi_slave/trunk/doc/src/content/Titel.tex (nonexistent) +++ spi_slave/trunk/doc/src/content/Titel.tex (revision 35) @@ -0,0 +1,13 @@ +\begin{titlepage} + \mbox{}\vspace{5\baselineskip}\\ + \sffamily\huge + \centering + specification OPB-SPI-Slave + \vspace{2\baselineskip}\\ + \rmfamily\Large + Daniel Koethe + \vspace{1\baselineskip}\\ + \today +\end{titlepage} + + Index: spi_slave/trunk/doc/src/content/Z-Anhang.tex =================================================================== --- spi_slave/trunk/doc/src/content/Z-Anhang.tex (nonexistent) +++ spi_slave/trunk/doc/src/content/Z-Anhang.tex (revision 35) @@ -0,0 +1,3 @@ +% \input{content/Z-Anhang-01-Herleitungen} + +\chapter*{} Index: spi_slave/trunk/doc/src/opb_spi_slave.h =================================================================== --- spi_slave/trunk/doc/src/opb_spi_slave.h (nonexistent) +++ spi_slave/trunk/doc/src/opb_spi_slave.h (revision 35) @@ -0,0 +1,67 @@ +#include "xparameters.h" + +#define XSS_CR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x00)) +#define XSS_SR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x01)) +#define XSS_TD (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x02)) +#define XSS_RD (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x03)) +#define XSS_TX_THRESH (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x04)) +#define XSS_RX_THRESH (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x05)) +#define XSS_TX_DMA_CTL (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x06)) +#define XSS_TX_DMA_ADR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x07)) +#define XSS_TX_DMA_NUM (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x08)) +#define XSS_RX_DMA_CTL (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x09)) +#define XSS_RX_DMA_ADR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x0A)) +#define XSS_RX_DMA_NUM (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x0B)) + +#define XSS_DGIE (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x10)) +#define XSS_IPISR (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x11)) +#define XSS_IPIER (XPAR_OPB_SPI_SLAVE_0_BASEADDR + (4* 0x12)) + +//XSS_SPI_CR +#define XSS_CR_SPE_MASK (0x01) +#define XSS_CR_TX_EN_MASK (0x02) +#define XSS_CR_RX_EN_MASK (0x04) +#define XSS_CR_RESET_MASK (0x08) + +//XSS_SPI +// Transmit +#define XSS_SR_TX_PROG_FULL_MASK 0x0001 +#define XSS_SR_TX_FULL_MASK 0x0002 +#define XSS_SR_TX_OVERFLOW_MASK 0x0004 +#define XSS_SR_TX_PROG_EMPTY_MASK 0x0008 +#define XSS_SR_TX_EMPTY_MASK 0x0010 +#define XSS_SR_TX_UNDERFLOW_MASK 0x0020 +// Receive +#define XSS_SR_RX_PROG_FULL_MASK 0x0040 +#define XSS_SR_RX_FULL_MASK 0x0080 +#define XSS_SR_RX_OVERFLOW_MASK 0x0100 +#define XSS_SR_RX_PROG_EMPTY_MASK 0x0200 +#define XSS_SR_RX_EMPTY_MASK 0x0400 +#define XSS_SR_RX_UNDERFLOW_MASK 0x0800 +// Chip Select +#define XSS_SR_CHIP_SELECT_MASK 0x1000 +// DMA +#define XSS_SR_TX_DMA_done 0x2000 +#define XSS_SR_RX_DMA_done 0x4000 + + +// Device Global Interrupt Enable +#define XSS_DGIE_Bit_Enable 0x0001 + +// Interrupt /Enable Status Register +#define XSS_ISR_Bit_TX_Prog_Empty 0x0001 +#define XSS_ISR_Bit_TX_Empty 0x0002 +#define XSS_ISR_Bit_TX_Underflow 0x0004 +#define XSS_ISR_Bit_RX_Prog_Full 0x0008 +#define XSS_ISR_Bit_RX_Full 0x0010 +#define XSS_ISR_Bit_RX_Overflow 0x0020 +#define XSS_ISR_Bit_SS_Fall 0x0040 +#define XSS_ISR_Bit_SS_Rise 0x0080 +#define XSS_ISR_Bit_TX_DMA_done 0x0100 +#define XSS_ISR_Bit_RX_DMA_done 0x0200 + +// TX DMA Control Register +#define XSS_TX_DMA_CTL_EN 0x0001 + +// RX DMA Control Register +#define XSS_RX_DMA_CTL_EN 0x0001 Index: spi_slave/trunk/doc/src/Grafik/block_diagramm.eps =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spi_slave/trunk/doc/src/Grafik/block_diagramm.eps =================================================================== --- spi_slave/trunk/doc/src/Grafik/block_diagramm.eps (nonexistent) +++ spi_slave/trunk/doc/src/Grafik/block_diagramm.eps (revision 35)

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spi_slave/trunk/doc/src/Grafik/block_diagramm.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spi_slave/trunk/doc/src/opb_spi_slave.tex =================================================================== --- spi_slave/trunk/doc/src/opb_spi_slave.tex (nonexistent) +++ spi_slave/trunk/doc/src/opb_spi_slave.tex (revision 35) @@ -0,0 +1,46 @@ +\documentclass[11pt, a4paper, german, oneside]{scrbook} +\textheight240mm +\usepackage{hyperref} +\usepackage[latin1]{inputenc} +\usepackage{graphicx} +\usepackage{colortbl} +\usepackage{tabularx} +\usepackage{longtable} +\definecolor{yellow1}{rgb}{0.98, 1.0, 0.6} +\pagestyle{plain} +\pagenumbering{arabic} +\usepackage{verbatim} + +\title{Specification OPB-SPI Slave} +\author{Daniel Koethe} +\date{\today} + + +\begin{document} + \maketitle +\tableofcontents + +\input{content/spec} + + +% Anhang (Bibliographie darf im deutschen nicht in den Anhang!) +\bibliography{bib/BibtexDatabase} +\bibliographystyle{plain} +\clearpage +\listoffigures +\listoftables + + + + + + + +% Anhang +\appendix +\input{content/Z-Anhang} + + +%% Dokument ENDE %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\end{document} + Index: spi_slave/trunk/doc/src/opb_spi_slave.tcp =================================================================== --- spi_slave/trunk/doc/src/opb_spi_slave.tcp (nonexistent) +++ spi_slave/trunk/doc/src/opb_spi_slave.tcp (revision 35) @@ -0,0 +1,12 @@ +[FormatInfo] +Type=TeXnicCenterProjectInformation +Version=4 + +[ProjectInfo] +MainFile=opb_spi_slave.tex +UseBibTeX=0 +UseMakeIndex=0 +ActiveProfile=LaTeX => PDF +ProjectLanguage=de +ProjectDialect=DE + Index: spi_slave/trunk/doc/opb_spi_slave.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spi_slave/trunk/doc/opb_spi_slave.pdf =================================================================== --- spi_slave/trunk/doc/opb_spi_slave.pdf (nonexistent) +++ spi_slave/trunk/doc/opb_spi_slave.pdf (revision 35)

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spi_slave/tags/V100/doc/src/Grafik/block_diagramm.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spi_slave/tags/V100/doc/src/opb_spi_slave.tex =================================================================== --- spi_slave/tags/V100/doc/src/opb_spi_slave.tex (nonexistent) +++ spi_slave/tags/V100/doc/src/opb_spi_slave.tex (revision 35) @@ -0,0 +1,46 @@ +\documentclass[11pt, a4paper, german, oneside]{scrbook} +\textheight240mm +\usepackage{hyperref} +\usepackage[latin1]{inputenc} +\usepackage{graphicx} +\usepackage{colortbl} +\usepackage{tabularx} +\usepackage{longtable} +\definecolor{yellow1}{rgb}{0.98, 1.0, 0.6} +\pagestyle{plain} +\pagenumbering{arabic} +\usepackage{verbatim} + +\title{Specification OPB-SPI Slave} +\author{Daniel Koethe} +\date{\today} + + +\begin{document} + \maketitle +\tableofcontents + +\input{content/spec} + + +% Anhang (Bibliographie darf im deutschen nicht in den Anhang!) +\bibliography{bib/BibtexDatabase} +\bibliographystyle{plain} +\clearpage +\listoffigures +\listoftables + + + + + + + +% Anhang +\appendix +\input{content/Z-Anhang} + + +%% Dokument ENDE %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\end{document} + Index: spi_slave/tags/V100/doc/src/content/Titel.tex =================================================================== --- spi_slave/tags/V100/doc/src/content/Titel.tex (nonexistent) +++ spi_slave/tags/V100/doc/src/content/Titel.tex (revision 35) @@ -0,0 +1,13 @@ +\begin{titlepage} + \mbox{}\vspace{5\baselineskip}\\ + \sffamily\huge + \centering + specification OPB-SPI-Slave + \vspace{2\baselineskip}\\ + \rmfamily\Large + Daniel Koethe + \vspace{1\baselineskip}\\ + \today +\end{titlepage} + + Index: spi_slave/tags/V100/doc/src/content/Z-Anhang.tex =================================================================== --- spi_slave/tags/V100/doc/src/content/Z-Anhang.tex (nonexistent) +++ spi_slave/tags/V100/doc/src/content/Z-Anhang.tex (revision 35) @@ -0,0 +1,3 @@ +% \input{content/Z-Anhang-01-Herleitungen} + +\chapter*{} Index: spi_slave/tags/V100/doc/src/content/spec.tex =================================================================== --- spi_slave/tags/V100/doc/src/content/spec.tex (nonexistent) +++ spi_slave/tags/V100/doc/src/content/spec.tex (revision 35) @@ -0,0 +1,410 @@ +\chapter{Introduction} +This document describe a SPI Slave core designed for the Xilinx EDK. \cite{bib_xilinx_edk} + +\section{Features} +\begin{itemize} +\item OPB-Clock and SPI-Clock are complete independent +\item SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX-FIFO Overrunn occure. +\item variable transfer length 2..32 +\end{itemize} + + + + +\section{Limitations} +\begin{itemize} +\item designed only for Xilinx Spartan-3/Virtex-4 at the moment +\item only Slave Operation +\end{itemize} + +\chapter{Core configuration} +\begin{table} [h] + \centering + \begin{tabular} {|l|l|c|c|} \hline + Description & Parameter Name & Allowable Values & Default Value \\ \hline + \multicolumn{4} {|c|} {System Parameter} \\ \hline + Base address for OPB SPI& C\_BASEADDR & 0x00 & 0x00000000 \\ \hline + High address for OPB SPI& C\_HIGHADDR & BASEADDR+0x3F & BASEADDR+0x3f \\ \hline + OPB address bus width & C\_OPB\_AWIDTH & 32 & 32 \\ \hline + OPB data bus width & C\_OPB\_DWIDTH & 32 & 32 \\ \hline + Target FPGA Family & C\_FAMILY & spartan3,virtex4 & virtex4 \\ \hline + \multicolumn{4} {|c|} {User Parameter} \\ \hline + Shift register width & C\_SR\_WIDTH & 8-32 & 8 \\ \hline + Shift MSB First & C\_MSB\_FIRST & true, false & true \\ \hline + SPI Clock Polarity & C\_CPOL & 0,1 & 0 \\ \hline + SPI Clock Phase & C\_CPHA & 0,1 & 0 \\ \hline + FIFO Size Width(TX/RX)\footnotemark[1] & C\_FIFO\_DEPTH & 4-7 & 4 \\ \hline + DMA\_EN & C\_DMA\_EN & true, false & false \\ \hline + \end{tabular} + \caption{Generics} + \label{tab:Generics} +\end{table} + +\footnotetext[1]{FIFO depth is $2^{Value}$ =(16,32,64,128)} + + + +\chapter{IO-Ports} +\begin{table} [h] + \centering + \begin{tabular}{|l|l|l|l|} \hline + \textbf{Port} & \textbf{width} & \textbf{direction} & \textbf{Description} \\ \hline + SPI\_SCLK & 1 & input & Serial clock input \\ + SPI\_MOSI & 1 & input & Master Out Slave in \\ + SPI\_MISO & 1 & output & Master in Slave out \\ + SPI\_SS & 1 & input & Slave select \\ \hline + opb\_irq & 1 & output & IRQ Output \\ \hline + \end{tabular} + \caption{external ports} + \label{tab:externalPorts} +\end{table} + +\chapter{Registers} +\section{Adressmap} +\begin{table} [!h] + \centering + \begin{tabular}{|l|c|c|l|} \hline + \textbf{Name} & \textbf{Adress} & \textbf{Acess} & \textbf{Description} \\ \hline + SPI\_CR & 0x00 & R/W & SPI Control Register \\ \hline + SPI\_SR & 0x04 & R/W & SPI Status Register \\ \hline + SPI\_TD & 0x08 & W & SPI Transmit Data Register \\ \hline + SPI\_RD & 0x0C & R & SPI Receive Data Register \\ \hline + TX\_THRESH & 0x10 & R/W & TX-Threshold Prog Full/Emty \\ \hline + RX\_THRESH & 0x14 & R/W & RX-Threshold Prog Full/Emty \\ \hline + TX\_DMA\_CTL & 0x18 & R/W & TX DMA Control \\ \hline + TX\_DMA\_ADDR & 0x1C & R/W & TX DMA Base Adress Offset \\ \hline + TX\_DMA\_NUM & 0x20 & R/W & TX DMA Number of Transfers \\ \hline + RX\_DMA\_CTL & 0x24 & R/W & RX DMA Control \\ \hline + RX\_DMA\_ADDR & 0x28 & R/W & RX DMA Base Adress Offset \\ \hline + RX\_DMA\_NUM & 0x2C & R/W & RX DMA Number of Transfers \\ \hline + + DGIE & 0x40 & R/W & Device global IRQ Enable Register \\ \hline + IPISR & 0x44 & R/W & IRQ Status Register \\ \hline + IPIER & 0x48 & R/W & IRQ Enable Register \\ \hline + \end{tabular} + \caption{Address-Map} + \label{tab:registers} +\end{table} + +\section{SPI\_CR} +\begin{table} [!h] + \centering + \begin{tabular} {|l|c|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & DGE & R/W & 0 & Device Global Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 30 & TX\_EN & R/W & 0 & Transmit Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29 & RX\_EN & R/W & 0 & Receive Enable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29 & RESET & R/W & 0 & Reset Device(self cleared) \\ + & & & & 0: Normal Operation \\ + & & & & 1: Reset SPI-Core(SR/FIFO) \\ \hline 29..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} + \caption{SPI\_CR Register} + \label{tab:SPI_CR} +\end{table} + + +\section{SPI\_SR} +\begin{table} [!h] + \centering + \begin{tabular} {|l|l|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX Prog Full & R & 0 & Prog Full Flag \\ + & & & & 1: FIFO Prog Full \\ \hline + 30 & TX Full & R & 0 & Full Flag \\ + & & & & 1: FIFO Full \\ \hline + 29 & TX Overflow & R & 0 & Overflow Flag \\ + & & & & 1: FIFO Overflow \\ + & & & & (Cleared only at Reset) \\ \hline + 28 & TX Prog Empty & R & 0 & Prog Empty Flag \\ + & & & & 1: FIFO Prog Empty \\ \hline + 27 & TX Empty & R & 0 & Full Flag \\ + & & & & 1: FIFO Empty \\ \hline + 26 & TX Underflow & R & 0 & Underflow Flag \\ + & & & & 1: FIFO Underflow \\ + & & & & (Cleared only at Reset) \\ \hline + 25 & RX Prog Full & R & 0 & Prog Full Flag \\ + & & & & 1: FIFO Prog Full \\ \hline + 24 & RX Full & R & 0 & Full Flag \\ + & & & & 1: FIFO Full \\ \hline + 23 & RX Overflow & R & 0 & Overflow Flag \\ + & & & & 1: FIFO Overflow \\ + & & & & (Cleared only at Reset) \\ \hline + 22 & RX Prog Empty & R & 0 & Prog Empty Flag \\ + & & & & 1: FIFO Prog Empty \\ \hline + 21 & RX Empty & R & 0 & Full Flag \\ + & & & & 1: FIFO Empty \\ \hline + 20 & RX Underflow & R & 0 & Underflow Flag \\ + & & & & 1: FIFO Underflow \\ + & & & & (Cleared only at Reset) \\ \hline + 19 & Chip Select & R & 0 & Chip Select Flag \\ + & & & & 0: CS\_N Low \\ + & & & & 1: CS\_N High \\ \hline + 18 & TX DMA Done & R & 0 & Transmit DMA done \\ + & & & & 0: TX DMA in progress \\ + & & & & 1: TX DMA all Transfers done\\ \hline 17 & RX DMA Done & R & 0 & Receive DMA done \\ + & & & & 0: RX DMA in progress \\ + & & & & 1: RX DMA all Transfers done\\ \hline + 16..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} + \caption{SPI\_SR Register} + \label{tab:SPI_SR} +\end{table} + +\newpage +\section{TX\_THRESH} +\begin{table}[!h] + \centering + \begin{tabular} {|l|l|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ + & & & \textbf{Value} & \\ \hline + 31..16 & TX\_THRESH\_PROG\_FULL & R/W & 0 & Transmit Prog Full Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + 15..0 & TX\_THRESH\_PROG\_EMPTY & R/W & 0 & Transmit Prog Empty Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + \end{tabular} + \caption{TX\_THRESH Register} + \label{tab:TX_THRESH} +\end{table} + + +\section{RX\_THRESH} +\begin{table}[!h] + \centering + \begin{tabular} {|l|l|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\ + & & & \textbf{Value} & \\ \hline + 31..16 & RX\_THRESH\_PROG\_FULL & R/W & 0 & Receive Prog Full Threshold \\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline + 15..0 & RX\_THRESH\_PROG\_EMPTY & R/W & 0 & Receive Prog Empty Threshold\\ + & & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline \end{tabular} + \caption{RX\_THRESH Register} + \label{tab:RX_THRESH} +\end{table} + + +\section{DGIE} +\begin{table} [!h] + \centering + \begin{tabular} {|l|c|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & DGIE & R/W & 0 & Global IRQ Ebable \\ + & & & & 0: Disable \\ + & & & & 1: Enable \\ \hline + 29..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} + \caption{DGIE Register} + \label{tab:dgie} +\end{table} + +\newpage +\section{IPISR} +\begin{table} [!h] + \centering + \begin{tabular} {|l|l|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX\_Prog\_Empty & R/ToW\footnotemark[1] & 0 & IRQ Prog Empty Flag \\ \hline + 29 & TX\_Empty & R/ToW & 0 & IRQ Full Flag \\ \hline + 28 & RX\_Prog\_Full& R/ToW & 0 & IRQ Prog Full Flag \\ \hline + 27 & RX\_Full & R/ToW & 0 & IRQ Full Flag \\ \hline + 26 & SS\_FALL & R/ToW & 0 & IRQ SS FALL Flag \\ \hline + 25 & SS\_RISE & R/ToW & 0 & IRQ SS RISE Flag \\ \hline + 24..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} + \caption{IPISR Register} + \label{tab:IPISR} +\end{table} + +\footnotetext[1]{Read and ToggleOnWrite (writing 1 clears the bit)} + +\section{IPISE} +\begin{table} [!h] + \centering + \begin{tabular} {|l|l|c|c|l|} \hline + \textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline + 31 & TX\_Prog\_Empty & R/W & 0 & IRQ Prog Empty Enable \\ \hline + 29 & TX\_Empty & R/W & 0 & IRQ Full Enable \\ \hline + 28 & RX\_Prog\_Full & R/W & 0 & IRQ Prog Full Enable \\ \hline + 27 & RX\_Full & R/W & 0 & IRQ Full Enable \\ \hline + 26 & SS\_FALL & R/W & 0 & IRQ SS FALL Enable \\ \hline + 25 & SS\_RISE & R/W & 0 & IRQ SS RISE Enable \\ \hline + 24 & TX\_DMA\_DONE & R/W & 0 & IRQ TX Transfer done Enable\\ \hline + 23 & TX\_DMA\_DONE & R/W & 0 & IRQ RX Transfer done Enable\\ \hline 22..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabular} + \caption{IPISE Register} + \label{tab:IPISE} +\end{table} + +1: IRQ enabled + +\chapter{System Integration} +To integrate this IP-Core in your System, unzip the opb\_spi\_slave.zip to your project-directory. Then Rescan the user repository with \textit{Project $\rightarrow$ Rescan User Repositories}. This will take some seconds. After this you find the core in the \textit{IP Catalog $\rightarrow$ Project Repository}. + +\section{MPD-File} +\begin{verbatim} +BEGIN opb_spi_slave + PARAMETER INSTANCE = opb_spi_slave_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x7d600000 + PARAMETER C_HIGHADDR = 0x7d60ffff + BUS_INTERFACE MSOPB = mb_opb + PORT sclk = opb_spi_slave_0_sclk + PORT ss_n = opb_spi_slave_0_ss_n + PORT mosi = opb_spi_slave_0_mosi + PORT miso = opb_spi_slave_0_miso + PORT opb_irq = opb_spi_slave_0_opb_irq +END +\end{verbatim} + +\section{UCF-File} +\begin{verbatim} +# assign I/O Pins +NET opb_spi_slave_0_sclk_pin LOC= AA24; # must CC capable IO in virtex-4 +NET opb_spi_slave_0_ss_n_pin LOC= V20; +NET opb_spi_slave_0_mosi_pin LOC= AC25; +NET opb_spi_slave_0_miso_pin LOC= AC24; +NET opb_spi_slave_0_miso_pin SLEW = FAST; + +#### Module OPB_SPI_Slave constraints +Net opb_spi_slave_0_sclk_pin TNM_NET = spi_clk; +TIMESPEC TS_spi_clk = PERIOD spi_clk 40 ns; + +NET "opb_spi_slave_0_mosi_pin" TNM = "spi_in"; +#NET "opb_spi_slave_0_cs_n_pin" TNM = "spi_in"; +TIMEGRP "spi_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "opb_spi_slave_0_sclk_pin" HIGH ; + +NET "opb_spi_slave_0_miso_pin" TNM = "spi_out"; +TIMEGRP "spi_out" OFFSET = OUT 14 ns AFTER "opb_spi_slave_0_sclk_pin" LOW ; +\end{verbatim} + +\section{Register Header} + +\verbatiminput{opb_spi_slave.h} + + +\chapter{Operations} + +\chapter{Architecture} + +\begin{figure}[h] + \centering + \includegraphics[width=1.00\textwidth]{Grafik/block_diagramm} + \caption{Blockdiagramm} + \label{fig:blockdiagramm} +\end{figure} + +\section{Serial Shift Register} +\begin{table}[!h] + \centering + \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} + \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline + \multicolumn{3} {c|} {Generics} \\ \hline + C\_SR\_WIDTH & - & Shift register width \\ \hline + C\_MSB\_FIRST & - & Transfer MSB First \\ \hline + \multicolumn{3} {c|} {Global} \\ \hline + rst & input & Async-Reset \\ \hline + \multicolumn{3} {c|} {External Interface} \\ \hline + sclk & input & Serial clock input \\ \hline + cs\_n & input & Chip Select \\ \hline + mosi & input & Master Out Slave in \\ \hline + miso\_o & output & Master in Slave out \\ \hline + miso\_i & input & not used \\ \hline + miso\_t & output & MISO Tristate \\ \hline + \multicolumn{3} {c|} {TX-FIFO (1)} \\ \hline + sr\_tx\_clk & output & FIFO-TX CLK \\ \hline + sr\_tx\_en & output & FIFO-TX enable \\ \hline + sr\_tx\_data[C\_SR\_WIDTH:0] & input & FIFO-TX Data \\ \hline + \multicolumn{3} {c|} {RX-FIFO (3)} \\ \hline + sr\_rx\_clk & output & FIFO-RX CLK \\ \hline + sr\_rx\_en & output & FIFO-RX enable \\ \hline + sr\_rx\_data[C\_SR\_WIDTH:0] & output & FIFO-RX Data \\ \hline + \end{tabular} + \caption{Serial-Register} + \label{tab:SerialRegister} +\end{table} +\clearpage + +\section{FIFO} +\begin{table}[!h] + \centering + \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} + \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline + \multicolumn{3} { c|} {Generics} \\ \hline + C\_FIFO\_WIDTH & - & Shift register width \\ \hline + C\_FIFO\_SIZE & - & FIFO Size Width \\ \hline + C\_SYNC\_TO & - & FIFO Sync Flags to Clock \\ \hline + \multicolumn{3} { c|} {Global} \\ \hline + rst & input & Async-Reset \\ \hline + \multicolumn{3} { c|} {Write-Port (2,3)} \\ \hline + wr\_clk & input & FIFO Write CLK \\ \hline + wr\_en & input & FIFO Write enable \\ \hline + din[C\_FIFO\_WIDTH:0] & input & FIFO Write data \\ \hline + \multicolumn{3} { c|} {READ-Port (1,4)} \\ \hline + rd\_clk & input & FIFO Read CLK \\ \hline + rd\_en & input & FIFO Read enable \\ \hline + dout[C\_FIFO\_WIDTH:0] & output & FIFO Read data \\ \hline + \multicolumn{3} { c|} {Flags (4)} \\ \hline + empty & output & FIFO Emtpy \\ \hline + full & output & FIFO Full \\ \hline + overflow & output & FIFO Overflow \\ \hline + underflow & output & FIFO Underflow \\ \hline + prog\_full\_thresh[C\_FIFO\_WIDTH:0] & output & FIFO Programmable Full Threshold \\ \hline + prog\_empty\_thresh[C\_FIFO\_WIDTH:0] & output & FIFO Programmable Empty Threshold\\ \hline + prog\_full & output & FIFO Programmable Full \\ \hline + prog\_empty & output & FIFO Programmable Empty \\ \hline + \end{tabular} + \caption{TX-FIFO} + \label{tab:tx-fifo} +\end{table} + +\newpage +\section{OPB\_IF} +\begin{table}[!h] + \centering + \begin{tabular} {|l|c|l|} \hline \rowcolor{yellow1} + \textbf{Signal} & \textbf{Direction}& \textbf{Description} \\ \hline + \multicolumn{3} { c|} {Generics} \\ \hline + C\_BASEADDR & - & Base address for OPB SPI \\ \hline + C\_HIGHADDR & - & High address for OPB SPI \\ \hline + C\_OPB\_AWIDTH & - & OPB address bus width \\ \hline + C\_OPB\_DWIDTH & - & OPB data bus width \\ \hline + C\_FAMILY & - & Target FPGA Family \\ \hline + C\_SR\_WIDTH & - & Shift register width \\ \hline + C\_FIFO\_WIDTH & - & Shift register width \\ \hline + C\_FIFO\_SIZE & - & FIFO Size Width \\ \hline + C\_NUM\_FLG & - & Number of FIFO Status flags \\ \hline + C\_NUM\_INT & - & Number of IRQ Sources \\ \hline + \multicolumn{3} { c|} {OPB-Bus} \\ \hline + OPB\_rst & input & Async-Reset \\ \hline + OPB\_ABus[C\_OPB\_AWIDTH-1:0] & input & Adress-Bus \\ \hline + OPB\_BE[C\_OPB\_DWIDTH/8-1:0] & input & Bytes Enables \\ \hline + OPB\_Clk & input & Clock \\ \hline + OPB\_DBus[C\_OPB\_DWIDTH-1:0] & input & Data-Bus to slave \\ \hline + OPB\_RNW & input & Read/Write \\ \hline + OPB\_Rst & input & Reset \\ \hline + OPB\_select & input & Select \\ \hline + OPB\_seqAddr & input & Sequential Adress Enable \\ \hline + Sln\_DBus & output & Data-Bus to Master \\ \hline + Sln\_errAck & output & Error Acknowledge \\ \hline + Sln\_retry & output & Retry \\ \hline + Sln\_toutSup & output & Timeout Suppression \\ \hline + Sln\_xferAck & output & transfer Acknowledge \\ \hline + \multicolumn{3} { c|} {FIFO-PORT (2)} \\ \hline + opb\_tx\_en & output & FIFO-TX Write Enable \\ \hline + opb\_tx\_data[C\_SR\_WIDTH:0] & output & FIFO-TX Write Data \\ \hline + tx\_thresh[(2*C\_FIFO\_SIZE)-1:0] & output & FIFO-TX Prog Thresholds \\ \hline + \multicolumn{3} { c|} {FIFO-PORT (4)} \\ \hline + opb\_rx\_en & output & FIFO-RX Read Enable \\ \hline + opb\_rx\_data[C\_SR\_WIDTH:0] & input & FIFO-RX Read Data \\ \hline + rx\_thresh[(2*C\_FIFO\_SIZE)-1:0] & output & FIFO-RX Prog Thresholds \\ \hline + \multicolumn{3} { c|} {FIFO-Flags(2,4)} \\ \hline + opb\_fifo\_flg[C\_NUM\_FLG-1:0] & input & FIFO Flags \\ \hline + \multicolumn{3} { c|} {IRQ-Signals} \\ \hline + opb\_dgie & output & Device Global IRQ Enable \\ \hline + opb\_ier(C\_NUM\_INT-1:0) & output & IRQ Enable Register \\ \hline + opb\_isr(C\_NUM\_INT-1:0) & input & IRQ Status Register \\ \hline + opb\_isr\_clr(C\_NUM\_INT-1:0) & output & Clear IRQ Flags \\ \hline + \end{tabular} + \caption{OPB\_IF} + \label{tab:opb_if} +\end{table} Index: spi_slave/tags/V100/doc/src/opb_spi_slave.tcp =================================================================== --- spi_slave/tags/V100/doc/src/opb_spi_slave.tcp (nonexistent) +++ spi_slave/tags/V100/doc/src/opb_spi_slave.tcp (revision 35) @@ -0,0 +1,12 @@ +[FormatInfo] +Type=TeXnicCenterProjectInformation +Version=4 + +[ProjectInfo] +MainFile=opb_spi_slave.tex +UseBibTeX=0 +UseMakeIndex=0 +ActiveProfile=LaTeX => PDF +ProjectLanguage=de +ProjectDialect=DE + Index: spi_slave/tags/V100/doc/opb_spi_slave.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spi_slave/tags/V100/doc/opb_spi_slave.pdf =================================================================== --- spi_slave/tags/V100/doc/opb_spi_slave.pdf (nonexistent) +++ spi_slave/tags/V100/doc/opb_spi_slave.pdf (revision 35)

spi_slave/tags/V100/doc/opb_spi_slave.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/ram.vhd (revision 35) @@ -0,0 +1,46 @@ +------------------------------------------------------------------------------- +--* +--* @short RAM Sync-Write, Async Read +--* +--* @generic C_FIFO_WIDTH RAM-With (1..xx) +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity ram is + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4); + + port (clk : in std_logic; + we : in std_logic; + a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); +end ram; + +architecture behavior of ram is + type ram_type is array (2**C_FIFO_SIZE_WIDTH-1 downto 0) of std_logic_vector (C_FIFO_WIDTH-1 downto 0); + signal RAM : ram_type; +begin + + process (clk) + begin + if (clk'event and clk = '1') then + if (we = '1') then + RAM(conv_integer(a)) <= di; + end if; + end if; + end process; + + dpo <= RAM(conv_integer(dpra)); + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray_adder.vhd (revision 35) @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------- +--* +--* @short gray Adder +--* +--* @generic width with of adder vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity gray_adder is + generic ( + width : integer := 4); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); +end gray_adder; + +architecture behavior of gray_adder is + --* convert gray to bin + component gray2bin + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); + end component; + --* convert bin to gray + component bin2gray + generic ( + width : integer); + port ( + in_bin : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + signal out_bin : std_logic_vector(width-1 downto 0); + signal bin_add : std_logic_vector(width-1 downto 0); + +begin -- behavior + --* convert input gray signal to binary + gray2bin_1 : gray2bin + generic map ( + width => width) + port map ( + in_gray => in_gray, + out_bin => out_bin); + + --* add one to signal + bin_add <= out_bin + 1; + --* convert signal back to gray + bin2gray_1 : bin2gray + generic map ( + width => width) + port map ( + in_bin => bin_add, + out_gray => out_gray); + + + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/shift_register.vhd (revision 35) @@ -0,0 +1,190 @@ +------------------------------------------------------------------------------- +--* +--* @short Shift-Register +--* +--* Control Register Description: +--* @li Bit0: DGE : Global Device Enable +--* @li Bit1: TX_EN: Transmit enable +--* @li Bit2: RX_EN: Receive enable +--* +--* Generics described in top entity. +--* @port opb_ctl_reg Control Register +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.1 +--* @date: 2007-11-11 +--/ +-- Version 1.0 Initial Release +-- Version 1.1 rx_cnt/tx_cnt only increment if < C_SR_WIDTH +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.opb_spi_slave_pack.all; + +entity shift_register is + + generic ( + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0); + + port ( + rst : in std_logic; + -- control register + opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + -- external + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + -- transmit fifo + sr_tx_clk : out std_logic; + sr_tx_en : out std_logic; + sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- receive fifo + sr_rx_clk : out std_logic; + sr_rx_en : out std_logic; + sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); +end shift_register; + + +architecture behavior of shift_register is + --* Global + signal sclk_int : std_logic; + signal sclk_int_inv : std_logic; + signal rx_cnt : integer range 0 to 31 := 0; + + -- RX + signal rx_sr_reg : std_logic_vector(C_SR_WIDTH-2 downto 0); + signal sr_rx_en_int : std_logic; + signal sr_rx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + + -- tx + signal miso_int : std_logic; + signal tx_cnt : integer range 0 to 31 := 0; + signal sr_tx_en_int : std_logic; + signal sr_tx_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0); + + +begin -- behavior + + miso_t <= ss_n; -- tristate + + + sclk_int <= sclk when (C_PHA = 0 and C_CPOL = 0) else + sclk when (C_PHA = 1 and C_CPOL = 1) else + not sclk; + + + sr_rx_en <= transport sr_rx_en_int after 1 ns; + sr_tx_en <= transport sr_tx_en_int after 1 ns; + + --* reorder received bits if not "MSB_First" + reorder_rx_bits : process(sr_rx_data_int) + begin + for i in 0 to C_SR_WIDTH-1 loop + if C_MSB_FIRST then + sr_rx_data(i) <= transport sr_rx_data_int(i) after 1 ns; + else + sr_rx_data(C_SR_WIDTH-1-i) <= transport sr_rx_data_int(i)after 1 ns; + end if; + end loop; -- i + end process reorder_rx_bits; + + --* reorder transmit bits if not "MSB_First" + reorder_tx_bits : process(sr_tx_data) + begin + for i in 0 to C_SR_WIDTH-1 loop + if C_MSB_FIRST then + sr_tx_data_int(i) <= sr_tx_data(i); + else + sr_tx_data_int(C_SR_WIDTH-1-i) <= sr_tx_data(i); + end if; + end loop; -- i + end process reorder_tx_bits; + + + ----------------------------------------------------------------------------- + + sr_rx_clk <= sclk_int; + + sr_rx_data_int <= rx_sr_reg & mosi; + + --* RX-Shift-Register + rx_shift_proc : process(rst, opb_ctl_reg, sclk_int) + begin + if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_RX_EN) = '0') then + rx_cnt <= 0; + sr_rx_en_int <= '0'; + rx_sr_reg <= (others => '0'); + + elsif rising_edge(sclk_int) then + if (ss_n = '0') then + rx_sr_reg <= rx_sr_reg(C_SR_WIDTH-3 downto 0) & mosi; + if (rx_cnt = C_SR_WIDTH-2) then + rx_cnt <= rx_cnt +1; + sr_rx_en_int <= '1'; + elsif (rx_cnt = C_SR_WIDTH-1) then + rx_cnt <= 0; + sr_rx_en_int <= '0'; + else + rx_cnt <= rx_cnt +1; + end if; + else + -- ss_n high + -- assert framing error if cnt != 0? + sr_rx_en_int <= '0'; + rx_cnt <= 0; + end if; + end if; + end process rx_shift_proc; + +------------------------------------------------------------------------------- + -- TX Shift Register + sr_tx_clk <= sclk_int_inv; + sclk_int_inv <= not sclk_int; + + miso_o <= sr_tx_data_int(C_SR_WIDTH-1) when (tx_cnt = 0) else + miso_int; + + + --* TX Shift-Register + tx_shift_proc : process(rst, opb_ctl_reg, sclk_int_inv) + begin + if (rst = '1' or opb_ctl_reg(C_OPB_CTL_REG_DGE) = '0' or opb_ctl_reg(C_OPB_CTL_REG_TX_EN) = '0') then + tx_cnt <= 0; + sr_tx_en_int <= '0'; + miso_int <= '0'; + elsif rising_edge(sclk_int_inv) then + if (ss_n = '0') then + if (tx_cnt /= C_SR_WIDTH-1) then + miso_int <= sr_tx_data_int(C_SR_WIDTH-1-(tx_cnt+1)); + end if; + if (tx_cnt = C_SR_WIDTH-2) then + sr_tx_en_int <= '1'; + tx_cnt <= tx_cnt +1; + elsif (tx_cnt = C_SR_WIDTH-1) then + tx_cnt <= 0; + sr_tx_en_int <= '0'; + else + tx_cnt <= tx_cnt +1; + end if; + else + -- ss_n high + -- assert framing error if cnt != 0? + sr_tx_en_int <= '0'; + tx_cnt <= 0; + end if; + end if; + end process tx_shift_proc; +------------------------------------------------------------------------------- + + end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo.vhd (revision 35) @@ -0,0 +1,262 @@ +------------------------------------------------------------------------------- +--* +--* @short Configurable FIFO +--* +--* @generic C_FIFO_WIDTH RAM-With (1..xx) +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* @generic C_SYNC_TO Sync FIFO Flags to read or write clock +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +entity fifo is + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4; + C_SYNC_TO : string := "RD"); + port ( + rst : in std_logic; + -- write port + wr_clk : in std_logic; + wr_en : in std_logic; + din : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + -- read port + rd_clk : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(C_FIFO_WIDTH-1 downto 0); + -- flags + empty : out std_logic; + full : out std_logic; + overflow : out std_logic; + underflow : out std_logic; + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + +end fifo; + +architecture behavior of fifo is + --* ram with sync write and async read + component ram + generic ( + C_FIFO_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4); + port ( + clk : in std_logic; + we : in std_logic; + a : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + dpra : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + di : in std_logic_vector(C_FIFO_WIDTH-1 downto 0); + dpo : out std_logic_vector(C_FIFO_WIDTH-1 downto 0)); + end component; + + --* component generates fifo flag + component fifo_prog_flags + generic ( + C_FIFO_SIZE_WIDTH : integer; + C_SYNC_TO : string); + port ( + rst : in std_logic; + clk : in std_logic; + cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + end component; + + --* logic coded gray counter + component gray_adder + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); + end component; + + signal wr_cnt_gray_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal wr_cnt_next_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal rd_cnt_grey_add_one : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + attribute fsm_extract : string; + -- wr_clock domain + -- main wr grey code counter + signal wr_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of wr_cnt_grey : signal is "no"; + + -- main grey code counter for full + signal wr_cnt_next_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of wr_cnt_next_grey : signal is "no"; + + -- rd_clk domain + -- main rd grey code counter + signal rd_cnt_grey : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + attribute fsm_extract of rd_cnt_grey : signal is "no"; + + -- binary counter for prog full/empty + signal rd_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + signal wr_cnt : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + signal empty_int : std_logic; + signal full_int : std_logic; + +begin -- behavior + + empty <= empty_int; + full <= full_int; + +--* write counter generation + fifo_write_proc: process(rst, wr_clk) + begin + if (rst = '1') then + wr_cnt_grey <= (others => '0'); + wr_cnt <= (others => '0'); + wr_cnt_next_grey(C_FIFO_SIZE_WIDTH-1 downto 1) <= (others => '0'); + wr_cnt_next_grey(0) <= '1'; + elsif rising_edge(wr_clk) then + if (wr_en = '1') then + wr_cnt <= wr_cnt+1; + + -- wr_cnt_grey <= add_grey_rom(conv_integer(wr_cnt_grey)); + wr_cnt_grey <= wr_cnt_gray_add_one; + + -- wr_cnt_next_grey <= add_grey_rom(conv_integer(wr_cnt_next_grey)); + wr_cnt_next_grey <= wr_cnt_next_grey_add_one; + + end if; + end if; + end process fifo_write_proc; + + --* add one to wr_cnt_gray + gray_adder_1 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => wr_cnt_grey, + out_gray => wr_cnt_gray_add_one); + + --* add one to wr_cnt_next_grey + gray_adder_2 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => wr_cnt_next_grey, + out_gray => wr_cnt_next_grey_add_one); + + +--* read counter generation + fifo_read_proc: process(rst, rd_clk) + begin + if (rst = '1') then + rd_cnt_grey <= (others => '0'); + rd_cnt <= (others => '0'); + elsif rising_edge(rd_clk) then + -- rd grey code counter + if (rd_en = '1') then + -- rd_cnt_grey <= add_grey_rom(conv_integer(rd_cnt_grey)); + rd_cnt_grey <= rd_cnt_grey_add_one; + rd_cnt <= rd_cnt+1; + end if; + end if; + end process fifo_read_proc; + + --* add one to rd_cnt_grey + gray_adder_3 : gray_adder + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => rd_cnt_grey, + out_gray => rd_cnt_grey_add_one); + + + --* FIFO Memory + ram_1 : ram + generic map ( + C_FIFO_WIDTH => C_FIFO_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) + port map ( + clk => wr_clk, + we => wr_en, + a => wr_cnt_grey, + di => din, + dpra => rd_cnt_grey, + dpo => dout); + + + --* generate overflow + gen_of_proc: process(rst, wr_clk) + begin + if (rst = '1') then + overflow <= '0'; + elsif rising_edge(wr_clk) then + if (full_int = '1' and wr_en = '1') then + overflow <= '1'; + end if; + end if; + end process gen_of_proc; + + --* generate underflow + gen_uf_proc: process(rst, rd_clk) + begin + if (rst = '1') then + underflow <= '0'; + elsif rising_edge(rd_clk) then + if (empty_int = '1' and rd_en = '1') then + underflow <= '1'; + end if; + end if; + end process gen_uf_proc; + + -- generate empty + empty_int <= '1' when (wr_cnt_grey = rd_cnt_grey) else + '0'; + + -- generate full + full_int <= '1' when (wr_cnt_next_grey = rd_cnt_grey) else + '0'; + + --* select clock side for flags + u1 : if (C_SYNC_TO = "WR") generate + --* sync flags to write clock + fifo_prog_flags_1 : fifo_prog_flags + generic map ( + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => C_SYNC_TO) + port map ( + rst => rst, + clk => wr_clk, + cnt_grey => rd_cnt_grey, + cnt => wr_cnt, + prog_full_thresh => prog_full_thresh, + prog_empty_thresh => prog_empty_thresh, + prog_empty => prog_empty, + prog_full => prog_full); + end generate u1; + + u2 : if (C_SYNC_TO = "RD") generate + --* sync flags to read clock + fifo_prog_flags_1 : fifo_prog_flags + generic map ( + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => C_SYNC_TO) + port map ( + rst => rst, + clk => rd_clk, + cnt_grey => wr_cnt_grey, + cnt => rd_cnt, + prog_full_thresh => prog_full_thresh, + prog_empty_thresh => prog_empty_thresh, + prog_empty => prog_empty, + prog_full => prog_full); + end generate u2; +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave_pack.vhd (revision 35) @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +package opb_spi_slave_pack is + + constant C_ADR_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#0#, 6); + constant C_ADR_STATUS : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#1#, 6); + constant C_ADR_TX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#2#, 6); + constant C_ADR_RX_DATA : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#3#, 6); + constant C_ADR_TX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#4#, 6); + constant C_ADR_RX_THRESH : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#5#, 6); + constant C_ADR_TX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#6#, 6); + constant C_ADR_TX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#7#, 6); + constant C_ADR_TX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#8#, 6); + constant C_ADR_RX_DMA_CTL : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#9#, 6); + constant C_ADR_RX_DMA_ADDR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#A#, 6); + constant C_ADR_RX_DMA_NUM : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#B#, 6); + +-- XIIF_V123B compatible + constant C_ADR_DGIE : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#10#, 6); + constant C_ADR_ISR : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#11#, 6); + constant C_ADR_IER : std_logic_vector(7 downto 2) := conv_std_logic_vector(16#12#, 6); + + constant C_NUM_FLG : integer := 15; + constant C_NUM_INT : integer := 10; + + +-- CTL_Register + -- width + constant C_OPB_CTL_REG_WIDTH : integer := 4; + -- bits + constant C_OPB_CTL_REG_DGE : integer := 0; + constant C_OPB_CTL_REG_TX_EN : integer := 1; + constant C_OPB_CTL_REG_RX_EN : integer := 2; + constant C_OPB_CTL_REG_RST : integer := 3; + + + -- Status Register + constant SPI_SR_Bit_TX_Prog_Full : integer := 0; + constant SPI_SR_Bit_TX_Full : integer := 1; + constant SPI_SR_Bit_TX_Overflow : integer := 2; + constant SPI_SR_Bit_TX_Prog_empty : integer := 3; + constant SPI_SR_Bit_TX_Empty : integer := 4; + constant SPI_SR_Bit_TX_Underflow : integer := 5; + + constant SPI_SR_Bit_RX_Prog_Full : integer := 6; + constant SPI_SR_Bit_RX_Full : integer := 7; + constant SPI_SR_Bit_RX_Overflow : integer := 8; + constant SPI_SR_Bit_RX_Prog_empty : integer := 9; + constant SPI_SR_Bit_RX_Empty : integer := 10; + constant SPI_SR_Bit_RX_Underflow : integer := 11; + + constant SPI_SR_Bit_SS_n : integer := 12; + + -- Interrupt Status Register + constant SPI_ISR_Bit_TX_Prog_Empty : integer := 0; + constant SPI_ISR_Bit_TX_Empty : integer := 1; + constant SPI_ISR_Bit_TX_Underflow : integer := 2; + constant SPI_ISR_Bit_RX_Prog_Full : integer := 3; + constant SPI_ISR_Bit_RX_Full : integer := 4; + constant SPI_ISR_Bit_RX_Overflow : integer := 5; + constant SPI_ISR_Bit_SS_Fall : integer := 6; + constant SPI_ISR_Bit_SS_Rise : integer := 7; +end opb_spi_slave_pack; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_spi_slave.vhd (revision 35) @@ -0,0 +1,562 @@ +------------------------------------------------------------------------------- +--* +--* @short Top entity of the project opi_spi_slave +--* +--* @generic C_FAMILY virtex-4 and generic supported +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +library UNISIM; +use UNISIM.vcomponents.all; + +library work; +use work.opb_spi_slave_pack.all; + + +entity opb_spi_slave is + + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 0; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + + C_FAMILY : string := "virtex4"; + -- user ports + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0; + C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32 + C_DMA_EN : boolean := false); + + port ( + -- OPB signals (Slave Side) + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + + -- OPB signals (Master Side) + -- Arbitration + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + -- + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + -- spi ports + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + -- irq output + opb_irq : out std_logic); + +end opb_spi_slave; + +architecture behavior of opb_spi_slave is + + component opb_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_DMA_EN : boolean); + port ( + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + opb_s_tx_en : out std_logic; + opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_s_rx_en : out std_logic; + opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); + opb_dgie : out std_logic; + opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_ctl : out std_logic_vector(0 downto 0); + opb_tx_dma_num : out std_logic_vector(15 downto 0); + opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_ctl : out std_logic_vector(0 downto 0); + opb_rx_dma_num : out std_logic_vector(15 downto 0)); + end component; + + + component opb_m_if + generic ( + C_BASEADDR : std_logic_vector(0 to 31); + C_HIGHADDR : std_logic_vector(0 to 31); + C_USER_ID_CODE : integer; + C_OPB_AWIDTH : integer; + C_OPB_DWIDTH : integer; + C_FAMILY : string; + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1; + C_FIFO_SIZE_WIDTH : integer range 4 to 7); + port ( + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + opb_m_tx_req : in std_logic; + opb_m_tx_en : out std_logic; + opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_tx_dma_ctl : in std_logic_vector(0 downto 0); + opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_num : in std_logic_vector(15 downto 0); + opb_tx_dma_done : out std_logic; + opb_m_rx_req : in std_logic; + opb_m_rx_en : out std_logic; + opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_rx_dma_ctl : in std_logic_vector(0 downto 0); + opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_num : in std_logic_vector(15 downto 0); + opb_rx_dma_done : out std_logic); + end component; + + component shift_register + generic ( + C_SR_WIDTH : integer; + C_MSB_FIRST : boolean; + C_CPOL : integer range 0 to 1; + C_PHA : integer range 0 to 1); + port ( + rst : in std_logic; + opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + sclk : in std_logic; + ss_n : in std_logic; + mosi : in std_logic; + miso_o : out std_logic; + miso_i : in std_logic; + miso_t : out std_logic; + sr_tx_clk : out std_logic; + sr_tx_en : out std_logic; + sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + sr_rx_clk : out std_logic; + sr_rx_en : out std_logic; + sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0)); + end component; + + component fifo + generic ( + C_FIFO_WIDTH : integer; + C_FIFO_SIZE_WIDTH : integer; + C_SYNC_TO : string); + port ( + rst : in std_logic; + wr_clk : in std_logic; + wr_en : in std_logic; + din : in std_logic_vector(C_SR_WIDTH-1 downto 0); + rd_clk : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(C_SR_WIDTH-1 downto 0); + empty : out std_logic; + full : out std_logic; + overflow : out std_logic; + underflow : out std_logic; + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + end component; + + component irq_ctl + generic ( + C_ACTIVE_EDGE : std_logic); + port ( + rst : in std_logic; + clk : in std_logic; + opb_fifo_flg : in std_logic; + opb_ier : in std_logic; + opb_isr : out std_logic; + opb_isr_clr : in std_logic); + end component; + +-- opb_if + signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + + signal opb_s_tx_en : std_logic; + signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_s_rx_en : std_logic; + signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + + signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_tx_dma_num : std_logic_vector(15 downto 0); + signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_ctl : std_logic_vector(0 downto 0); + signal opb_rx_dma_num : std_logic_vector(15 downto 0); + + -- opb_m_if + signal opb_m_tx_en : std_logic; + signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal opb_m_rx_en : std_logic; + signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + +-- shift_register + signal sr_tx_clk : std_logic; + signal sr_tx_en : std_logic; + signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal sr_rx_clk : std_logic; + signal sr_rx_en : std_logic; + signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + + signal sclk_ibuf : std_logic; + signal sclk_bufr : std_logic; + + signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0); + signal opb_irq_flg : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0'); + signal rst : std_logic; + + + signal opb_dgie : std_logic; + signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0); + + -- opb_spi_slave + signal fifo_tx_en : std_logic; + signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + signal fifo_rx_en : std_logic; + signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + +begin -- behavior + + --* + virtex4_slk_buf : if C_FAMILY = "virtex4" generate + --* If C_FAMILY=Virtex-4 use "IBUF" + IBUF_1 : IBUF + port map ( + I => sclk, + O => sclk_ibuf); + +--* If C_FAMILY=Virtex-4 use "BUFR" + BUFR_1 : BUFR + generic map ( + BUFR_DIVIDE => "BYPASS", + SIM_DEVICE => "VIRTEX4") + port map ( + O => sclk_bufr, + CE => '0', + CLR => '0', + I => sclk_ibuf); + end generate virtex4_slk_buf; + + generic_sclk_buf : if C_FAMILY /= "virtex4" generate + sclk_bufr <= sclk; + end generate generic_sclk_buf; + + --* OPB-Slave Interface(Register-Interface) + opb_if_2 : opb_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_DMA_EN => C_DMA_EN) + port map ( + OPB_ABus => OPB_ABus, + OPB_BE => OPB_BE, + OPB_Clk => OPB_Clk, + OPB_DBus => OPB_DBus, + OPB_RNW => OPB_RNW, + OPB_Rst => OPB_Rst, + OPB_select => OPB_select, + OPB_seqAddr => OPB_seqAddr, + Sln_DBus => Sln_DBus, + Sln_errAck => Sln_errAck, + Sln_retry => Sln_retry, + Sln_toutSup => Sln_toutSup, + Sln_xferAck => Sln_xferAck, + opb_s_tx_en => opb_s_tx_en, + opb_s_tx_data => opb_s_tx_data, + opb_s_rx_en => opb_s_rx_en, + opb_s_rx_data => opb_s_rx_data, + opb_ctl_reg => opb_ctl_reg, + tx_thresh => tx_thresh, + rx_thresh => rx_thresh, + opb_fifo_flg => opb_fifo_flg, + opb_dgie => opb_dgie, + opb_ier => opb_ier, + opb_isr => opb_isr, + opb_isr_clr => opb_isr_clr, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_num => opb_tx_dma_num, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_num => opb_rx_dma_num); + + --* OPB-Master-Interface + --* + --* (DMA Read/Write Transfers to TX/RX-FIFO) + + dma_enable : if (C_DMA_EN = true) generate + opb_m_if_1 : opb_m_if + generic map ( + C_BASEADDR => C_BASEADDR, + C_HIGHADDR => C_HIGHADDR, + C_USER_ID_CODE => C_USER_ID_CODE, + C_OPB_AWIDTH => C_OPB_AWIDTH, + C_OPB_DWIDTH => C_OPB_DWIDTH, + C_FAMILY => C_FAMILY, + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH) + port map ( + OPB_Clk => OPB_Clk, + OPB_Rst => OPB_Rst, + OPB_DBus => OPB_DBus, + M_request => M_request, + MOPB_MGrant => MOPB_MGrant, + M_busLock => M_busLock, + M_ABus => M_ABus, + M_BE => M_BE, + M_DBus => M_DBus, + M_RNW => M_RNW, + M_select => M_select, + M_seqAddr => M_seqAddr, + MOPB_errAck => MOPB_errAck, + MOPB_retry => MOPB_retry, + MOPB_timeout => MOPB_timeout, + MOPB_xferAck => MOPB_xferAck, + opb_m_tx_req => opb_fifo_flg(3), + opb_m_tx_en => opb_m_tx_en, + opb_m_tx_data => opb_m_tx_data, + opb_tx_dma_ctl => opb_tx_dma_ctl, + opb_tx_dma_addr => opb_tx_dma_addr, + opb_tx_dma_num => opb_tx_dma_num, + opb_tx_dma_done => opb_fifo_flg(13), + opb_m_rx_req => opb_fifo_flg(6), + opb_m_rx_en => opb_m_rx_en, + opb_m_rx_data => opb_m_rx_data, + opb_rx_dma_ctl => opb_rx_dma_ctl, + opb_rx_dma_addr => opb_rx_dma_addr, + opb_rx_dma_num => opb_rx_dma_num, + opb_rx_dma_done => opb_fifo_flg(14)); + end generate dma_enable; + + dma_disable : if (C_DMA_EN = false) generate + M_request <= '0'; + M_busLock <= '0'; + M_ABus <= (others => '0'); + M_BE <= (others => '0'); + M_DBus <= (others => '0'); + M_RNW <= '0'; + M_select <= '0'; + M_seqAddr <= '0'; + opb_m_tx_en <= '0'; + opb_m_tx_data <= (others => '0'); + opb_fifo_flg(13) <= '0'; + opb_m_rx_en <= '0'; + opb_fifo_flg(14) <= '0'; + end generate dma_disable; + + --* Shift-Register + shift_register_1 : shift_register + generic map ( + C_SR_WIDTH => C_SR_WIDTH, + C_MSB_FIRST => C_MSB_FIRST, + C_CPOL => C_CPOL, + C_PHA => C_PHA) + port map ( + rst => rst, + opb_ctl_reg => opb_ctl_reg, + sclk => sclk_bufr, + ss_n => ss_n, + mosi => mosi, + miso_o => miso_o, + miso_i => miso_i, + miso_t => miso_t, + sr_tx_clk => sr_tx_clk, + sr_tx_en => sr_tx_en, + sr_tx_data => sr_tx_data, + sr_rx_clk => sr_rx_clk, + sr_rx_en => sr_rx_en, + sr_rx_data => sr_rx_data); + + --* Transmit FIFO + tx_fifo_1 : fifo + generic map ( + C_FIFO_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => "WR") + port map ( + -- global + rst => rst, + prog_full_thresh => tx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), + prog_empty_thresh => tx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), + -- write port + wr_clk => OPB_Clk, + wr_en => fifo_tx_en, + din => fifo_tx_data, + -- flags + prog_full => opb_fifo_flg(0), + full => opb_fifo_flg(1), + overflow => opb_fifo_flg(2), + -- read port + rd_clk => sr_tx_clk, + rd_en => sr_tx_en, + dout => sr_tx_data, + -- flags + prog_empty => opb_fifo_flg(3), + empty => opb_fifo_flg(4), + underflow => opb_fifo_flg(5)); + + fifo_tx_en <= opb_s_tx_en or opb_m_tx_en; + fifo_tx_data <= opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else + opb_s_tx_data; + + --* Receive FIFO + rx_fifo_1 : fifo + generic map ( + C_FIFO_WIDTH => C_SR_WIDTH, + C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, + C_SYNC_TO => "RD") + port map ( + -- global + rst => rst, + prog_full_thresh => rx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0), + prog_empty_thresh => rx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH), + -- write port + wr_clk => sr_rx_clk, + wr_en => sr_rx_en, + din => sr_rx_data, + -- flags + prog_full => opb_fifo_flg(6), + full => opb_fifo_flg(7), + overflow => opb_fifo_flg(8), + -- read port + rd_clk => opb_clk, + rd_en => fifo_rx_en, + dout => fifo_rx_data, + -- flags + prog_empty => opb_fifo_flg(9), + empty => opb_fifo_flg(10), + underflow => opb_fifo_flg(11)); + + fifo_rx_en <= opb_s_rx_en or opb_m_rx_en; + opb_s_rx_data <= fifo_rx_data; + opb_m_rx_data <= fifo_rx_data; + + rst <= OPB_Rst or opb_ctl_reg(C_OPB_CTL_REG_RST); + + opb_fifo_flg(12) <= ss_n; + + + + + -- Bit 0 : TX_PROG_EMPTY + opb_irq_flg(0) <= opb_fifo_flg(3); + -- Bit 1 : TX_EMPTY + opb_irq_flg(1) <= opb_fifo_flg(4); + -- Bit 2 : TX_Underflow + opb_irq_flg(2) <= opb_fifo_flg(5); + -- Bit 3 : RX_PROG_FULL + opb_irq_flg(3) <= opb_fifo_flg(6); + -- Bit 4 : RX_FULL + opb_irq_flg(4) <= opb_fifo_flg(7); + -- Bit 5 : RX_Overflow + opb_irq_flg(5) <= opb_fifo_flg(9); + -- Bit 6: CS_H_TO_L + opb_irq_flg(6) <= not opb_fifo_flg(12); + -- Bit 7: CS_L_TO_H + opb_irq_flg(7) <= opb_fifo_flg(12); + -- Bit 8: TX DMA Done + opb_irq_flg(8) <= opb_fifo_flg(13); + -- Bit 9: RX DMA Done + opb_irq_flg(9) <= opb_fifo_flg(14); + + --* IRQ Enable, Detection and Flags Control + irq_gen : for i in 0 to C_NUM_INT-1 generate + irq_ctl_1 : irq_ctl + generic map ( + C_ACTIVE_EDGE => '1') + port map ( + rst => rst, + clk => OPB_Clk, + opb_fifo_flg => opb_irq_flg(i), + opb_ier => opb_ier(i), + opb_isr => opb_isr(i), + opb_isr_clr => opb_isr_clr(i)); + end generate irq_gen; + + -- assert irq if one Interupt Status bit set + opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else + '0'; + + + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/fifo_prog_flags.vhd (revision 35) @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +--* +--* @short Generate fifo flags +--* +--* @generic C_FIFO_SIZE_WIDTH RAM Size = 2**C_FIFO_SIZE_WIDTH +--* @generic C_SYNC_TO Sync FIFO Flags to read or write clock +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +entity fifo_prog_flags is + generic ( + C_FIFO_SIZE_WIDTH : integer := 4; + C_SYNC_TO : string := "WR"); + port ( + rst : in std_logic; + clk : in std_logic; + cnt_grey : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + cnt : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + prog_empty : out std_logic; + prog_full : out std_logic); + +end fifo_prog_flags; +architecture behavior of fifo_prog_flags is + + -- sync register for clock domain transfer + signal cnt_grey_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + type rom_t is array (0 to (2**C_FIFO_SIZE_WIDTH)-1) of std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + + --* convert from gray to binary + component gray2bin + generic ( + width : integer); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); + end component; + + signal cnt_bin_reg : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + +begin -- behavior + + --* Generate fifo flags + gen_flags_proc: process(rst, clk) + variable diff : std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0); + begin + if (rst = '1') then + cnt_grey_reg <= (others => '0'); + prog_empty <= '1'; + prog_full <= '0'; + elsif rising_edge(clk) then + -- transfer to rd_clk domain + cnt_grey_reg <= cnt_grey; + -- fifo prog full/empty + if (C_SYNC_TO = "RD") then + -- diff := conv_grey_rom(conv_integer(cnt_grey_reg))- cnt; + diff := cnt_bin_reg - cnt; + else + -- diff := cnt - conv_grey_rom(conv_integer(cnt_grey_reg)); + diff := cnt - cnt_bin_reg; + end if; + + if (diff > prog_full_thresh) then + prog_full <= '1'; + else + prog_full <= '0'; + end if; + + if (diff < prog_empty_thresh) then + prog_empty <= '1'; + else + prog_empty <= '0'; + end if; + end if; + end process gen_flags_proc; + + --* convert gray to bin + gray2bin_1: gray2bin + generic map ( + width => C_FIFO_SIZE_WIDTH) + port map ( + in_gray => cnt_grey_reg, + out_bin => cnt_bin_reg); + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_m_if.vhd (revision 35) @@ -0,0 +1,300 @@ +------------------------------------------------------------------------------- +--* +--* @short OPB-Master Interface +--* +--* Generics described in top entity. +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +entity opb_m_if is + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 0; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "virtex-4"; + C_SR_WIDTH : integer := 8; + C_MSB_FIRST : boolean := true; + C_CPOL : integer range 0 to 1 := 0; + C_PHA : integer range 0 to 1 := 0; + C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 7); + + port ( + -- opb master interface + OPB_Clk : in std_logic; + OPB_Rst : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + M_request : out std_logic; + MOPB_MGrant : in std_logic; + M_busLock : out std_logic; + M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); + M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); + M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + M_RNW : out std_logic; + M_select : out std_logic; + M_seqAddr : out std_logic; + MOPB_errAck : in std_logic; + MOPB_retry : in std_logic; + MOPB_timeout : in std_logic; + MOPB_xferAck : in std_logic; + --------------------------------------------------------------------------- + -- read transfer + -- read data from memory and fill fifo + opb_m_tx_req : in std_logic; + opb_m_tx_en : out std_logic; + opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + -- enable/disable dma transfer + opb_tx_dma_ctl : in std_logic_vector(0 downto 0); + -- base adress for transfer + opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_num : in std_logic_vector(15 downto 0); + opb_tx_dma_done : out std_logic; + --------------------------------------------------------------------------- + -- write transfer + -- read fifo an write to memory + opb_m_rx_req : in std_logic; + opb_m_rx_en : out std_logic; + opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- enable/disable dma transfer + opb_rx_dma_ctl : in std_logic_vector(0 downto 0); + -- base adress for transfer + opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_num : in std_logic_vector(15 downto 0); + opb_rx_dma_done : out std_logic); +end opb_m_if; + +architecture behavior of opb_m_if is + + type state_t is (idle, + wait_grant, + transfer_write, + transfer_read, + done); + + + signal state : state_t := idle; + + signal M_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal M_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + + signal M_select_int : std_logic; + signal read_transfer : boolean; + + -- read transfer + signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_en : std_logic; + signal opb_tx_dma_num_int : std_logic_vector(15 downto 0); + signal opb_tx_dma_done_int : std_logic; + + -- write transfer + signal opb_rx_dma_en : std_logic; + signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_num_int : std_logic_vector(15 downto 0); + signal opb_rx_dma_done_int : std_logic; + + + +begin -- behavior + + --* convert M_DBus_big_end to little endian + process(M_DBus_big_end) + begin + for i in 0 to 31 loop + M_DBus(31-i) <= M_DBus_big_end(i); + end loop; -- i + end process; + + --* convert M_ABus_big_end to little endian + process(M_ABus_big_end) + begin + for i in 0 to 31 loop + M_ABus(31-i) <= M_ABus_big_end(i); + end loop; -- i + end process; + + --* convert OPB_DBus to bi endian + process(OPB_DBus) + begin + for i in 0 to 31 loop + OPB_DBus_big_end(31-i) <= OPB_DBus(i); + end loop; -- i + end process; + + -- for both sides + M_ABus_big_end <= opb_tx_dma_addr_int when (M_select_int = '1' and (read_transfer = true)) else + opb_rx_dma_addr_int when (M_select_int = '1' and (read_transfer = false)) else + (others => '0'); + M_select <= M_select_int; + + + + -- write transfer + opb_m_rx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = false)) else + '0'; + + M_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_m_rx_data when (M_select_int = '1' and (read_transfer = false)) else + (others => '0'); + M_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0'); + + opb_tx_dma_done <= opb_tx_dma_done_int; + + -- read transfer + opb_m_tx_en <= MOPB_xferAck when (M_select_int = '1' and (read_transfer = true)) else + '0'; + opb_m_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); + + opb_rx_dma_done <= opb_rx_dma_done_int; + + + +------------------------------------------------------------------------------- + opb_masteer_proc: process(OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + M_BE <= (others => '0'); + M_busLock <= '0'; + M_request <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_seqAddr <= '0'; + opb_tx_dma_done_int <= '0'; + opb_rx_dma_done_int <= '0'; + elsif rising_edge(OPB_Clk) then + case state is + when idle => + opb_tx_dma_en <= opb_tx_dma_ctl(0); + opb_rx_dma_en <= opb_rx_dma_ctl(0); + + if (opb_tx_dma_ctl(0) = '1' and opb_tx_dma_en = '0') then + opb_tx_dma_addr_int <= opb_tx_dma_addr; + opb_tx_dma_num_int <= opb_tx_dma_num; + opb_tx_dma_done_int <= '0'; + + end if; + + if (opb_rx_dma_ctl(0) = '1' and opb_rx_dma_en = '0') then + opb_rx_dma_addr_int <= opb_rx_dma_addr; + opb_rx_dma_num_int <= opb_rx_dma_num; + opb_rx_dma_done_int <= '0'; + end if; + + if (opb_tx_dma_en = '1' and opb_m_tx_req = '1' and opb_tx_dma_done_int = '0') then + -- read from memory to fifo + M_request <= '1'; + read_transfer <= true; + state <= wait_grant; + elsif (opb_rx_dma_en = '1' and opb_m_rx_req = '1'and opb_rx_dma_done_int = '0') then + -- read from fifo and write memory + M_request <= '1'; + read_transfer <= false; + state <= wait_grant; + else + state <= idle; + end if; + + when wait_grant => + if (MOPB_MGrant = '1') then + M_request <= '0'; + M_busLock <= '1'; + M_select_int <= '1'; + M_seqAddr <= '1'; + M_BE <= "1111"; + if (read_transfer) then + -- read + M_RNW <= '1'; + state <= transfer_read; + else + -- write + M_RNW <= '0'; + state <= transfer_write; + end if; + else + state <= wait_grant; + end if; + + when transfer_read => + if (MOPB_xferAck = '1') then + opb_tx_dma_addr_int <= opb_tx_dma_addr_int +4; + if (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then + -- cycle 14 + -- deassert buslock and seq_address 1 cycle before transfer complete + M_busLock <= '0'; + M_seqAddr <= '0'; + elsif (opb_tx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then + -- cycle 15 + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + if (conv_integer(opb_tx_dma_num_int) = 0) then + opb_tx_dma_done_int <= '1'; + else + opb_tx_dma_num_int <= opb_tx_dma_num_int-1; + end if; + state <= done; + end if; + elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then + -- cancel transfer + M_busLock <= '0'; + M_seqAddr <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + state <= done; + else + state <= transfer_read; + end if; + + when transfer_write => + if (MOPB_xferAck = '1') then + opb_rx_dma_addr_int <= opb_rx_dma_addr_int +4; + if (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(14, 4)) then + -- cycle 14 + -- deassert buslock and seq_address 1 cycle before transfer complete + M_busLock <= '0'; + M_seqAddr <= '0'; + elsif (opb_rx_dma_addr_int(5 downto 2) = conv_std_logic_vector(15, 4)) then + -- cycle 15 + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + if (conv_integer(opb_rx_dma_num_int) = 0) then + opb_rx_dma_done_int <= '1'; + else + opb_rx_dma_num_int <= opb_rx_dma_num_int-1; + end if; + state <= done; + end if; + elsif (MOPB_retry = '1' or MOPB_errAck = '1' or MOPB_timeout = '1') then + -- cancel transfer + M_busLock <= '0'; + M_seqAddr <= '0'; + M_RNW <= '0'; + M_select_int <= '0'; + M_BE <= (others => '0'); + state <= done; + else + state <= transfer_write; + end if; + + when done => + + state <= idle; + + when others => + state <= idle; + end case; + end if; + end process opb_masteer_proc; +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/bin2gray.vhd (revision 35) @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------- +--* +--* @short convert binary input vector to gray +--* +--* @generic width with of input vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity bin2gray is + generic ( + width : integer := 4); + port ( + in_bin : in std_logic_vector(width-1 downto 0); + out_gray : out std_logic_vector(width-1 downto 0)); +end bin2gray; + +architecture behavior of bin2gray is + +begin -- behavior + + -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 + --* convert binary input vector to gray + bin2gray_proc : process(in_bin) + begin + out_gray(width-1) <= in_bin(width-1); + -- out_gray(3) <= in_bin(3); + + for i in 1 to width-1 loop + out_gray(width-1-i) <= in_bin(width-i) xor in_bin(width-1-i); + end loop; -- i + end process bin2gray_proc; + + -- i=1 out_gray(2) <= in_bin(3) xor in_bin(2); + -- i=2 out_gray(1) <= in_bin(2) xor in_bin(1); + -- i=3 out_gray(0) <= in_bin(1) xor in_bin(0); + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/gray2bin.vhd (revision 35) @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------- +--* +--* @short convert gray input vector to binary +--* +--* @generic width with of input vector +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity gray2bin is + generic ( + width : integer := 4); + port ( + in_gray : in std_logic_vector(width-1 downto 0); + out_bin : out std_logic_vector(width-1 downto 0)); +end gray2bin; + +architecture behavior of gray2bin is + + signal out_bin_int : std_logic_vector(width-1 downto 0); +begin -- behavior + + out_bin <= out_bin_int; + + -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8 + --* convert gray input vector to binary + gray2bin_proc: process(in_gray, out_bin_int) + begin + out_bin_int(width-1) <= in_gray(width-1); + -- out_gray(3) <= in_gray(3); + for i in 1 to width-1 loop + out_bin_int(width-1-i) <= out_bin_int(width-i) xor in_gray(width-1-i); + end loop ; -- i + end process gray2bin_proc; + -- i=1 out_bin(2) <= out_bin_int(3) xor out_bin(2); + -- i=2 out_bin(1) <= out_bin_int(2) xor out_bin(1); + -- i=3 out_bin(0) <= out_bin_int(1) xor out_bin(0); +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/irq_ctl.vhd (revision 35) @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------- +--* +--* @short Control Unit for IRQ detection, enable and clear +--* +--* @generic C_ACTIVE_EDGE Select active edge for IRQ-Source 0: H->L;1: L->H +--* +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +entity irq_ctl is + generic ( + C_ACTIVE_EDGE : std_logic := '0'); + port ( + rst : in std_logic; + clk : in std_logic; + opb_fifo_flg : in std_logic; + opb_ier : in std_logic; + opb_isr : out std_logic; + opb_isr_clr : in std_logic); + +end irq_ctl; + +architecture behavior of irq_ctl is + + signal opb_fifo_flg_int : std_logic; + signal opb_fifo_flg_reg : std_logic; +begin -- behavior + + opb_fifo_flg_int <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else + not opb_fifo_flg; + + irq_ctl_proc: process(rst, clk) + begin + if (rst = '1') then + opb_isr <= '0'; + elsif rising_edge(clk) then + opb_fifo_flg_reg <= opb_fifo_flg_int; + if (opb_ier= '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then + opb_isr <= '1'; + elsif (opb_isr_clr = '1') then + opb_isr <= '0'; + end if; + end if; + end process irq_ctl_proc; + + +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/hdl/vhdl/opb_if.vhd (revision 35) @@ -0,0 +1,336 @@ +------------------------------------------------------------------------------- +--* +--* @short OPB-Slave Interface +--* +--* Generics described in top entity. +--* +--* @see opb_spi_slave +--* @author: Daniel Köthe +--* @version: 1.0 +--* @date: 2007-11-11 +--/ +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; -- conv_integer() + +library work; +use work.opb_spi_slave_pack.all; + +entity opb_if is + + generic ( + C_BASEADDR : std_logic_vector(0 to 31) := X"00000000"; + C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF"; + C_USER_ID_CODE : integer := 3; + C_OPB_AWIDTH : integer := 32; + C_OPB_DWIDTH : integer := 32; + C_FAMILY : string := "virtex-4"; + C_SR_WIDTH : integer := 8; + C_FIFO_SIZE_WIDTH : integer := 4; + C_DMA_EN : boolean := true); + port ( + -- OPB-Bus Signals + OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); + OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); + OPB_Clk : in std_logic; + OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); + OPB_RNW : in std_logic; + OPB_Rst : in std_logic; + OPB_select : in std_logic; + OPB_seqAddr : in std_logic; + Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); + Sln_errAck : out std_logic; + Sln_retry : out std_logic; + Sln_toutSup : out std_logic; + Sln_xferAck : out std_logic; + -- fifo ports + opb_s_tx_en : out std_logic; + opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0); + opb_s_rx_en : out std_logic; + opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0); + -- control register + opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + -- Fifo almost full/empty thresholds + tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0); + -- interrupts + opb_dgie : out std_logic; + opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0); + opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0); + -- dma register + opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_tx_dma_ctl : out std_logic_vector(0 downto 0); + opb_tx_dma_num : out std_logic_vector(15 downto 0); + opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0); + opb_rx_dma_ctl : out std_logic_vector(0 downto 0); + opb_rx_dma_num : out std_logic_vector(15 downto 0)); +end opb_if; + +architecture behavior of opb_if is + + + signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + + + type state_t is (idle, + done); + signal state : state_t := idle; + + -- internal signals to enable readback + + signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0); + signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0); + signal opb_dgie_int : std_logic; + + signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0); + + + -- only used if C_DMA_EN=true + signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0); + signal opb_tx_dma_num_int : std_logic_vector(15 downto 0); + signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0); + signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0); + signal opb_rx_dma_num_int : std_logic_vector(15 downto 0); + +begin -- behavior + + tx_thresh <= tx_thresh_int; + rx_thresh <= rx_thresh_int; + opb_ier <= opb_ier_int; + opb_dgie <= opb_dgie_int; + + opb_ctl_reg <= opb_ctl_reg_int; + + --* Signals for DMA-Engine control + u1 : if C_DMA_EN generate + opb_tx_dma_ctl <= opb_tx_dma_ctl_int; + opb_tx_dma_addr <= opb_tx_dma_addr_int; + opb_tx_dma_num <= opb_tx_dma_num_int; + opb_rx_dma_ctl <= opb_rx_dma_ctl_int; + opb_rx_dma_addr <= opb_rx_dma_addr_int; + opb_rx_dma_num <= opb_rx_dma_num_int; + end generate u1; + + +-- unused outputs + Sln_errAck <= '0'; + Sln_retry <= '0'; + Sln_toutSup <= '0'; + + --* convert Sln_DBus_big_end to little mode + conv_big_Sln_DBus_proc: process(Sln_DBus_big_end) + begin + for i in 0 to 31 loop + Sln_DBus(31-i) <= Sln_DBus_big_end(i); + end loop; -- i + end process conv_big_Sln_DBus_proc; + + --* convert OPB_ABus to big endian + conv_big_OPB_ABus_proc: process(OPB_ABus) + begin + for i in 0 to 31 loop + OPB_ABus_big_end(31-i) <= OPB_ABus(i); + end loop; -- i + end process conv_big_OPB_ABus_proc; + + --* convert OPB_DBus to little mode + conv_big_OPB_DBus_proc: process(OPB_DBus) + begin + for i in 0 to 31 loop + OPB_DBus_big_end(31-i) <= OPB_DBus(i); + end loop; -- i + end process conv_big_OPB_DBus_proc; + + --* control OPB requests + --* + --* handles OPB-read and -write request + opb_slave_proc: process (OPB_Rst, OPB_Clk) + begin + if (OPB_Rst = '1') then + -- OPB + Sln_xferAck <= '0'; + Sln_DBus_big_end <= (others => '0'); + -- FIFO + opb_s_rx_en <= '0'; + opb_s_tx_en <= '0'; + -- + state <= idle; + -- Register + tx_thresh_int <= (others => '0'); + rx_thresh_int <= (others => '0'); + opb_ier_int <= (others => '0'); + opb_dgie_int <= '0'; + opb_ctl_reg_int <= (others => '0'); + + if C_DMA_EN then + opb_tx_dma_ctl_int <= (others => '0'); + opb_tx_dma_addr_int <= (others => '0'); + opb_tx_dma_num_int <= (others => '0'); + opb_rx_dma_ctl_int <= (others => '0'); + opb_rx_dma_addr_int <= (others => '0'); + opb_rx_dma_num_int <= (others => '0'); + end if; + + + elsif (OPB_Clk'event and OPB_Clk = '1') then + case state is + when idle => + if (OPB_select = '1' and + ((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then + -- *device selected + Sln_xferAck <= '1'; + state <= done; + if (OPB_RNW = '1') then + -- read acess + case OPB_ABus_big_end(7 downto 2) is + when C_ADR_CTL => + Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int; + + when C_ADR_RX_DATA => + opb_s_rx_en <= '1'; + Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data; + + when C_ADR_STATUS => + Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg; + + when C_ADR_TX_THRESH => + Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); + Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); + + when C_ADR_RX_THRESH => + Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0); + Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH); + + when C_ADR_DGIE => + Sln_DBus_big_end(0) <= opb_dgie_int; + when C_ADR_IER => + Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int; + + when C_ADR_ISR => + Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr; + + when C_ADR_TX_DMA_CTL => + if C_DMA_EN then + Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int; + end if; + + when C_ADR_TX_DMA_ADDR => + if C_DMA_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int; + end if; + + when C_ADR_TX_DMA_NUM => + if C_DMA_EN then + Sln_DBus_big_end(15 downto 0) <= opb_tx_dma_num_int; + end if; + + + when C_ADR_RX_DMA_CTL => + if C_DMA_EN then + Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int; + end if; + + when C_ADR_RX_DMA_ADDR => + if C_DMA_EN then + Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int; + end if; + + when C_ADR_RX_DMA_NUM => + if C_DMA_EN then + Sln_DBus_big_end(15 downto 0) <= opb_rx_dma_num_int; + end if; + + + + when others => + null; + end case; + else + -- write acess + case OPB_ABus_big_end(7 downto 2) is + when C_ADR_CTL => + opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0); + + when C_ADR_TX_DATA => + opb_s_tx_en <= '1'; + opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0); + + when C_ADR_TX_THRESH => + tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); + tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); + + when C_ADR_RX_THRESH => + rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0); + rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16); + + when C_ADR_DGIE => + opb_dgie_int <= OPB_DBus_big_end(0); + + when C_ADR_IER => + opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); + + when C_ADR_ISR => + opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0); + + when C_ADR_TX_DMA_CTL => + if C_DMA_EN then + opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); + end if; + + when C_ADR_TX_DMA_ADDR => + if C_DMA_EN then + opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); + end if; + + when C_ADR_TX_DMA_NUM => + if C_DMA_EN then + opb_tx_dma_num_int <= OPB_DBus_big_end(15 downto 0); + end if; + + when C_ADR_RX_DMA_CTL => + if C_DMA_EN then + opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0); + end if; + + when C_ADR_RX_DMA_ADDR => + if C_DMA_EN then + opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0); + end if; + + when C_ADR_RX_DMA_NUM => + if C_DMA_EN then + opb_rx_dma_num_int <= OPB_DBus_big_end(15 downto 0); + end if; + + when others => + null; + end case; + end if; -- OPB_RNW + else + -- not selected + state <= idle; + end if; + when done => + opb_ctl_reg_int(3) <= '0'; + opb_isr_clr <= (others => '0'); + opb_s_rx_en <= '0'; + opb_s_tx_en <= '0'; + Sln_xferAck <= '0'; + Sln_DBus_big_end <= (others => '0'); + state <= idle; + + when others => + state <= idle; + end case; + end if; + end process opb_slave_proc; +end behavior; Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.ucf (revision 35) @@ -0,0 +1,7 @@ +NET "mosi" TNM = "_mosi"; +TIMEGRP "_mosi" OFFSET = IN 5 ns VALID 10 ns BEFORE "sclk" HIGH ; + +NET "miso_o" TNM = "_miso_o"; +TIMEGRP "_miso_o" OFFSET = OUT 10 ns AFTER "sclk" LOW ; + + Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao (revision 35) @@ -0,0 +1,18 @@ +############################################################################## +## Filename: E:\Eigene_Dateien\Entwicklung\cpld\spi-core\edk\test_opb_spi_slave\pcores/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Mon Oct 29 20:54:19 2007 (by Create and Import Peripheral Wizard) +############################################################################## + +lib opb_spi_slave_v1_00_a opb_spi_slave_pack vhdl +lib opb_spi_slave_v1_00_a shift_register vhdl +lib opb_spi_slave_v1_00_a bin2gray vhdl +lib opb_spi_slave_v1_00_a gray2bin vhdl +lib opb_spi_slave_v1_00_a gray_adder vhdl +lib opb_spi_slave_v1_00_a fifo vhdl +lib opb_spi_slave_v1_00_a fifo_prog_flags vhdl +lib opb_spi_slave_v1_00_a irq_ctl vhdl +lib opb_spi_slave_v1_00_a opb_m_if vhdl +lib opb_spi_slave_v1_00_a opb_if vhdl +lib opb_spi_slave_v1_00_a opb_spi_slave vhdl +lib opb_spi_slave_v1_00_a ram vhdl Index: spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd =================================================================== --- spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (nonexistent) +++ spi_slave/tags/V100/pcore/opb_spi_slave_v1_00_a/data/opb_spi_slave_v2_1_0.mpd (revision 35) @@ -0,0 +1,72 @@ +################################################################### +## +## Name : opb_spi_slave +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN opb_spi_slave + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VHDL +OPTION CORE_STATE = ACTIVE +OPTION IP_GROUP = MICROBLAZE:PPC:USER + + +## Bus Interfaces +BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR +PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR +PARAMETER C_USER_ID_CODE = 0, DT = INTEGER +PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB +PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB +PARAMETER C_FAMILY = virtex-4, DT = STRING +PARAMETER C_SR_WIDTH = 8, DT = INTEGER +PARAMETER C_MSB_FIRST = true, DT = BOOLEAN +PARAMETER C_CPOL = 0, DT = INTEGER +PARAMETER C_PHA = 0, DT = INTEGER +PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER +PARAMETER C_DMA_EN = true, DT = BOOLEAN + +## Ports +PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB +PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB +PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK +PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB +PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST +PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB +PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB +PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB +PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB +PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB +PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB +PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB +PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB +PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB +PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB +PORT M_request = M_request, DIR = O, BUS = MSOPB +PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB +PORT M_select = M_select, DIR = O, BUS = MSOPB +PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB +PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB +PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB +PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB +PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB +PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB +PORT sclk = "", DIR = I, SIGIS = CLK +PORT ss_n = "", DIR = I +PORT mosi = "", DIR = I +PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T +PORT miso_o = "", DIR = O +PORT miso_i = "", DIR = I +PORT miso_t = "", DIR = O +PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH + +END Index: spi_slave/tags =================================================================== --- spi_slave/tags (nonexistent) +++ spi_slave/tags (revision 35)

spi_slave/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##