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URL https://opencores.org/ocsvn/mlite/mlite/trunk

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    from Rev 345 to Rev 346
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Rev 345 → Rev 346

/trunk/vhdl/tbench.vhd
12,6 → 12,7
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
 
entity tbench is
end; --entity tbench
31,13 → 32,17
signal reset : std_logic := '1';
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal mem_address : std_logic_vector(31 downto 2);
signal mem_data : std_logic_vector(31 downto 0);
signal mem_pause : std_logic := '0';
signal mem_byte_sel: std_logic_vector(3 downto 0);
--signal uart_read : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal data_read : std_logic_vector(31 downto 0);
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
begin --architecture
--Uncomment the line below to test interrupts
interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
44,12 → 49,18
 
clk <= not clk after 50 ns;
reset <= '0' after 500 ns;
--mem_pause <= not mem_pause after 100 ns;
--uart_read <= '0';
data_read <= interrupt & ZERO(30 downto 0);
pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause <= pause1 or pause2;
gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
 
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '1',
use_cache => '1',
log_file => log_file)
PORT MAP (
clk => clk,
57,13 → 68,52
uart_read => uart_write,
uart_write => uart_write,
address => mem_address,
byte_we => mem_byte_sel,
data_write => mem_data,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => mem_pause,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => data_read);
gpioA_in => gpioA_in);
 
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
 
if byte_we(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
 
if pause = '0' then
data_read <= data;
end if;
end process;
 
 
end; --architecture logic
/trunk/vhdl/plasma_3e.vhd
82,7 → 82,8
component plasma
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
93,6 → 94,8
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
108,6 → 111,8
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
 
SD_CK_P : out std_logic; --clock_positive
137,6 → 142,8
signal write_enable : std_logic;
signal pause_ddr : std_logic;
signal pause : std_logic;
signal no_ddr_start : std_logic;
signal no_ddr_stop : std_logic;
signal ddr_active : std_logic;
signal flash_active : std_logic;
signal flash_cnt : std_logic_vector(1 downto 0);
179,7 → 186,8
u1_plama: plasma
generic map (memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '1')
ethernet => '1',
use_cache => '1')
--generic map (memory_type => "DUAL_PORT_",
-- log_file => "output2.txt",
-- ethernet => '1')
194,6 → 202,8
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
 
gpio0_out => gpio0_out,
gpioA_in => gpio0_in);
209,6 → 219,8
data_w => data_write,
data_r => data_r_ddr,
active => ddr_active,
no_start => no_ddr_start,
no_stop => no_ddr_stop,
pause => pause_ddr,
 
SD_CK_P => SD_CK_P, --clock_positive
261,7 → 273,8
SF_OE <= write_enable or not flash_active;
SF_WE <= flash_we;
SF_BYTE <= '1'; --16-bit access
SF_A <= address(25 downto 2) & '0';
SF_A <= address(25 downto 2) & '0' when flash_active = '1' else
"0000000000000000000000000";
SF_D <= data_write(15 downto 1) when
flash_active = '1' and write_enable = '1'
else "ZZZZZZZZZZZZZZZ";
/trunk/vhdl/mlite_pack.vhd
179,7 → 179,7
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
 
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
346,6 → 346,21
mem_pause : in std_logic);
end component;
 
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
 
cache_check : out std_logic; --Stage1: address_next in first 2MB DDR
cache_checking : out std_logic; --Stage2: cache checking
cache_miss : out std_logic); --Stage2-3: cache miss
end component; --cache
 
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
400,20 → 415,23
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
 
component ddr_ctrl
426,6 → 444,8
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
 
SD_CK_P : out std_logic; --clock_positive
/trunk/vhdl/plasma.vhd
39,7 → 39,8
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
 
51,6 → 52,8
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
57,40 → 60,54
end; --entity plasma
 
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal mem_address : std_logic_vector(31 downto 2);
signal mem_byte_we : std_logic_vector(3 downto 0);
signal data_r : std_logic_vector(31 downto 0);
signal data_w : std_logic_vector(31 downto 0);
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal mem_pause : std_logic;
signal eth_pause : std_logic;
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
 
signal enable_internal_ram : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
 
signal gpio0_reg : std_logic_vector(31 downto 0);
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
 
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
 
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r : std_logic_vector(31 downto 0);
 
signal cache_check : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
 
begin --architecture
write_enable <= '1' when mem_byte_we /= "0000" else '0';
mem_pause <= ((mem_pause_in or eth_pause) and not enable_misc) or
(uart_write_busy and enable_uart and write_enable);
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --DDR in use
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
99,12 → 116,12
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
 
enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0111" else '0';
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
 
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
113,46 → 130,79
reset_in => reset,
intr_in => irq,
address_next => address_next,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
 
address => mem_address,
byte_we => mem_byte_we,
data_w => data_w,
data_r => data_r,
mem_pause => mem_pause);
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
 
misc_proc: process(clk, reset, address_next, mem_address, enable_misc,
data_read_ram, data_read, data_read_uart, mem_pause,
opt_cache: if use_cache = '0' generate
cache_check <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
 
cache_check => cache_check, --Stage1: address_next in first 2MB DDR
cache_checking => cache_checking, --Stage2
cache_miss => cache_miss); --Stage3
end generate; --opt_cache2
 
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
 
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
gpioA_in, counter_reg, data_w)
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case mem_address(30 downto 28) is
when "000" => --internal RAM
data_r <= data_read_ram;
when "001" => --external RAM
data_r <= data_read;
when "010" => --misc
case mem_address(6 downto 4) is
case cpu_address(30 downto 28) is
when "000" => --internal RAM
cpu_data_r <= ram_data_r;
when "001" => --external RAM
if cache_checking = '1' then
cpu_data_r <= ram_data_r; --cache
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
data_r <= ZERO(31 downto 8) & data_read_uart;
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
data_r <= ZERO(31 downto 8) & irq_mask_reg;
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
data_r <= ZERO(31 downto 8) & irq_status;
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
data_r <= gpio0_reg;
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
data_r <= gpioA_in;
cpu_data_r <= gpioA_in;
when "110" => --counter
data_r <= counter_reg;
cpu_data_r <= counter_reg;
when others =>
data_r <= gpioA_in;
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
data_r <= data_read;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
data_r <= ZERO;
cpu_data_r <= ZERO;
end case;
 
if reset = '1' then
160,14 → 210,14
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if mem_pause = '0' then
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if mem_address(6 downto 4) = "001" then
irq_mask_reg <= data_w(7 downto 0);
elsif mem_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or data_w;
elsif mem_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not data_w;
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
end if;
end if;
end if;
175,15 → 225,24
end if;
end process;
 
ram_enable <= '1' when address_next(30 downto 28) = "000" or
cache_check = '1' or cache_miss = '1' else '0';
ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
ram_address(31 downto 13) <= ZERO(31 downto 13);
ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
when cache_miss = '0' else
'1' & cpu_address(11 downto 2); --Update cache after cache miss
ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
 
u2_ram: ram
generic map (memory_type => memory_type)
port map (
clk => clk,
enable => enable_internal_ram,
write_byte_enable => byte_we_next,
address => address_next,
data_write => data_w,
data_read => data_read_ram);
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
 
u3_uart: uart
generic map (log_file => log_file)
192,7 → 251,7
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => data_w(7 downto 0),
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
200,9 → 259,9
data_avail => uart_data_avail);
 
dma_gen: if ethernet = '0' generate
address <= mem_address;
byte_we <= mem_byte_we;
data_write <= data_w;
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
223,11 → 282,11
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => mem_pause_in,
pause_in => eth_pause_in,
 
mem_address => mem_address, --from CPU
mem_byte_we => mem_byte_we,
data_w => data_w,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
 
E_RX_CLK => gpioA_in(20),
239,3 → 298,4
end generate;
 
end; --architecture logic
 
/trunk/vhdl/ddr_ctrl.vhd
52,6 → 52,8
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
 
SD_CK_P : out std_logic; --clock_positive
111,7 → 113,7
 
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
145,7 → 147,7
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' then
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
159,7 → 161,7
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' then
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
185,7 → 187,9
state_current := STATE_READ3;
 
when STATE_READ3 =>
state_current := STATE_ROW_ACTIVE;
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
 
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;

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