URL
https://opencores.org/ocsvn/mlite/mlite/trunk
Subversion Repositories mlite
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 347 to Rev 348
- ↔ Reverse comparison
Rev 347 → Rev 348
/trunk/tools/ddr_init.c
8,6 → 8,10
* Software 'as is' without warranty. Author liable for nothing. |
* DESCRIPTION: |
* Plasma DDR Initialization |
* Supports 64MB (512Mb) MT46V32M16 by default. |
* For 32 MB and 128 MB DDR parts change AddressLines and Bank shift: |
* For 32 MB change 13->12 and 11->10. MT46V16M16 |
* For 128 MB change 13->14 and 11->12. MT46V64M16 |
*--------------------------------------------------------------------*/ |
#define DDR_BASE 0x10000000 |
#define MemoryRead(A) (*(volatile int*)(A)) |
/trunk/vhdl/ddr_ctrl.vhd
8,9 → 8,22
-- Software 'as is' without warranty. Author liable for nothing. |
-- DESCRIPTION: |
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface |
-- |
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default) |
-- ROW = address(25 downto 13) |
-- BANK = address(12 downto 11) |
-- COL = address(10 downto 2) |
-- |
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16 |
-- ROW = address(24 downto 12) -- 25 ignored |
-- BANK = address(11 downto 10) |
-- COL = address(9 downto 2) --also change ddr_init.c |
-- |
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16 |
-- ROW = address(26 downto 14) |
-- BANK = address(13 downto 12) |
-- COL = address(11 downto 2) --also change ddr_init.c |
-- |
-- Requires CAS latency=2; burst size=2. |
-- Requires clk changes on rising_edge(clk_2x). |
-- Requires active, address, byte_we, data_w stable throughout transfer. |