URL
https://opencores.org/ocsvn/t80/t80/trunk
Subversion Repositories t80
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/trunk/rtl/vhdl/T80_RegX.vhd
1,7 → 1,7
-- |
-- T80 Registers for Xilinx Select RAM |
-- |
-- Version : 0242 |
-- Version : 0244 |
-- |
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) |
-- |
46,12 → 46,12
-- |
-- 0242 : Initial release |
-- |
-- 0244 : Removed UNISIM library and added componet declaration |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
library UNISIM; |
use UNISIM.vcomponents.all; |
|
entity T80_Reg is |
port( |
75,6 → 75,23
|
architecture rtl of T80_Reg is |
|
component RAM16X1D |
port( |
DPO : out std_ulogic; |
SPO : out std_ulogic; |
A0 : in std_ulogic; |
A1 : in std_ulogic; |
A2 : in std_ulogic; |
A3 : in std_ulogic; |
D : in std_ulogic; |
DPRA0 : in std_ulogic; |
DPRA1 : in std_ulogic; |
DPRA2 : in std_ulogic; |
DPRA3 : in std_ulogic; |
WCLK : in std_ulogic; |
WE : in std_ulogic); |
end component; |
|
signal ENH : std_logic; |
signal ENL : std_logic; |
|