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Rev 37 → Rev 38

/rs232_with_buffer_and_wb/trunk/uart_wb.vhd File deleted
/rs232_with_buffer_and_wb/trunk/uart_rx_fifo.vhd File deleted \ No newline at end of file
/rs232_with_buffer_and_wb/trunk/uart_tx_fifo.vhd File deleted \ No newline at end of file
/rs232_with_buffer_and_wb/trunk/uart_top.vhd File deleted \ No newline at end of file
/rs232_with_buffer_and_wb/trunk/uart_tx.vhd File deleted \ No newline at end of file
/rs232_with_buffer_and_wb/trunk/uart_rx.vhd File deleted \ No newline at end of file
/rs232_with_buffer_and_wb/trunk/rtl/uart_wb.vhd
0,0 → 1,193
------------------------------------------------------------------------
-- File infomation
------------------------------------------------------------------------
-- Tobias N. Jeppe - 22-01-2013
-- Wish Bone interface
-- Implemented with standard single write cycle and single read cycle
-- 8 bit address, 8 bit in and out put data
--
------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity uart_wb is
port( --WB interface
CLK_I : in std_logic;
master_rst : in std_logic;
RST_I : in std_logic;
ADR_I : in std_logic_vector(7 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
CYC_I : in std_logic;
DAT_O : out std_logic_vector(7 downto 0);
ACK_O : out std_logic;
--uart controll
word_width : out std_logic_vector(3 downto 0);
baud_period : out std_logic_vector(15 downto 0);
use_parity_bit : out std_logic;
parity_type : out std_logic;
stop_bits : out std_logic_vector(1 downto 0);
idle_line_lvl : out std_logic;
rx_enable : out std_logic; --rx specific
start_samples : out std_logic_vector(3 downto 0); --rx specific
line_samples : out std_logic_vector(3 downto 0); --rx specific
uart_rx_rst : out std_logic;
uart_rx_fifo_rst : out std_logic;
uart_tx_rst : out std_logic;
uart_tx_fifo_rst : out std_logic;
--FIFO control/data
tx_fifo_entries_free : in std_logic_vector (7 downto 0);
write_tx_data : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
read_rx_data : out std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_fifo_entries_free : in std_logic_vector (7 downto 0));
end entity uart_wb;
 
 
architecture behaviour of uart_wb is
-- Components
-- Signals
signal we_ok : std_logic;
signal uart_setup_rst : std_logic;
signal write_reg_addr_1 : std_logic;
signal reg_addr_1_q, reg_addr_1_d : std_logic;
 
signal write_reg_addr_100 : std_logic;
signal reg_addr_100_q, reg_addr_100_d : std_logic_vector(7 downto 0); --00000100 = rx_idle_line_lvl(r/w)(rst.1)|x|rx_use_parity(r/w)(rst.0)|rx_parity_type|rx_stop_bits(rw)(rst.01)|word_width
signal write_reg_addr_101 : std_logic;
signal reg_addr_101_q, reg_addr_101_d : std_logic_vector(7 downto 0); --00000101 = start_samples(4) | reg_samples(4)
signal write_reg_addr_110 : std_logic;
signal reg_addr_110_q, reg_addr_110_d : std_logic_vector(7 downto 0); --00000110 = period low LSB ( 7 downto 0) (Baud / Frequenzy, min 32, max 655??)
signal write_reg_addr_111 : std_logic;
signal reg_addr_111_q, reg_addr_111_d : std_logic_vector(7 downto 0); --00000111 = period high MSB (15 downto 8)
signal write_reg_addr_1000 : std_logic;
signal reg_addr_1000_q, reg_addr_1000_d : std_logic_vector(4 downto 0); --00001000 = xxx | rst_uart_rx | rst_uart_rx_fifo | rst_uart_tx | rst_uart_tx_fifo | rst_uart_setup
signal write_reg_addr_1001 : std_logic;
signal reg_addr_1001_q : std_logic_vector(4 downto 0);-- := "11111"; --00001001 = xxx | rst_uart_rx_if_rst_wb | rst_uart_rx_fifo_if_rst_wb | rst_uart_tx_if_rst_wb | rst_uart_tx_fifo_if_rst_wb | rst_uart_setup_if_rst_wb |
signal reg_addr_1001_d : std_logic_vector(4 downto 0);
Begin
-------------------------
-- Combinational Logic --
-------------------------
we_ok <= WE_I and CYC_I;
ACK_O <= STB_I;
 
--DAT_O asynchronous
with ADR_I select
DAT_O <= "0000000" & reg_addr_1_q when "00000001",
rx_fifo_entries_free when "00000010",
tx_fifo_entries_free when "00000011",
reg_addr_100_q when "00000100",
reg_addr_101_q when "00000101",
reg_addr_110_q when "00000110",
reg_addr_111_q when "00000111",
"000" & reg_addr_1000_q when "00001000",
"000" & reg_addr_1001_q when "00001001",
rx_data when others;
 
rx_enable <= reg_addr_1_q;
write_reg_addr_1 <= '1' when (ADR_I = "00000001" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_1_d <= '0' when uart_setup_rst = '1' else
DAT_I(0);
 
idle_line_lvl <= reg_addr_100_q(7);
use_parity_bit <= reg_addr_100_q(6);
parity_type <= reg_addr_100_q(5);
stop_bits <= reg_addr_100_q(4 downto 3);
word_width <= '0' & reg_addr_100_q(2 downto 0); --the msb is missing
write_reg_addr_100 <= '1' when (ADR_I = "00000100" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_100_d <= "10001000" when uart_setup_rst = '1' else
DAT_I;
start_samples <= reg_addr_101_q(7 downto 4);
line_samples <= reg_addr_101_q(3 downto 0);
write_reg_addr_101 <= '1' when (ADR_I = "00000101" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_101_d <= "0110" & "0100" when uart_setup_rst = '1' else
DAT_I;
baud_period <= reg_addr_111_q & reg_addr_110_q;
write_reg_addr_110 <= '1' when (ADR_I = "00000110" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_110_d <= "00010000" when uart_setup_rst = '1' else
DAT_I;
write_reg_addr_111 <= '1' when (ADR_I = "00000111" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_111_d <= "00000000" when uart_setup_rst = '1' else
DAT_I;
 
uart_rx_rst <= (RST_I and reg_addr_1001_q(4)) or reg_addr_1000_q(4) or master_rst;
uart_rx_fifo_rst <= (RST_I and reg_addr_1001_q(3)) or reg_addr_1000_q(3) or master_rst;
uart_tx_rst <= (RST_I and reg_addr_1001_q(2)) or reg_addr_1000_q(2) or master_rst;
uart_tx_fifo_rst <= (RST_I and reg_addr_1001_q(1)) or reg_addr_1000_q(1) or master_rst;
uart_setup_rst <= (RST_I and reg_addr_1001_q(0)) or reg_addr_1000_q(0) or master_rst;
write_reg_addr_1000 <= '1' when (ADR_I = "00001000" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_1000_d <= "00000" when uart_setup_rst = '1' else
DAT_I(4 downto 0);
write_reg_addr_1001 <= '1' when (ADR_I = "00001001" and we_ok = '1') or uart_setup_rst = '1' else
'0';
reg_addr_1001_d <= "11111" when uart_setup_rst = '1' else
DAT_I(4 downto 0);
--Write to tx_fifo
write_tx_data <= '1' when ADR_I = "00000000" and we_ok = '1' else '0';
tx_data <= DAT_I;
--Read from rx_fifo
read_rx_data <= '1' when ADR_I = "00000000" and (WE_I='0' and CYC_I = '1') else '0';
 
--------------------
-- Register Logic --
--------------------
register_logic : process(CLK_I, write_reg_addr_100, write_reg_addr_101, write_reg_addr_110,write_reg_addr_111,write_reg_addr_1000,write_reg_addr_1001)
begin
if rising_edge(CLK_I) then
if write_reg_addr_1 = '1' then
reg_addr_1_q <= reg_addr_1_d;
end if;
if write_reg_addr_100 = '1' then
reg_addr_100_q <= reg_addr_100_d;
end if;
if write_reg_addr_101 = '1' then
reg_addr_101_q <= reg_addr_101_d;
end if;
if write_reg_addr_110 = '1' then
reg_addr_110_q <= reg_addr_110_d;
end if;
if write_reg_addr_111 = '1' then
reg_addr_111_q <= reg_addr_111_d;
end if;
if write_reg_addr_1000 = '1' then
reg_addr_1000_q <= reg_addr_1000_d;
end if;
if write_reg_addr_1001 = '1' then
reg_addr_1001_q <= reg_addr_1001_d;
end if;
end if;
end process;
 
end architecture behaviour;
/rs232_with_buffer_and_wb/trunk/rtl/uart_rx.vhd
0,0 → 1,211
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity rx_func is
port( clk, reset, rx_enable : in std_logic;
rx : in std_logic;
word_width : in std_logic_vector(3 downto 0);
baud_period : in std_logic_vector(15 downto 0);
use_parity_bit, parity_type : in std_logic;
stop_bits : in std_logic_vector(1 downto 0);
idle_line_lvl : in std_logic;
start_samples : in std_logic_vector(3 downto 0); --How many correct samples should give a start bit
line_samples : in std_logic_vector(3 downto 0); --How many samples should tip the internal rx value
data : out std_logic_vector(7 downto 0);
data_ready : out std_logic;
parity_error : out std_logic;
stop_bit_error : out std_logic);
end entity rx_func;
 
architecture behaviour of rx_func is
type state_type is (idle, data_bit0, data_bit1, data_bit2, data_bit3, data_bit4, data_bit5, data_bit6, data_bit7, parity_bit, stop_bit1, stop_bit2, data_check, data_rdy);
signal current_state : state_type := idle;
signal next_state, next_state_rst : state_type;
signal next_state_from_data_bit4 : state_type;
signal next_state_from_data_bit5 : state_type;
signal next_state_from_data_bit6 : state_type;
signal next_state_from_data_bit7 : state_type;
signal next_state_from_stop_bit1 : state_type;
signal sampled_data : std_logic_vector(9 downto 0);-- := "0000000000";
 
signal period_count_enable : std_logic;
signal period_count_q : std_logic_vector(15 downto 0);-- := "0000000000000000";
signal period_count_d : std_logic_vector(15 downto 0);
signal baud_tick : std_logic;
signal period16_count_q : std_logic_vector(11 downto 0);-- := "000000000000";
signal period16_count_d : std_logic_vector(11 downto 0);
signal sample_tick : std_logic;
signal sample_reg_q, sample_reg_start_bit_q : std_logic_vector(3 downto 0);-- := "0000";
signal sample_reg_start_bit_d, sample_reg_d : std_logic_vector(3 downto 0);
signal rx_sampled_q : std_logic;-- := '0';
signal rx_sampled_d : std_logic;
signal xored_sampled_data_bit_q : std_logic;-- := '0';
signal xored_sampled_data_bit_d : std_logic;
begin
-------------------------
-- Combinational logic --
-------------------------
 
--State Logic
next_state <= idle when reset = '1' else
next_state_rst;
with current_state select
next_state_rst <= data_bit0 when idle, --Identifying start bit
data_bit1 when data_bit0,
data_bit2 when data_bit1,
data_bit3 when data_bit2,
data_bit4 when data_bit3,
next_state_from_data_bit4 when data_bit4,
next_state_from_data_bit5 when data_bit5,
next_state_from_data_bit6 when data_bit6,
next_state_from_data_bit7 when data_bit7,
stop_bit1 when parity_bit,
next_state_from_stop_bit1 when stop_bit1,
data_check when stop_bit2,
data_rdy when data_check,
idle when data_rdy,
idle when others;
 
next_state_from_data_bit4 <= parity_bit when word_width = "0101" and use_parity_bit = '1' else
stop_bit1 when word_width = "0101" and use_parity_bit = '0' else
data_bit5;
 
next_state_from_data_bit5 <= parity_bit when word_width = "0110" and use_parity_bit = '1' else
stop_bit1 when word_width = "0110" and use_parity_bit = '0' else
data_bit6;
next_state_from_data_bit6 <= parity_bit when word_width = "0111" and use_parity_bit = '1' else
stop_bit1 when word_width = "0111" and use_parity_bit = '0' else
data_bit7;
next_state_from_data_bit7 <= parity_bit when use_parity_bit = '1' else
stop_bit1;
next_state_from_stop_bit1 <= stop_bit2 when stop_bits = "10" else
data_check;
 
 
--Sample logic
period16_count_d <= period16_count_q + 1 when reset = '0' and period16_count_q /= baud_period(15 downto 4) else
"000000000001";
sample_tick <= '1' when period16_count_q = baud_period(15 downto 4) else
'0';
 
--Baud logic
with current_state select
period_count_enable <= '0' when idle,
'0' when data_check,
'0' when data_rdy,
'1' when others;
period_count_d <= period_count_q + 1 when reset = '0' and period_count_q /= baud_period else
"0000000000000001";
baud_tick <= '1' when period_count_q = baud_period else
'0';
 
--RX sampled, by saturation counter
sample_reg_d <= sample_reg_q + 1 when reset = '0' and rx = '1' and sample_reg_q /= line_samples else
sample_reg_q - 1 when reset = '0' and rx = '0' and sample_reg_q /= "0000" else
sample_reg_q when reset = '0' else
"0000";
 
rx_sampled_d <= '1' when reset = '0' and sample_reg_q = line_samples else
'0' when reset = '0' and sample_reg_q = "0000" else
rx_sampled_q;
sample_reg_start_bit_d <= sample_reg_start_bit_q + 1 when reset = '0' and rx /= idle_line_lvl and sample_reg_start_bit_q /= start_samples else
sample_reg_start_bit_q - 1 when reset = '0' and rx = idle_line_lvl and sample_reg_start_bit_q /= "0000" else
sample_reg_start_bit_q when reset = '0' else
"0000";
 
--Parity bit
with current_state select
xored_sampled_data_bit_d <= '0' when idle,
xored_sampled_data_bit_q when stop_bit1,
xored_sampled_data_bit_q when stop_bit2,
xored_sampled_data_bit_q when data_check,
xored_sampled_data_bit_q xor rx_sampled_q when others;
 
--Reciving status signals
data_ready <= '1' when current_state = data_rdy else
'0';
parity_error <= '1' when xored_sampled_data_bit_q /= parity_type and current_state = data_check else
'0';
stop_bit_error <= '1' when current_state = data_check and (sampled_data(8) /= idle_line_lvl or (sampled_data(9) /= idle_line_lvl and stop_bits = "10")) else
'0';
 
 
--------------------
-- Register logic --
--------------------
register_logic : process(clk, reset, rx_enable, period_count_enable, sample_tick, baud_tick, current_state, use_parity_bit)
begin
if rising_edge(clk) then
--sample counter
if rx_enable = '1' or reset = '1' then
period16_count_q <= period16_count_d;
end if;
--baud counter
if period_count_enable = '1' or reset = '1' then
period_count_q <= period_count_d;
end if;
if sample_tick = '1' then
sample_reg_q <= sample_reg_d;
rx_sampled_q <= rx_sampled_d;
sample_reg_start_bit_q <= sample_reg_start_bit_d;
end if;
if baud_tick = '1' or (current_state = idle and sample_reg_start_bit_q = start_samples) or current_state = data_check or current_state = data_rdy then
current_state <= next_state;
end if;
if baud_tick = '1' and current_state = data_bit0 then
sampled_data(0) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit1 then
sampled_data(1) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit2 then
sampled_data(2) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit3 then
sampled_data(3) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit4 then
sampled_data(4) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit5 then
sampled_data(5) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit6 then
sampled_data(6) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = data_bit7 then
sampled_data(7) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = stop_bit1 then
sampled_data(8) <= rx_sampled_q;
end if;
if baud_tick = '1' and current_state = stop_bit2 then
sampled_data(9) <= rx_sampled_q;
end if;
 
if current_state = data_check then
data <= sampled_data(7 downto 0);
end if;
if baud_tick = '1' and use_parity_bit = '1' then
xored_sampled_data_bit_q <= xored_sampled_data_bit_d;
end if;
end if;
end process register_logic;
end architecture behaviour;
/rs232_with_buffer_and_wb/trunk/rtl/uart_tx.vhd
0,0 → 1,139
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity tx_func is
port( clk, reset : in std_logic;
data : in std_logic_vector(7 downto 0);
transmit_data : in std_logic;
word_width : in std_logic_vector(3 downto 0);
baud_period : in std_logic_vector(15 downto 0);
use_parity_bit, parity_type : in std_logic;
stop_bits : in std_logic_vector(1 downto 0);
idle_line_lvl : in std_logic;
 
tx : out std_logic;
sending : out std_logic);
end entity tx_func;
 
 
architecture behaviour of tx_func is
type state_type is (idle, start_bit, data_bit0, data_bit1, data_bit2, data_bit3, data_bit4, data_bit5, data_bit6, data_bit7, parity_bit, stop_bit1, stop_bit2);
signal current_state : state_type;-- := idle;
signal next_state : state_type;
 
signal register_enable : std_logic;
 
signal next_state_from_data_bit4 : state_type;
signal next_state_from_data_bit5 : state_type;
signal next_state_from_data_bit6 : state_type;
signal next_state_from_data_bit7 : state_type;
signal next_state_from_stop_bit1 : state_type;
 
signal baud_tick : std_logic;-- := '0';
signal baud_counter_d : std_logic_vector(15 downto 0);
signal baud_counter_q : std_logic_vector(15 downto 0);-- := (others => '0');
 
signal cal_parity_bit : std_logic;
signal data_q : std_logic_vector(7 downto 0);-- := (others => '0');
 
begin
-----------------------
--Combinational logic
-----------------------
--Tilstands encoding
with current_state select
next_state <= start_bit when idle,
data_bit0 when start_bit,
data_bit1 when data_bit0,
data_bit2 when data_bit1,
data_bit3 when data_bit2,
data_bit4 when data_bit3,
next_state_from_data_bit4 when data_bit4,
next_state_from_data_bit5 when data_bit5,
next_state_from_data_bit6 when data_bit6,
next_state_from_data_bit7 when data_bit7,
stop_bit1 when parity_bit,
next_state_from_stop_bit1 when stop_bit1,
idle when stop_bit2,
idle when others;
 
next_state_from_data_bit4 <= parity_bit when word_width = "0101" and use_parity_bit = '1' else
stop_bit1 when word_width = "0101" and use_parity_bit = '0' else
data_bit5;
 
next_state_from_data_bit5 <= parity_bit when word_width = "0110" and use_parity_bit = '1' else
stop_bit1 when word_width = "0110" and use_parity_bit = '0' else
data_bit6;
 
next_state_from_data_bit6 <= parity_bit when word_width = "0111" and use_parity_bit = '1' else
stop_bit1 when word_width = "0111" and use_parity_bit = '0' else
data_bit7;
next_state_from_data_bit7 <= parity_bit when use_parity_bit = '1' else
stop_bit1;
 
next_state_from_stop_bit1 <= stop_bit2 when stop_bits = "10" else
idle;
 
--Baud logic
baud_tick <= '1' when baud_counter_q = baud_period else '0';
baud_counter_d <= baud_counter_q + 1 when baud_tick = '0' and current_state /= idle else
"0000000000000001";
 
--Parity_bit logic
cal_parity_bit <= data_q(0) xor data_q(1) xor data_q(2) xor data_q(3) xor data_q(4) xor data_q(5) xor data_q(6) xor data_q(7) xor parity_type;
 
--TX Line logic
with current_state select
tx <= idle_line_lvl when idle,
not idle_line_lvl when start_bit,
data_q(0) when data_bit0,
data_q(1) when data_bit1,
data_q(2) when data_bit2,
data_q(3) when data_bit3,
data_q(4) when data_bit4,
data_q(5) when data_bit5,
data_q(6) when data_bit6,
data_q(7) when data_bit7,
cal_parity_bit when parity_bit,
idle_line_lvl when stop_bit1,
idle_line_lvl when stop_bit2,
idle_line_lvl when others;
--Signal logic
sending <= '0' when current_state = idle else '1';
 
------------------
--Register logic
------------------
register_enable <= '1' when (transmit_data = '1' and current_state = idle) or baud_tick = '1' else
'0';
 
register_logic : process(clk, reset)
begin
if rising_edge(clk) then
--State Control
if reset = '1' then
current_state <= idle;
elsif register_enable = '1' then
current_state <= next_state;
end if;
--BAUD Counter Control
if current_state /= idle or (current_state = idle and transmit_data = '1')then
baud_counter_q <= baud_counter_d;
end if;
--DATA control
if current_state = idle and transmit_data = '1' then
data_q <= data;
end if;
end if;
end process;
 
end architecture behaviour;
/rs232_with_buffer_and_wb/trunk/rtl/uart_rx_fifo.vhd
0,0 → 1,112
-----------------------------
-- rx_fifo
------------------------------
-- WB interface has the highest priority.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity rx_fifo is
generic(address_width : integer := 3);
port( clk, reset : in std_logic;
 
read_rx_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_fifo_full : out std_logic;
rx_fifo_empty : out std_logic;
rx_fifo_entries_free : out std_logic_vector(7 downto 0);
 
rx_func_data : in std_logic_vector(7 downto 0);
rx_func_data_ready : in std_logic);
end entity rx_fifo;
 
architecture behaviour of rx_fifo is
type ram_type is array (0 to 2**address_width-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
signal ram_we : std_logic;
signal ram_address : std_logic_vector(address_width-1 downto 0);
signal rx_in_addr_d, rx_out_addr_d : std_logic_vector(address_width-1 downto 0);
signal rx_in_addr_q, rx_out_addr_q : std_logic_vector(address_width-1 downto 0) := (others => '0');
signal rx_fifo_full_i, rx_fifo_empty_i : std_logic;
constant max_fifo_entries : std_logic_vector(address_width downto 0) := conv_std_logic_vector(2**address_width, address_width+1);
signal fifo_entries_back_q, fifo_entries_back_d : std_logic_vector(address_width downto 0);
signal data_ready_q, data_ready_d : std_logic;
begin
-------------------------
-- Combinational Logic --
-------------------------
ram_we <= '1' when read_rx_data = '0' and rx_fifo_full_i = '0' and data_ready_q = '1' else
'0';
data_ready_d <= not (reset or ram_we);
--'0' when reset = '1' or ram_we = '1' else
--'1';-- when rx_func_data_ready = '1' else --taken care of by register enable
--'0' when ram_we = '1' else
--data_ready_q;
ram_address <= rx_in_addr_q when ram_we = '1' else
rx_out_addr_q;
rx_in_addr_d <= (others => '0') when reset = '1' else
rx_in_addr_q + 1;-- when ram_we = '1' else --taken care of by register enable
--rx_in_addr_q;
rx_out_addr_d <= (others => '0') when reset = '1' else --taken care of by register enable
rx_out_addr_q + 1;-- when rx_read = '1' else
--rx_out_addr_q;
 
 
rx_fifo_entries_free <= conv_std_logic_vector(0, 7 - address_width) & fifo_entries_back_q;
fifo_entries_back_d <= max_fifo_entries when reset = '1' else
fifo_entries_back_q + 1 when read_rx_data = '1' else
fifo_entries_back_q - 1 when ram_we = '1' else --taken care of by register enable
fifo_entries_back_q;
rx_fifo_full <= rx_fifo_full_i;
rx_fifo_full_i <= '1' when fifo_entries_back_q = conv_std_logic_vector(0, address_width+1) else
'0';
rx_fifo_empty <= rx_fifo_empty_i;
rx_fifo_empty_i <= '1' when fifo_entries_back_q = max_fifo_entries else
'0';
 
--------------------
-- Register Logic --
--------------------
reg_control : process(clk)
begin
if rising_edge(clk) then
--if reset = '1' or read_rx_data = '1' or ram_we = '1' then
fifo_entries_back_q <= fifo_entries_back_d;
--end if;
if reset = '1' or ram_we = '1' or rx_func_data_ready = '1' then
data_ready_q <= data_ready_d;
end if;
if reset = '1' or ram_we = '1' then
rx_in_addr_q <= rx_in_addr_d;
end if;
if reset = '1' or read_rx_data = '1' then
rx_out_addr_q <= rx_out_addr_d;
end if;
end if;
end process;
 
 
-----------------------------------
-- RAM synchronous - single port --
-----------------------------------
ram_control : process(clk, ram_we, ram_address, rx_func_data)
begin
if rising_edge(clk) then
if ram_we = '1' then
ram(conv_integer(ram_address)) <= rx_func_data;
end if;
end if;
end process ram_control;
rx_data <= ram(conv_integer(ram_address));
 
end architecture behaviour;
/rs232_with_buffer_and_wb/trunk/rtl/uart_tx_fifo.vhd
0,0 → 1,115
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity tx_fifo is
generic(address_width : integer := 3);
port( clk, reset : in std_logic;
 
write_tx_data : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_fifo_full : out std_logic;
tx_fifo_empty : out std_logic;
tx_fifo_entries_free : out std_logic_vector(7 downto 0);
 
tx_func_data : out std_logic_vector(7 downto 0);
tx_func_apply_data : out std_logic;
tx_func_sending : in std_logic);
end entity tx_fifo;
 
architecture behaviour of tx_fifo is
type ram_type is array (0 to 2**address_width-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
 
constant max_fifo_entries : std_logic_vector(address_width downto 0) := conv_std_logic_vector(2**address_width, address_width+1);
signal tx_entries_back_d : std_logic_vector(address_width downto 0);
signal tx_entries_back_q : std_logic_vector(address_width downto 0) := max_fifo_entries ;
signal tx_in_addr_d, tx_out_addr_d : std_logic_vector(address_width-1 downto 0);
signal tx_in_addr_q, tx_out_addr_q : std_logic_vector(address_width-1 downto 0) := (others => '0');
signal ram_we : std_logic;
signal ram_address : std_logic_vector(address_width-1 downto 0) := (others => '0');
signal tx_fifo_empty_i : std_logic := '1';
signal tx_fifo_full_i : std_logic := '0';
signal tx_func_apply_data_i : std_logic;
begin
--------------------
-- Component used --
--------------------
 
 
-------------------------
-- Combinational Logic --
-------------------------
ram_we <= write_tx_data and not tx_fifo_full_i;
-- ram_we <= '1' when write_tx_data = '1' and tx_fifo_full_i = '0' else
-- '0';
with ram_we select
ram_address <= tx_in_addr_q when '1',
tx_out_addr_q when '0',
tx_out_addr_q when others;
 
tx_in_addr_d <= (others => '0') when reset = '1' else
tx_in_addr_q + 1;-- when ram_we = '1' else --taken care of by the register enable
--tx_in_addr_q;
tx_out_addr_d <= (others => '0') when reset = '1' else
tx_out_addr_q + 1;-- when tx_func_apply_data_i = '1' else
--tx_out_addr_q;
tx_func_apply_data <= tx_func_apply_data_i;
tx_func_apply_data_i <= not(ram_we or tx_func_sending or tx_fifo_empty_i);
-- tx_func_apply_data_i <= '1' when ram_we = '0' and tx_func_sending = '0' and tx_fifo_empty_i = '0' else
-- '0';
 
tx_fifo_empty <= tx_fifo_empty_i;
tx_fifo_empty_i <= '0' when tx_entries_back_q /= max_fifo_entries else
'1';
tx_fifo_full <= tx_fifo_full_i;
tx_fifo_full_i <= '0' when tx_entries_back_q /= conv_std_logic_vector(0, address_width+1) else
'1';
 
tx_fifo_entries_free <= conv_std_logic_vector(0,7-address_width) & tx_entries_back_q;
tx_entries_back_d <= max_fifo_entries when reset = '1' else
tx_entries_back_q - 1 when ram_we = '1' else
tx_entries_back_q + 1;-- when tx_func_apply_data_i = '1' else
--tx_entries_back_q;
 
--------------------
-- Register Logic --
--------------------
reg_control : process(clk, reset, ram_we, tx_func_apply_data_i, tx_data)
begin
if rising_edge(clk) then
if reset = '1' or ram_we = '1' or tx_func_apply_data_i = '1' then
tx_entries_back_q <= tx_entries_back_d;
end if;
if reset = '1' or tx_func_apply_data_i = '1' then
tx_out_addr_q <= tx_out_addr_d;
end if;
if reset = '1' or ram_we = '1' then
tx_in_addr_q <= tx_in_addr_d;
end if;
end if;
end process reg_control;
 
-----------------------------------
-- RAM synchronous - single port --
-----------------------------------
ram_control : process(clk, ram_we, ram_address, tx_data)
begin
if rising_edge(clk) then
if ram_we = '1' then
ram(conv_integer(ram_address)) <= tx_data;
end if;
end if;
end process ram_control;
tx_func_data <= ram(conv_integer(ram_address));
end architecture behaviour;
/rs232_with_buffer_and_wb/trunk/rtl/uart_top.vhd
0,0 → 1,163
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity uart_top is
generic(address_width : integer := 3);
port( clk, master_rst : in std_logic;
RST_I : in std_logic;
ADR_I : in std_logic_vector(7 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
CYC_I : in std_logic;
DAT_O : out std_logic_vector(7 downto 0);
ACK_O : out std_logic;
rx : in std_logic;
tx : out std_logic;
rx_fifo_empty : out std_logic;
rx_fifo_full : out std_logic;
tx_fifo_empty : out std_logic;
tx_fifo_full : out std_logic;
parity_error : out std_logic;
stop_bit_error : out std_logic;
transmitting : out std_logic);
end entity uart_top;
 
 
 
architecture behaviour of uart_top is
component uart_wb is
port( --WB interface
CLK_I : in std_logic;
master_rst : in std_logic;
RST_I : in std_logic;
ADR_I : in std_logic_vector(7 downto 0);
DAT_I : in std_logic_vector(7 downto 0);
WE_I : in std_logic;
STB_I : in std_logic;
CYC_I : in std_logic;
DAT_O : out std_logic_vector(7 downto 0);
ACK_O : out std_logic;
--uart controll
word_width : out std_logic_vector(3 downto 0);
baud_period : out std_logic_vector(15 downto 0);
use_parity_bit : out std_logic;
parity_type : out std_logic;
stop_bits : out std_logic_vector(1 downto 0);
idle_line_lvl : out std_logic;
rx_enable : out std_logic; --rx specific
start_samples : out std_logic_vector(3 downto 0); --rx specific
line_samples : out std_logic_vector(3 downto 0); --rx specific
uart_rx_rst : out std_logic;
uart_rx_fifo_rst : out std_logic;
uart_tx_rst : out std_logic;
uart_tx_fifo_rst : out std_logic;
--FIFO control/data
tx_fifo_entries_free : in std_logic_vector (7 downto 0);
write_tx_data : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
read_rx_data : out std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_fifo_entries_free : in std_logic_vector (7 downto 0));
end component;
 
component tx_func is
port( clk, reset : in std_logic;
data : in std_logic_vector(7 downto 0);
transmit_data : in std_logic;
word_width : in std_logic_vector(3 downto 0);
baud_period : in std_logic_vector(15 downto 0);
use_parity_bit, parity_type : in std_logic;
stop_bits : in std_logic_vector(1 downto 0);
idle_line_lvl : in std_logic;
 
tx : out std_logic;
sending : out std_logic);
end component;
 
component rx_func is
port( clk, reset, rx_enable : in std_logic;
rx : in std_logic;
word_width : in std_logic_vector(3 downto 0);
baud_period : in std_logic_vector(15 downto 0);
use_parity_bit, parity_type : in std_logic;
stop_bits : in std_logic_vector(1 downto 0);
idle_line_lvl : in std_logic;
start_samples : in std_logic_vector(3 downto 0); --How many correct samples should give a start bit
line_samples : in std_logic_vector(3 downto 0); --How many samples should tip the internal rx value
data : out std_logic_vector(7 downto 0);
data_ready : out std_logic;
parity_error : out std_logic;
stop_bit_error : out std_logic);
end component;
 
component rx_fifo is
generic(address_width : integer := 3);
port( clk, reset : in std_logic;
 
read_rx_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_fifo_full : out std_logic;
rx_fifo_empty : out std_logic;
rx_fifo_entries_free : out std_logic_vector(7 downto 0);
 
rx_func_data : in std_logic_vector(7 downto 0);
rx_func_data_ready : in std_logic);
end component;
 
component tx_fifo is
generic(address_width : integer := 3);
port( clk, reset : in std_logic;
 
write_tx_data : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_fifo_full : out std_logic;
tx_fifo_empty : out std_logic;
tx_fifo_entries_free : out std_logic_vector(7 downto 0);
 
tx_func_data : out std_logic_vector(7 downto 0);
tx_func_apply_data : out std_logic;
tx_func_sending : in std_logic);
end component;
 
signal word_width : std_logic_vector(3 downto 0);
signal baud_period : std_logic_vector(15 downto 0);
signal start_samples, line_samples : std_logic_vector(3 downto 0);
signal use_parity_bit, parity_type, idle_line_lvl : std_logic;
signal uart_rx_rst, uart_tx_rst, uart_rx_fifo_rst, uart_tx_fifo_rst : std_logic;
signal rx_fifo_entries_free, tx_fifo_entries_free : std_logic_vector(7 downto 0);
signal read_rx_data, write_tx_data : std_logic;
signal tx_data, rx_data : std_logic_vector(7 downto 0);
signal sending : std_logic;
signal stop_bits : std_logic_vector(1 downto 0);
signal rx_func_data, tx_func_data : std_logic_vector(7 downto 0);
signal rx_func_data_ready, tx_func_apply_data : std_logic;
signal rx_enable: std_logic;
 
begin
transmitting <= sending;
 
wishBoneInterFace : uart_wb port map (clk, master_rst, RST_I,ADR_I,DAT_I,WE_I,STB_I,CYC_I,DAT_O,ACK_O,word_width,baud_period,use_parity_bit,parity_type,stop_bits,idle_line_lvl,rx_enable,start_samples,line_samples,uart_rx_rst,uart_rx_fifo_rst,uart_tx_rst,uart_tx_fifo_rst,tx_fifo_entries_free,write_tx_data,tx_data,read_rx_data,rx_data,rx_fifo_entries_free);
 
UartRx : rx_func port map (clk, uart_rx_rst, rx_enable, rx, word_width, baud_period, use_parity_bit, parity_type, stop_bits, idle_line_lvl, start_samples, line_samples, rx_func_data, rx_func_data_ready,parity_error,stop_bit_error);
 
UartTx : tx_func port map(clk, uart_tx_rst, tx_func_data, tx_func_apply_data,word_width,baud_period,use_parity_bit, parity_type,stop_bits,idle_line_lvl,tx,sending);
 
RxFifo : rx_fifo generic map(address_width) port map(clk, uart_rx_fifo_rst, read_rx_data, rx_data, rx_fifo_full, rx_fifo_empty, rx_fifo_entries_free, rx_func_data, rx_func_data_ready);
TxFifo : tx_fifo generic map(address_width) port map(clk, uart_tx_fifo_rst, write_tx_data,tx_data,tx_fifo_full,tx_fifo_empty,tx_fifo_entries_free,tx_func_data,tx_func_apply_data,sending);
 
end architecture behaviour;

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