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URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

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    from Rev 37 to Rev 38
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Rev 37 → Rev 38

/xucpu/trunk/ss/entity/board.vhdl
1,14 → 1,15
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY board IS
 
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SWITCH : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
BUTTON : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
clock : IN STD_LOGIC; -- Board level clock
reseta : IN STD_LOGIC; -- Asynchronous reset from button
led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Output to LEDs
switch : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Input from slide switches
button : IN STD_LOGIC_VECTOR(4 DOWNTO 0)); -- Input from push buttons
 
END ENTITY board;
 
/xucpu/trunk/ss/arch/board.vhdl
18,6 → 18,13
 
ARCHITECTURE Structural OF board IS
 
-- System constants
CONSTANT nr_of_masters : INTEGER := 2;
CONSTANT nr_of_devices : INTEGER := 5;
 
CONSTANT addr_width : INTEGER := 15;
CONSTANT data_width : INTEGER := 16;
 
-- Definition of bus signals
 
SIGNAL data_bus : STD_LOGIC_VECTOR(15 DOWNTO 0);
27,6 → 34,21
SIGNAL bus_wait : STD_LOGIC;
SIGNAL bus_ack : STD_LOGIC;
 
-- Interconnection signals
 
TYPE data_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL device_data_out : data_bus_array(0 TO nr_of_devices - 1);
 
TYPE address_bus_array IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
SIGNAL device_address_out : address_bus_array(0 TO nr_of_masters - 1);
 
-- Board level components
-- Clock buffer
SIGNAL clk : STD_LOGIC := '0';
 
-- From asynchronous reset to synchronous reset
SIGNAL rst : STD_LOGIC := '0';
 
-- Definition of components related to the bus
 
COMPONENT data_mux IS
47,8 → 69,57
COMPONENT bus_arbiter IS
END COMPONENT bus_arbiter;
 
-- Definition of components attached to the bus
-- Definition of master devices attached to the bus
COMPONENT icache IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC);
END COMPONENT icache;
 
COMPONENT dcache IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
addr_out : OUT STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
data_rd : OUT STD_LOGIC;
data_wr : OUT STD_LOGIC;
bus_wait : IN STD_LOGIC);
END COMPONENT dcache;
 
-- Definition of io devices attached to the bus
COMPONENT led_out IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
port_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT led_out;
 
COMPONENT button_in IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
port_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END COMPONENT button_in;
 
COMPONENT switch_in IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
addr_in : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0);
port_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT switch_in;
 
BEGIN -- ARCHITECTURE Structural
 
-- Mapping of bus related components
62,10 → 133,31
-- Data cache
 
-- LED output device
led_out_1 : led_out
PORT MAP (
clk => clk,
rst => rst,
data_in => data_bus(7 DOWNTO 0),
addr_in => address_bus,
port_out => led);
 
-- Push button input device
button_in_1 : button_in
PORT MAP (
clk => clk,
rst => rst,
data_out => device_data_out(0)(7 DOWNTO 0),
addr_in => address_bus,
port_in => button);
 
-- Slide switch input device
switch_in_1 : switch_in
PORT MAP (
clk => clk,
rst => rst,
data_out => device_data_out(1)(7 DOWNTO 0),
addr_in => address_bus,
port_in => switch);
 
-- Serial communication device
 

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