URL
https://opencores.org/ocsvn/gecko4/gecko4/trunk
Subversion Repositories gecko4
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- This comparison shows the changes necessary to convert path
/
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/gecko4/trunk/GECKO4com/spartan200_an/config/project.toplevel
0,0 → 1,?rev2len?
xc3s200an_top |
/gecko4/trunk/GECKO4com/spartan200_an/config/project.xilinx
0,0 → 1,14
# Map parameters |
MAP_EFFORT = std |
MAP_OPTIONS = |
MAP_COVER_MODE = area |
|
#PAR parameters |
GUIDED_PAR = 0 |
PAR_EFFORT = high |
GENERATE_SIMULATION_FILES = 0 |
GENERATE_TIMING_TRACE_FILE = 1 |
NR_OF_TIMING_TRACES = 10 |
|
#Bitgen Parameters |
UNUSED_PINS = Pullup |
/gecko4/trunk/GECKO4com/spartan200_an/config/project.ucf
0,0 → 1,682
NET "CLOCK_25MHZ" LOC = "A9" ; |
NET "CLOCK_25MHZ" TNM_NET = "CLOCK_25MHZ"; |
TIMESPEC "TS_CLOCK_25MHZ" = PERIOD "CLOCK_25MHZ" 25 MHz HIGH 50 %; |
|
NET "CLOCK_16MHZ" LOC = "P9" ; |
NET "CLOCK_16MHZ" TNM_NET = "CLOCK_16MHZ"; |
TIMESPEC "TS_CLOCK_16MHZ" = PERIOD "CLOCK_16MHZ" 16 MHz HIGH 50 %; |
|
NET "USER_CLOCK_1_IN" LOC = "H3" | IOSTANDARD = LVTTL | PULLUP ; |
NET "USER_CLOCK_1_IN" TNM_NET = "USER_CLOCK_1_IN"; |
TIMESPEC "TS_USER_CLOCK_1_IN" = PERIOD "USER_CLOCK_1_IN" 100 MHz HIGH 50 %; |
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NET "USER_CLOCK_2_IN" LOC = "J3" | IOSTANDARD = LVTTL | PULLUP ; |
NET "USER_CLOCK_2_IN" TNM_NET = "USER_CLOCK_2_IN"; |
TIMESPEC "TS_USER_CLOCK_2_IN" = PERIOD "USER_CLOCK_2_IN" 100 MHz HIGH 50 %; |
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NET "user_clock_1_fb" FEEDBACK = 10 ps NET "user_clock_1_out" ; |
NET "user_clock_2_fb" FEEDBACK = 10 ps NET "user_clock_2_out" ; |
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NET "user_clock_2_out" LOC = "B15" | IOSTANDARD = LVCMOS25 ; #CLK2 |
NET "user_clock_2_fb" LOC = "T8" | IOSTANDARD = LVCMOS25 ; |
NET "user_clock_2_lock" LOC = "E7" | IOSTANDARD = LVCMOS25 ; #FPGA_C1 |
NET "user_clock_1_out" LOC = "B14" | IOSTANDARD = LVCMOS25 ; #CLK1 |
NET "user_clock_1_fb" LOC = "D9" | IOSTANDARD = LVCMOS25 ; |
NET "user_clock_1_lock" LOC = "A6" | IOSTANDARD = LVCMOS25 ; #FPGA_C0 |
|
NET "clock_25MHz_out" LOC = "A14" | IOSTANDARD = LVCMOS25 ; #CLK2 |
NET "clock_48MHz_out" LOC = "A13" | IOSTANDARD = LVCMOS25 ; #CLK3 |
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INST "clockgen/clk48_ff" IOB = TRUE ; |
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PIN "clockgen/buf5.O" TNM = "TS_VGA" ; |
PIN "clockgen/buf3.O" TNM = "TS_MAIN" ; |
TIMESPEC "TS_FP1" = FROM "TS_MAIN" TO "TS_VGA" TIG ; |
TIMESPEC "TS_FP2" = FROM "TS_VGA" TO "TS_MAIN" TIG ; |
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NET "button1" LOC = "K5" | PULLUP | IOSTANDARD = LVTTL ; |
NET "button2" LOC = "K6" | PULLUP | IOSTANDARD = LVTTL ; |
NET "button3" LOC = "L6" | PULLUP | IOSTANDARD = LVTTL ; |
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NET "n_usb_power" LOC = "H10" | IOSTANDARD = LVTTL | PULLUP ; |
NET "n_bus_power" LOC = "J11" | IOSTANDARD = LVTTL | PULLUP ; |
NET "n_usb_charge" LOC = "J10" | IOSTANDARD = LVTTL | PULLUP ; |
|
NET "n_reset_system" LOC = "H5" | IOSTANDARD = LVTTL | DRIVE = 2; |
NET "user_n_reset" LOC = "C4" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
|
NET "RxD_in" LOC = "L5" | IOSTANDARD = LVTTL ; |
NET "TxD_out" LOC = "N3" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "RxD_out" LOC = "C5" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "TxD_in" LOC = "A5" | IOSTANDARD = LVCMOS25 ; |
|
NET "scpi_disabled" LOC = "C6" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "ESB_bit" LOC = "B6" | IOSTANDARD = LVCMOS25 ; |
NET "STATUS3_bit" LOC = "D7" | IOSTANDARD = LVCMOS25 ; |
|
NET "fx2_n_int0" LOC = "G1" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "fx2_pa1" LOC = "H1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_pa3" LOC = "J2" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_flaga" LOC = "G6" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_flagb" LOC = "F4" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<0>" LOC = "P2" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<1>" LOC = "P1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<2>" LOC = "N2" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<3>" LOC = "N1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<4>" LOC = "D1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<5>" LOC = "E1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<6>" LOC = "E2" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data<7>" LOC = "F1" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_fifo_addr<0>" LOC = "K1" | IOSTANDARD = LVTTL ; |
NET "fx2_fifo_addr<1>" LOC = "L1" | IOSTANDARD = LVTTL ; |
NET "fx2_ifclock" LOC = "K3" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "fx2_n_oe" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "fx2_n_re" LOC = "L4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "fx2_n_we" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "fx2_n_pkt_end" LOC = "H6" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
INST "fx2/IFCLK_FF" IOB = TRUE ; |
INST "fx2/EP8_flag_FF" IOB = TRUE ; |
INST "fx2/EP6_flag_FF" IOB = TRUE ; |
INST "fx2/EP_n_PKTEND_FF" IOB = TRUE ; |
INST "fx2/make_addr_ff.0.one_ff" IOB = TRUE ; |
INST "fx2/make_addr_ff.1.one_ff" IOB = TRUE ; |
INST "fx2/n_oe_ff" IOB = TRUE ; |
INST "fx2/n_re_ff" IOB = TRUE ; |
INST "fx2/EP_n_WE_FF" IOB = TRUE ; |
INST "fx2/make_data_in_ff.0.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.1.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.2.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.3.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.4.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.5.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.6.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.7.one_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.0.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.1.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.2.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.3.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.4.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.5.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.6.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.7.out_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.0.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.1.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.2.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.3.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.4.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.5.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.6.tri_ff" IOB = TRUE ; |
INST "fx2/make_data_in_ff.7.tri_ff" IOB = TRUE ; |
|
|
NET "fx2_data_nibble<0>" LOC = "E3" | IOSTANDARD = LVTTL ; |
NET "fx2_data_nibble<1>" LOC = "F3" | IOSTANDARD = LVTTL ; |
NET "fx2_data_nibble<2>" LOC = "G3" | IOSTANDARD = LVTTL ; |
NET "fx2_data_nibble<3>" LOC = "H4" | IOSTANDARD = LVTTL ; |
NET "fx2_data_select<0>" LOC = "J4" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data_select<1>" LOC = "L2" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data_select<2>" LOC = "K4" | IOSTANDARD = LVTTL | PULLUP ; |
NET "fx2_data_select<3>" LOC = "L3" | IOSTANDARD = LVTTL | PULLUP ; |
INST "fx2/gen_data_nibble.0.in_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.0.out_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.1.in_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.1.out_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.2.in_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.2.out_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.3.in_ff" IOB = TRUE; |
INST "fx2/gen_data_nibble.3.out_ff" IOB = TRUE; |
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#NET "fx2_flagc" LOC = "E4" | IOSTANDARD = LVTTL | PULLUP ; |
|
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NET "RED" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "BLUE" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "GREEN" LOC = "D3" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "HSYNC" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
NET "VSYNC" LOC = "D4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
INST "vga/hsync_ff" IOB = TRUE; |
INST "vga/vsync_ff" IOB = TRUE; |
INST "vga/red_ff" IOB = TRUE; |
INST "vga/green_ff" IOB = TRUE; |
INST "vga/blue_ff" IOB = TRUE; |
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NET "JTAG_nDET" LOC = "G5" | IOSTANDARD = LVTTL ; |
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NET "fx2_clk" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST ; |
INST "usb_dff_2" IOB = TRUE; |
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NET "sda" LOC = "R1" | PULLUP | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = FAST; |
NET "scl" LOC = "J7" | PULLUP | IOSTANDARD = LVTTL ; |
INST "sda_oe_ff" IOB = TRUE; |
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NET "data_request_irq" LOC = "N12" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "data_available_irq" LOC = "C8" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "error_irq" LOC = "E10" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_reset" LOC = "L10" | PULLUP | IOSTANDARD = LVCMOS25 ; |
NET "bus_n_start_transmission" LOC = "L9" | PULLUP | IOSTANDARD = LVCMOS25 ; |
NET "bus_n_end_transmission" LOC = "A7" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_n_data_valid<0>" LOC = "F8" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_n_data_valid<1>" LOC = "A8" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<0>" LOC = "P7" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<1>" LOC = "N8" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<2>" LOC = "M10" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<3>" LOC = "N10" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<4>" LOC = "P11" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<5>" LOC = "N11" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<6>" LOC = "C13" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<7>" LOC = "D13" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<8>" LOC = "C12" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<9>" LOC = "C11" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<10>" LOC = "D11" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<11>" LOC = "P8" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<12>" LOC = "B3" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<13>" LOC = "A3" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<14>" LOC = "B4" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_data_addr_cntrl<15>" LOC = "A4" | PULLUP | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_n_start_send" LOC = "R5" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "bus_n_error" LOC = "B8" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
INST "the_bus/n_send_ff" IOB = TRUE ; |
INST "the_bus/n_error_ff" IOB = TRUE ; |
INST "the_bus/start_trans_ff" IOB = TRUE ; |
INST "the_bus/end_tri_ff" IOB = TRUE ; |
INST "the_bus/end_out_ff" IOB = TRUE ; |
INST "the_bus/end_in_ff" IOB = TRUE ; |
INST "the_bus/reset_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.0.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.0.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.0.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.1.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.1.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.1.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.2.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.2.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.2.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.3.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.3.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.3.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.4.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.4.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.4.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.5.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.5.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.5.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.6.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.6.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.6.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.7.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.7.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.7.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.8.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.8.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.8.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.9.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.9.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.9.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.10.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.10.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.10.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.11.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.11.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.11.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.12.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.12.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.12.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.13.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.13.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.13.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.14.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.14.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.14.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.15.din_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.15.dout_ff" IOB = TRUE ; |
INST "the_bus/make_data_ffs.15.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.0.in_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.0.out_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.0.tri_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.1.in_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.1.out_ff" IOB = TRUE ; |
INST "the_bus/make_data_valid_ffs.1.tri_ff" IOB = TRUE ; |
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NET "n_hex_switch<0>" LOC = "F12" | PULLUP | IOSTANDARD = LVTTL ; |
NET "n_hex_switch<1>" LOC = "G12" | PULLUP | IOSTANDARD = LVTTL ; |
NET "n_hex_switch<2>" LOC = "F11" | PULLUP | IOSTANDARD = LVTTL ; |
NET "n_hex_switch<3>" LOC = "G11" | PULLUP | IOSTANDARD = LVTTL ; |
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NET "LEDS_A<0>" LOC="R3" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<0>" LOC="T2" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<1>" LOC="T6" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<1>" LOC="T5" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<2>" LOC="T7" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<2>" LOC="R7" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<3>" LOC="T9" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<3>" LOC="R9" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<4>" LOC="T11" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<4>" LOC="T10" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<5>" LOC="T12" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<5>" LOC="R11" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<6>" LOC="R13" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<6>" LOC="T13" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_A<7>" LOC="R14" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
NET "LEDS_K<7>" LOC="T14" | IOSTANDARD = LVCMOS25 | DRIVE = 2; |
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NET "flash_address<0>" LOC="M16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<1>" LOC="K15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<2>" LOC="J16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<3>" LOC="F15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<4>" LOC="H16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<5>" LOC="K16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<6>" LOC="H15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<7>" LOC="F16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<8>" LOC="E16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<9>" LOC="D16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<10>" LOC="F14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<11>" LOC="F13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<12>" LOC="C15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<13>" LOC="C16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<14>" LOC="E14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<15>" LOC="E13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<16>" LOC="J12" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<17>" LOC="G16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<18>" LOC="G14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_address<19>" LOC="G13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<0>" LOC="L16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<1>" LOC="R15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<2>" LOC="H14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<3>" LOC="K13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<4>" LOC="L14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<5>" LOC="H13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<6>" LOC="L13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<7>" LOC="D14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<8>" LOC="M15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<9>" LOC="P15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<10>" LOC="J14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<11>" LOC="K14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<12>" LOC="J13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<13>" LOC="M14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<14>" LOC="N14" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_data<15>" LOC="M13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_n_byte" LOC="N13" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_n_ce" LOC="N16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_n_oe" LOC="P16" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_n_we" LOC="D15" | IOSTANDARD = LVTTL | DRIVE = 2 ; |
NET "flash_ready_n_busy" LOC="H11" | IOSTANDARD = LVTTL | PULLUP ; |
INST "flash/address_ffs.0.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.1.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.2.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.3.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.4.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.5.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.6.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.7.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.8.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.9.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.10.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.11.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.12.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.13.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.14.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.15.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.16.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.17.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.18.one_ff" IOB = TRUE ; |
INST "flash/address_ffs.19.one_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.0.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.0.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.0.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.1.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.1.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.1.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.2.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.2.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.2.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.3.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.3.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.3.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.4.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.4.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.4.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.5.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.5.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.5.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.6.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.6.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.6.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.7.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.7.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.7.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.8.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.8.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.8.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.9.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.9.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.9.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.10.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.10.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.10.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.11.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.11.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.11.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.12.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.12.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.12.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.13.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.13.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.13.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.14.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.14.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.14.oe_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.15.in_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.15.out_ff" IOB = TRUE ; |
INST "flash/data_in_out_ffs.15.oe_ff" IOB = TRUE ; |
INST "flash/nce_reg" IOB = TRUE; |
INST "flash/noe_reg" IOB = TRUE; |
INST "flash/nwe_reg" IOB = TRUE; |
|
NET "fpga_done" LOC = "M11" | IOSTANDARD = LVCMOS25 ; |
NET "fpga_busy" LOC = "B10" | IOSTANDARD = LVCMOS25 | PULLDOWN; |
NET "fpga_n_init" LOC = "N9" | IOSTANDARD = LVCMOS25 | PULLUP; |
NET "fpga_n_prog" LOC = "T4" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_rd_n_wr" LOC = "N7" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_n_cs" LOC = "P6" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_cclk" LOC = "P13" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<0>" LOC = "A12" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<1>" LOC = "B12" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<2>" LOC = "A11" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<3>" LOC = "A10" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<4>" LOC = "D10" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<5>" LOC = "C9" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<6>" LOC = "D8" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
NET "fpga_data<7>" LOC = "C10" | IOSTANDARD = LVCMOS25 | DRIVE = 2 ; |
INST "fpga/cclk_ff" IOB = TRUE ; |
INST "fpga/n_prog_ff" IOB = TRUE ; |
INST "fpga/n_cs_ff" IOB = TRUE ; |
INST "fpga/rd_n_wr_ff" IOB = TRUE ; |
INST "fpga/n_init_ff" IOB = TRUE ; |
INST "fpga/busy_ff" IOB = TRUE ; |
INST "fpga/done_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.0.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.0.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.0.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.1.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.1.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.1.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.2.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.2.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.2.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.3.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.3.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.3.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.4.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.4.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.4.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.5.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.5.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.5.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.6.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.6.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.6.out_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.7.in_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.7.tri_ff" IOB = TRUE ; |
INST "make_fpga_data_ffs.7.out_ff" IOB = TRUE ; |
|
|
INST "vga/usbtmc_buf" INIT_00 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_01 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_02 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_03 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_04 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_05 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_06 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_07 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_08 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_09 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_0F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_10 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_11 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_12 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_13 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_14 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_15 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_16 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_17 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_18 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_19 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_1F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_20 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_21 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_22 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_23 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_24 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_25 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_26 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_27 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_28 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_29 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_2F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_30 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_31 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_32 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_33 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_34 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_35 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_36 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_37 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_38 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_39 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/usbtmc_buf" INIT_3F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
|
INST "vga/fpga_buf" INIT_00 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_01 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_02 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_03 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_04 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_05 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_06 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_07 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_08 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_09 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_0F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_10 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_11 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_12 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_13 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_14 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_15 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_16 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_17 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_18 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_19 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_1F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_20 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_21 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_22 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_23 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_24 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_25 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_26 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_27 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_28 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_29 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_2F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_30 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_31 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_32 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_33 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_34 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_35 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_36 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_37 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_38 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_39 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3A = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3B = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3C = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3E = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/fpga_buf" INIT_3F = 2020202020202020202020202020202020202020202020202020202020202020 ; |
|
INST "vga/ascii_buf0" INIT_00 = 205F5F2020202020202020202020205F2020205F202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_01 = 20202020202020202020202020202020202020202020202020205F5F5F5F2020 ; |
INST "vga/ascii_buf0" INIT_02 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_03 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_04 = 7C5F202F202020202020202020207C207C202F202F2020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_05 = 202020202020202020202020202020202020202020202020207C5F5F20207C20 ; |
INST "vga/ascii_buf0" INIT_06 = 61206E69616D344F4B4345472020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_07 = 20202020202020202020202020202020202020206D6F63344F4B43454720646E ; |
INST "vga/ascii_buf0" INIT_08 = 20202F202F20205F2020205F20207C207C5F7C207C2020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_09 = 2020202020202020202020202020202020202020202020202020205F7C207C20 ; |
INST "vga/ascii_buf0" INIT_0A = 2D2D2D2D2D2D2D2D2D2D2D2D2020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_0B = 20202020202020202020202020202020202020202D2D2D2D2D2D2D2D2D2D2D2D ; |
INST "vga/ascii_buf0" INIT_0C = 20207C207C207C207C207C207C207C20205F20207C2020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_0D = 20202020202020202020202020202020202020202020202020207C5F20207C20 ; |
INST "vga/ascii_buf0" INIT_0E = 70206C6172656E65672061207369206D6574737973204F4B4345472065685420 ; |
INST "vga/ascii_buf0" INIT_0F = 202020202D6F63206572617774666F732F65726177647261682065736F707275 ; |
INST "vga/ascii_buf0" INIT_10 = 205F5C205C207C207C5F7C207C207C207C207C207C2020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_11 = 20202020202020202020202020202020202020202020202020205F5F7C207C20 ; |
INST "vga/ascii_buf0" INIT_12 = 6D69742D6C61657220726F6620746E656D6E6F7269766E65206E676973656420 ; |
INST "vga/ascii_buf0" INIT_13 = 2020202020726F20676E69737365636F7270206E6F6974616D726F666E692065 ; |
INST "vga/ascii_buf0" INIT_14 = 7C5F5F5C20207C5F5F5F5F5F5C207C5F7C207C5F7C2020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_15 = 2020202020202020202020202020202062614C6F7263696D207C5F5F5F5F7C20 ; |
INST "vga/ascii_buf0" INIT_16 = 6974756C6F732029436F532820706968632D6E6F2D6D657473797320726F6620 ; |
INST "vga/ascii_buf0" INIT_17 = 207374726F70707573207463656A6F7270204F4B43454720656854202E736E6F ; |
INST "vga/ascii_buf0" INIT_18 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_19 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_1A = 797320726F662079676F6C6F646F6874656D206E67697365642077656E206120 ; |
INST "vga/ascii_buf0" INIT_1B = 2020202020202020202020206863696877202C73706968632D6E6F2D6D657473 ; |
INST "vga/ascii_buf0" INIT_1C = 704120666F2079746973726576696E55206E7265422020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_1D = 2020202020202020202020202948464228207365636E65696353206465696C70 ; |
INST "vga/ascii_buf0" INIT_1E = 7774666F7320666F206E67697365642D6F632073657461746973736563656E20 ; |
INST "vga/ascii_buf0" INIT_1F = 20202020202020202020646E612065726177647261682074736166202C657261 ; |
INST "vga/ascii_buf0" INIT_20 = 202020202020202031322065737361676C6C6575512020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_21 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_22 = 636F7270206C616E67697320656D69742D6C6165722064657461636964656420 ; |
INST "vga/ascii_buf0" INIT_23 = 2020202020656874206E6968746957202E657261776472616820676E69737365 ; |
INST "vga/ascii_buf0" INIT_24 = 20202020202020202033332E34204748206D6F6F522020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_25 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_26 = 6D206E69616D344F4B43454720656874202C7463656A6F7270204F4B43454720 ; |
INST "vga/ascii_buf0" INIT_27 = 6C61746E656D697265707865206E612073746E6573657270657220656C75646F ; |
INST "vga/ascii_buf0" INIT_28 = 2020202020656E6E6569422F6C65694220313035322020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_29 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_2A = 6563656E206568742073726566666F206863696877202C6D726F6674616C7020 ; |
INST "vga/ascii_buf0" INIT_2B = 20646565707320726F66207265776F7020676E697475706D6F63207972617373 ; |
INST "vga/ascii_buf0" INIT_2C = 20202020202020202020646E616C72657A746977532020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_2D = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_2E = 20736D687469726F676C6120656D69742D6C61657220657669736E65746E6920 ; |
INST "vga/ascii_buf0" INIT_2F = 202020202020202079726173736563656E20656874207361206C6C6577207361 ; |
INST "vga/ascii_buf0" INIT_30 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_31 = 2020202020202020202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_32 = 69736E65746E69206C6F72746E6F6320726F66207974696C69626978656C6620 ; |
INST "vga/ascii_buf0" INIT_33 = 20202020202020202020202020202E736B736174206572617774666F73206576 ; |
INST "vga/ascii_buf0" INIT_34 = 632E62616C6F7263696D2E7777772F2F3A707474682020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_35 = 2020202020202020202020202020202020202020202020202020202020202068 ; |
INST "vga/ascii_buf0" INIT_36 = 3A70747468203A656573206E6F6974616D726F666E692065726F6D20726F4620 ; |
INST "vga/ascii_buf0" INIT_37 = 2020202020202020202020202068632E62616C6F7263696D2E6F6B6365672F2F ; |
INST "vga/ascii_buf0" INIT_38 = 5F5F5F5F5F5F5F5F202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_39 = 2020202020202020202020202020202020202020202020205F5F5F5F5F5F5F5F ; |
INST "vga/ascii_buf0" INIT_3A = 5F5F5F5F5F5F5F20202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_3B = 202020202020202020202020202020202020202020202020205F5F5F5F5F5F5F ; |
INST "vga/ascii_buf0" INIT_3C = 6D20434D544253552F2020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_3D = 20202020202020202020202020202020202020202020205C3A73656761737365 ; |
INST "vga/ascii_buf0" INIT_3E = 656D20414750462F202020202020202020202020202020202020202020202020 ; |
INST "vga/ascii_buf0" INIT_3F = 2020202020202020202020202020202020202020202020205C3A736567617373 ; |
|
INST "vga/rom_lo" INIT_00 = 000000007E818199BD8181A5817E000000000000000000000000000000000000 ; |
INST "vga/rom_lo" INIT_01 = 0000000010387CFEFEFEFE6C00000000000000007EFFFFE7C3FFFFDBFF7E0000 ; |
INST "vga/rom_lo" INIT_02 = 000000003C1818E7E7E73C3C18000000000000000010387CFE7C381000000000 ; |
INST "vga/rom_lo" INIT_03 = 000000000000183C3C18000000000000000000003C18187EFFFF7E3C18000000 ; |
INST "vga/rom_lo" INIT_04 = 00000000003C664242663C0000000000FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF ; |
INST "vga/rom_lo" INIT_05 = 0000000078CCCCCCCC78321A0E1E0000FFFFFFFFFFC399BDBD99C3FFFFFFFFFF ; |
INST "vga/rom_lo" INIT_06 = 00000000E0F070303030303F333F00000000000018187E183C666666663C0000 ; |
INST "vga/rom_lo" INIT_07 = 000000001818DB3CE73CDB1818000000000000C0E6E767636363637F637F0000 ; |
INST "vga/rom_lo" INIT_08 = 0000000002060E1E3EFE3E1E0E0602000000000080C0E0F0F8FEF8F0E0C08000 ; |
INST "vga/rom_lo" INIT_09 = 000000006666006666666666666600000000000000183C7E1818187E3C180000 ; |
INST "vga/rom_lo" INIT_0A = 0000007CC60C386CC6C66C3860C67C00000000001B1B1B1B1B7BDBDBDB7F0000 ; |
INST "vga/rom_lo" INIT_0B = 000000007E183C7E1818187E3C18000000000000FEFEFEFE0000000000000000 ; |
INST "vga/rom_lo" INIT_0C = 00000000183C7E18181818181818000000000000181818181818187E3C180000 ; |
INST "vga/rom_lo" INIT_0D = 0000000000003060FE60300000000000000000000000180CFE0C180000000000 ; |
INST "vga/rom_lo" INIT_0E = 0000000000002466FF66240000000000000000000000FEC0C0C0000000000000 ; |
INST "vga/rom_lo" INIT_0F = 00000000001038387C7CFEFE000000000000000000FEFE7C7C38381000000000 ; |
INST "vga/rom_lo" INIT_10 = 000000001818001818183C3C3C18000000000000000000000000000000000000 ; |
INST "vga/rom_lo" INIT_11 = 000000006C6CFE6C6C6CFE6C6C00000000000000000000000000002466666600 ; |
INST "vga/rom_lo" INIT_12 = 0000000086C66030180CC6C200000000000018187CC68606067CC0C2C67C1818 ; |
INST "vga/rom_lo" INIT_13 = 000000000000000000000060303030000000000076CCCCCCDC76386C6C380000 ; |
INST "vga/rom_lo" INIT_14 = 0000000030180C0C0C0C0C0C18300000000000000C18303030303030180C0000 ; |
INST "vga/rom_lo" INIT_15 = 00000000000018187E18180000000000000000000000663CFF3C660000000000 ; |
INST "vga/rom_lo" INIT_16 = 00000000000000007E0000000000000000000030181818000000000000000000 ; |
INST "vga/rom_lo" INIT_17 = 0000000080C06030180C06020000000000000000181800000000000000000000 ; |
INST "vga/rom_lo" INIT_18 = 000000007E1818181818187838180000000000007CC6C6E6F6DECEC6C67C0000 ; |
INST "vga/rom_lo" INIT_19 = 000000007CC60606063C0606C67C000000000000FEC6C06030180C06C67C0000 ; |
INST "vga/rom_lo" INIT_1A = 000000007CC6060606FCC0C0C0FE0000000000001E0C0C0CFECC6C3C1C0C0000 ; |
INST "vga/rom_lo" INIT_1B = 0000000030303030180C0606C6FE0000000000007CC6C6C6C6FCC0C060380000 ; |
INST "vga/rom_lo" INIT_1C = 00000000780C0606067EC6C6C67C0000000000007CC6C6C6C67CC6C6C67C0000 ; |
INST "vga/rom_lo" INIT_1D = 0000000030181800000018180000000000000000001818000000181800000000 ; |
INST "vga/rom_lo" INIT_1E = 000000000000007E00007E000000000000000000060C18306030180C06000000 ; |
INST "vga/rom_lo" INIT_1F = 000000001818001818180CC6C67C0000000000006030180C060C183060000000 ; |
INST "vga/rom_lo" INIT_20 = 00000000C6C6C6C6FEC6C66C38100000000000007CC0DCDEDEDEC6C6C67C0000 ; |
INST "vga/rom_lo" INIT_21 = 000000003C66C2C0C0C0C0C2663C000000000000FC666666667C666666FC0000 ; |
INST "vga/rom_lo" INIT_22 = 00000000FE6662606878686266FE000000000000F86C6666666666666CF80000 ; |
INST "vga/rom_lo" INIT_23 = 000000003A66C6C6DEC0C0C2663C000000000000F06060606878686266FE0000 ; |
INST "vga/rom_lo" INIT_24 = 000000003C18181818181818183C000000000000C6C6C6C6C6FEC6C6C6C60000 ; |
INST "vga/rom_lo" INIT_25 = 00000000E666666C78786C6666E600000000000078CCCCCC0C0C0C0C0C1E0000 ; |
INST "vga/rom_lo" INIT_26 = 00000000C3C3C3C3C3DBFFFFE7C3000000000000FE6662606060606060F00000 ; |
INST "vga/rom_lo" INIT_27 = 000000007CC6C6C6C6C6C6C6C67C000000000000C6C6C6C6CEDEFEF6E6C60000 ; |
INST "vga/rom_lo" INIT_28 = 00000E0C7CDED6C6C6C6C6C6C67C000000000000F0606060607C666666FC0000 ; |
INST "vga/rom_lo" INIT_29 = 000000007CC6C6060C3860C6C67C000000000000E66666666C7C666666FC0000 ; |
INST "vga/rom_lo" INIT_2A = 000000007CC6C6C6C6C6C6C6C6C60000000000003C18181818181899DBFF0000 ; |
INST "vga/rom_lo" INIT_2B = 000000006666FFDBDBC3C3C3C3C3000000000000183C66C3C3C3C3C3C3C30000 ; |
INST "vga/rom_lo" INIT_2C = 000000003C181818183C66C3C3C3000000000000C3C3663C18183C66C3C30000 ; |
INST "vga/rom_lo" INIT_2D = 000000003C30303030303030303C000000000000FFC3C16030180C86C3FF0000 ; |
INST "vga/rom_lo" INIT_2E = 000000003C0C0C0C0C0C0C0C0C3C00000000000002060E1C3870E0C080000000 ; |
INST "vga/rom_lo" INIT_2F = 0000FF00000000000000000000000000000000000000000000000000C66C3810 ; |
INST "vga/rom_lo" INIT_30 = 0000000076CCCCCC7C0C78000000000000000000000000000000000000183030 ; |
INST "vga/rom_lo" INIT_31 = 000000007CC6C0C0C0C67C0000000000000000007C666666666C786060E00000 ; |
INST "vga/rom_lo" INIT_32 = 000000007CC6C0C0FEC67C00000000000000000076CCCCCCCC6C3C0C0C1C0000 ; |
INST "vga/rom_lo" INIT_33 = 0078CC0C7CCCCCCCCCCC76000000000000000000F060606060F060646C380000 ; |
INST "vga/rom_lo" INIT_34 = 000000003C181818181838001818000000000000E666666666766C6060E00000 ; |
INST "vga/rom_lo" INIT_35 = 00000000E6666C78786C666060E00000003C66660606060606060E0006060000 ; |
INST "vga/rom_lo" INIT_36 = 00000000DBDBDBDBDBFFE60000000000000000003C1818181818181818380000 ; |
INST "vga/rom_lo" INIT_37 = 000000007CC6C6C6C6C67C000000000000000000666666666666DC0000000000 ; |
INST "vga/rom_lo" INIT_38 = 001E0C0C7CCCCCCCCCCC76000000000000F060607C6666666666DC0000000000 ; |
INST "vga/rom_lo" INIT_39 = 000000007CC60C3860C67C000000000000000000F06060606676DC0000000000 ; |
INST "vga/rom_lo" INIT_3A = 0000000076CCCCCCCCCCCC0000000000000000001C3630303030FC3030100000 ; |
INST "vga/rom_lo" INIT_3B = 0000000066FFDBDBC3C3C3000000000000000000183C66C3C3C3C30000000000 ; |
INST "vga/rom_lo" INIT_3C = 00F80C067EC6C6C6C6C6C6000000000000000000C3663C183C66C30000000000 ; |
INST "vga/rom_lo" INIT_3D = 000000000E18181818701818180E000000000000FEC6603018CCFE0000000000 ; |
INST "vga/rom_lo" INIT_3E = 0000000070181818180E18181870000000000000181818181800181818180000 ; |
INST "vga/rom_lo" INIT_3F = 0000000000FEC6C6C66C381000000000000000000000000000000000DC760000 ; |
/gecko4/trunk/GECKO4com/spartan200_an/config/project.force
0,0 → 1,12
vsim -t ps xc3s2000an_top |
add wave -hex * |
force clock_25MHz 0 0 , 1 20 ns -repeat 40 ns |
force clock_16MHz 0 0 , 1 31250 ps -repeat 62500 ps |
force clock_25MHz_fb 0 0 , 1 20 ns -repeat 40 ns |
force clock_48MHz_fb 0 0 , 1 10416 ps -repeat 20833 ps |
force n_reset 0 0 , 1 100 ns |
foce jtag_ndet 1 |
force fx2_sda 1 |
force fx2_scl 1 |
force flasg_ready_n_busy 1 |
run 10 ms |
/gecko4/trunk/GECKO4com/spartan200_an/config/project.device
0,0 → 1,4
TECHNOLOGY=Spartan3A |
PART=XC3S200AN |
PACKAGE=FTG256 |
SPEED_GRADE=-4 |
/gecko4/trunk/GECKO4com/spartan200_an/config/project.files
0,0 → 1,54
flipflops/flip-flops_entity.vhdl |
flipflops/flip-flops_behavior_generic.vhdl |
i2c/edge_detector-entity.vhdl |
i2c/edge_detector-behavior.vhdl |
i2c/spi-entity.vhdl |
i2c/spi-behavior-xilinx.vhdl |
i2c/24LC32A_emu-entity.vhdl |
i2c/24LC32A_emu-behavior.vhdl |
clockgen/clocks-entity.vhdl |
clockgen/clocks-behavior-xilinx.vhdl |
vga/vga_controller-entity.vhdl |
vga/vga_controller-behavior-xilinx.vhdl |
vga/vga_leds_buttons_bus-entity.vhdl |
vga/vga_leds_buttons_bus-behavior.vhdl |
fifos/fifo_2kb_ef-entity.vhdl |
fifos/fifo_2kb_ef-behavior-xilinx.vhdl |
fifos/fifo_2kb-entity.vhdl |
fifos/fifo_2kb-behavior-xilinx.vhdl |
fifos/fifo_4kb_16w_8r-entity.vhdl |
fifos/fifo_4kb_16w_8r-behavior-xilinx.vhdl |
fifos/fifo_4kb_8w_16r-entity.vhdl |
fifos/fifo_4kb_8w_16r-behavior-xilinx.vhdl |
config/config-entity.vhdl |
config/config-behavior.vhdl |
ieee488.2_status/ieee488.2_status-entity.vhdl |
ieee488.2_status/ieee488.2_status-behavior.vhdl |
fpga_if/idreg_rom-entity.vhdl |
fpga_if/idreg_rom-behavior.vhdl |
fpga_if/fpga_if-entity.vhdl |
fpga_if/fpga_if-behavior.vhdl |
fpga_if/bitfile_interpreter-entity.vhdl |
fpga_if/bitfile_interpreter-behavior.vhdl |
fx2_fifo_if/usbtmc-entity.vhdl |
fx2_fifo_if/usbtmc-behavior-xilinx.vhdl |
flash/flash-entity.vhdl |
flash/flash-behavior-xilinx.vhdl |
cmd_09_if/cmd_09-entity.vhdl |
cmd_09_if/cmd_09-behavior.vhdl |
cmd_23_24_if/hexswitch-entity.vhdl |
cmd_23_24_if/hexswitch-behavior.vhdl |
cmd_25_if/cmd_25-entity.vhdl |
cmd_25_if/cmd_25-behavior.vhdl |
cmd_18_1e_if/cmd_18_1e_if-entity.vhdl |
cmd_18_1e_if/cmd_18_1e_if-behavior-xilinx.vhdl |
reset_if/reset_if-entity.vhdl |
reset_if/reset_if-behavior.vhdl |
scpi_if/scpi_if-entity.vhdl |
scpi_if/scpi_if-behavior-xilinx.vhdl |
bus_if/bus_if-entity.vhdl |
bus_if/bus_if-behavior-xilinx.vhdl |
user_fifo/user_fifo-entity.vhdl |
user_fifo/user_fifo-behavior.vhdl |
toplevel/xc3s200an_top-entity.vhdl |
toplevel/xc3s200an_top-behavior.vhdl |
/gecko4/trunk/GECKO4com/spartan200_an/Makefile.synthesis
0,0 → 1,72
################################################################################ |
## _ _ __ ____ ## |
## / / | | / _| | __| ## |
## | |_| | _ _ / / | |_ ## |
## | _ | | | | | | | | _| ## |
## | | | | | |_| | \ \_ | |__ ## |
## |_| |_| \_____| \__| |____| microLab ## |
## ## |
## Bern University of Applied Sciences (BFH) ## |
## Quellgasse 21 ## |
## Room HG 4.33 ## |
## 2501 Biel/Bienne ## |
## Switzerland ## |
## ## |
## http://www.microlab.ch ## |
################################################################################ |
SYNTHESIZER=synplify_premier_dp |
|
TOPLEVEL := $(shell cat $(REL_PATH)/$(PROJECT_TOP)) |
VHDL_FILES := $(shell cat $(REL_PATH)/$(PROJECT_LIST)) |
VHDL_FILES_EXTENDED = $(addprefix $(REL_PATH)/vhdl/,$(VHDL_FILES)) |
PROJECT_PRJ=$(TOPLEVEL).prj |
PROJECT_EDF=$(TOPLEVEL).edf |
PROJECT_NCF=$(TOPLEVEL).ncf |
|
include $(REL_PATH)/$(PROJECT_DEVICE) |
|
define create_prj |
echo "Generating Synplify project:" $(PROJECT_PRJ) |
echo -e "# Automatic generated project file.\n# DO NOT EDIT!\n# Edit options in the file $(PROJECT_OPTIONS)!\n" > $(PROJECT_PRJ) |
echo -e $(foreach file, $(VHDL_FILES_EXTENDED),\ |
"add_file -vhdl -lib work \"../$(file)\"\n") >> $(PROJECT_PRJ) |
echo "impl -add $(TOPLEVEL) -type fpga" >> $(PROJECT_PRJ) |
echo "set_option -technology $(TECHNOLOGY)" >> $(PROJECT_PRJ) |
echo "set_option -part $(PART)" >> $(PROJECT_PRJ) |
echo "set_option -package $(PACKAGE)" >> $(PROJECT_PRJ) |
echo "set_option -speed_grade $(SPEED_GRADE)" >> $(PROJECT_PRJ) |
if test -f $(REL_PATH)/$(PROJECT_OPTIONS); then\ |
cat $(REL_PATH)/$(PROJECT_OPTIONS) >> $(PROJECT_PRJ); else\ |
echo "# You can add project options in $(PROJECT_OPTIONS)" >> $(PROJECT_PRJ);\ |
fi |
echo "project -result_file \"./$(TOPLEVEL).edf\"" >> $(PROJECT_PRJ) |
endef #create_prj |
|
define run_synth |
@echo "===========================================================" |
@echo " Synthetizing with $(SYNTHESIZER)" |
@echo "===========================================================" |
rm -rf synth |
rm -f $(PROJECT_EDF) |
mkdir synth |
cp $(PROJECT_PRJ) synth/$(PROJECT_PRJ) |
cd synth; $(SYNTHESIZER) -log ./$(TOPLEVEL).log -batch ./$(PROJECT_PRJ) >& /dev/null |
cp synth/$(PROJECT_EDF) . |
cp synth/$(PROJECT_NCF) . |
endef #run_synth |
|
.PHONY: default |
|
#rules |
default : $(PROJECT_EDF) |
|
force_synth : |
@$(run_synth) |
|
$(PROJECT_EDF) : $(PROJECT_PRJ) |
@$(run_synth) |
|
$(PROJECT_PRJ) : $(VHDL_FILES_EXTENDED) $(REL_PATH)/$(PROJECT_OPT) |
@$(create_prj) |
|
.PRECIOUS: %.prj |
/gecko4/trunk/GECKO4com/spartan200_an/Makefile.modelsim
0,0 → 1,32
################################################################################ |
## _ _ __ ____ ## |
## / / | | / _| | __| ## |
## | |_| | _ _ / / | |_ ## |
## | _ | | | | | | | | _| ## |
## | | | | | |_| | \ \_ | |__ ## |
## |_| |_| \_____| \__| |____| microLab ## |
## ## |
## Bern University of Applied Sciences (BFH) ## |
## Quellgasse 21 ## |
## Room HG 4.33 ## |
## 2501 Biel/Bienne ## |
## Switzerland ## |
## ## |
## http://www.microlab.ch ## |
################################################################################ |
VHDL_FILES := $(shell cat $(REL_PATH)/$(PROJECT_LIST)) |
TOPLEVEL := $(shell cat $(REL_PATH)/$(PROJECT_TOP)) |
MODELSIM_LIB=vlib |
MODELSIM_VHDL_COMP=vcom |
MODELSIM_VERILOG_COMP=vlog |
MODELSIM_SIM=vsim |
|
define run_modelsim |
rm -rf work |
$(MODELSIM_LIB) work |
echo -e $(foreach file, $(VHDL_FILES) , "$(REL_PATH)/vhdl/$(file)\n" ) | xargs $(MODELSIM_VHDL_COMP) |
$(MODELSIM_SIM) -do $(REL_PATH)/$(PROJECT_FORCE) |
endef #run_modelsim |
|
default: $(REL_PATH)/$(PROJECT_LIST) $(REL_PATH)/$(PROJECT_FORCE) |
@$(run_modelsim) |
/gecko4/trunk/GECKO4com/spartan200_an/Makefile.xilinx
0,0 → 1,173
################################################################################ |
## _ _ __ ____ ## |
## / / | | / _| | __| ## |
## | |_| | _ _ / / | |_ ## |
## | _ | | | | | | | | _| ## |
## | | | | | |_| | \ \_ | |__ ## |
## |_| |_| \_____| \__| |____| microLab ## |
## ## |
## Bern University of Applied Sciences (BFH) ## |
## Quellgasse 21 ## |
## Room HG 4.33 ## |
## 2501 Biel/Bienne ## |
## Switzerland ## |
## ## |
## http://www.microlab.ch ## |
################################################################################ |
TOPLEVEL := $(shell cat $(REL_PATH)/$(PROJECT_TOP)) |
PROJECT_NGD=$(TOPLEVEL).ngd |
PROJECT_EDF=$(TOPLEVEL).edf |
PROJECT_NCF=$(TOPLEVEL).ncf |
PROJECT_MAP=$(TOPLEVEL)-map.ncd |
PROJECT_MAP_PCF=$(TOPLEVEL)-map.pcf |
PROJECT_PAR=$(TOPLEVEL)-par.ncd |
PROJECT_TRACE=$(TOPLEVEL).twr |
PROJECT_BIT=$(TOPLEVEL).bit |
|
include $(REL_PATH)/$(PROJECT_DEVICE) |
include $(REL_PATH)/$(PROJECT_XILINX) |
|
define run_translate |
@echo "===========================================================" |
@echo " Translating " |
@echo "===========================================================" |
rm -rf ngdbuild |
rm -f $(PROJECT_NGD) |
mkdir ngdbuild |
cd ngdbuild && ngdbuild -intstyle ise -dd temp -nt timestamp \ |
-uc ../$(REL_PATH)/$(PROJECT_UCF)\ |
../$(PROJECT_EDF) $(PROJECT_NGD) >& /dev/null |
cp ngdbuild/$(PROJECT_NGD) $(PROJECT_NGD) |
endef #run_translate |
|
define run_map |
@echo "===========================================================" |
@echo " Mapping " |
@echo "===========================================================" |
rm -rf map |
rm -f $(PROJECT_MAP) |
mkdir map |
cd map && map -intstyle ise -ol $(MAP_EFFORT) $(MAP_OPTIONS) -cm $(MAP_COVER_MODE) \ |
-pr b -c 100 -tx off \ |
-o $(PROJECT_MAP) ../$(PROJECT_NGD) >& /dev/null |
cp map/$(PROJECT_MAP) $(PROJECT_MAP) |
cp map/$(PROJECT_MAP_PCF) $(PROJECT_MAP_PCF) |
endef #run_map |
|
define run_guided_par |
@echo "===========================================================" |
@echo " Guided Placing and Routing " |
@echo "===========================================================" |
if test ! -f $(PROJECT_PAR) ; then \ |
echo "INFO: No previous placement run found. Running normal PAR"; \ |
rm -rf par; \ |
rm -f $(PROJECT_PAR); \ |
mkdir par; \ |
cd par && par -w -intstyle ise -ol high ../$(PROJECT_MAP) \ |
$(PROJECT_PAR) ../$(PROJECT_MAP_PCF) >& \dev\null;\ |
cp $(PROJECT_PAR) .. \ |
; \ |
else \ |
rm -rf par; \ |
mkdir par; \ |
mv -f $(PROJECT_PAR) par/$(PROJECT_PAR).guide.ncd; \ |
cd par && par -w -intstyle ise -ol high -gf $(PROJECT_PAR).guide.ncd -gm leverage ../$(PROJECT_MAP) \ |
$(PROJECT_PAR) ../$(PROJECT_MAP_PCF) >& \dev\null;\ |
cp $(PROJECT_PAR) .. \ |
; \ |
fi |
endef #run_guided_par |
|
define run_par |
@echo "===========================================================" |
@echo " Placing and Routing " |
@echo "===========================================================" |
rm -rf par |
rm -f $(PROJECT_PAR) |
mkdir par |
cd par && par -w -intstyle ise -ol $(PAR_EFFORT) ../$(PROJECT_MAP) \ |
$(PROJECT_PAR) ../$(PROJECT_MAP_PCF) >& /dev/null |
cp par/$(PROJECT_PAR) $(PROJECT_PAR) |
endef #run_par |
|
define run_gentimsim |
@echo "===========================================================" |
@echo " Generating Full Timing Simulation Netlist " |
@echo " ... " |
rm -rf timsim |
mkdir timsim |
netgen -sim -ofmt vhdl -dir timsim -w $(PROJECT_PAR) >& timsim/netgen.log |
@echo vlib work > timsim/$(TOPLEVEL)-par.do |
@echo vcom -work work $(TOPLEVEL)-par.vhd >> timsim/$(TOPLEVEL)-par.do |
@echo vsim -t ps -sdftyp $(TOPLEVEL)=./$(TOPLEVEL)-par.sdf -sdfnoerror work.$(TOPLEVEL) >> timsim/$(TOPLEVEL)-par.do |
@echo " Full Timing Simulation Netlist available in sandbox/timsim" |
@echo "===========================================================" |
endef #run_gentimsim |
|
define run_trace |
@echo "===========================================================" |
@echo " Generating Timing Report " |
@echo " ... " |
rm -rf trace |
mkdir trace |
rm -f $(PROJECT_TRACE) |
cd trace && trce -intstyle ise -e $(NR_OF_TIMING_TRACES) -s $(subst -,,$(SPEED_GRADE)) ../$(PROJECT_PAR)\ |
-o $(PROJECT_TRACE) ../$(PROJECT_MAP_PCF) -ucf ../$(REL_PATH)/$(PROJECT_UCF) >& trace.log |
cp trace/$(PROJECT_TRACE) . |
@echo " Full Timing trace available in sandbox/$(PROJECT_TRACE)" |
@echo "===========================================================" |
endef #run_trace |
|
define run_bitgen |
@echo "===========================================================" |
@echo " Generating Bitfile " |
@echo " ... " |
rm -rf bitgen |
mkdir bitgen |
rm -f $(PROJECT_BIT) |
cd bitgen && bitgen -w -g UnusedPin:$(UNUSED_PINS) ../$(PROJECT_PAR) $(PROJECT_BIT) >& bitgen.log |
cp bitgen/$(PROJECT_BIT) ../bitfile/$(PROJECT_BIT) |
@echo " Xilinx bitfile available in bitfile/$(PROJECT_BIT)" |
@echo "===========================================================" |
endef #run_bitgen |
|
|
|
|
default: $(PROJECT_NGD) $(PROJECT_MAP) $(PROJECT_MAP_PCF) $(PROJECT_PAR) $(PROJECT_BIT) |
|
force_translate: |
@$(run_translate) |
force_map: |
@$(run_map) |
|
$(PROJECT_NGD): $(PROJECT_EDF) $(PROJECT_NCF) $(REL_PATH)/$(PROJECT_UCF) |
@$(run_translate) |
|
$(PROJECT_MAP) $(PROJECT_MAP_PCF): $(PROJECT_NGD) $(REL_PATH)/$(PROJECT_XILINX) |
@$(run_map) |
$(PROJECT_PAR): $(PROJECT_MAP) $(PROJECT_MAP_PCF) $(REL_PATH)/$(PROJECT_XILINX) |
ifeq ($(GUIDED_PAR),1) |
@$(run_guided_par) |
else |
@$(run_par) |
endif |
ifeq ($(GENERATE_SIMULATION_FILES),1) |
@$(run_gentimsim) |
else |
@echo "===========================================================" |
@echo " Timing Simulation netlist NOT generated " |
@echo "===========================================================" |
endif |
ifeq ($(GENERATE_TIMING_TRACE_FILE),1) |
@$(run_trace) |
else |
@echo "===========================================================" |
@echo " Timing Trace File NOT generated " |
@echo "===========================================================" |
endif |
|
$(PROJECT_BIT) : $(PROJECT_PAR) $(REL_PATH)/$(PROJECT_XILINX) |
@$(run_bitgen) |
|
.PRECIOUS: %.prj %.bit %.edf %.ngd %-map.ncd %-par.ncd %.twr |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fx2_fifo_if/usbtmc-behavior-xilinx.vhdl
0,0 → 1,1067
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
-- For sending messages to the PC, the FIFO has to contain: |
-- 1) The size of the message (in bytes) with the size bit set (can have 1, |
-- 2,3, or 4 bytes to indicate size (LSB first)) |
-- 2) The message itself. |
|
ARCHITECTURE xilinx OF USBTMC IS |
|
TYPE USBTMC_STATE_TYPE IS (WAIT_HEADER,INIT_READ_HEADER,READ_HEADER, |
INTERPRET_HEADER,SIGNAL_ERROR,ERROR_WAIT, |
INIT_COPY_PAYLOAD,DET_RX_SIZE,CHECK_TX_FIFO, |
REQUEST_PAYLOAD_BYTES,CHECK_PAYLOAD_BYTES, |
INIT_DUMMY_READ,DO_DUMMY_READ,DUMMY_NOP, |
DET_MAX_TRASF_SIZE,CHECK_FIFO_STATUS, |
RESET_MESSAGE_SIZE,GET_MESSAGE_SIZE_0, |
GET_MESSAGE_SIZE_1,GET_MESSAGE_SIZE_2, |
GET_MESSAGE_SIZE_3,MESSAGE_UPDATE,SEND_HEADER, |
SEND_PAYLOAD,SEND_PKT_END,CHECK_FULL_STATUS, |
TX_NOP); |
|
COMPONENT FD |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FD_1 |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FDE |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
CE : IN std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT fifo_2kb_ef |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
high_speed : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_last : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_last : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
early_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT fifo_2kb |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_size : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END COMPONENT; |
|
CONSTANT c_high_speed_packet_size : std_logic_vector( 9 DOWNTO 0 ) := "10"&X"00"; |
CONSTANT c_full_speed_packet_size : std_logic_vector( 9 DOWNTO 0 ) := "00"&X"40"; |
|
SIGNAL s_fifo_clock_reg : std_logic; |
SIGNAL s_reset : std_logic; |
SIGNAL s_reset_count_reg : std_logic_vector( 2 DOWNTO 0 ); |
|
SIGNAL s_EP8_not_empty : std_logic; |
SIGNAL s_EP6_not_full : std_logic; |
SIGNAL s_endpoint_addr_next : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_endpoint_n_oe_next : std_logic; |
SIGNAL s_endpoint_n_re_next : std_logic; |
|
SIGNAL s_ena_out_ffs : std_logic; |
SIGNAL s_ena_in_ffs : std_logic; |
SIGNAL s_ena_data_in : std_logic; |
SIGNAL s_ready_to_receive_reg : std_logic; |
|
SIGNAL s_usbtmc_state_reg : USBTMC_STATE_TYPE; |
SIGNAL s_request_header_byte : std_logic; |
SIGNAL s_header_byte_request_pending : std_logic; |
SIGNAL s_header_byte_valid : std_logic; |
SIGNAL s_header_byte_pending_id : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_header_byte_valid_id : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_header_byte_request_id : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_header_request_done : std_logic; |
SIGNAL s_header_error_reg : std_logic; |
SIGNAL s_header_error_next : std_logic; |
SIGNAL s_Message_ID_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_known_Message_ID : std_logic; |
SIGNAL s_bTag_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_bTag_inverse : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_bTag_error : std_logic; |
SIGNAL s_data_in_is_zero : std_logic; |
SIGNAL s_reserved_3_error : std_logic; |
SIGNAL s_transfer_size_reg : std_logic_vector( 31 DOWNTO 0 ); |
SIGNAL s_zero_payload_size_reg : std_logic; |
SIGNAL s_eom_bit_reg : std_logic; |
SIGNAL s_rx_message_in_progress_reg : std_logic; |
|
SIGNAL s_data_in : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_read_fifo_full : std_logic; |
SIGNAL s_last_message_byte : std_logic; |
|
SIGNAL s_data_out_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_ep_n_we_reg : std_logic; |
SIGNAL s_ep_pkt_end_reg : std_logic; |
SIGNAL s_ep_n_tri_next : std_logic; |
SIGNAL s_tx_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_tx_pop_data_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_tx_pop_size : std_logic; |
SIGNAL s_tx_fifo_empty : std_logic; |
|
SIGNAL s_tx_fifo_data_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_tx_fifo_data_valid_reg : std_logic; |
SIGNAL s_tx_fifo_size_bit_reg : std_logic; |
SIGNAL s_tx_fifo_pop : std_logic; |
SIGNAL s_outstanding_messages_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_message_in_progress_reg : std_logic; |
SIGNAL s_message_size_reg : std_logic_vector( 31 DOWNTO 0 ); |
SIGNAL s_valid_msg_size_byte : std_logic; |
SIGNAL s_valid_payload_byte : std_logic; |
SIGNAL s_tx_data_pop : std_logic; |
SIGNAL s_can_tx_complete_message : std_logic; |
SIGNAL s_can_tx_complete_message_reg : std_logic; |
SIGNAL s_real_payload_size_reg : std_logic_vector( 32 DOWNTO 0 ); |
SIGNAL s_header_insert_count_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_bytes_send_cnt_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_require_n_pkt_end : std_logic; |
SIGNAL s_send_payload_byte : std_logic; |
|
SIGNAL s_nr_of_bytes_req_cnt_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_resting_buffer_bytes : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_rx_payload_cnt_reg : std_logic_vector( 32 DOWNTO 0 ); |
SIGNAL s_rx_payload_cnt_next : std_logic_vector( 32 DOWNTO 0 ); |
SIGNAL s_rx_cnt_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_can_rx_all : std_logic; |
SIGNAL s_req_payload_byte : std_logic; |
SIGNAL s_rx_pending_pipe_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_lmb_pipe_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_rf_last_data_byte : std_logic; |
SIGNAL s_dummy_read_cnt_reg : std_logic_vector( 2 DOWNTO 0 ); |
|
SIGNAL s_wf_push : std_logic; |
SIGNAL s_wf_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_wf_push_size : std_logic; |
|
SIGNAL s_fx2_data_nibble : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_fx2_data_select : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_ind_pipe_reg : std_logic_vector( 1 DOWNTO 0 ); |
|
BEGIN |
|
-------------------------------------------------------------------------------- |
-- define outputs -- |
-------------------------------------------------------------------------------- |
sync_reset_out <= s_reset; |
transfer_in_prog <= s_rx_message_in_progress_reg; |
rf_last_data_byte<= s_rf_last_data_byte; |
wf_fifo_empty <= s_tx_fifo_empty; |
indicator_pulse <= s_ind_pipe_reg(0) AND NOT(s_ind_pipe_reg(1)); |
|
-------------------------------------------------------------------------------- |
-- define control signals -- |
-------------------------------------------------------------------------------- |
s_endpoint_addr_next <= "11" WHEN |
s_usbtmc_state_reg = INIT_READ_HEADER OR |
s_usbtmc_state_reg = READ_HEADER OR |
s_usbtmc_state_reg = INTERPRET_HEADER OR |
s_usbtmc_state_reg = INIT_COPY_PAYLOAD OR |
s_usbtmc_state_reg = DET_RX_SIZE OR |
s_usbtmc_state_reg = CHECK_TX_FIFO OR |
s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES OR |
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES OR |
s_usbtmc_state_reg = INIT_DUMMY_READ OR |
s_usbtmc_state_reg = DO_DUMMY_READ OR |
s_usbtmc_state_reg = DUMMY_NOP |
ELSE |
"10" WHEN |
s_usbtmc_state_reg = CHECK_FIFO_STATUS OR |
s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3 OR |
s_usbtmc_state_reg = MESSAGE_UPDATE OR |
s_usbtmc_state_reg = SEND_HEADER OR |
s_usbtmc_state_reg = SEND_PAYLOAD OR |
s_usbtmc_state_reg = SEND_PKT_END OR |
s_usbtmc_state_reg = CHECK_FULL_STATUS OR |
s_usbtmc_state_reg = TX_NOP |
ELSE "00"; |
s_endpoint_n_oe_next <= '0' WHEN |
s_usbtmc_state_reg = INIT_READ_HEADER OR |
s_usbtmc_state_reg = READ_HEADER OR |
s_usbtmc_state_reg = INTERPRET_HEADER OR |
s_usbtmc_state_reg = INIT_COPY_PAYLOAD OR |
s_usbtmc_state_reg = DET_RX_SIZE OR |
s_usbtmc_state_reg = CHECK_TX_FIFO OR |
s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES OR |
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES OR |
s_usbtmc_state_reg = INIT_DUMMY_READ OR |
s_usbtmc_state_reg = DO_DUMMY_READ OR |
s_usbtmc_state_reg = DUMMY_NOP |
ELSE '1'; |
s_endpoint_n_re_next <= '0' WHEN s_request_header_byte = '1' OR |
s_req_payload_byte = '1' OR |
s_usbtmc_state_reg = DO_DUMMY_READ ELSE |
'1'; |
s_ena_in_ffs <= NOT(s_fifo_clock_reg); |
s_ena_out_ffs <= s_fifo_clock_reg; |
s_ena_data_in <= (s_header_byte_request_pending OR |
s_rx_pending_pipe_reg(0)) AND s_ena_in_ffs; |
s_ep_n_tri_next <= '0' WHEN |
s_usbtmc_state_reg = CHECK_FIFO_STATUS OR |
s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3 OR |
s_usbtmc_state_reg = MESSAGE_UPDATE OR |
s_usbtmc_state_reg = SEND_HEADER OR |
s_usbtmc_state_reg = SEND_PAYLOAD OR |
s_usbtmc_state_reg = SEND_PKT_END OR |
s_usbtmc_state_reg = CHECK_FULL_STATUS OR |
s_usbtmc_state_reg = TX_NOP |
ELSE '1'; |
|
-------------------------------------------------------------------------------- |
-- Here the state machine is defined -- |
-------------------------------------------------------------------------------- |
make_state_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg , |
s_EP8_not_empty , s_header_request_done , |
s_header_error_reg , s_header_byte_valid , |
s_message_in_progress_reg , |
s_ready_to_receive_reg , s_outstanding_messages_reg , |
s_tx_fifo_empty , s_tx_pop_size , s_EP6_not_full ) |
VARIABLE v_next_state : USBTMC_STATE_TYPE; |
BEGIN |
CASE (s_usbtmc_state_reg) IS |
WHEN WAIT_HEADER => IF (s_EP8_not_empty = '1' AND |
s_ready_to_receive_reg = '1') THEN |
v_next_state := INIT_READ_HEADER; |
ELSE |
v_next_state := WAIT_HEADER; |
END IF; |
WHEN INIT_READ_HEADER => v_next_state := READ_HEADER; |
WHEN READ_HEADER => IF (s_header_request_done = '1') THEN |
v_next_state := INTERPRET_HEADER; |
ELSIF (s_EP8_not_empty = '0') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := READ_HEADER; |
END IF; |
WHEN INTERPRET_HEADER => IF (s_header_byte_valid = '1') THEN |
v_next_state := INTERPRET_HEADER; |
ELSIF (s_header_error_reg = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
CASE (s_Message_ID_reg) IS |
WHEN X"01" => v_next_state := INIT_COPY_PAYLOAD; |
WHEN X"02" => v_next_state := DET_MAX_TRASF_SIZE; |
WHEN OTHERS => v_next_state := SIGNAL_ERROR; |
END CASE; |
END IF; |
WHEN INIT_COPY_PAYLOAD => v_next_state := DET_RX_SIZE; |
WHEN DET_RX_SIZE => v_next_state := CHECK_TX_FIFO; |
WHEN CHECK_TX_FIFO => IF (s_read_fifo_full = '1') THEN |
v_next_state := CHECK_TX_FIFO; |
ELSE |
v_next_state := REQUEST_PAYLOAD_BYTES; |
END IF; |
WHEN REQUEST_PAYLOAD_BYTES => IF (s_rx_cnt_reg(9) = '1') THEN |
v_next_state := CHECK_PAYLOAD_BYTES; |
ELSE |
v_next_state := REQUEST_PAYLOAD_BYTES; |
END IF; |
WHEN CHECK_PAYLOAD_BYTES => IF (s_rx_payload_cnt_reg(32) = '1') THEN |
IF (s_transfer_size_reg(1 DOWNTO 0) = "00") THEN |
v_next_state := DUMMY_NOP; |
ELSE |
v_next_state := INIT_DUMMY_READ; |
END IF; |
ELSE |
IF (s_EP8_not_empty = '1') THEN |
v_next_state := DET_RX_SIZE; |
ELSE |
v_next_state := CHECK_PAYLOAD_BYTES; |
END IF; |
END IF; |
WHEN INIT_DUMMY_READ => v_next_state := DO_DUMMY_READ; |
WHEN DO_DUMMY_READ => IF (s_dummy_read_cnt_reg(2) = '1') THEN |
v_next_state := DUMMY_NOP; |
ELSE |
v_next_state := DO_DUMMY_READ; |
END IF; |
WHEN DET_MAX_TRASF_SIZE => IF (s_message_in_progress_reg = '1') THEN |
v_next_state := CHECK_FIFO_STATUS; |
ELSE |
v_next_state := RESET_MESSAGE_SIZE; |
END IF; |
WHEN RESET_MESSAGE_SIZE => IF (s_outstanding_messages_reg(9) = '0') THEN |
v_next_state := GET_MESSAGE_SIZE_0; |
ELSE |
v_next_state := CHECK_FIFO_STATUS; |
END IF; |
WHEN GET_MESSAGE_SIZE_0 => IF (s_tx_data_pop = '1') THEN |
v_next_state := GET_MESSAGE_SIZE_1; |
ELSE |
v_next_state := GET_MESSAGE_SIZE_0; |
END IF; |
WHEN GET_MESSAGE_SIZE_1 => IF (s_tx_data_pop = '1' OR |
s_valid_payload_byte = '1') THEN |
v_next_state := GET_MESSAGE_SIZE_2; |
ELSE |
v_next_state := GET_MESSAGE_SIZE_1; |
END IF; |
WHEN GET_MESSAGE_SIZE_2 => IF (s_tx_data_pop = '1' OR |
s_valid_payload_byte = '1') THEN |
v_next_state := GET_MESSAGE_SIZE_3; |
ELSE |
v_next_state := GET_MESSAGE_SIZE_2; |
END IF; |
WHEN GET_MESSAGE_SIZE_3 => IF (s_tx_data_pop = '1' OR |
s_valid_payload_byte = '1') THEN |
v_next_state := MESSAGE_UPDATE; |
ELSE |
v_next_state := GET_MESSAGE_SIZE_3; |
END IF; |
WHEN MESSAGE_UPDATE => v_next_state := CHECK_FIFO_STATUS; |
WHEN CHECK_FIFO_STATUS => IF (s_EP6_not_full = '0') THEN |
v_next_state := CHECK_FIFO_STATUS; |
ELSE |
v_next_state := SEND_HEADER; |
END IF; |
WHEN SEND_HEADER => IF (s_header_insert_count_reg(4) = '1') THEN |
v_next_state := SEND_PAYLOAD; |
ELSE |
v_next_state := SEND_HEADER; |
END IF; |
WHEN SEND_PAYLOAD => IF (s_require_n_pkt_end = '1' OR |
s_real_payload_size_reg(32) = '1') THEN |
v_next_state := SEND_PKT_END; |
ELSE |
v_next_state := SEND_PAYLOAD; |
END IF; |
WHEN SEND_PKT_END => v_next_state := CHECK_FULL_STATUS; |
WHEN CHECK_FULL_STATUS => IF (s_real_payload_size_reg(32) = '1') THEN |
v_next_state := TX_NOP; |
ELSIF (s_EP6_not_full = '0') THEN |
v_next_state := CHECK_FULL_STATUS; |
ELSE |
v_next_state := SEND_PAYLOAD; |
END IF; |
WHEN SIGNAL_ERROR => v_next_state := ERROR_WAIT; |
WHEN ERROR_WAIT => v_next_state := ERROR_WAIT; |
WHEN OTHERS => v_next_state := WAIT_HEADER; |
END CASE; |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_usbtmc_state_reg <= WAIT_HEADER; |
ELSE s_usbtmc_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_reg; |
|
make_ready_to_receive_reg : PROCESS( clock_48MHz , s_reset , |
s_usbtmc_state_reg , rf_pop ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1' OR |
(rf_pop = '1' AND |
s_rf_last_data_byte = '1')) THEN s_ready_to_receive_reg <= '1'; |
ELSIF (s_usbtmc_state_reg = INIT_COPY_PAYLOAD) THEN |
s_ready_to_receive_reg <= s_rx_message_in_progress_reg; |
END IF; |
END IF; |
END PROCESS make_ready_to_receive_reg; |
|
-------------------------------------------------------------------------------- |
-- Here the message sending is defined -- |
-------------------------------------------------------------------------------- |
s_tx_fifo_pop <= '1' WHEN (s_tx_fifo_data_valid_reg = '0' OR |
s_tx_data_pop = '1' OR |
s_send_payload_byte = '1') AND |
s_tx_fifo_empty = '0' ELSE '0'; |
s_valid_msg_size_byte <= s_tx_fifo_data_valid_reg AND |
s_tx_fifo_size_bit_reg; |
s_valid_payload_byte <= s_tx_fifo_data_valid_reg AND |
NOT(s_tx_fifo_size_bit_reg); |
s_tx_data_pop <= '1' WHEN s_valid_msg_size_byte = '1' AND |
(s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3) |
ELSE '0'; |
s_can_tx_complete_message <= '0' WHEN unsigned(s_message_size_reg) > |
unsigned(s_transfer_size_reg) |
ELSE '1'; |
s_require_n_pkt_end <= s_bytes_send_cnt_reg(9) WHEN FX2_hi_speed = '1' ELSE |
s_bytes_send_cnt_reg(6); |
s_send_payload_byte <= '1' WHEN s_usbtmc_state_reg = SEND_PAYLOAD AND |
s_require_n_pkt_end = '0' AND |
s_real_payload_size_reg(32) = '0' AND |
s_valid_payload_byte = '1' ELSE '0'; |
|
make_tx_fifo_regs : PROCESS( clock_48MHz , s_reset , s_tx_fifo_pop , |
s_tx_pop_data , s_tx_pop_size , s_tx_data_pop , |
s_send_payload_byte ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_tx_fifo_pop = '1') THEN |
s_tx_fifo_data_reg <= s_tx_pop_data; |
s_tx_fifo_data_valid_reg <= '1'; |
s_tx_fifo_size_bit_reg <= s_tx_pop_size; |
ELSIF (s_reset = '1' OR |
s_tx_data_pop = '1' OR |
s_send_payload_byte = '1') THEN |
s_tx_fifo_data_reg <= (OTHERS => '0'); |
s_tx_fifo_data_valid_reg <= '0'; |
s_tx_fifo_size_bit_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_tx_fifo_regs; |
|
make_message_in_progress_reg : PROCESS( clock_48MHz , s_reset ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_message_in_progress_reg <= '0'; |
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN |
s_message_in_progress_reg <= NOT(s_can_tx_complete_message); |
END IF; |
END IF; |
END PROCESS make_message_in_progress_reg; |
|
make_outstanding_messages_reg : PROCESS( clock_48MHz , s_reset ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_outstanding_messages_reg <= (OTHERS => '1'); |
ELSIF (s_usbtmc_state_reg = MESSAGE_UPDATE AND |
pending_message = '0') THEN |
s_outstanding_messages_reg <= unsigned(s_outstanding_messages_reg)-1; |
ELSIF (s_usbtmc_state_reg /= MESSAGE_UPDATE AND |
pending_message = '1') THEN |
s_outstanding_messages_reg <= unsigned(s_outstanding_messages_reg)+1; |
END IF; |
END IF; |
END PROCESS make_outstanding_messages_reg; |
|
make_message_size_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg , |
s_send_payload_byte ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR |
s_reset = '1') THEN s_message_size_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR |
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3) THEN |
IF (s_valid_payload_byte = '1') THEN |
s_message_size_reg <= X"00"&s_message_size_reg(31 DOWNTO 8); |
ELSIF (s_tx_data_pop = '1') THEN |
s_message_size_reg <= s_tx_fifo_data_reg&s_message_size_reg(31 DOWNTO 8); |
END IF; |
ELSIF (s_send_payload_byte = '1') THEN |
s_message_size_reg <= unsigned(s_message_size_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_message_size_reg; |
|
make_can_tx_complete_message_reg : PROCESS( clock_48MHz , s_reset , |
s_usbtmc_state_reg , |
s_can_tx_complete_message ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_can_tx_complete_message_reg <= '0'; |
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN |
s_can_tx_complete_message_reg <= s_can_tx_complete_message; |
END IF; |
END IF; |
END PROCESS make_can_tx_complete_message_reg; |
|
make_real_payload_size_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg , |
s_can_tx_complete_message , |
s_transfer_size_reg , |
s_send_payload_byte ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_real_payload_size_reg <= (OTHERS => '1'); |
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN |
IF (s_can_tx_complete_message = '1') THEN |
s_real_payload_size_reg <= "0"&s_message_size_reg; |
ELSE |
s_real_payload_size_reg <= "0"&s_transfer_size_reg; |
END IF; |
ELSIF ((s_header_insert_count_reg(4) = '1' AND |
s_usbtmc_state_reg = SEND_HEADER) OR |
s_send_payload_byte = '1') THEN |
s_real_payload_size_reg <= unsigned(s_real_payload_size_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_real_payload_size_reg; |
|
make_header_insert_count_reg : PROCESS( clock_48MHz , s_reset , |
s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = CHECK_FIFO_STATUS OR |
s_reset = '1') THEN s_header_insert_count_reg <= "0"&X"A"; |
ELSIF (s_usbtmc_state_reg = SEND_HEADER) THEN |
s_header_insert_count_reg <= unsigned(s_header_insert_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_header_insert_count_reg; |
|
make_bytes_send_cnt_reg : PROCESS( clock_48MHz , s_reset , |
s_usbtmc_state_reg , s_send_payload_byte ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = CHECK_FIFO_STATUS OR |
s_usbtmc_state_reg = SEND_PKT_END OR |
s_reset = '1') THEN s_bytes_send_cnt_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = SEND_HEADER OR |
s_send_payload_byte = '1') THEN |
s_bytes_send_cnt_reg <= unsigned(s_bytes_send_cnt_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_bytes_send_cnt_reg; |
|
make_fx2_data_reg : PROCESS( clock_48MHz , s_header_insert_count_reg , |
s_Message_ID_reg , s_bTag_reg , |
s_real_payload_size_reg , |
s_can_tx_complete_message_reg , |
s_tx_fifo_data_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
CASE (s_header_insert_count_reg) IS |
WHEN "01010" => s_data_out_reg <= s_Message_ID_reg; |
WHEN "01001" => s_data_out_reg <= s_bTag_reg; |
WHEN "01000" => s_data_out_reg <= NOT(s_bTag_reg); |
WHEN "00111" => s_data_out_reg <= X"00"; |
WHEN "00110" => s_data_out_reg <= s_real_payload_size_reg( 7 DOWNTO 0 ); |
WHEN "00101" => s_data_out_reg <= s_real_payload_size_reg( 15 DOWNTO 8 ); |
WHEN "00100" => s_data_out_reg <= s_real_payload_size_reg( 23 DOWNTO 16 ); |
WHEN "00011" => s_data_out_reg <= s_real_payload_size_reg( 31 DOWNTO 24 ); |
WHEN "00010" => s_data_out_reg <= "0000000"&s_can_tx_complete_message_reg; |
WHEN "00001" | |
"00000" | |
"11111" => s_data_out_reg <= X"00"; |
WHEN OTHERS => s_data_out_reg <= s_tx_fifo_data_reg; |
END CASE; |
END IF; |
END PROCESS make_fx2_data_reg; |
|
make_n_we_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg , |
s_send_payload_byte ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = SEND_HEADER OR |
s_send_payload_byte = '1') THEN |
s_ep_n_we_reg <= '0'; |
ELSE |
s_ep_n_we_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_n_we_reg; |
|
make_ep_pkt_end_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = SEND_PKT_END) THEN s_ep_pkt_end_reg <= '0'; |
ELSE s_ep_pkt_end_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_ep_pkt_end_reg; |
|
make_pip_regs : PROCESS( clock_48MHz ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
s_wf_push <= wf_push; |
s_wf_push_data <= wf_push_data; |
s_wf_push_size <= wf_push_size_bit; |
END IF; |
END PROCESS make_pip_regs; |
|
tx_fifo : fifo_2kb |
PORT MAP ( clock => clock_48MHz, |
reset => s_reset, |
-- push port |
push => s_wf_push, |
push_data => s_wf_push_data, |
push_size => s_wf_push_size, |
-- pop port |
pop => s_tx_fifo_pop, |
pop_data => s_tx_pop_data, |
pop_size => s_tx_pop_size, |
-- control port |
fifo_full => wf_fifo_full, |
fifo_empty => s_tx_fifo_empty ); |
|
-------------------------------------------------------------------------------- |
-- Here the payload copying is defined -- |
-------------------------------------------------------------------------------- |
|
s_resting_buffer_bytes <= unsigned(c_high_speed_packet_size) - |
unsigned(s_nr_of_bytes_req_cnt_reg) |
WHEN FX2_hi_speed = '1' ELSE |
unsigned(c_full_speed_packet_size) - |
unsigned(s_nr_of_bytes_req_cnt_reg); |
s_can_rx_all <= '0' WHEN s_rx_payload_cnt_reg(31 DOWNTO 10) /= |
"0000000000000000000000" OR |
unsigned(s_resting_buffer_bytes) < |
unsigned(s_rx_payload_cnt_reg(9 DOWNTO 0)) |
ELSE '1'; |
s_req_payload_byte <= '1' WHEN s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES AND |
s_rx_cnt_reg(9) = '0' ELSE '0'; |
s_rx_payload_cnt_next <= unsigned(s_rx_payload_cnt_reg) - 1; |
s_last_message_byte <= s_rx_payload_cnt_next(32) AND |
s_req_payload_byte AND |
s_eom_bit_reg; |
|
make_nr_of_bytes_req_cnt_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = WAIT_HEADER OR |
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES) THEN |
s_nr_of_bytes_req_cnt_reg <= (OTHERS => '0'); |
ELSIF (s_request_header_byte = '1' OR |
s_req_payload_byte = '1') THEN |
s_nr_of_bytes_req_cnt_reg <= unsigned(s_nr_of_bytes_req_cnt_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_nr_of_bytes_req_cnt_reg; |
|
make_rx_payload_cnt_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg, |
s_transfer_size_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_rx_payload_cnt_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = INIT_COPY_PAYLOAD) THEN |
s_rx_payload_cnt_reg <= unsigned("0"&s_transfer_size_reg) - 1; |
ELSIF (s_req_payload_byte = '1') THEN |
s_rx_payload_cnt_reg <= s_rx_payload_cnt_next; |
END IF; |
END IF; |
END PROCESS make_rx_payload_cnt_reg; |
|
make_rx_cnt_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_rx_cnt_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = DET_RX_SIZE) THEN |
IF (s_can_rx_all = '1') THEN |
s_rx_cnt_reg <= s_rx_payload_cnt_reg(9 DOWNTO 0); |
ELSE |
s_rx_cnt_reg <= unsigned(s_resting_buffer_bytes)-1; |
END IF; |
ELSIF (s_req_payload_byte = '1') THEN |
s_rx_cnt_reg <= unsigned(s_rx_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_rx_cnt_reg; |
|
make_rx_pending_regs : PROCESS( clock_96MHz , s_reset ) |
BEGIN |
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN |
IF (s_reset = '1') THEN s_rx_pending_pipe_reg <= "00"; |
s_lmb_pipe_reg <= "00"; |
ELSIF (s_ena_out_ffs = '1') THEN |
s_rx_pending_pipe_reg(0) <= s_req_payload_byte; |
s_lmb_pipe_reg(0) <= s_last_message_byte; |
ELSIF (s_ena_in_ffs = '1') THEN |
s_rx_pending_pipe_reg(1) <= s_rx_pending_pipe_reg(0); |
s_lmb_pipe_reg(1) <= s_lmb_pipe_reg(0); |
END IF; |
END IF; |
END PROCESS make_rx_pending_regs; |
|
make_dummy_read_cnt_reg : PROCESS( clock_48MHz , s_reset , |
s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_dummy_read_cnt_reg <= "000"; |
ELSIF (s_usbtmc_state_reg = INIT_DUMMY_READ) THEN |
CASE (s_transfer_size_reg( 1 DOWNTO 0 )) IS |
WHEN "01" => s_dummy_read_cnt_reg <= "001"; |
WHEN "10" => s_dummy_read_cnt_reg <= "000"; |
WHEN OTHERS => s_dummy_read_cnt_reg <= "111"; |
END CASE; |
ELSIF (s_usbtmc_state_reg = DO_DUMMY_READ) THEN |
s_dummy_read_cnt_reg <= unsigned(s_dummy_read_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_dummy_read_cnt_reg; |
|
read_fifo : fifo_2kb_ef |
PORT MAP ( clock => clock_48MHz, |
reset => s_reset, |
high_speed => FX2_hi_speed, |
-- push port |
push => s_rx_pending_pipe_reg(1), |
push_data => s_data_in, |
push_last => s_lmb_pipe_reg(1), |
-- pop port |
pop => rf_pop, |
pop_data => rf_pop_data, |
pop_last => s_rf_last_data_byte, |
-- control port |
fifo_full => OPEN, |
early_full => s_read_fifo_full, |
fifo_empty => rf_fifo_empty ); |
|
-------------------------------------------------------------------------------- |
-- Here the header read is defined -- |
-------------------------------------------------------------------------------- |
s_header_request_done <= '1' WHEN s_header_byte_request_id = X"B" ELSE '0'; |
s_request_header_byte <= '1' WHEN s_usbtmc_state_reg = READ_HEADER ELSE '0'; |
s_header_error_next <= '0' WHEN s_usbtmc_state_reg = INIT_READ_HEADER OR |
s_reset = '1' |
ELSE |
'1' WHEN s_known_Message_ID = '0' OR |
s_bTag_error = '1' OR |
s_reserved_3_error = '1' OR |
(s_zero_payload_size_reg = '1' AND |
s_header_byte_valid_id = X"8" AND |
s_header_byte_valid = '1') |
ELSE s_header_error_reg; |
s_known_Message_ID <= '1' WHEN s_Message_ID_reg = X"01" OR |
s_Message_ID_reg = X"02" OR |
s_Message_ID_reg = X"7E" OR |
s_Message_ID_reg = X"7F" ELSE '0'; |
s_bTag_inverse <= NOT(s_bTag_reg); |
s_bTag_error <= '1' WHEN s_bTag_inverse /= s_data_in AND |
s_header_byte_valid = '1' AND |
s_header_byte_valid_id = X"2" ELSE '0'; |
s_data_in_is_zero <= '1' WHEN s_data_in = X"00" ELSE '0'; |
s_reserved_3_error <= '1' WHEN s_data_in_is_zero = '0' AND |
s_header_byte_valid = '1' AND |
(s_header_byte_valid_id = X"3" OR |
s_header_byte_valid_id = X"A" OR |
s_header_byte_valid_id = X"B") ELSE '0'; |
|
|
make_header_byte_request_id : PROCESS( s_reset , clock_48MHz , |
s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_READ_HEADER OR |
s_reset = '1') THEN |
s_header_byte_request_id <= X"0"; |
ELSIF (s_usbtmc_state_reg = READ_HEADER) THEN |
s_header_byte_request_id <= unsigned(s_header_byte_request_id)+1; |
END IF; |
END IF; |
END PROCESS make_header_byte_request_id; |
|
make_pending_regs : PROCESS( s_reset , clock_96MHz , s_ena_out_ffs , |
s_request_header_byte , s_header_byte_request_id ) |
BEGIN |
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN |
IF (s_reset = '1') THEN s_header_byte_request_pending <= '0'; |
s_header_byte_pending_id <= X"0"; |
ELSIF (s_ena_out_ffs = '1') THEN |
s_header_byte_request_pending <= s_request_header_byte; |
s_header_byte_pending_id <= s_header_byte_request_id; |
END IF; |
END IF; |
END PROCESS make_pending_regs; |
|
make_valid_regs : PROCESS( s_reset , clock_96MHz , s_ena_in_ffs , |
s_header_byte_request_pending , |
s_header_byte_pending_id ) |
BEGIN |
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN |
IF (s_reset = '1') THEN s_header_byte_valid <= '0'; |
s_header_byte_valid_id <= X"0"; |
ELSIF (s_ena_in_ffs = '1') THEN |
s_header_byte_valid <= s_header_byte_request_pending; |
s_header_byte_valid_id <= s_header_byte_pending_id; |
END IF; |
END IF; |
END PROCESS make_valid_regs; |
|
make_header_error_reg : PROCESS( clock_48MHz , s_header_error_next ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
s_header_error_reg <= s_header_error_next; |
END IF; |
END PROCESS make_header_error_reg; |
|
make_message_id_reg : PROCESS( clock_48MHz , s_reset , s_data_in , |
s_header_byte_valid , s_header_byte_valid_id ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_Message_ID_reg <= X"01"; |
ELSIF (s_header_byte_valid = '1' AND |
s_header_byte_valid_id = X"0") THEN |
s_Message_ID_reg <= s_data_in; |
END IF; |
END IF; |
END PROCESS make_message_id_reg; |
|
make_btag_reg : PROCESS( clock_48MHz , s_reset , s_data_in , |
s_header_byte_valid , s_header_byte_valid_id ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_bTag_reg <= X"00"; |
ELSIF (s_header_byte_valid = '1' AND |
s_header_byte_valid_id = X"1") THEN |
s_bTag_reg <= s_data_in; |
END IF; |
END IF; |
END PROCESS make_btag_reg; |
|
make_transfer_size_reg : PROCESS( clock_48MHz , s_reset , s_data_in , |
s_header_byte_valid , s_header_byte_valid_id ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_transfer_size_reg <= (OTHERS => '0'); |
ELSIF (s_header_byte_valid = '1') THEN |
CASE (s_header_byte_valid_id) IS |
WHEN X"4" => s_transfer_size_reg( 7 DOWNTO 0 ) <= s_data_in; |
WHEN X"5" => s_transfer_size_reg( 15 DOWNTO 8 ) <= s_data_in; |
WHEN X"6" => s_transfer_size_reg( 23 DOWNTO 16 ) <= s_data_in; |
WHEN X"7" => s_transfer_size_reg( 31 DOWNTO 24 ) <= s_data_in; |
WHEN OTHERS => NULL; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_transfer_size_reg; |
|
make_zero_payload_size_reg : PROCESS( clock_48MHz , s_reset , |
s_data_in_is_zero , s_header_byte_valid , |
s_header_byte_valid_id , |
s_usbtmc_state_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_READ_HEADER OR |
s_reset = '1') THEN s_zero_payload_size_reg <= '1'; |
ELSIF ((s_header_byte_valid_id = X"4" OR |
s_header_byte_valid_id = X"5" OR |
s_header_byte_valid_id = X"6" OR |
s_header_byte_valid_id = X"7") AND |
s_data_in_is_zero = '0') THEN s_zero_payload_size_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_zero_payload_size_reg; |
|
make_eom_bit_reg : PROCESS( clock_48MHz , s_reset , s_header_byte_valid , |
s_header_byte_valid_id , s_data_in ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_eom_bit_reg <= '1'; |
s_rx_message_in_progress_reg <= '0'; |
ELSIF (s_header_byte_valid = '1' AND |
s_header_byte_valid_id = X"8") THEN |
IF (s_Message_ID_reg = X"01") THEN |
s_rx_message_in_progress_reg <= NOT(s_data_in(0)); |
s_eom_bit_reg <= s_data_in(0); |
ELSE |
s_rx_message_in_progress_reg <= '0'; |
s_eom_bit_reg <= '1'; |
END IF; |
END IF; |
END IF; |
END PROCESS make_eom_bit_reg; |
|
-------------------------------------------------------------------------------- |
-- Define the synchronized clock signal for this module -- |
-------------------------------------------------------------------------------- |
s_reset <= s_reset_count_reg(2); |
|
make_reset_count_reg : PROCESS( cpu_reset , clock_48MHz , FX2_n_ready , |
s_reset_count_reg , s_reset ) |
BEGIN |
IF (cpu_reset = '1' OR |
FX2_n_ready = '1') THEN s_reset_count_reg <= (OTHERS => '1'); |
ELSIF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN |
s_reset_count_reg <= unsigned(s_reset_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_reset_count_reg; |
|
-------------------------------------------------------------------------------- |
-- Define the clock of the FX2 FIFOs -- |
-------------------------------------------------------------------------------- |
make_fifo_clock_reg : PROCESS( clock_96MHz , cpu_reset , s_fifo_clock_reg ) |
BEGIN |
IF (cpu_reset = '1') THEN s_fifo_clock_reg <= '1'; |
ELSIF (clock_96MHz'event AND (clock_96MHz = '1')) THEN |
s_fifo_clock_reg <= NOT(s_fifo_clock_reg); |
END IF; |
END PROCESS make_fifo_clock_reg; |
|
-------------------------------------------------------------------------------- |
--- Define the fx2 data reporting --- |
-------------------------------------------------------------------------------- |
make_fx2_data_nibble : PROCESS( clock_48MHz , s_fx2_data_select , |
status_nibble , s_bTag_reg ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
CASE (s_fx2_data_select) IS |
WHEN X"C" => s_fx2_data_nibble <= s_bTag_reg( 3 DOWNTO 0 ); |
WHEN X"D" => s_fx2_data_nibble <= s_bTag_reg( 7 DOWNTO 4 ); |
WHEN X"F" => s_fx2_data_nibble <= status_nibble; |
WHEN OTHERS => s_fx2_data_nibble <= X"F"; |
END CASE; |
END IF; |
END PROCESS make_fx2_data_nibble; |
|
make_ind_pipe_reg : PROCESS( clock_48MHz , s_reset , s_fx2_data_select ) |
BEGIN |
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN |
IF (s_reset = '1') THEN s_ind_pipe_reg <= "00"; |
ELSE |
s_ind_pipe_reg(1) <= s_ind_pipe_reg(0); |
IF (s_fx2_data_select = X"E") THEN |
s_ind_pipe_reg(0) <= '1'; |
ELSE |
s_ind_pipe_reg(0) <= '0'; |
END IF; |
END IF; |
END IF; |
END PROCESS make_ind_pipe_reg; |
|
-------------------------------------------------------------------------------- |
-- Define the IOB flipflops and tri-state buffers used -- |
-------------------------------------------------------------------------------- |
gen_data_nibble : FOR n IN 3 DOWNTO 0 GENERATE |
in_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_fx2_data_select(n), |
C => clock_48MHz, |
D => data_select(n) ); |
out_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => data_nibble(n), |
C => clock_48MHz, |
D => s_fx2_data_nibble(n) ); |
END GENERATE gen_data_nibble; |
|
IFCLK_FF : FD_1 |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_IFCLOCK, |
C => clock_96MHz, |
D => s_fifo_clock_reg ); |
EP8_flag_FF : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => s_EP8_not_empty, |
CE => s_ena_in_ffs, |
C => clock_96MHz, |
D => EP8_n_empty ); |
EP6_flag_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP( Q => s_EP6_not_full, |
CE => s_ena_in_ffs, |
C => clock_96MHz, |
D => EP6_n_full ); |
EP_n_WE_FF : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_n_WE, |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_ep_n_we_reg ); |
EP_n_PKTEND_FF : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_n_PKTEND, |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_ep_pkt_end_reg ); |
make_addr_ff : FOR n IN 1 DOWNTO 0 GENERATE |
one_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_address(n), |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_endpoint_addr_next(n) ); |
END GENERATE make_addr_ff; |
n_oe_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_n_OE, |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_endpoint_n_oe_next ); |
n_re_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_n_RE, |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_endpoint_n_re_next ); |
make_data_in_ff : FOR n IN 7 DOWNTO 0 GENERATE |
one_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => s_data_in(n), |
CE => s_ena_data_in, |
C => clock_96MHz, |
D => EP_data_in(n) ); |
out_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => EP_data_out(n), |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_data_out_reg(n) ); |
tri_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP( Q => EP_n_tri_out(n), |
CE => s_ena_out_ffs, |
C => clock_96MHz, |
D => s_ep_n_tri_next ); |
END GENERATE make_data_in_ff; |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fx2_fifo_if/usbtmc-entity.vhdl
0,0 → 1,85
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY USBTMC IS |
PORT ( clock_96MHz : IN std_logic; |
clock_48MHz : IN std_logic; |
cpu_reset : IN std_logic; |
sync_reset_out : OUT std_logic; |
|
-- FX2 control interface |
FX2_n_ready : IN std_logic; |
FX2_hi_speed : IN std_logic; |
|
-- SCPI command interpretor interface |
pending_message : IN std_logic; |
transfer_in_prog : OUT std_logic; |
|
-- read fifo interface |
rf_pop : IN std_logic; |
rf_pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
rf_last_data_byte: OUT std_logic; |
rf_fifo_empty : OUT std_logic; |
|
-- Write fifo interface |
wf_push : IN std_logic; |
wf_push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
wf_push_size_bit : IN std_logic; |
wf_fifo_full : OUT std_logic; |
wf_fifo_empty : OUT std_logic; |
|
-- status interface |
status_nibble : IN std_logic_vector( 3 DOWNTO 0 ); |
indicator_pulse : OUT std_logic; |
|
-- FX2 port D interface |
data_nibble : OUT std_logic_vector( 3 DOWNTO 0 ); |
data_select : IN std_logic_vector( 3 DOWNTO 0 ); |
|
-- FX2 FIFO interface |
EP8_n_empty : IN std_logic; |
EP6_n_full : IN std_logic; |
EP_data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
EP_address : OUT std_logic_vector( 1 DOWNTO 0 ); |
EP_IFCLOCK : OUT std_logic; |
EP_n_PKTEND : OUT std_logic; |
EP_n_OE : OUT std_logic; |
EP_n_RE : OUT std_logic; |
EP_n_WE : OUT std_logic; |
EP_data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
EP_n_tri_out : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END USBTMC; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/user_fifo/user_fifo-entity.vhdl
0,0 → 1,82
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY user_fifo IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- Here the bus signals are defined |
n_bus_reset : IN std_logic; |
n_start_transmission : IN std_logic; |
n_end_transmission_in : IN std_logic; |
n_end_transmission_out : OUT std_logic; |
n_data_valid_in : IN std_logic_vector( 1 DOWNTO 0 ); |
n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
data_in : IN std_logic_vector(15 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
read_n_write : IN std_logic; |
burst_size : IN std_logic_vector( 8 DOWNTO 0 ); |
bus_address : IN std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : OUT std_logic; |
n_bus_error : OUT std_logic; |
|
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
transparent_mode : IN std_logic; |
command_done : OUT std_logic; |
command_error : OUT std_logic; |
message_available : OUT std_logic; |
|
-- Here the tx_fifo is defined |
push : OUT std_logic; |
push_size : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
fifo_full : IN std_logic; |
|
-- Here the rx_fifo is defined |
pop : OUT std_logic; |
pop_last : IN std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_empty : IN std_logic; |
|
-- Here the big fpga interface is defined |
data_request_irq : OUT std_logic; |
data_available_irq : OUT std_logic; |
error_irq : OUT std_logic); |
END user_fifo; |
|
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/user_fifo/user_fifo-behavior.vhdl
0,0 → 1,481
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
--memory map: |
-- 0x00 -> TX-fifo write data (WO) |
-- 0x01 -> TX-fifo write message size (WO) |
-- 0x02 -> Nr. of bytes in TX-fifo (RO) |
-- 0x03 -> Max. size in bytes of TX-fifo (RO) |
-- 0x04 -> Nr. of shorts in TX-fifo (RO) |
-- 0x05 -> Max. size in shorts of TX-fifo (RO) |
-- 0x06 -> Nr. of words in TX-fifo (RO) |
-- 0x07 -> Max. size in words of TX-fifo (RO) |
-- 0x08 -> RX-fifo read data (RO) |
-- 0x09 -> RX-fifo read data (RO) |
-- 0x0A -> Nr. of bytes in RX-fifo (RO) |
-- 0x0B -> Max. size in bytes of RX-fifo (RO) |
-- 0x0C -> Nr. of shorts in RX-fifo (RO) |
-- 0x0D -> Max. size in shorts of RX-fifo (RO) |
-- 0x0E -> Nr. of words in RX-fifo (RO) |
-- 0x0F -> Max. size in words of RX-fifo (RO) |
|
ARCHITECTURE no_target_specific OF user_fifo IS |
|
COMPONENT fifo_4kb_16w_8r |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 15 DOWNTO 0 ); |
push_size : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic; |
byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) ); |
END COMPONENT; |
|
COMPONENT fifo_4kb_8w_16r |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_last : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 15 DOWNTO 0 ); |
pop_last : OUT std_logic_vector( 1 DOWNTO 0 ); |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic; |
byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) ); |
END COMPONENT; |
|
TYPE STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,SIGNAL_REQUEST, |
GET_SIZE_0,GET_SIZE_1,GET_SIZE_2,GET_SIZE_3, |
INIT_COPY,FLUSH_TX,COPY_TX_DATA,SIGNAL_MESSAGE, |
COPY_RX_DATA,INSERT_DUMMY,SIGNAL_AVAILABLE); |
|
SIGNAL s_tx_fifo_byte_count_value : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_n_bus_error_next : std_logic; |
SIGNAL s_tx_fifo_full : std_logic; |
SIGNAL s_tx_fifo_empty : std_logic; |
SIGNAL s_n_bus_error_reg : std_logic; |
SIGNAL s_burst_cnt_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_burst_cnt_next : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_n_end_reg : std_logic; |
SIGNAL s_is_my_write_burst_reg : std_logic; |
SIGNAL s_do_push : std_logic; |
|
SIGNAL s_fifo_state_reg : STATE_TYPE; |
SIGNAL s_tx_pop : std_logic; |
SIGNAL s_tx_pop_size : std_logic; |
SIGNAL s_tx_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_tx_payload_cnt_reg : std_logic_vector( 32 DOWNTO 0 ); |
|
SIGNAL s_rx_fifo_byte_count_value : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_rx_push : std_logic; |
SIGNAL s_rx_fifo_full : std_logic; |
SIGNAL s_rx_byte_cnt_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pop_last : std_logic; |
SIGNAL s_dummy_data_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_rx_fifo_empty : std_logic; |
SIGNAL s_rx_fifo_pop : std_logic; |
SIGNAL s_rx_fifo_data : std_logic_vector( 15 DOWNTO 0 ); |
SIGNAL s_rx_fifo_last : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_reset : std_logic; |
|
BEGIN |
s_reset <= reset OR NOT(n_bus_reset); |
|
-------------------------------------------------------------------------------- |
--- Here the signalling is defined --- |
-------------------------------------------------------------------------------- |
make_error_irq : PROCESS( clock , s_do_push , s_tx_fifo_full , |
s_rx_fifo_empty , s_rx_fifo_pop ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF ((s_do_push = '1' AND |
s_tx_fifo_full = '1') OR |
(s_rx_fifo_empty = '1' AND |
s_rx_fifo_pop = '1') OR |
(s_fifo_state_reg = FLUSH_TX)) THEN error_irq <= '1'; |
ELSE error_irq <= '0'; |
END IF; |
END IF; |
END PROCESS make_error_irq; |
|
make_data_req_irg : PROCESS( clock , reset , s_fifo_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '0' AND |
s_fifo_state_reg = SIGNAL_REQUEST) THEN data_request_irq <= '1'; |
ELSE data_request_irq <= '0'; |
END IF; |
END IF; |
END PROCESS make_data_req_irg; |
|
make_data_available_irq : PROCESS( clock , reset , s_fifo_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '0' AND |
s_fifo_state_reg = SIGNAL_AVAILABLE) THEN data_available_irq <= '1'; |
ELSE data_available_irq <= '0'; |
END IF; |
END IF; |
END PROCESS make_data_available_irq; |
|
-------------------------------------------------------------------------------- |
--- Here the bus handling is defined --- |
-------------------------------------------------------------------------------- |
n_start_send <= '0' WHEN bus_address( 5 DOWNTO 4 ) = "00" AND |
n_start_transmission = '0' AND |
read_n_write = '0' AND |
s_n_bus_error_next = '1' ELSE '1'; |
n_bus_error <= s_n_bus_error_reg; |
n_end_transmission_out <= '0' WHEN s_n_bus_error_reg = '0' OR |
s_n_end_reg = '0' ELSE '1'; |
make_data_valid : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '0' AND |
n_bus_reset = '1' AND |
s_burst_cnt_reg(9) = '0') THEN |
IF (s_rx_fifo_pop = '1' AND |
s_rx_fifo_last /= "00") THEN n_data_valid_out <= "01"; |
ELSE n_data_valid_out <= "00"; |
END IF; |
ELSE n_data_valid_out <= "11"; |
END IF; |
END IF; |
END PROCESS make_data_valid; |
|
s_n_bus_error_next <= '0' WHEN bus_address( 5 DOWNTO 4) = "00" AND |
n_start_transmission = '0' AND |
((bus_address(3 DOWNTO 1) = "000" AND |
(read_n_write = '1' OR |
s_tx_fifo_full = '1')) OR |
(bus_address(3 DOWNTO 1) /= "000" AND |
read_n_write = '0')) ELSE '1'; |
s_burst_cnt_next <= unsigned(s_burst_cnt_reg) - 1; |
|
make_data_out : PROCESS( clock , bus_address , s_tx_fifo_byte_count_value ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (bus_address(5 DOWNTO 4) = "00") THEN |
CASE (bus_address( 3 DOWNTO 0 )) IS |
WHEN X"2" => data_out <= "000"&s_tx_fifo_byte_count_value; |
WHEN X"3" => data_out <= X"1000"; |
WHEN X"4" => data_out <= X"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 1); |
WHEN X"5" => data_out <= X"0800"; |
WHEN X"6" => data_out <= X"0"&"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 2); |
WHEN X"7" => data_out <= X"0400"; |
WHEN X"8" | |
X"9" => data_out <= s_rx_fifo_data; |
WHEN X"A" => data_out <= "000"&s_rx_fifo_byte_count_value; |
WHEN X"B" => data_out <= X"1000"; |
WHEN X"C" => data_out <= X"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 1 ); |
WHEN X"D" => data_out <= X"0800"; |
WHEN X"E" => data_out <= X"0"&"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 2 ); |
WHEN X"F" => data_out <= X"0400"; |
WHEN OTHERS => data_out <= X"0000"; |
END CASE; |
ELSE |
data_out <= X"0000"; |
END IF; |
END IF; |
END PROCESS make_data_out; |
|
make_n_bus_error_reg : PROCESS( clock , s_n_bus_error_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
s_n_bus_error_reg <= s_n_bus_error_next; |
END IF; |
END PROCESS make_n_bus_error_reg; |
|
make_n_end_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg , |
s_burst_cnt_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '0' AND |
n_bus_reset = '1' AND |
s_burst_cnt_reg(9) = '0' AND |
s_burst_cnt_next(9) = '1') THEN s_n_end_reg <= '0'; |
ELSE s_n_end_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_n_end_reg; |
|
make_burst_cnt_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (n_bus_reset = '0' OR |
reset = '1') THEN s_burst_cnt_reg <= (OTHERS => '1'); |
ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND |
n_start_transmission = '0' AND |
read_n_write = '1' AND |
s_n_bus_error_next = '1') THEN |
s_burst_cnt_reg <= "0"&burst_size; |
ELSIF (s_burst_cnt_reg(9) = '0') THEN |
s_burst_cnt_reg <= s_burst_cnt_next; |
END IF; |
END IF; |
END PROCESS make_burst_cnt_reg; |
|
make_is_my_write_burst_reg : PROCESS( clock , reset , n_bus_reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0' OR |
n_end_transmission_in = '0') THEN s_is_my_write_burst_reg <= '0'; |
ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND |
n_start_transmission = '0' AND |
read_n_write = '0' AND |
s_n_bus_error_next = '1') THEN s_is_my_write_burst_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_is_my_write_burst_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the usbtmc interface is defined --- |
-------------------------------------------------------------------------------- |
command_done <= '1' WHEN s_fifo_state_reg = SIGNAL_DONE OR |
s_fifo_state_reg = SIGNAL_ERROR ELSE '0'; |
command_error <= '1' WHEN s_fifo_state_reg = SIGNAL_ERROR ELSE '0'; |
message_available <= '1' WHEN s_fifo_state_reg = SIGNAL_MESSAGE ELSE '0'; |
|
make_state_machine : PROCESS( clock , reset , s_fifo_state_reg ) |
VARIABLE v_next_state : STATE_TYPE; |
BEGIN |
CASE (s_fifo_state_reg) IS |
WHEN IDLE => IF (start_command = '1' AND |
command_id = "0011100") THEN |
v_next_state := SIGNAL_REQUEST; |
ELSIF ((start_command = '1' AND |
command_id = "0011011") OR |
(transparent_mode = '1' AND |
pop_empty = '0')) THEN |
v_next_state := SIGNAL_AVAILABLE; |
ELSIF (transparent_mode = '1' AND |
s_tx_fifo_empty = '0') THEN |
v_next_state := SIGNAL_MESSAGE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN SIGNAL_REQUEST | |
SIGNAL_MESSAGE => v_next_state := GET_SIZE_0; |
WHEN GET_SIZE_0 => IF (s_tx_fifo_empty = '0') THEN |
IF (s_tx_pop_size = '0') THEN |
v_next_state := FLUSH_TX; |
ELSE |
v_next_state := GET_SIZE_1; |
END IF; |
ELSE |
v_next_state := GET_SIZE_0; |
END IF; |
WHEN GET_SIZE_1 => IF (s_tx_fifo_empty = '0') THEN |
v_next_state := GET_SIZE_2; |
ELSE |
v_next_state := GET_SIZE_1; |
END IF; |
WHEN GET_SIZE_2 => IF (s_tx_fifo_empty = '0') THEN |
v_next_state := GET_SIZE_3; |
ELSE |
v_next_state := GET_SIZE_2; |
END IF; |
WHEN GET_SIZE_3 => IF (s_tx_fifo_empty = '0') THEN |
v_next_state := INIT_COPY; |
ELSE |
v_next_state := GET_SIZE_3; |
END IF; |
WHEN INIT_COPY => v_next_state := COPY_TX_DATA; |
WHEN COPY_TX_DATA => IF (s_tx_payload_cnt_reg(32) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := COPY_TX_DATA; |
END IF; |
WHEN FLUSH_TX => IF (s_tx_fifo_empty = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := FLUSH_TX; |
END IF; |
WHEN SIGNAL_AVAILABLE => v_next_state := COPY_RX_DATA; |
WHEN COPY_RX_DATA => IF (s_rx_push = '1' AND |
pop_last = '1') THEN |
v_next_state := INSERT_DUMMY; |
ELSE |
v_next_state := COPY_RX_DATA; |
END IF; |
WHEN INSERT_DUMMY => IF (s_rx_byte_cnt_reg = "00") THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := INSERT_DUMMY; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_fifo_state_reg <= IDLE; |
ELSE s_fifo_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
make_tx_payload_cnt_reg : PROCESS( clock , reset , s_tx_payload_cnt_reg ) |
VARIABLE v_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_tx_payload_cnt_reg <= (OTHERS => '1'); |
ELSIF (s_tx_fifo_empty = '0' AND |
(s_fifo_state_reg = GET_SIZE_0 OR |
s_fifo_state_reg = GET_SIZE_1 OR |
s_fifo_state_reg = GET_SIZE_2 OR |
s_fifo_state_reg = GET_SIZE_3)) THEN |
IF (s_tx_pop = '1') THEN v_pop_data := s_tx_pop_data; |
ELSE v_pop_data := X"00"; |
END IF; |
s_tx_payload_cnt_reg(32) <= '0'; |
s_tx_payload_cnt_reg(31 DOWNTO 24) <= v_pop_data; |
s_tx_payload_cnt_reg(23 DOWNTO 0) <= s_tx_payload_cnt_reg(31 DOWNTO 8 ); |
ELSIF (s_tx_pop = '1' OR |
s_fifo_state_reg = INIT_COPY) THEN |
s_tx_payload_cnt_reg <= unsigned(s_tx_payload_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_tx_payload_cnt_reg; |
|
make_rx_byte_cnt_reg : PROCESS( clock , reset , s_fifo_state_reg , s_rx_push) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_fifo_state_reg = IDLE) THEN s_rx_byte_cnt_reg <= "00"; |
ELSIF (s_rx_push = '1') THEN |
s_rx_byte_cnt_reg <= unsigned(s_rx_byte_cnt_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_rx_byte_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the tx-fifo is defined --- |
-------------------------------------------------------------------------------- |
s_do_push <= '1' WHEN s_is_my_write_burst_reg = '1' AND |
n_data_valid_in = "00" ELSE '0'; |
s_tx_pop <= '1' WHEN s_tx_fifo_empty = '0' AND |
(s_fifo_state_reg = FLUSH_TX OR |
(s_tx_pop_size = '1' AND |
(s_fifo_state_reg = GET_SIZE_0 OR |
s_fifo_state_reg = GET_SIZE_1 OR |
s_fifo_state_reg = GET_SIZE_2 OR |
s_fifo_state_reg = GET_SIZE_3)) OR |
(s_fifo_state_reg = COPY_TX_DATA AND |
s_tx_payload_cnt_reg(32) = '0' AND |
fifo_full = '0')) ELSE '0'; |
s_rx_push <= '1' WHEN (s_fifo_state_reg = COPY_RX_DATA AND |
s_rx_fifo_full = '0' AND |
pop_empty = '0') OR |
(s_fifo_state_reg = INSERT_DUMMY AND |
s_rx_byte_cnt_reg /= "00") ELSE '0'; |
pop <= '1' WHEN s_fifo_state_reg = COPY_RX_DATA AND |
s_rx_push = '1' ELSE '0'; |
s_pop_data <= s_dummy_data_reg WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_data; |
s_pop_last <= '1' WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_last; |
s_rx_fifo_pop <= '1' WHEN s_burst_cnt_reg(9) = '0' AND |
(bus_address( 3 DOWNTO 0 ) = X"8" OR |
bus_address( 3 DOWNTO 0 ) = X"9") ELSE '0'; |
|
make_scpi_fifo_if : PROCESS( clock , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_tx_pop = '0') THEN push <= '0'; |
push_size <= '0'; |
push_data <= (OTHERS => '0'); |
ELSE |
IF (s_fifo_state_reg = FLUSH_TX) THEN push <= '0'; |
ELSE push <= '1'; |
END IF; |
push_size <= s_tx_pop_size; |
push_data <= s_tx_pop_data; |
END IF; |
END IF; |
END PROCESS make_scpi_fifo_if; |
|
make_dummy_data_reg : PROCESS( clock , reset , pop_data , pop_last , |
s_rx_push ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_dummy_data_reg <= X"00"; |
ELSIF (s_rx_push = '1' AND |
pop_last = '1') THEN s_dummy_data_reg <= NOT(pop_data); |
END IF; |
END IF; |
END PROCESS make_dummy_data_reg; |
|
tx_fifo : fifo_4kb_16w_8r |
PORT MAP ( clock => clock, |
reset => s_reset, |
-- push port |
push => s_do_push, |
push_data => data_in, |
push_size => bus_address(0), |
-- pop port |
pop => s_tx_pop, |
pop_data => s_tx_pop_data, |
pop_size => s_tx_pop_size, |
-- control port |
fifo_full => s_tx_fifo_full, |
fifo_empty => s_tx_fifo_empty, |
byte_cnt => s_tx_fifo_byte_count_value ); |
|
rx_fifo : fifo_4kb_8w_16r |
PORT MAP ( clock => clock, |
reset => s_reset, |
-- push port |
push => s_rx_push, |
push_data => s_pop_data, |
push_last => s_pop_last, |
-- pop port |
pop => s_rx_fifo_pop, |
pop_data => s_rx_fifo_data, |
pop_last => s_rx_fifo_last, |
-- control port |
fifo_full => s_rx_fifo_full, |
fifo_empty => s_rx_fifo_empty, |
byte_cnt => s_rx_fifo_byte_count_value ); |
|
|
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/clockgen/clocks-behavior-xilinx.vhdl
0,0 → 1,362
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF clocks IS |
|
COMPONENT DCM |
generic |
( |
CLKDV_DIVIDE : real := 2.0; |
CLKFX_DIVIDE : integer := 1; |
CLKFX_MULTIPLY : integer := 4; |
CLKIN_DIVIDE_BY_2 : boolean := false; |
CLKIN_PERIOD : real := 10.0; |
CLKOUT_PHASE_SHIFT : string := "NONE"; |
CLK_FEEDBACK : string := "1X"; |
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; |
DFS_FREQUENCY_MODE : string := "LOW"; |
DLL_FREQUENCY_MODE : string := "LOW"; |
DSS_MODE : string := "NONE"; |
DUTY_CYCLE_CORRECTION : boolean := true; |
FACTORY_JF : bit_vector := X"C080"; |
PHASE_SHIFT : integer := 0; |
STARTUP_WAIT : boolean := false --non-simulatable |
); |
port |
( |
CLK0 : out std_ulogic := '0'; |
CLK180 : out std_ulogic := '0'; |
CLK270 : out std_ulogic := '0'; |
CLK2X : out std_ulogic := '0'; |
CLK2X180 : out std_ulogic := '0'; |
CLK90 : out std_ulogic := '0'; |
CLKDV : out std_ulogic := '0'; |
CLKFX : out std_ulogic := '0'; |
CLKFX180 : out std_ulogic := '0'; |
LOCKED : out std_ulogic := '0'; |
PSDONE : out std_ulogic := '0'; |
STATUS : out std_logic_vector(7 downto 0) := "00000000"; |
CLKFB : in std_ulogic := '0'; |
CLKIN : in std_ulogic := '0'; |
DSSEN : in std_ulogic := '0'; |
PSCLK : in std_ulogic := '0'; |
PSEN : in std_ulogic := '0'; |
PSINCDEC : in std_ulogic := '0'; |
RST : in std_ulogic := '0' |
); |
END COMPONENT; |
|
COMPONENT BUFG |
PORT ( I : IN std_logic; |
O : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT FD |
GENERIC ( INIT : bit ); |
PORT( C : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END COMPONENT; |
|
SIGNAL s_user_clock_1_reset_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_user_clock_1_reset : std_logic; |
SIGNAL s_user_clock_1_out_ub : std_logic; |
SIGNAL s_user_clock_2_reset_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_user_clock_2_reset : std_logic; |
SIGNAL s_user_clock_2_out_ub : std_logic; |
SIGNAL s_lock_48_mul : std_logic; |
SIGNAL s_48MHz_mul : std_logic; |
SIGNAL s_mul_reset_count_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_clk_48_ubuf : std_logic; |
SIGNAL s_clk_96_ubuf : std_logic; |
SIGNAL s_clk_75_ubuf : std_logic; |
SIGNAL s_clk_48MHz : std_logic; |
SIGNAL s_clk_96MHz : std_logic; |
SIGNAL s_lock_48 : std_logic; |
SIGNAL s_reset_count_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_clock_div_reg : std_logic; |
SIGNAL s_msec_counter_reg : std_logic_vector(16 DOWNTO 0 ); |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here some outputs are defined --- |
-------------------------------------------------------------------------------- |
clk_48MHz <= s_clk_48MHz; |
clk_96MHz <= s_clk_96MHz; |
reset_out <= s_reset_count_reg(7); |
msec_tick <= s_msec_counter_reg(16); |
|
make_clock_div_reg : PROCESS( s_reset_count_reg , s_clk_96MHz ) |
BEGIN |
IF (s_reset_count_reg(7) = '1') THEN s_clock_div_reg <= '0'; |
ELSIF (s_clk_96MHz'event AND (s_clk_96MHz = '1')) THEN |
s_clock_div_reg <= NOT(s_clock_div_reg); |
END IF; |
END PROCESS make_clock_div_reg; |
|
clk48_ff : FD |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( C => s_clk_96MHz, |
D => s_clock_div_reg, |
Q => clock_48MHz_out ); |
|
make_msec_counter : PROCESS( s_clk_48MHz , s_reset_count_reg , |
s_msec_counter_reg ) |
BEGIN |
IF (s_reset_count_reg(7) = '1') THEN |
s_msec_counter_reg <= (OTHERS => '0'); |
ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN |
IF (s_msec_counter_reg(16) = '1') THEN |
s_msec_counter_reg <= "0"&X"BB7E"; |
ELSE |
s_msec_counter_reg <= unsigned(s_msec_counter_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_msec_counter; |
|
-------------------------------------------------------------------------------- |
--- Here all internal FPGA signals are generated --- |
-------------------------------------------------------------------------------- |
dcm3 : DCM |
GENERIC MAP ( CLKDV_DIVIDE => 2.0, |
CLKFX_DIVIDE => 1, |
CLKFX_MULTIPLY => 3, |
CLKIN_DIVIDE_BY_2 => false, |
CLKIN_PERIOD => 62.5, |
CLKOUT_PHASE_SHIFT => "NONE", |
CLK_FEEDBACK => "NONE", |
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", |
DFS_FREQUENCY_MODE => "LOW", |
DLL_FREQUENCY_MODE => "LOW", |
DSS_MODE => "NONE", |
DUTY_CYCLE_CORRECTION => true, |
FACTORY_JF => X"C080", |
PHASE_SHIFT => 0, |
STARTUP_WAIT => false ) |
PORT MAP ( CLK0 => OPEN, |
CLK180 => OPEN, |
CLK270 => OPEN, |
CLK2X => OPEN, |
CLK2X180 => OPEN, |
CLK90 => OPEN, |
CLKDV => OPEN, |
CLKFX => s_48MHz_mul, |
CLKFX180 => OPEN, |
LOCKED => s_lock_48_mul, |
PSDONE => OPEN, |
STATUS => OPEN, |
CLKFB => '0', |
CLKIN => clock_16MHz, |
DSSEN => '1', |
PSCLK => '0', |
PSEN => '0', |
PSINCDEC => '0', |
RST => '0'); |
make_mul_reset_counter : PROCESS( s_48MHz_mul , s_lock_48_mul ) |
BEGIN |
IF (s_lock_48_mul = '0') THEN s_mul_reset_count_reg <= (OTHERS => '1'); |
ELSIF (s_48MHz_mul'event AND (s_48MHz_mul = '1')) THEN |
IF (s_mul_reset_count_reg(7) = '1') THEN |
s_mul_reset_count_reg <= unsigned(s_mul_reset_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_mul_reset_counter; |
|
dcm4 : DCM |
GENERIC MAP ( CLKDV_DIVIDE => 2.0, |
CLKFX_DIVIDE => 16, |
CLKFX_MULTIPLY => 25, |
CLKIN_DIVIDE_BY_2 => false, |
CLKIN_PERIOD => 20.83, |
CLKOUT_PHASE_SHIFT => "NONE", |
CLK_FEEDBACK => "1X", |
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", |
DFS_FREQUENCY_MODE => "LOW", |
DLL_FREQUENCY_MODE => "LOW", |
DSS_MODE => "NONE", |
DUTY_CYCLE_CORRECTION => true, |
FACTORY_JF => X"C080", |
PHASE_SHIFT => 0, |
STARTUP_WAIT => false ) |
PORT MAP ( CLK0 => s_clk_48_ubuf, |
CLK180 => OPEN, |
CLK270 => OPEN, |
CLK2X => s_clk_96_ubuf, |
CLK2X180 => OPEN, |
CLK90 => OPEN, |
CLKDV => OPEN, |
CLKFX => s_clk_75_ubuf, |
CLKFX180 => OPEN, |
LOCKED => s_lock_48, |
PSDONE => OPEN, |
STATUS => OPEN, |
CLKFB => s_clk_48MHz, |
CLKIN => s_48MHz_mul, |
DSSEN => '1', |
PSCLK => '0', |
PSEN => '0', |
PSINCDEC => '0', |
RST => s_mul_reset_count_reg(7)); |
buf3 : BUFG |
PORT MAP ( I => s_clk_48_ubuf, |
O => s_clk_48MHz ); |
buf4 : BUFG |
PORT MAP ( I => s_clk_96_ubuf, |
O => s_clk_96MHz ); |
buf5 : BUFG |
PORT MAP ( I => s_clk_75_ubuf, |
O => clk_75MHz ); |
|
make_reset_count_reg : PROCESS( s_clk_48MHz , s_lock_48 ) |
BEGIN |
IF (s_lock_48 = '0') THEN s_reset_count_reg <= (OTHERS => '1'); |
ELSIF (s_clk_48MHz'event AND (s_clk_48MHz = '1')) THEN |
IF (s_reset_count_reg(7) = '1') THEN |
s_reset_count_reg <= unsigned(s_reset_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_reset_count_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the 25MHz is defined --- |
-------------------------------------------------------------------------------- |
clock_25MHz_out <= NOT(clock_25MHz); |
|
-------------------------------------------------------------------------------- |
--- Here the user clocks are defined --- |
-------------------------------------------------------------------------------- |
make_user_clock_1_reset_reg : PROCESS( user_clock_1 , system_n_reset ) |
BEGIN |
IF (system_n_reset = '0') THEN s_user_clock_1_reset_reg <= (OTHERS => '0'); |
ELSIF (user_clock_1'event AND (user_clock_1 = '1')) THEN |
IF (s_user_clock_1_reset_reg(7) = '0') THEN |
s_user_clock_1_reset_reg <= unsigned(s_user_clock_1_reset_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_user_clock_1_reset_reg; |
|
s_user_clock_1_reset <= NOT(s_user_clock_1_reset_reg(7)); |
|
dcm1 : DCM |
GENERIC MAP ( CLKDV_DIVIDE => 2.0, |
CLKFX_DIVIDE => 1, |
CLKFX_MULTIPLY => 3, |
CLKIN_DIVIDE_BY_2 => false, |
CLKIN_PERIOD => 10.0, |
CLKOUT_PHASE_SHIFT => "NONE", |
CLK_FEEDBACK => "1X", |
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", |
DFS_FREQUENCY_MODE => "LOW", |
DLL_FREQUENCY_MODE => "LOW", |
DSS_MODE => "NONE", |
DUTY_CYCLE_CORRECTION => true, |
FACTORY_JF => X"C080", |
PHASE_SHIFT => 0, |
STARTUP_WAIT => false ) |
PORT MAP ( CLK0 => s_user_clock_1_out_ub, |
CLK180 => OPEN, |
CLK270 => OPEN, |
CLK2X => OPEN, |
CLK2X180 => OPEN, |
CLK90 => OPEN, |
CLKDV => OPEN, |
CLKFX => OPEN, |
CLKFX180 => OPEN, |
LOCKED => user_clock_1_lock, |
PSDONE => OPEN, |
STATUS => OPEN, |
CLKFB => user_clock_1_fb, |
CLKIN => user_clock_1, |
DSSEN => '1', |
PSCLK => '0', |
PSEN => '0', |
PSINCDEC => '0', |
RST => s_user_clock_1_reset); |
buf1 : BUFG |
PORT MAP ( I => s_user_clock_1_out_ub, |
O => user_clock_1_out ); |
|
make_user_clock_2_reset_reg : PROCESS( user_clock_2 , system_n_reset ) |
BEGIN |
IF (system_n_reset = '0') THEN s_user_clock_2_reset_reg <= (OTHERS => '0'); |
ELSIF (user_clock_2'event AND (user_clock_2 = '1')) THEN |
IF (s_user_clock_2_reset_reg(7) = '0') THEN |
s_user_clock_2_reset_reg <= unsigned(s_user_clock_2_reset_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_user_clock_2_reset_reg; |
|
s_user_clock_2_reset <= NOT(s_user_clock_2_reset_reg(7)); |
|
dcm2 : DCM |
GENERIC MAP ( CLKDV_DIVIDE => 2.0, |
CLKFX_DIVIDE => 1, |
CLKFX_MULTIPLY => 3, |
CLKIN_DIVIDE_BY_2 => false, |
CLKIN_PERIOD => 10.0, |
CLKOUT_PHASE_SHIFT => "NONE", |
CLK_FEEDBACK => "1X", |
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", |
DFS_FREQUENCY_MODE => "LOW", |
DLL_FREQUENCY_MODE => "LOW", |
DSS_MODE => "NONE", |
DUTY_CYCLE_CORRECTION => true, |
FACTORY_JF => X"C080", |
PHASE_SHIFT => 0, |
STARTUP_WAIT => false ) |
PORT MAP ( CLK0 => s_user_clock_2_out_ub, |
CLK180 => OPEN, |
CLK270 => OPEN, |
CLK2X => OPEN, |
CLK2X180 => OPEN, |
CLK90 => OPEN, |
CLKDV => OPEN, |
CLKFX => OPEN, |
CLKFX180 => OPEN, |
LOCKED => user_clock_2_lock, |
PSDONE => OPEN, |
STATUS => OPEN, |
CLKFB => user_clock_2_fb, |
CLKIN => user_clock_2, |
DSSEN => '1', |
PSCLK => '0', |
PSEN => '0', |
PSINCDEC => '0', |
RST => s_user_clock_2_reset); |
buf2 : BUFG |
PORT MAP ( I => s_user_clock_2_out_ub, |
O => user_clock_2_out ); |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/clockgen/clocks-entity.vhdl
0,0 → 1,63
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY clocks IS |
PORT ( system_n_reset : IN std_logic; |
clock_25MHz : IN std_logic; |
clock_16MHz : IN std_logic; |
user_clock_1 : IN std_logic; |
user_clock_2 : IN std_logic; |
|
-- Here the compensated clocks are defined |
user_clock_1_out : OUT std_logic; |
user_clock_1_fb : IN std_logic; |
user_clock_1_lock : OUT std_logic; |
user_clock_2_out : OUT std_logic; |
user_clock_2_fb : IN std_logic; |
user_clock_2_lock : OUT std_logic; |
|
-- Here the master clocks are defined |
clock_25MHz_out : OUT std_logic; |
clock_48MHz_out : OUT std_logic; |
|
-- Here the FPGA internal clocks are defined |
clk_48MHz : OUT std_logic; |
clk_96MHz : OUT std_logic; |
clk_75MHz : OUT std_logic; |
reset_out : OUT std_logic; |
msec_tick : OUT std_logic ); |
END clocks; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_25_if/cmd_25-entity.vhdl
0,0 → 1,52
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY identify_handler IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
indicator : IN std_logic; |
done : OUT std_logic; |
flash_idle : IN std_logic; |
|
msec_tick : IN std_logic; |
leds_a_in : IN std_logic_vector( 7 DOWNTO 0 ); |
leds_k_in : IN std_logic_vector( 7 DOWNTO 0 ); |
leds_a : OUT std_logic_vector( 7 DOWNTO 0 ); |
leds_k : OUT std_logic_vector( 7 DOWNTO 0 )); |
END identify_handler; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_25_if/cmd_25-behavior.vhdl
0,0 → 1,122
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_platform_specific OF identify_handler IS |
|
SIGNAL s_real_start : std_logic; |
SIGNAL s_active_reg : std_logic; |
SIGNAL s_down_count_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_shift_tick : std_logic; |
SIGNAL s_shift_dir_reg : std_logic; |
SIGNAL s_shift_a_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_shift_k_reg : std_logic_vector( 8 DOWNTO 0 ); |
SIGNAL s_stop : std_logic; |
|
BEGIN |
-- Assign outputs |
done <= s_stop; |
leds_a <= X"80" WHEN flash_idle = '0' ELSE |
s_shift_a_reg WHEN s_active_reg = '1' ELSE leds_a_in; |
leds_k <= (OTHERS => '0') WHEN flash_idle = '0' ELSE |
s_shift_k_reg(8 DOWNTO 1) WHEN s_active_reg = '1' ELSE leds_k_in; |
|
-- Assign control signals |
s_real_start <= '1' WHEN (start = '1' AND command = "0100101") OR |
indicator = '1' ELSE '0'; |
s_shift_tick <= '1' WHEN msec_tick = '1' AND |
s_down_count_reg = "000000" ELSE '0'; |
s_stop <= '1' WHEN s_shift_tick = '1' AND |
s_shift_k_reg(1) = '0' AND |
s_shift_k_reg(0) = '1' ELSE '0'; |
|
-- make processes |
make_active_reg : PROCESS( clock , reset , s_real_start , s_stop ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_stop = '1') THEN s_active_reg <= '0'; |
ELSIF (s_real_start = '1') THEN s_active_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_active_reg; |
|
make_shift_dir_reg : PROCESS( clock , s_active_reg , s_shift_a_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_active_reg = '0') THEN s_shift_dir_reg <= '1'; |
ELSIF (s_shift_a_reg(7) = '1') THEN s_shift_dir_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_shift_dir_reg; |
|
make_shift_a_reg : PROCESS( clock , s_active_reg , s_shift_dir_reg , |
s_shift_tick ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_active_reg = '0') THEN s_shift_a_reg <= (OTHERS => '0'); |
ELSIF (s_shift_tick = '1') THEN |
IF (s_shift_dir_reg = '1') THEN |
s_shift_a_reg <= s_shift_a_reg(6 DOWNTO 0)&'1'; |
ELSE |
s_shift_a_reg <= '0'&s_shift_a_reg(7 DOWNTO 1); |
END IF; |
END IF; |
END IF; |
END PROCESS make_shift_a_reg; |
|
make_shift_k_reg : PROCESS( clock , s_active_reg , s_shift_dir_reg , |
s_shift_tick , s_shift_a_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_active_reg = '0') THEN s_shift_k_reg <= (OTHERS => '0'); |
ELSIF (s_shift_tick = '1' AND s_shift_dir_reg = '0') THEN |
s_shift_k_reg <= s_shift_a_reg(0)&s_shift_k_reg(8 DOWNTO 1); |
END IF; |
END IF; |
END PROCESS make_shift_k_reg; |
|
make_down_count_reg : PROCESS( clock , reset , s_active_reg , |
msec_tick , s_shift_tick ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_shift_tick = '1' OR |
(s_active_reg = '0' AND |
flash_idle = '1') OR |
reset = '1') THEN s_down_count_reg <= "100111"; |
ELSIF (msec_tick = '1') THEN |
s_down_count_reg <= unsigned(s_down_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_down_count_reg; |
|
END no_platform_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_09_if/cmd_09-entity.vhdl
0,0 → 1,50
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY IDN_handler IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
fifo_full : IN std_logic; |
|
done : OUT std_logic; |
|
push : OUT std_logic; |
size_bit : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END IDN_handler; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_09_if/cmd_09-behavior.vhdl
0,0 → 1,103
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_target_specific OF IDN_handler IS |
|
SIGNAL s_rom_index : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_done : std_logic; |
SIGNAL s_push : std_logic; |
SIGNAL s_start : std_logic; |
|
BEGIN |
done <= s_done; |
push <= s_push; |
size_bit <= '1' WHEN s_rom_index = "000000" ELSE '0'; |
|
s_done <= '1' WHEN s_rom_index = "011110" AND fifo_full = '0' ELSE '0'; |
s_push <= '1' WHEN s_rom_index(5) = '0' AND fifo_full = '0' ELSE '0'; |
s_start <= '1' WHEN command = "0001001" AND |
start = '1' ELSE '0'; |
|
make_rom_index : PROCESS( clock , s_start , reset , s_done , |
s_push ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR s_done = '1') THEN |
s_rom_index <= (OTHERS => '1'); |
ELSIF (s_start = '1') THEN |
s_rom_index <= (OTHERS => '0'); |
ELSIF (s_rom_index(5) = '0' AND |
s_push = '1') THEN |
s_rom_index <= unsigned(s_rom_index) + 1; |
END IF; |
END IF; |
END PROCESS make_rom_index; |
|
make_rom_data : PROCESS( s_rom_index ) |
BEGIN |
CASE (s_rom_index) IS |
WHEN "011110" => push_data <= X"0A"; |
WHEN "011101" => push_data <= X"39"; |
WHEN "011100" => push_data <= X"2E"; |
WHEN "011011" => push_data <= X"30"; |
WHEN "011010" => push_data <= X"2C"; |
WHEN "011001" => push_data <= X"30"; |
WHEN "011000" => push_data <= X"2C"; |
WHEN "010111" => push_data <= X"4D"; |
WHEN "010110" => push_data <= X"4F"; |
WHEN "010101" => push_data <= X"43"; |
WHEN "010100" => push_data <= X"34"; |
WHEN "010011" => push_data <= X"4F"; |
WHEN "010010" => push_data <= X"4B"; |
WHEN "010001" => push_data <= X"43"; |
WHEN "010000" => push_data <= X"45"; |
WHEN "001111" => push_data <= X"47"; |
WHEN "001110" => push_data <= X"2C"; |
WHEN "001101" => push_data <= X"62"; |
WHEN "001100" => push_data <= X"61"; |
WHEN "001011" => push_data <= X"4C"; |
WHEN "001010" => push_data <= X"6F"; |
WHEN "001001" => push_data <= X"72"; |
WHEN "001000" => push_data <= X"63"; |
WHEN "000111" => push_data <= X"69"; |
WHEN "000110" => push_data <= X"6D"; |
WHEN "000101" => push_data <= X"2D"; |
WHEN "000100" => push_data <= X"45"; |
WHEN "000011" => push_data <= X"43"; |
WHEN "000010" => push_data <= X"55"; |
WHEN "000001" => push_data <= X"48"; |
WHEN "000000" => push_data <= X"1E"; |
WHEN OTHERS => push_data <= X"00"; |
END CASE; |
END PROCESS make_rom_data; |
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/toplevel/xc3s200an_top-entity.vhdl
0,0 → 1,146
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY xc3s200an_top IS |
PORT ( clock_25MHz : IN std_logic; |
clock_16MHz : IN std_logic; |
|
user_clock_1_in : IN std_logic; |
user_clock_1_fb : IN std_logic; |
user_clock_2_in : IN std_logic; |
user_clock_2_fb : IN std_logic; |
|
user_clock_1_out : OUT std_logic; |
user_clock_2_out : OUT std_logic; |
clock_25MHz_out : OUT std_logic; |
clock_48MHz_out : OUT std_logic; |
|
user_clock_1_lock : OUT std_logic; |
user_clock_2_lock : OUT std_logic; |
|
jtag_ndet : IN std_logic; |
|
fx2_clk : OUT std_logic; |
|
leds_a : OUT std_logic_vector( 7 DOWNTO 0 ); |
leds_k : OUT std_logic_vector( 7 DOWNTO 0 ); |
|
flash_address : OUT std_logic_vector( 19 DOWNTO 0 ); |
flash_data : INOUT std_logic_vector( 15 DOWNTO 0 ); |
flash_n_byte : OUT std_logic; |
flash_n_ce : OUT std_logic; |
flash_n_oe : OUT std_logic; |
flash_n_we : OUT std_logic; |
flash_ready_n_busy : IN std_logic; |
|
SDA : INOUT std_logic; |
SCL : IN std_logic; |
|
-- FX2 Interface |
fx2_n_int0 : OUT std_logic; |
fx2_pa1 : IN std_logic; -- 0 when fx2 is ready |
fx2_pa3 : IN std_logic; -- 1 full_speed 0 high-speed |
fx2_flaga : IN std_logic; -- ep8 fifo n_empty flag |
fx2_flagb : IN std_logic; -- ep6 fifo n_full flag |
-- fx2_flagc : IN std_logic; -- ep6 fifo n_full flag |
|
fx2_data : INOUT std_logic_vector( 7 DOWNTO 0 ); |
fx2_fifo_addr : OUT std_logic_vector( 1 DOWNTO 0 ); |
fx2_ifclock : OUT std_logic; |
fx2_n_oe : OUT std_logic; |
fx2_n_re : OUT std_logic; |
fx2_n_we : OUT std_logic; |
fx2_n_pkt_end : OUT std_logic; |
|
fx2_data_nibble : OUT std_logic_vector( 3 DOWNTO 0 ); |
fx2_data_select : IN std_logic_vector( 3 DOWNTO 0 ); |
|
-- power sensing interface |
n_usb_power : IN std_logic; |
n_bus_power : IN std_logic; |
n_usb_charge : IN std_logic; |
|
-- Switches |
n_hex_switch : IN std_logic_vector( 3 DOWNTO 0 ); |
button1 : IN std_logic; |
button2 : IN std_logic; |
button3 : IN std_logic; |
|
-- fpga interface |
fpga_done : IN std_logic; |
fpga_busy : IN std_logic; |
fpga_n_init : IN std_logic; |
fpga_n_prog : OUT std_logic; |
fpga_rd_n_wr : OUT std_logic; |
fpga_n_cs : OUT std_logic; |
fpga_cclk : OUT std_logic; |
fpga_data : INOUT std_logic_vector( 7 DOWNTO 0 ); |
|
-- RS232 passthrough |
RxD_in : IN std_logic; |
RxD_out : OUT std_logic; |
TxD_in : IN std_logic; |
TxD_out : OUT std_logic; |
|
-- Signals for transparent mode |
scpi_disabled : OUT std_logic; |
ESB_bit : IN std_logic; |
STATUS3_bit : IN std_logic; |
|
-- reset interface |
n_reset_system : INOUT std_logic; |
|
-- bus interface |
bus_reset : IN std_logic; |
bus_n_start_transmission : IN std_logic; |
bus_n_end_transmission : INOUT std_logic; |
bus_n_data_valid : INOUT std_logic_vector( 1 DOWNTO 0 ); |
bus_data_addr_cntrl : INOUT std_logic_vector(15 DOWNTO 0 ); |
bus_n_start_send : OUT std_logic; |
bus_n_error : OUT std_logic; |
data_request_irq : OUT std_logic; |
data_available_irq : OUT std_logic; |
error_irq : OUT std_logic; |
user_n_reset : OUT std_logic; |
|
-- vga interface |
red : OUT std_logic; |
green : OUT std_logic; |
blue : OUT std_logic; |
hsync : OUT std_logic; |
vsync : OUT std_logic); |
END xc3s200an_top; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/toplevel/xc3s200an_top-behavior.vhdl
0,0 → 1,1351
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE behave OF xc3s200an_top IS |
|
COMPONENT clocks |
PORT ( system_n_reset : IN std_logic; |
clock_25MHz : IN std_logic; |
clock_16MHz : IN std_logic; |
user_clock_1 : IN std_logic; |
user_clock_2 : IN std_logic; |
-- Here the compensated clocks are defined |
user_clock_1_out : OUT std_logic; |
user_clock_1_fb : IN std_logic; |
user_clock_1_lock : OUT std_logic; |
user_clock_2_out : OUT std_logic; |
user_clock_2_fb : IN std_logic; |
user_clock_2_lock : OUT std_logic; |
-- Here the master clocks are defined |
clock_25MHz_out : OUT std_logic; |
clock_48MHz_out : OUT std_logic; |
-- Here the FPGA internal clocks are defined |
clk_48MHz : OUT std_logic; |
clk_96MHz : OUT std_logic; |
clk_75MHz : OUT std_logic; |
reset_out : OUT std_logic; |
msec_tick : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT eeprom_emu |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
button : IN std_logic; |
SDA_in : IN std_logic; |
SCL_in : IN std_logic; |
SDA_out : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT USBTMC |
PORT ( clock_96MHz : IN std_logic; |
clock_48MHz : IN std_logic; |
cpu_reset : IN std_logic; |
sync_reset_out : OUT std_logic; |
-- FX2 control interface |
FX2_n_ready : IN std_logic; |
FX2_hi_speed : IN std_logic; |
-- SCPI command interpretor interface |
pending_message : IN std_logic; |
transfer_in_prog : OUT std_logic; |
-- read fifo interface |
rf_pop : IN std_logic; |
rf_pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
rf_last_data_byte: OUT std_logic; |
rf_fifo_empty : OUT std_logic; |
-- Write fifo interface |
wf_push : IN std_logic; |
wf_push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
wf_push_size_bit : IN std_logic; |
wf_fifo_full : OUT std_logic; |
wf_fifo_empty : OUT std_logic; |
-- status interface |
status_nibble : IN std_logic_vector( 3 DOWNTO 0 ); |
indicator_pulse : OUT std_logic; |
-- FX2 port D interface |
data_nibble : OUT std_logic_vector( 3 DOWNTO 0 ); |
data_select : IN std_logic_vector( 3 DOWNTO 0 ); |
-- FX2 FIFO interface |
EP8_n_empty : IN std_logic; |
EP6_n_full : IN std_logic; |
EP_data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
EP_address : OUT std_logic_vector( 1 DOWNTO 0 ); |
EP_IFCLOCK : OUT std_logic; |
EP_n_PKTEND : OUT std_logic; |
EP_n_OE : OUT std_logic; |
EP_n_RE : OUT std_logic; |
EP_n_WE : OUT std_logic; |
EP_data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
EP_n_tri_out : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END COMPONENT; |
|
COMPONENT vga_controller |
PORT ( clock_75MHz : IN std_logic; |
reset : IN std_logic; |
vga_off : IN std_logic; |
clock : IN std_logic; |
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
command_error : OUT std_logic; |
-- Here the usbtmc fifo interface is defined |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic; |
-- Here the PUD interface is defined |
we_char : IN std_logic; |
we_ascii : IN std_logic_vector( 7 DOWNTO 0 ); |
we_addr : IN std_logic_vector( 10 DOWNTO 0 ); |
-- Here the fpga interface is defined |
cursor_pos : IN std_logic_vector( 10 DOWNTO 0 ); |
screen_offset : IN std_logic_vector( 4 DOWNTO 0 ); |
fg_color : IN std_logic_vector( 2 DOWNTO 0 ); |
bg_color : IN std_logic_vector( 2 DOWNTO 0 ); |
write_address : IN std_logic_vector( 10 DOWNTO 0 ); |
ascii_data : IN std_logic_vector( 7 DOWNTO 0 ); |
we : IN std_logic; |
vga_red : OUT std_logic; |
vga_green : OUT std_logic; |
vga_blue : OUT std_logic; |
vga_hsync : OUT std_logic; |
vga_vsync : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT SCPI_INTERFACE |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- The command interface |
transparent_mode : IN std_logic; |
start_command : OUT std_logic; |
command_id : OUT std_logic_vector( 6 DOWNTO 0 ); |
cmd_gen_respons : OUT std_logic; |
command_done : IN std_logic; |
command_error : IN std_logic; |
unknown_command : OUT std_logic; |
slave_pop : IN std_logic; |
-- USBTMC fifo interface |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_empty : IN std_logic; |
pop_last : IN std_logic); |
END COMPONENT; |
|
COMPONENT IDN_handler |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
fifo_full : IN std_logic; |
done : OUT std_logic; |
push : OUT std_logic; |
size_bit : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END COMPONENT; |
|
COMPONENT identify_handler |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
indicator : IN std_logic; |
done : OUT std_logic; |
flash_idle : IN std_logic; |
msec_tick : IN std_logic; |
leds_a_in : IN std_logic_vector( 7 DOWNTO 0 ); |
leds_k_in : IN std_logic_vector( 7 DOWNTO 0 ); |
leds_a : OUT std_logic_vector( 7 DOWNTO 0 ); |
leds_k : OUT std_logic_vector( 7 DOWNTO 0 )); |
END COMPONENT; |
|
COMPONENT fpga_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- Here the FPGA info is provided |
fpga_idle : OUT std_logic; |
fpga_revision : OUT std_logic_vector( 3 DOWNTO 0 ); |
fpga_type : OUT std_logic_vector( 2 DOWNTO 0 ); |
fpga_configured : OUT std_logic; |
fpga_crc_error : OUT std_logic; |
-- Here the bitfile fifo if is defined |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
last_byte : IN std_logic; |
fifo_full : OUT std_logic; |
-- Here the select map pins are defined |
fpga_done : IN std_logic; |
fpga_busy : IN std_logic; |
fpga_n_init : IN std_logic; |
fpga_n_prog : OUT std_logic; |
fpga_rd_n_wr : OUT std_logic; |
fpga_n_cs : OUT std_logic; |
fpga_cclk : OUT std_logic; |
fpga_data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
fpga_data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
fpga_n_tri : OUT std_logic_vector( 7 DOWNTO 0 ); |
fpga_data_in_ena : OUT std_logic; |
fpga_data_out_ena : OUT std_logic); |
END COMPONENT; |
|
COMPONENT bitfile_interpreter |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
-- Here the handshake interface is defined |
start : IN std_logic; |
write_flash : IN std_logic; |
done : OUT std_logic; |
error_detected : OUT std_logic; |
-- Here the FX2 fifo interface is defined |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
fifo_empty : IN std_logic; |
-- Here the FPGA_IF fifo interface is defined |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
last_byte : OUT std_logic; |
fifo_full : IN std_logic; |
reset_fpga_if : OUT std_logic; |
-- Here the flash write fifo interface is defined |
bitfile_size : OUT std_logic_vector(31 DOWNTO 0 ); |
we_fifo : OUT std_logic; |
we_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
we_last : OUT std_logic; |
we_fifo_full : IN std_logic; |
start_write : OUT std_logic; |
size_error : IN std_logic; |
-- Here the debug vga interface is defined |
we_char : OUT std_logic; |
ascii_data : OUT std_logic_vector( 7 DOWNTO 0 )); |
END COMPONENT; |
|
COMPONENT flash_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
-- here the control interface is defined |
start_erase : IN std_logic; |
start_read : IN std_logic; |
start_write : IN std_logic; |
done : OUT std_logic; |
flash_present : OUT std_logic; |
flash_s1_empty : OUT std_logic; |
flash_idle : OUT std_logic; |
size_error : OUT std_logic; |
flash_n_busy : OUT std_logic; |
start_config : OUT std_logic; |
-- here the push fifo interface is defined |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_last : OUT std_logic; |
fifo_full : IN std_logic; |
-- here the write fifo is defined |
bitfile_size : IN std_logic_vector( 31 DOWNTO 0 ); |
we_fifo : IN std_logic; |
we_data : IN std_logic_vector( 7 DOWNTO 0 ); |
we_last : IN std_logic; |
we_fifo_full : OUT std_logic; |
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
scpi_pop : OUT std_logic; |
scpi_pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
scpi_pop_last : IN std_logic; |
scpi_empty : IN std_logic; |
scpi_push : OUT std_logic; |
scpi_push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
scpi_push_size : OUT std_logic; |
scpi_full : IN std_logic; |
-- Here the vga interface is defined |
we_char : OUT std_logic; |
we_ascii : OUT std_logic_vector( 7 DOWNTO 0 ); |
we_addr : OUT std_logic_vector( 10 DOWNTO 0 ); |
-- define the flash interface |
flash_address : OUT std_logic_vector( 19 DOWNTO 0 ); |
flash_data_in : IN std_logic_vector( 15 DOWNTO 0 ); |
flash_data_out : OUT std_logic_vector( 15 DOWNTO 0 ); |
flash_data_oe : OUT std_logic_vector( 15 DOWNTO 0 ); |
flash_n_byte : OUT std_logic; |
flash_n_ce : OUT std_logic; |
flash_n_oe : OUT std_logic; |
flash_n_we : OUT std_logic; |
flash_ready_n_busy : IN std_logic); |
END COMPONENT; |
|
COMPONENT cmd_18_1e_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
-- Here the tx_fifo is defined |
push : OUT std_logic; |
push_size : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
fifo_full : IN std_logic; |
-- Here the fpga_if is defined |
fpga_type : IN std_logic_vector( 2 DOWNTO 0 ); |
fpga_configured : IN std_logic; |
flash_empty : IN std_logic; |
-- Here the board interface is defined |
n_usb_power : IN std_logic; |
n_bus_power : IN std_logic; |
n_usb_charge : IN std_logic); |
END COMPONENT; |
|
COMPONENT reset_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
-- Here the fpga_interface is defined |
fpga_configured: IN std_logic; |
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
-- Here the system reset is defined |
n_reset_system : OUT std_logic; |
user_n_reset : OUT std_logic); |
END COMPONENT; |
|
COMPONENT hexswitch |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
n_hex_sw : IN std_logic_vector( 3 DOWNTO 0 ); |
hex_value : OUT std_logic_vector( 3 DOWNTO 0 ); |
-- here the scpi interface is defined |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
command_error : OUT std_logic; |
done : OUT std_logic; |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic ); |
END COMPONENT; |
|
COMPONENT config_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- here the flash interface is defined |
start_config : IN std_logic; |
flash_start_read : OUT std_logic; |
flash_done : IN std_logic; |
flash_present : IN std_logic; |
flash_s1_empty : IN std_logic; |
flash_idle : IN std_logic; |
flash_push : IN std_logic; |
flash_push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
flash_push_size : IN std_logic; |
flash_push_last : IN std_logic; |
flash_fifo_full : OUT std_logic; |
-- here the flash usbtmc interface is defined |
flash_u_start_read : IN std_logic; |
flash_u_done : OUT std_logic; |
flash_u_push : OUT std_logic; |
flash_u_push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
flash_u_push_size : OUT std_logic; |
flash_u_fifo_full : IN std_logic; |
-- here the bitfile interface is defined |
bitfile_start : OUT std_logic; |
bitfile_pop : IN std_logic; |
bitfile_pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
bitfile_last : OUT std_logic; |
bitfile_fifo_empty : OUT std_logic; |
-- here the bitfile usbtmc interface is defined |
bitfile_u_start : IN std_logic; |
bitfile_u_pop : OUT std_logic; |
bitfile_u_pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
bitfile_u_last : IN std_logic; |
bitfile_u_fifo_empty : IN std_logic; |
-- here the fpga interface is defined |
fpga_idle : IN std_logic; |
fpga_type : IN std_logic_vector( 2 DOWNTO 0 ); |
-- here the power interface is defined |
n_bus_power : IN std_logic; |
-- here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_error : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT status_controller |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
fpga_configured : IN std_logic; |
-- Here the fx2 interface is defined |
status_nibble : OUT std_logic_vector( 3 DOWNTO 0 ); |
-- Here the external status if is defined |
ESB_bit : IN std_logic; |
STATUS3_bit : IN std_logic; |
-- Here the scpi interface is defined |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
cmd_error : OUT std_logic; |
command_error : IN std_logic; |
execution_error : IN std_logic; |
done : OUT std_logic; |
transparent : OUT std_logic; |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic; |
push_empty : IN std_logic ); |
END COMPONENT; |
|
COMPONENT bus_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- Here the IOB interface is defined |
bus_reset : IN std_logic; |
bus_n_start_transmission : IN std_logic; |
bus_n_end_transmission : INOUT std_logic; |
bus_n_data_valid : INOUT std_logic_vector( 1 DOWNTO 0 ); |
bus_data_addr_cntrl : INOUT std_logic_vector(15 DOWNTO 0 ); |
bus_n_start_send : OUT std_logic; |
bus_n_error : OUT std_logic; |
-- Here the FPGA internal interface is defined |
b_n_reset : OUT std_logic; |
b_n_start_transmission : OUT std_logic; |
b_n_end_transmission_out : OUT std_logic; |
b_n_end_transmission_in : IN std_logic; |
b_n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
b_n_data_valid_in : IN std_logic_vector( 1 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
data_in : IN std_logic_vector(15 DOWNTO 0 ); |
read_n_write : OUT std_logic; |
burst_size : OUT std_logic_vector( 8 DOWNTO 0 ); |
address : OUT std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : IN std_logic; |
n_bus_error : IN std_logic); |
END COMPONENT; |
|
COMPONENT vga_bus |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
-- Here the bus signals are defined |
n_bus_reset : IN std_logic; |
n_start_transmission : IN std_logic; |
n_end_transmission_in : IN std_logic; |
n_end_transmission_out : OUT std_logic; |
n_data_valid_in : IN std_logic; -- Only for low byte! |
n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
read_n_write : IN std_logic; |
burst_size : IN std_logic_vector( 8 DOWNTO 0 ); |
bus_address : IN std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : OUT std_logic; |
n_bus_error : OUT std_logic; |
-- Here the button interface is defined |
n_button_1 : IN std_logic; |
n_button_2 : IN std_logic; |
n_button_3 : IN std_logic; |
hexswitch : IN std_logic_vector( 3 DOWNTO 0 ); |
-- Here the LED interface is defined |
leds_a : OUT std_logic_vector( 7 DOWNTO 0 ); |
leds_k : OUT std_logic_vector( 7 DOWNTO 0 ); |
-- Here the VGA interface is defined |
cursor_pos : OUT std_logic_vector( 10 DOWNTO 0 ); |
screen_offset : OUT std_logic_vector( 4 DOWNTO 0 ); |
fg_color : OUT std_logic_vector( 2 DOWNTO 0 ); |
bg_color : OUT std_logic_vector( 2 DOWNTO 0 ); |
write_address : OUT std_logic_vector( 10 DOWNTO 0 ); |
ascii_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
we : OUT std_logic); |
END COMPONENT; |
|
COMPONENT user_fifo |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- Here the bus signals are defined |
n_bus_reset : IN std_logic; |
n_start_transmission : IN std_logic; |
n_end_transmission_in : IN std_logic; |
n_end_transmission_out : OUT std_logic; |
n_data_valid_in : IN std_logic_vector( 1 DOWNTO 0 ); |
n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
data_in : IN std_logic_vector(15 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
read_n_write : IN std_logic; |
burst_size : IN std_logic_vector( 8 DOWNTO 0 ); |
bus_address : IN std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : OUT std_logic; |
n_bus_error : OUT std_logic; |
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
transparent_mode : IN std_logic; |
command_done : OUT std_logic; |
command_error : OUT std_logic; |
message_available : OUT std_logic; |
-- Here the tx_fifo is defined |
push : OUT std_logic; |
push_size : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
fifo_full : IN std_logic; |
-- Here the rx_fifo is defined |
pop : OUT std_logic; |
pop_last : IN std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_empty : IN std_logic; |
-- Here the big fpga interface is defined |
data_request_irq : OUT std_logic; |
data_available_irq : OUT std_logic; |
error_irq : OUT std_logic); |
END COMPONENT; |
|
COMPONENT DFF |
PORT ( clock : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT FDE |
PORT ( Q : OUT std_logic; |
CE : IN std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FD |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
SIGNAL s_clock_75MHz : std_logic; |
SIGNAL s_clock_96MHz : std_logic; |
SIGNAL s_reset : std_logic; |
SIGNAL s_vga_red : std_logic; |
SIGNAL s_vga_green : std_logic; |
SIGNAL s_vga_blue : std_logic; |
SIGNAL s_vga_hsync : std_logic; |
SIGNAL s_vga_vsync : std_logic; |
SIGNAL s_usb_clk : std_logic; |
SIGNAL s_n_usb_clk : std_logic; |
SIGNAL s_clk_48MHz : std_logic; |
SIGNAL s_msec_tick : std_logic; |
SIGNAL s_usb_reset : std_logic; |
|
SIGNAL s_SDA : std_logic; |
SIGNAL s_SDA_pin : std_logic; |
SIGNAL s_SDA_OE : std_logic; |
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SIGNAL s_wf_push : std_logic; |
SIGNAL s_wf_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_wf_push_size_bit : std_logic; |
SIGNAL s_wf_fifo_full : std_logic; |
SIGNAL s_wf_fifo_empty : std_logic; |
SIGNAL s_fx2_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fx2_n_tri : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_start_scpi_command : std_logic; |
SIGNAL s_scpi_command_id : std_logic_vector( 6 DOWNTO 0 ); |
SIGNAL s_scpi_command_done : std_logic; |
SIGNAL s_cmd_09_done : std_logic; |
SIGNAL s_cmd_09_push : std_logic; |
SIGNAL s_cmd_09_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_cmd_09_push_size : std_logic; |
SIGNAL s_cmd_25_done : std_logic; |
SIGNAL s_pending_message : std_logic; |
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SIGNAL s_leds_a : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_leds_k : std_logic_vector( 7 DOWNTO 0 ); |
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SIGNAL s_fifo_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fifo_empty : std_logic; |
SIGNAL s_fifo_pop : std_logic; |
SIGNAL s_fifo_last : std_logic; |
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SIGNAL s_fpga_revision : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_fpga_type : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_fpga_configured : std_logic; |
SIGNAL s_reset_fpga_if : std_logic; |
SIGNAL s_fpga_data_in_ena : std_logic; |
SIGNAL s_fpga_data_out_ena : std_logic; |
SIGNAL s_fpga_data_in : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_data_out : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_n_tri : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_data_out_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_n_tri_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_crc_error : std_logic; |
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SIGNAL s_fpga_fifo_push : std_logic; |
SIGNAL s_fpga_fifo_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fpga_fifo_last_byte : std_logic; |
SIGNAL s_fpga_fifo_full : std_logic; |
SIGNAL s_fpga_idle : std_logic; |
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SIGNAL s_bitfile_pop : std_logic; |
SIGNAL s_bitfile_u_pop : std_logic; |
SIGNAL s_bitfile_done : std_logic; |
SIGNAL s_bitfile_start : std_logic; |
SIGNAL s_bitfile_u_start : std_logic; |
SIGNAL s_bitfile_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_bitfile_last : std_logic; |
SIGNAL s_bitfile_fifo_empty : std_logic; |
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SIGNAL s_bitfile_error : std_logic; |
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SIGNAL s_bitfile_size : std_logic_vector(31 DOWNTO 0 ); |
SIGNAL s_we_fifo : std_logic; |
SIGNAL s_we_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_we_last : std_logic; |
SIGNAL s_we_fifo_full : std_logic; |
SIGNAL s_start_write : std_logic; |
SIGNAL s_flash_data_out : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_flash_data_oe : std_logic_vector(15 DOWNTO 0 ); |
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SIGNAL s_start_erase : std_logic; |
SIGNAL s_start_read : std_logic; |
SIGNAL s_start_flash_read : std_logic; |
SIGNAL s_prog_flash : std_logic; |
SIGNAL s_flash_present : std_logic; |
SIGNAL s_flash_s1_empty : std_logic; |
SIGNAL s_flash_idle : std_logic; |
SIGNAL s_flash_n_busy : std_logic; |
SIGNAL s_size_error : std_logic; |
SIGNAL s_flash_push : std_logic; |
SIGNAL s_flash_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_flash_push_size : std_logic; |
SIGNAL s_flash_push_last : std_logic; |
SIGNAL s_flash_fifo_full : std_logic; |
SIGNAL s_flash_u_push : std_logic; |
SIGNAL s_flash_u_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_flash_u_push_size : std_logic; |
SIGNAL s_flash_done : std_logic; |
SIGNAL s_flash_u_done : std_logic; |
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SIGNAL s_cmd_18_1e_done : std_logic; |
SIGNAL s_cmd_18_1e_push : std_logic; |
SIGNAL s_cmd_18_1e_size : std_logic; |
SIGNAL s_cmd_18_1e_data : std_logic_vector( 7 DOWNTO 0 ); |
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SIGNAL s_system_reset_done : std_logic; |
SIGNAL s_vga_command_done : std_logic; |
SIGNAL s_vga_command_error : std_logic; |
SIGNAL s_scpi_command_error : std_logic; |
SIGNAL s_vga_pop : std_logic; |
SIGNAL s_custom_pop : std_logic; |
SIGNAL s_vga_push : std_logic; |
SIGNAL s_vga_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_vga_push_size : std_logic; |
SIGNAL s_config_error : std_logic; |
SIGNAL s_pud_pop : std_logic; |
SIGNAL s_pud_push : std_logic; |
SIGNAL s_pud_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pud_push_size : std_logic; |
SIGNAL s_hex_switch : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_hex_error : std_logic; |
SIGNAL s_hex_done : std_logic; |
SIGNAL s_hex_pop : std_logic; |
SIGNAL s_hex_push : std_logic; |
SIGNAL s_hex_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_hex_push_size : std_logic; |
SIGNAL s_pud_we : std_logic; |
SIGNAL s_pud_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pud_addr : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_status_error : std_logic; |
SIGNAL s_status_done : std_logic; |
SIGNAL s_trans_mode : std_logic; |
SIGNAL s_status_pop : std_logic; |
SIGNAL s_status_push : std_logic; |
SIGNAL s_status_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_status_push_size : std_logic; |
SIGNAL s_unknown_command : std_logic; |
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SIGNAL s_status_nibble : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_fx2_data_nibble : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_indicator_pulse : std_logic; |
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SIGNAL s_b_n_reset : std_logic; |
SIGNAL s_b_n_start_transmission : std_logic; |
SIGNAL s_b_n_end_transmission_out : std_logic; |
SIGNAL s_b_n_end_transmission_in : std_logic; |
SIGNAL s_b_n_data_valid_out : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_b_n_data_valid_in : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_b_data_out : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_b_data_in : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_b_read_n_write : std_logic; |
SIGNAL s_b_burst_size : std_logic_vector( 8 DOWNTO 0 ); |
SIGNAL s_b_address : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_b_n_start_send : std_logic; |
SIGNAL s_b_n_bus_error : std_logic; |
|
SIGNAL s_vga_cursor_pos : std_logic_vector( 10 DOWNTO 0 ); |
SIGNAL s_vga_screen_offset : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_vga_fg_color : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_vga_bg_color : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_vga_write_address : std_logic_vector( 10 DOWNTO 0 ); |
SIGNAL s_vga_ascii_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_vga_we : std_logic; |
SIGNAL s_vga_n_end_transmission_out : std_logic; |
SIGNAL s_vga_n_data_valid_out : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_vga_data_out : std_logic_vector( 15 DOWNTO 0 ); |
SIGNAL s_vga_n_start_send : std_logic; |
SIGNAL s_vga_n_bus_error : std_logic; |
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SIGNAL s_ufifo_push : std_logic; |
SIGNAL s_ufifo_push_size : std_logic; |
SIGNAL s_ufifo_push_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_ufifo_error : std_logic; |
SIGNAL s_ufifo_done : std_logic; |
SIGNAL s_ufifo_n_error : std_logic; |
SIGNAL s_ufifo_n_start : std_logic; |
SIGNAL s_ufifo_data : std_logic_vector( 15 DOWNTO 0 ); |
SIGNAL s_ufifo_n_valid : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_ufifo_n_end : std_logic; |
SIGNAL s_ufifo_pop : std_logic; |
SIGNAL s_ufifo_msg_avail : std_logic; |
SIGNAL s_scpi_msg_avail : std_logic; |
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SIGNAL s_start_config : std_logic; |
|
BEGIN |
|
-- Assign outputs |
gen_fx_data : FOR n IN 7 DOWNTO 0 GENERATE |
fx2_data(n) <= s_fx2_data(n) WHEN s_fx2_n_tri(n) = '0' ELSE 'Z'; |
END GENERATE gen_fx_data; |
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fx2_data_nibble <= s_fx2_data_nibble WHEN fx2_pa1 = '0' |
AND s_b_n_data_valid_out(1) = '1' -- DUMMY: REMOVE AFTERWARDS! |
ELSE (OTHERS => 'Z'); |
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red <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_red ; |
green <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_green ; |
blue <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_blue ; |
hsync <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_hsync ; |
vsync <= 'Z' WHEN jtag_ndet = '0' ELSE s_vga_vsync ; |
SDA <= s_SDA_pin WHEN s_SDA_OE = '0' ELSE 'Z'; |
fx2_n_int0 <= s_reset; |
RxD_out <= RxD_in; |
TxD_out <= 'Z' when jtag_ndet = '0' ELSE TxD_in ; |
scpi_disabled <= s_trans_mode; |
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-- Assign control signals |
s_n_usb_clk <= NOT(s_usb_clk); |
s_bitfile_u_start <= '1' WHEN s_start_scpi_command = '1' AND |
(s_scpi_command_id = "0011101" OR |
s_scpi_command_id = "0010110") ELSE '0'; |
s_prog_flash <= '1' WHEN s_scpi_command_id = "0010110" ELSE '0'; |
s_start_erase <= '1' WHEN s_start_scpi_command = '1' AND |
s_scpi_command_id = "0011010" ELSE '0'; |
s_start_read <= '1' WHEN s_start_scpi_command = '1' AND |
s_scpi_command_id = "0010111" ELSE '0'; |
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s_wf_push <= s_flash_u_push OR s_cmd_09_push OR s_cmd_18_1e_push OR |
s_vga_push OR s_pud_push OR s_hex_push OR |
s_status_push OR s_ufifo_push; |
s_wf_push_data <= s_flash_u_push_data OR s_cmd_09_push_data OR |
s_cmd_18_1e_data OR s_vga_push_data OR |
s_pud_push_data OR s_hex_push_data OR |
s_status_push_data OR s_ufifo_push_data; |
s_wf_push_size_bit <= s_flash_u_push_size OR s_cmd_09_push_size OR |
s_cmd_18_1e_size OR s_vga_push_size OR |
s_pud_push_size OR s_hex_push_size OR |
s_status_push_size OR s_ufifo_push_size; |
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s_scpi_command_done <= s_cmd_09_done OR s_cmd_25_done OR s_bitfile_done OR |
s_flash_u_done OR s_cmd_18_1e_done OR s_hex_done OR |
s_system_reset_done OR s_vga_command_done OR |
s_status_done OR s_ufifo_done; |
s_scpi_command_error <= s_vga_command_error OR s_bitfile_error OR |
s_config_error OR s_hex_error OR s_status_error OR |
s_ufifo_error OR s_size_error; |
s_custom_pop <= s_vga_pop OR s_bitfile_u_pop OR s_pud_pop OR |
s_hex_pop OR s_status_pop OR s_ufifo_pop; |
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-- Map components |
clockgen : clocks |
PORT MAP ( system_n_reset => n_reset_system, |
clock_25MHz => clock_25MHz, |
clock_16MHz => clock_16MHz, |
user_clock_1 => user_clock_1_in, |
user_clock_2 => user_clock_2_in, |
-- Here the compensated clocks are defined |
user_clock_1_out => user_clock_1_out, |
user_clock_1_fb => user_clock_1_fb, |
user_clock_1_lock => user_clock_1_lock, |
user_clock_2_out => user_clock_2_out, |
user_clock_2_fb => user_clock_2_fb, |
user_clock_2_lock => user_clock_2_lock, |
-- Here the master clocks are defined |
clock_25MHz_out => clock_25MHz_out, |
clock_48MHz_out => clock_48MHz_out, |
-- Here the FPGA internal clocks are defined |
clk_48MHz => s_clk_48MHz, |
clk_96MHz => s_clock_96MHz, |
clk_75MHz => s_clock_75MHz, |
reset_out => s_reset, |
msec_tick => s_msec_tick ); |
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usb_dff_1 : DFF |
PORT MAP ( clock => s_clk_48MHz, |
D => s_n_usb_clk, |
Q => s_usb_clk ); |
usb_dff_2 : DFF |
PORT MAP ( clock => s_clk_48MHz, |
D => s_usb_clk, |
Q => fx2_clk ); |
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SDA_ff : DFF |
PORT MAP ( clock => clock_16MHz, |
D => s_SDA, |
Q => s_SDA_pin ); |
SDA_oe_ff : DFF |
PORT MAP ( clock => clock_16MHz, |
D => s_SDA, |
Q => s_SDA_OE ); |
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i2c : eeprom_emu |
PORT MAP ( clock => clock_16MHz, |
reset => s_reset, |
button => button3, |
SDA_in => SDA, |
SCL_in => SCL, |
SDA_out => s_SDA ); |
|
|
s_b_n_end_transmission_in <= s_vga_n_end_transmission_out AND s_ufifo_n_end; |
s_b_n_data_valid_in <= s_vga_n_data_valid_out AND s_ufifo_n_valid; |
s_b_data_in <= s_vga_data_out OR s_ufifo_data; |
s_b_n_start_send <= s_vga_n_start_send AND s_ufifo_n_start; |
s_b_n_bus_error <= s_vga_n_bus_error AND s_ufifo_n_error; |
|
the_bus : bus_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset, |
-- Here the IOB interface is defined |
bus_reset => bus_reset , |
bus_n_start_transmission => bus_n_start_transmission, |
bus_n_end_transmission => bus_n_end_transmission , |
bus_n_data_valid => bus_n_data_valid , |
bus_data_addr_cntrl => bus_data_addr_cntrl , |
bus_n_start_send => bus_n_start_send , |
bus_n_error => bus_n_error , |
-- Here the FPGA internal interface is defined |
b_n_reset => s_b_n_reset , |
b_n_start_transmission => s_b_n_start_transmission , |
b_n_end_transmission_out => s_b_n_end_transmission_out, |
b_n_end_transmission_in => s_b_n_end_transmission_in , |
b_n_data_valid_out => s_b_n_data_valid_out , |
b_n_data_valid_in => s_b_n_data_valid_in , |
data_out => s_b_data_out , |
data_in => s_b_data_in , |
read_n_write => s_b_read_n_write , |
burst_size => s_b_burst_size , |
address => s_b_address , |
n_start_send => s_b_n_start_send , |
n_bus_error => s_b_n_bus_error ); |
fifo_if : user_fifo |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
-- Here the bus signals are defined |
n_bus_reset => s_b_n_reset, |
n_start_transmission => s_b_n_start_transmission, |
n_end_transmission_in => s_b_n_end_transmission_out, |
n_end_transmission_out => s_ufifo_n_end, |
n_data_valid_in => s_b_n_data_valid_out, |
n_data_valid_out => s_ufifo_n_valid, |
data_in => s_b_data_out, |
data_out => s_ufifo_data, |
read_n_write => s_b_read_n_write, |
burst_size => s_b_burst_size, |
bus_address => s_b_address, |
n_start_send => s_ufifo_n_start, |
n_bus_error => s_ufifo_n_error, |
-- Here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
transparent_mode => s_trans_mode, |
command_done => s_ufifo_done, |
command_error => s_ufifo_error, |
message_available => s_ufifo_msg_avail, |
-- Here the tx_fifo is defined |
push => s_ufifo_push, |
push_size => s_ufifo_push_size, |
push_data => s_ufifo_push_data, |
fifo_full => s_wf_fifo_full, |
-- Here the rx_fifo is defined |
pop => s_ufifo_pop, |
pop_last => s_fifo_last, |
pop_data => s_fifo_data, |
pop_empty => s_fifo_empty, |
-- Here the big fpga interface is defined |
data_request_irq => data_request_irq, |
data_available_irq => data_available_irq, |
error_irq => error_irq); |
|
vga_bus_if : vga_bus |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset, |
msec_tick => s_msec_tick, |
-- Here the bus signals are defined |
n_bus_reset => s_b_n_reset, |
n_start_transmission => s_b_n_start_transmission, |
n_end_transmission_in => s_b_n_end_transmission_out, |
n_end_transmission_out => s_vga_n_end_transmission_out, |
n_data_valid_in => s_b_n_data_valid_out(0), |
n_data_valid_out => s_vga_n_data_valid_out, |
data_in => s_b_data_out( 7 DOWNTO 0 ), |
data_out => s_vga_data_out, |
read_n_write => s_b_read_n_write, |
burst_size => s_b_burst_size, |
bus_address => s_b_address, |
n_start_send => s_vga_n_start_send, |
n_bus_error => s_vga_n_bus_error, |
-- Here the button interface is defined |
n_button_1 => button1, |
n_button_2 => button2, |
n_button_3 => button3, |
hexswitch => s_hex_switch, |
-- Here the LED interface is defined |
leds_a => s_leds_a, |
leds_k => s_leds_k, |
-- Here the VGA interface is defined |
cursor_pos => s_vga_cursor_pos , |
screen_offset => s_vga_screen_offset, |
fg_color => s_vga_fg_color , |
bg_color => s_vga_bg_color , |
write_address => s_vga_write_address, |
ascii_data => s_vga_ascii_data , |
we => s_vga_we ); |
|
|
status : status_controller |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
fpga_configured => s_fpga_configured, |
-- Here the fx2 interface is defined |
status_nibble => s_status_nibble, |
-- Here the external status if is defined |
ESB_bit => ESB_bit, |
STATUS3_bit => STATUS3_bit, |
-- Here the scpi interface is defined |
start => s_start_scpi_command, |
command => s_scpi_command_id, |
cmd_error => s_status_error, |
command_error => s_unknown_command, |
execution_error => s_scpi_command_error, |
done => s_status_done, |
transparent => s_trans_mode, |
pop => s_status_pop, |
pop_data => s_fifo_data, |
pop_last => s_fifo_last, |
pop_empty => s_fifo_empty, |
push => s_status_push, |
push_data => s_status_push_data, |
push_size => s_status_push_size, |
push_full => s_wf_fifo_full, |
push_empty => s_wf_fifo_empty ); |
|
s_pending_message <= s_ufifo_msg_avail OR s_scpi_msg_avail; |
fx2 : USBTMC |
PORT MAP ( clock_96MHz => s_clock_96MHz, |
clock_48MHz => s_clk_48MHz, |
cpu_reset => s_reset, |
sync_reset_out => s_usb_reset, |
-- SCPI command interpretor interface |
pending_message => s_pending_message, |
transfer_in_prog => OPEN, |
-- FX2 control interface |
FX2_n_ready => fx2_pa1, |
FX2_hi_speed => fx2_pa3, |
-- read fifo interface |
rf_pop => s_fifo_pop, |
rf_pop_data => s_fifo_data, |
rf_last_data_byte=> s_fifo_last, |
rf_fifo_empty => s_fifo_empty, |
-- Write fifo interface |
wf_push => s_wf_push , |
wf_push_data => s_wf_push_data , |
wf_push_size_bit => s_wf_push_size_bit, |
wf_fifo_full => s_wf_fifo_full , |
wf_fifo_empty => s_wf_fifo_empty , |
-- status interface |
status_nibble => s_status_nibble, |
indicator_pulse => s_indicator_pulse, |
-- FX2 port D interface |
data_nibble => s_fx2_data_nibble, |
data_select => fx2_data_select, |
-- FX2 FIFO interface |
EP8_n_empty => fx2_flaga, |
EP6_n_full => fx2_flagb, |
EP_data_in => fx2_data, |
EP_address => fx2_fifo_addr, |
EP_IFCLOCK => fx2_ifclock, |
EP_n_PKTEND => fx2_n_pkt_end, |
EP_n_OE => fx2_n_oe, |
EP_n_RE => fx2_n_re, |
EP_n_WE => fx2_n_we, |
EP_data_out => s_fx2_data, |
EP_n_tri_out => s_fx2_n_tri); |
|
vga : vga_controller |
PORT MAP ( clock_75MHz => s_clock_75MHz, |
reset => s_reset, |
vga_off => s_reset, |
clock => s_clk_48MHz, |
-- Here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
command_done => s_vga_command_done, |
command_error => s_vga_command_error, |
-- Here the usbtmc fifo interface is defined |
pop => s_vga_pop, |
pop_data => s_fifo_data, |
pop_last => s_fifo_last, |
pop_empty => s_fifo_empty, |
push => s_vga_push, |
push_data => s_vga_push_data, |
push_size => s_vga_push_size, |
push_full => s_wf_fifo_full, |
-- Here the PUD interface is defined |
we_char => s_pud_we, |
we_ascii => s_pud_data, |
we_addr => s_pud_addr, |
-- Here the fpga interface is defined |
cursor_pos => s_vga_cursor_pos , |
screen_offset => s_vga_screen_offset, |
fg_color => s_vga_fg_color , |
bg_color => s_vga_bg_color , |
write_address => s_vga_write_address, |
ascii_data => s_vga_ascii_data , |
we => s_vga_we , |
vga_red => s_vga_red , |
vga_green => s_vga_green , |
vga_blue => s_vga_blue , |
vga_hsync => s_vga_hsync , |
vga_vsync => s_vga_vsync ); |
|
scpi : SCPI_INTERFACE |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
-- The command interface |
transparent_mode => s_trans_mode, |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
cmd_gen_respons => s_scpi_msg_avail, |
command_done => s_scpi_command_done, |
command_error => s_scpi_command_error, |
unknown_command => s_unknown_command, |
slave_pop => s_custom_pop, |
-- USBTMC fifo interface |
pop => s_fifo_pop, |
pop_data => s_fifo_data, |
pop_empty => s_fifo_empty, |
pop_last => s_fifo_last); |
|
cmd_18_1e : cmd_18_1e_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
-- Here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
command_done => s_cmd_18_1e_done, |
-- Here the tx_fifo is defined |
push => s_cmd_18_1e_push, |
push_size => s_cmd_18_1e_size, |
push_data => s_cmd_18_1e_data, |
fifo_full => s_wf_fifo_full, |
-- Here the fpga_if is defined |
fpga_type => s_fpga_type, |
fpga_configured => s_fpga_configured, |
flash_empty => s_flash_s1_empty, |
-- Here the board interface is defined |
n_usb_power => n_usb_power, |
n_bus_power => n_bus_power, |
n_usb_charge => n_usb_charge); |
|
cmd_09 : IDN_handler |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
start => s_start_scpi_command, |
command => s_scpi_command_id, |
fifo_full => s_wf_fifo_full, |
done => s_cmd_09_done, |
push => s_cmd_09_push, |
size_bit => s_cmd_09_push_size, |
push_data => s_cmd_09_push_data ); |
cmd_25 : identify_handler |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset, |
start => s_start_scpi_command, |
command => s_scpi_command_id, |
indicator => s_indicator_pulse, |
done => s_cmd_25_done, |
flash_idle => s_flash_n_busy, |
msec_tick => s_msec_tick, |
leds_a_in => s_leds_a, |
leds_k_in => s_leds_k, |
leds_a => leds_a, |
leds_k => leds_k); |
cmd_23_24 : hexswitch |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
n_hex_sw => n_hex_switch, |
hex_value => s_hex_switch, |
-- here the scpi interface is defined |
start => s_start_scpi_command, |
command => s_scpi_command_id, |
command_error => s_hex_error, |
done => s_hex_done, |
pop => s_hex_pop, |
pop_data => s_fifo_data, |
pop_last => s_fifo_last, |
pop_empty => s_fifo_empty, |
push => s_hex_push, |
push_data => s_hex_push_data, |
push_size => s_hex_push_size, |
push_full => s_wf_fifo_full ); |
|
|
system_reset : reset_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset, |
msec_tick => s_msec_tick, |
-- Here the fpga_interface is defined |
fpga_configured=> s_fpga_configured, |
-- Here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
command_done => s_system_reset_done, |
-- Here the system reset is defined |
n_reset_system => n_reset_system, |
user_n_reset => user_n_reset ); |
|
|
-------------------------------------------------------------------------------- |
--- Here the FPGA interface is defined --- |
--- NOTE: The FPGA data pins have dual function; however the configuration --- |
--- Interface MUST have priority --- |
-------------------------------------------------------------------------------- |
config : config_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset_fpga_if, |
-- here the flash interface is defined |
start_config => s_start_config, |
flash_start_read => s_start_flash_read, |
flash_done => s_flash_done, |
flash_present => s_flash_present, |
flash_s1_empty => s_flash_s1_empty, |
flash_idle => s_flash_idle, |
flash_push => s_flash_push, |
flash_push_data => s_flash_push_data, |
flash_push_size => s_flash_push_size, |
flash_push_last => s_flash_push_last, |
flash_fifo_full => s_flash_fifo_full, |
-- here the flash usbtmc interface is defined |
flash_u_start_read => s_start_read, |
flash_u_done => s_flash_u_done, |
flash_u_push => s_flash_u_push, |
flash_u_push_data => s_flash_u_push_data, |
flash_u_push_size => s_flash_u_push_size, |
flash_u_fifo_full => s_wf_fifo_full, |
-- here the bitfile interface is defined |
bitfile_start => s_bitfile_start, |
bitfile_pop => s_bitfile_pop, |
bitfile_pop_data => s_bitfile_pop_data, |
bitfile_last => s_bitfile_last, |
bitfile_fifo_empty => s_bitfile_fifo_empty, |
-- here the bitfile usbtmc interface is defined |
bitfile_u_start => s_bitfile_u_start, |
bitfile_u_pop => s_bitfile_u_pop, |
bitfile_u_pop_data => s_fifo_data, |
bitfile_u_last => s_fifo_last, |
bitfile_u_fifo_empty => s_fifo_empty, |
-- here the fpga interface is defined |
fpga_idle => s_fpga_idle, |
fpga_type => s_fpga_type, |
-- here the power interface is defined |
n_bus_power => n_bus_power, |
-- here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
command_error => s_config_error ); |
|
|
fpga : fpga_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset_fpga_if, |
-- Here the FPGA info is provided |
fpga_idle => s_fpga_idle, |
fpga_revision => s_fpga_revision, |
fpga_type => s_fpga_type, |
fpga_configured => s_fpga_configured, |
fpga_crc_error => s_fpga_crc_error, |
-- Here the bitfile fifo if is defined |
push => s_fpga_fifo_push, |
push_data => s_fpga_fifo_push_data, |
last_byte => s_fpga_fifo_last_byte, |
fifo_full => s_fpga_fifo_full, |
-- Here the select map pins are defined |
fpga_done => fpga_done, |
fpga_busy => fpga_busy, |
fpga_n_init => fpga_n_init, |
fpga_n_prog => fpga_n_prog, |
fpga_rd_n_wr => fpga_rd_n_wr, |
fpga_n_cs => fpga_n_cs, |
fpga_cclk => fpga_cclk, |
fpga_data_in => s_fpga_data_in, |
fpga_data_out => s_fpga_data_out, |
fpga_n_tri => s_fpga_n_tri, |
fpga_data_in_ena => s_fpga_data_in_ena, |
fpga_data_out_ena => s_fpga_data_out_ena); |
bitfile : bitfile_interpreter |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_usb_reset, |
msec_tick => s_msec_tick, |
-- Here the handshake interface is defined |
start => s_bitfile_start, |
write_flash => s_prog_flash, |
done => s_bitfile_done, |
error_detected => s_bitfile_error, |
-- Here the FX2 fifo interface is defined |
pop => s_bitfile_pop, |
pop_data => s_bitfile_pop_data, |
pop_last => s_bitfile_last, |
fifo_empty => s_bitfile_fifo_empty, |
-- Here the FPGA_IF fifo interface is defined |
push => s_fpga_fifo_push, |
push_data => s_fpga_fifo_push_data, |
last_byte => s_fpga_fifo_last_byte, |
fifo_full => s_fpga_fifo_full, |
reset_fpga_if => s_reset_fpga_if, |
-- Here the flash write fifo interface is defined |
bitfile_size => s_bitfile_size, |
we_fifo => s_we_fifo , |
we_data => s_we_data , |
we_last => s_we_last , |
we_fifo_full => s_we_fifo_full, |
start_write => s_start_write , |
size_error => s_size_error, |
-- Here the debug vga interface is defined |
we_char => OPEN, |
ascii_data => OPEN ); |
flash : flash_if |
PORT MAP ( clock => s_clk_48MHz, |
reset => s_reset_fpga_if, |
msec_tick => s_msec_tick, |
-- here the control interface is defined |
start_erase => s_start_erase, |
start_read => s_start_flash_read, |
start_write => s_start_write, |
done => s_flash_done, |
flash_present => s_flash_present , |
flash_s1_empty => s_flash_s1_empty, |
flash_idle => s_flash_idle , |
size_error => s_size_error , |
flash_n_busy => s_flash_n_busy , |
start_config => s_start_config, |
-- here the push fifo interface is defined |
push => s_flash_push , |
push_data => s_flash_push_data, |
push_size => s_flash_push_size, |
push_last => s_flash_push_last, |
fifo_full => s_flash_fifo_full, |
-- here the write fifo is defined |
bitfile_size => s_bitfile_size, |
we_fifo => s_we_fifo, |
we_data => s_we_data, |
we_last => s_we_last, |
we_fifo_full => s_we_fifo_full, |
-- Here the scpi interface is defined |
start_command => s_start_scpi_command, |
command_id => s_scpi_command_id, |
scpi_pop => s_pud_pop, |
scpi_pop_data => s_fifo_data, |
scpi_pop_last => s_fifo_last, |
scpi_empty => s_fifo_empty, |
scpi_push => s_pud_push, |
scpi_push_data => s_pud_push_data, |
scpi_push_size => s_pud_push_size, |
scpi_full => s_wf_fifo_full, |
-- Here the vga interface is defined |
we_char => s_pud_we, |
we_ascii => s_pud_data, |
we_addr => s_pud_addr, |
-- define the flash interface |
flash_address => flash_address, |
flash_data_in => flash_data, |
flash_data_out => s_flash_data_out, |
flash_data_oe => s_flash_data_oe, |
flash_n_byte => flash_n_byte, |
flash_n_ce => flash_n_ce, |
flash_n_oe => flash_n_oe, |
flash_n_we => flash_n_we, |
flash_ready_n_busy => flash_ready_n_busy ); |
|
make_flash_tri : FOR n IN 15 DOWNTO 0 GENERATE |
flash_data(n) <= s_flash_data_out(n) WHEN s_flash_data_oe(n) = '0' |
ELSE 'Z'; |
END GENERATE make_flash_tri; |
|
|
make_fpga_data_ffs : FOR n IN 7 DOWNTO 0 GENERATE |
fpga_data(n) <= s_fpga_data_out_reg(n) WHEN s_fpga_n_tri_reg(n) = '0' |
ELSE 'Z'; |
in_ff : FDE |
PORT MAP ( Q => s_fpga_data_in(n), |
CE => s_fpga_data_in_ena, |
C => s_clock_96MHz, |
D => fpga_data(n) ); |
tri_ff : FD |
PORT MAP ( Q => s_fpga_n_tri_reg(n), |
C => s_clock_96MHz, |
D => s_fpga_n_tri(n) ); |
out_ff : FDE |
PORT MAP ( Q => s_fpga_data_out_reg(n), |
CE => s_fpga_data_out_ena, |
C => s_clock_96MHz, |
D => s_fpga_data_out(n) ); |
END GENERATE make_fpga_data_ffs; |
|
END behave; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_23_24_if/hexswitch-behavior.vhdl
0,0 → 1,199
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_platform_specific OF hexswitch IS |
|
TYPE HEX_STATE_TYPE IS ( IDLE , SEND_SIZE , SEND_VALUE , SEND_END , GET_VALUE , |
SIGNAL_DONE , SIGNAL_ERROR ); |
|
SIGNAL s_override_reg : std_logic; |
SIGNAL s_hexswitch_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_hex_state_reg : HEX_STATE_TYPE; |
SIGNAL s_push : std_logic; |
SIGNAL s_fetched_value : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_pop : std_logic; |
SIGNAL s_update : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
hex_value <= s_hexswitch_reg; |
done <= '1' WHEN s_hex_state_reg = SIGNAL_DONE ELSE '0'; |
command_error <= '1' WHEN s_hex_state_reg = SIGNAL_ERROR ELSE '0'; |
push_size <= '1' WHEN s_hex_state_reg = SEND_SIZE ELSE '0'; |
push <= s_push; |
pop <= s_pop; |
|
make_push_data : PROCESS( s_hex_state_reg , s_hexswitch_reg ) |
BEGIN |
CASE (s_hex_state_reg) IS |
WHEN SEND_SIZE => push_data <= X"02"; |
WHEN SEND_VALUE => CASE (s_hexswitch_reg) IS |
WHEN X"0" => push_data <= X"30"; |
WHEN X"1" => push_data <= X"31"; |
WHEN X"2" => push_data <= X"32"; |
WHEN X"3" => push_data <= X"33"; |
WHEN X"4" => push_data <= X"34"; |
WHEN X"5" => push_data <= X"35"; |
WHEN X"6" => push_data <= X"36"; |
WHEN X"7" => push_data <= X"37"; |
WHEN X"8" => push_data <= X"38"; |
WHEN X"9" => push_data <= X"39"; |
WHEN X"A" => push_data <= X"41"; |
WHEN X"B" => push_data <= X"42"; |
WHEN X"C" => push_data <= X"43"; |
WHEN X"D" => push_data <= X"44"; |
WHEN X"E" => push_data <= X"45"; |
WHEN OTHERS => push_data <= X"46"; |
END CASE; |
WHEN SEND_END => push_data <= X"0A"; |
WHEN OTHERS => push_data <= X"00"; |
END CASE; |
END PROCESS make_push_data; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_push <= '1' WHEN push_full = '0' AND |
(s_hex_state_reg = SEND_SIZE OR |
s_hex_state_reg = SEND_VALUE OR |
s_hex_state_reg = SEND_END) ELSE '0'; |
s_pop <= '1' WHEN pop_empty = '0' AND |
s_hex_state_reg = GET_VALUE ELSE '0'; |
s_update <= s_pop AND s_fetched_value(4); |
|
make_fetched_value : PROCESS( pop_data ) |
BEGIN |
CASE (pop_data) IS |
WHEN X"30" => s_fetched_value <= "1"&X"0"; |
WHEN X"31" => s_fetched_value <= "1"&X"1"; |
WHEN X"32" => s_fetched_value <= "1"&X"2"; |
WHEN X"33" => s_fetched_value <= "1"&X"3"; |
WHEN X"34" => s_fetched_value <= "1"&X"4"; |
WHEN X"35" => s_fetched_value <= "1"&X"5"; |
WHEN X"36" => s_fetched_value <= "1"&X"6"; |
WHEN X"37" => s_fetched_value <= "1"&X"7"; |
WHEN X"38" => s_fetched_value <= "1"&X"8"; |
WHEN X"39" => s_fetched_value <= "1"&X"9"; |
WHEN X"41" => s_fetched_value <= "1"&X"A"; |
WHEN X"42" => s_fetched_value <= "1"&X"B"; |
WHEN X"43" => s_fetched_value <= "1"&X"C"; |
WHEN X"44" => s_fetched_value <= "1"&X"D"; |
WHEN X"45" => s_fetched_value <= "1"&X"E"; |
WHEN X"46" => s_fetched_value <= "1"&X"F"; |
WHEN X"61" => s_fetched_value <= "1"&X"A"; |
WHEN X"62" => s_fetched_value <= "1"&X"B"; |
WHEN X"63" => s_fetched_value <= "1"&X"C"; |
WHEN X"64" => s_fetched_value <= "1"&X"D"; |
WHEN X"65" => s_fetched_value <= "1"&X"E"; |
WHEN X"66" => s_fetched_value <= "1"&X"F"; |
WHEN OTHERS => s_fetched_value <= "0"&X"0"; |
END CASE; |
END PROCESS make_fetched_value; |
|
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_state_machine : PROCESS( clock , reset , s_hex_state_reg , start , |
command , s_push ) |
VARIABLE v_next_state : HEX_STATE_TYPE; |
BEGIN |
CASE (s_hex_state_reg) IS |
WHEN IDLE => IF (start = '1') THEN |
CASE (command) IS |
WHEN "0100011" => v_next_state := GET_VALUE; |
WHEN "0100100" => v_next_state := SEND_SIZE; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN SEND_SIZE => IF (s_push = '1') THEN |
v_next_state := SEND_VALUE; |
ELSE |
v_next_state := SEND_SIZE; |
END IF; |
WHEN SEND_VALUE => IF (s_push = '1') THEN |
v_next_state := SEND_END; |
ELSE |
v_next_state := SEND_VALUE; |
END IF; |
WHEN SEND_END => IF (s_push = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := SEND_END; |
END IF; |
WHEN GET_VALUE => IF (s_pop = '1') THEN |
IF (s_fetched_value(4) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSIF (pop_data = X"20" AND |
pop_last = '0') THEN |
v_next_state := GET_VALUE; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_VALUE; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_hex_state_reg <= IDLE; |
ELSE s_hex_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the base registers are defined --- |
-------------------------------------------------------------------------------- |
make_override_reg : PROCESS( clock , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_override_reg <= '0'; |
ELSIF (s_update = '1') THEN s_override_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_override_reg; |
|
make_hexswitch_reg : PROCESS( clock , s_override_reg , n_hex_sw ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_update = '1') THEN |
s_hexswitch_reg <= s_fetched_value( 3 DOWNTO 0 ); |
ELSIF (s_override_reg = '0') THEN s_hexswitch_reg <= NOT(n_hex_sw); |
END IF; |
END IF; |
END PROCESS make_hexswitch_reg; |
END no_platform_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_23_24_if/hexswitch-entity.vhdl
0,0 → 1,59
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
ENTITY hexswitch IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
n_hex_sw : IN std_logic_vector( 3 DOWNTO 0 ); |
|
hex_value : OUT std_logic_vector( 3 DOWNTO 0 ); |
|
-- here the scpi interface is defined |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
command_error : OUT std_logic; |
done : OUT std_logic; |
|
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
|
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic ); |
END hexswitch; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/idreg_rom-behavior.vhdl
0,0 → 1,59
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE spartan3 OF idreg_rom IS |
|
BEGIN |
make_data : PROCESS( index ) |
BEGIN |
CASE (index) IS |
WHEN "00000" => data <= X"00"; |
WHEN "00001" => data <= X"00"; |
WHEN "00010" => data <= X"00"; |
WHEN "00011" => data <= X"00"; |
WHEN "00100" => data <= X"00"; |
WHEN "00101" => data <= X"00"; |
WHEN "00110" => data <= X"00"; |
WHEN "00111" => data <= X"00"; |
WHEN "01000" => data <= X"02"; |
WHEN "01001" => data <= X"C0"; |
WHEN "01010" => data <= X"01"; |
WHEN "01011" => data <= X"28"; |
WHEN "01100" => data <= X"66"; |
WHEN "01101" => data <= X"55"; |
WHEN "01110" => data <= X"99"; |
WHEN "01111" => data <= X"AA"; |
WHEN OTHERS => data <= X"FF"; |
END CASE; |
END PROCESS make_data; |
END spartan3; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/fpga_if-entity.vhdl
0,0 → 1,78
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
-- fpga_type: |
-- 000 => XC3S1000 |
-- 001 => XC3S1500 |
-- 010 => XC3S2000 |
-- 011 => XC3S4000 |
-- 100 => XC3S5000 |
-- rest => Unknown FPGA or no FPGA mounted |
|
ENTITY fpga_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- Here the FPGA info is provided |
fpga_idle : OUT std_logic; |
fpga_revision : OUT std_logic_vector( 3 DOWNTO 0 ); |
fpga_type : OUT std_logic_vector( 2 DOWNTO 0 ); |
fpga_configured : OUT std_logic; |
fpga_crc_error : OUT std_logic; |
|
-- Here the bitfile fifo if is defined |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
last_byte : IN std_logic; |
fifo_full : OUT std_logic; |
|
-- Here the select map pins are defined |
fpga_done : IN std_logic; |
fpga_busy : IN std_logic; |
fpga_n_init : IN std_logic; |
fpga_n_prog : OUT std_logic; |
fpga_rd_n_wr : OUT std_logic; |
fpga_n_cs : OUT std_logic; |
fpga_cclk : OUT std_logic; |
|
fpga_data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
fpga_data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
fpga_n_tri : OUT std_logic_vector( 7 DOWNTO 0 ); |
fpga_data_in_ena : OUT std_logic; |
fpga_data_out_ena : OUT std_logic); |
END fpga_if; |
|
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/fpga_if-behavior.vhdl
0,0 → 1,555
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE no_platform_specific OF fpga_if IS |
|
COMPONENT FDE |
GENERIC( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
CE : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FD |
GENERIC( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT idreg_rom |
PORT( index : IN std_logic_vector( 4 DOWNTO 0 ); |
data : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END COMPONENT; |
|
COMPONENT fifo_2kb |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_size : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END COMPONENT; |
|
TYPE FPGA_STATE_TYPE IS (IDLE , RESET_STATE , GENERATE_N_PROG , |
WAIT_N_INIT_HI , WAIT_AFTER_N_INIT , SET_RDNWR_LO , |
WAIT_RDNWR_LO , SET_N_CS_LO_WRITE , DO_WRITE , |
WAIT_DONE , SET_CS_HI_WRITE , WAIT_CS_HI_WRITE , |
SET_RDNWR_HI , WAIT_RDNWR_HI , SET_CS_LO_READ , |
DO_READ , SET_CS_HI_READ , WAIT_AFTER_DONE , |
DO_FLUSH , SIGNAL_ERROR ); |
|
SIGNAL s_fpga_state_reg : FPGA_STATE_TYPE; |
SIGNAL s_data_to_fpga : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_data_from_fpga : std_logic_vector( 7 DOWNTO 0 ); |
|
SIGNAL s_cclk_reg : std_logic; |
SIGNAL s_n_prog_reg : std_logic; |
SIGNAL s_n_cs_reg : std_logic; |
SIGNAL s_rd_n_wr_reg : std_logic; |
SIGNAL s_n_init : std_logic; |
SIGNAL s_busy : std_logic; |
SIGNAL s_done : std_logic; |
SIGNAL s_ena_in_ffs : std_logic; |
SIGNAL s_ena_out_ffs : std_logic; |
|
SIGNAL s_wait_counter_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_wait_counter_load : std_logic; |
SIGNAL s_wait_counter_ena : std_logic; |
|
SIGNAL s_last_byte : std_logic; |
SIGNAL s_next_idx_byte : std_logic; |
SIGNAL s_last_idx_byte : std_logic; |
SIGNAL s_idx_index_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_idx_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_idx_count_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_idx_valid_reg : std_logic; |
SIGNAL s_idx_valid : std_logic; |
SIGNAL s_first_time_reg : std_logic; |
|
SIGNAL s_fpga_rev_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_fpga_type_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_valid_out_byte : std_logic; |
SIGNAL s_n_cs_next : std_logic; |
|
SIGNAL s_fifo_pop : std_logic; |
SIGNAL s_fifo_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fifo_last_byte : std_logic; |
SIGNAL s_fifo_empty : std_logic; |
SIGNAL s_ena_fpga_data_in : std_logic; |
SIGNAL s_ena_data_to_fpga : std_logic; |
|
BEGIN |
fpga_revision <= s_fpga_rev_reg; |
fpga_configured <= s_done; |
fpga_idle <= '1' WHEN s_fpga_state_reg = IDLE ELSE '0'; |
|
fpga_type <= s_fpga_type_reg; |
|
s_data_to_fpga <= (OTHERS => '1') WHEN |
s_fpga_state_reg = GENERATE_N_PROG |
ELSE |
s_idx_data WHEN s_first_time_reg = '1' ELSE |
s_fifo_data; |
fpga_n_tri <= X"00" WHEN s_rd_n_wr_reg = '0' ELSE (OTHERS => '1'); |
fpga_data_in_ena <= s_ena_fpga_data_in; |
fpga_data_out_ena <= s_ena_data_to_fpga; |
|
swap: FOR n IN 7 DOWNTO 0 GENERATE |
fpga_data_out(7-n) <= s_data_to_fpga(n); |
s_data_from_fpga(7-n) <= fpga_data_in(n); |
-- For simulation mask above and unmask below |
-- in_ff : FDE |
-- GENERIC MAP (INIT => '1') |
-- PORT MAP ( Q => s_data_from_fpga(n), |
-- CE => s_ena_fpga_data_in, |
-- C => clock, |
-- D => fpga_data_in(n)); |
-- one_ff : FDE |
-- GENERIC MAP ( INIT => '1' ) |
-- PORT MAP ( Q => fpga_data_out(n), |
-- CE => s_ena_data_to_fpga, |
-- C => clock, |
-- D => s_data_to_fpga(n) ); |
END GENERATE swap; |
|
------------------------------------------------------------------------------- |
--- here all control signals are defined --- |
------------------------------------------------------------------------------- |
s_ena_in_ffs <= s_cclk_reg; |
s_ena_out_ffs <= NOT(s_cclk_reg); |
s_last_byte <= s_last_idx_byte WHEN s_first_time_reg = '1' ELSE |
s_fifo_last_byte; |
s_valid_out_byte <= s_ena_out_ffs |
WHEN |
s_fpga_state_reg = DO_WRITE AND |
NOT (s_n_cs_reg = '0' AND |
s_busy = '1') AND |
(s_first_time_reg = '1' OR |
s_fifo_empty = '0') |
ELSE '0'; |
s_n_cs_next <= '0' WHEN s_fpga_state_reg = DO_READ OR |
(s_fpga_state_reg = DO_WRITE AND |
s_valid_out_byte = '1') OR |
(s_n_cs_reg = '0' AND |
s_busy = '1') ELSE '1'; |
s_ena_fpga_data_in <= s_ena_in_ffs WHEN |
s_fpga_state_reg = DO_READ |
ELSE '0'; |
s_ena_data_to_fpga <= '1' WHEN |
s_valid_out_byte = '1' OR |
s_fpga_state_reg = GENERATE_N_PROG |
ELSE '0'; |
|
------------------------------------------------------------------------------- |
--- Here the IOB intermediate flipflops are defined --- |
------------------------------------------------------------------------------- |
make_cclk_reg : PROCESS( clock , reset , s_fpga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_fpga_state_reg = IDLE) THEN s_cclk_reg <= '1'; |
ELSE s_cclk_reg <= NOT(s_cclk_reg); |
END IF; |
END IF; |
END PROCESS make_cclk_reg; |
|
make_n_prog_reg : PROCESS( clock , s_fpga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_fpga_state_reg = GENERATE_N_PROG) THEN s_n_prog_reg <= '0'; |
ELSE s_n_prog_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_n_prog_reg; |
|
make_n_cs_reg : PROCESS( clock , s_ena_out_ffs ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_ena_out_ffs = '1') THEN |
s_n_cs_reg <= s_n_cs_next; |
END IF; |
END IF; |
END PROCESS make_n_cs_reg; |
|
make_rd_n_wr_reg : PROCESS( clock , reset , s_fpga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_fpga_state_reg = RESET_STATE OR |
s_fpga_state_reg = SET_RDNWR_HI OR |
s_fpga_state_reg = DO_FLUSH) THEN s_rd_n_wr_reg <= '1'; |
ELSIF (s_fpga_state_reg = SET_RDNWR_LO) THEN s_rd_n_wr_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_rd_n_wr_reg; |
|
make_crc_error : PROCESS( clock , s_fpga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_fpga_state_reg = RESET_STATE) THEN fpga_crc_error <= '0'; |
ELSIF (s_fpga_state_reg = SIGNAL_ERROR) THEN fpga_crc_error <= '1'; |
END IF; |
END IF; |
END PROCESS make_crc_error; |
|
------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
------------------------------------------------------------------------------- |
fpga_state_machine : PROCESS( clock , reset , s_fpga_state_reg , |
s_wait_counter_reg , s_n_init , s_idx_valid , |
s_idx_count_reg ) |
VARIABLE v_next_state : FPGA_STATE_TYPE; |
BEGIN |
CASE (s_fpga_state_reg) IS |
WHEN RESET_STATE => v_next_state := GENERATE_N_PROG; |
WHEN GENERATE_N_PROG => IF (s_wait_counter_reg(7) = '1' AND |
s_n_init = '0') THEN |
v_next_state := WAIT_N_INIT_HI; |
ELSE |
v_next_state := GENERATE_N_PROG; |
END IF; |
WHEN WAIT_N_INIT_HI => IF (s_n_init = '1') THEN |
v_next_state := WAIT_AFTER_N_INIT; |
ELSE |
v_next_state := WAIT_N_INIT_HI; |
END IF; |
WHEN WAIT_AFTER_N_INIT => IF (s_wait_counter_reg(7) = '1') THEN |
v_next_state := SET_RDNWR_LO; |
ELSE |
v_next_state := WAIT_AFTER_N_INIT; |
END IF; |
WHEN SET_RDNWR_LO => v_next_state := WAIT_RDNWR_LO; |
WHEN WAIT_RDNWR_LO => IF (s_wait_counter_reg(7) = '1' AND |
s_ena_out_ffs = '1') THEN |
v_next_state := SET_N_CS_LO_WRITE; |
ELSE |
v_next_state := WAIT_RDNWR_LO; |
END IF; |
WHEN SET_N_CS_LO_WRITE => v_next_state := DO_WRITE; |
WHEN DO_WRITE => IF (s_last_byte = '1' AND |
s_valid_out_byte = '1') THEN |
v_next_state := SET_CS_HI_WRITE; |
ELSIF (s_n_init = '0') THEN |
v_next_state := DO_FLUSH; |
ELSE |
v_next_state := DO_WRITE; |
END IF; |
WHEN SET_CS_HI_WRITE => IF (s_n_cs_reg = '1') THEN |
v_next_state := WAIT_CS_HI_WRITE; |
ELSE |
v_next_state := SET_CS_HI_WRITE; |
END IF; |
WHEN WAIT_CS_HI_WRITE => IF (s_wait_counter_reg(7) = '1') THEN |
v_next_state := SET_RDNWR_HI; |
ELSE |
v_next_state := WAIT_CS_HI_WRITE; |
END IF; |
WHEN SET_RDNWR_HI => v_next_state := WAIT_RDNWR_HI; |
WHEN WAIT_RDNWR_HI => IF (s_wait_counter_reg(7) = '1' AND |
s_ena_out_ffs = '1') THEN |
IF (s_first_time_reg = '1') THEN |
v_next_state := SET_CS_LO_READ; |
ELSE |
v_next_state := WAIT_DONE; |
END IF; |
ELSE |
v_next_state := WAIT_RDNWR_HI; |
END IF; |
WHEN SET_CS_LO_READ => v_next_state := DO_READ; |
WHEN DO_READ => IF (s_idx_valid = '1' AND |
s_idx_count_reg = "11") THEN |
v_next_state := SET_CS_HI_READ; |
ELSE |
v_next_state := DO_READ; |
END IF; |
WHEN WAIT_DONE => IF (s_done = '1') THEN |
v_next_state := WAIT_AFTER_DONE; |
ELSE |
v_next_state := WAIT_DONE; |
END IF; |
WHEN WAIT_AFTER_DONE => IF (s_wait_counter_reg(7) = '1') THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := WAIT_AFTER_DONE; |
END IF; |
WHEN IDLE => IF (s_fifo_empty = '0') THEN |
v_next_state := RESET_STATE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN DO_FLUSH => IF (s_last_byte = '1' OR |
s_first_time_reg = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := DO_FLUSH; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_fpga_state_reg <= RESET_STATE; |
ELSE s_fpga_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS fpga_state_machine; |
|
------------------------------------------------------------------------------- |
--- Here the identification signals are defined --- |
------------------------------------------------------------------------------- |
|
s_next_idx_byte <= '1' WHEN |
s_fpga_state_reg = DO_WRITE AND |
s_ena_out_ffs = '1' AND |
NOT( s_n_cs_reg = '0' AND |
s_busy = '1' ) AND |
s_first_time_reg = '1' |
ELSE '0'; |
s_last_idx_byte <= '1' WHEN |
s_idx_index_reg = "00000" |
ELSE '0'; |
s_idx_valid <= '1' WHEN |
s_idx_valid_reg = '1' AND |
s_first_time_reg = '1' AND |
s_busy = '0' |
ELSE '0'; |
|
make_idx_valid : PROCESS( clock , s_fpga_state_reg , |
s_ena_in_ffs ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_fpga_state_reg = DO_READ) THEN |
s_idx_valid_reg <= s_ena_in_ffs; |
ELSE |
s_idx_valid_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_idx_valid; |
|
make_idx_count_reg : PROCESS( clock , reset , s_idx_valid ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_idx_count_reg <= "00"; |
ELSIF (s_idx_valid = '1') THEN |
s_idx_count_reg <= unsigned(s_idx_count_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_idx_count_reg; |
|
make_idx_index_reg : PROCESS( clock , reset , s_next_idx_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_idx_index_reg <= "10011"; |
ELSIF (s_next_idx_byte = '1') THEN |
s_idx_index_reg <= unsigned(s_idx_index_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_idx_index_reg; |
|
make_fpga_rev_reg : PROCESS( clock , reset , s_idx_valid , |
s_idx_count_reg , s_data_from_fpga ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_fpga_rev_reg <= X"F"; |
ELSIF (s_idx_valid = '1' AND |
s_idx_count_reg = "00") THEN |
s_fpga_rev_reg <= s_data_from_fpga( 7 DOWNTO 4 ); |
END IF; |
END IF; |
END PROCESS make_fpga_rev_reg; |
|
make_fpga_type_reg : PROCESS( clock , reset , s_idx_valid , |
s_idx_count_reg , s_data_from_fpga ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_fpga_type_reg <= "111"; |
ELSIF (s_idx_valid = '1') THEN |
CASE (s_idx_count_reg) IS |
WHEN "00" => IF (s_data_from_fpga(3 DOWNTO 0) = X"1") THEN |
s_fpga_type_reg <= "000"; |
ELSE |
s_fpga_type_reg <= "111"; |
END IF; |
WHEN "01" => CASE (s_data_from_fpga) IS |
WHEN X"42" => NULL; |
WHEN X"43" => s_fpga_type_reg(0) <= '1'; |
WHEN X"44" => s_fpga_type_reg(1) <= '1'; |
WHEN X"45" => s_fpga_type_reg(2) <= '1'; |
WHEN OTHERS=> s_fpga_type_reg <= "111"; |
END CASE; |
WHEN "10" => CASE (s_data_from_fpga) IS |
WHEN X"00" | |
X"40" => NULL; |
WHEN X"80" => s_fpga_type_reg(0) <= |
s_fpga_type_reg(1); |
WHEN OTHERS => s_fpga_type_reg <= "111"; |
END CASE; |
WHEN OTHERS => IF (s_data_from_fpga /= X"93") THEN |
s_fpga_type_reg <= "111"; |
END IF; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_fpga_type_reg; |
|
make_first_time_reg : PROCESS( clock , reset , s_fpga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_first_time_reg <= '1'; |
ELSIF (s_fpga_state_reg = SET_CS_HI_READ) THEN s_first_time_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_first_time_reg; |
|
idx_rom : idreg_rom |
PORT MAP ( index => s_idx_index_reg, |
data => s_idx_data ); |
|
|
------------------------------------------------------------------------------- |
--- Here the wait counter is defined --- |
------------------------------------------------------------------------------- |
|
s_wait_counter_load <= '1' WHEN |
s_fpga_state_reg = RESET_STATE OR |
s_fpga_state_reg = WAIT_N_INIT_HI OR |
s_fpga_state_reg = SET_RDNWR_LO OR |
s_fpga_state_reg = SET_CS_HI_WRITE OR |
s_fpga_state_reg = SET_RDNWR_HI OR |
s_fpga_state_reg = WAIT_DONE |
ELSE '0'; |
s_wait_counter_ena <= NOT(s_wait_counter_reg(7)) |
WHEN |
s_fpga_state_reg = GENERATE_N_PROG OR |
s_fpga_state_reg = WAIT_AFTER_N_INIT OR |
s_fpga_state_reg = WAIT_RDNWR_LO OR |
s_fpga_state_reg = WAIT_CS_HI_WRITE OR |
s_fpga_state_reg = WAIT_RDNWR_HI OR |
s_fpga_state_reg = WAIT_AFTER_DONE |
ELSE '0'; |
|
make_wait_counter_reg : PROCESS( clock , s_wait_counter_load , |
s_wait_counter_ena ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_wait_counter_load = '1') THEN |
s_wait_counter_reg <= X"7F"; |
ELSIF (s_wait_counter_ena = '1') THEN |
s_wait_counter_reg <= unsigned(s_wait_counter_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_wait_counter_reg; |
|
------------------------------------------------------------------------------- |
--- Here the bitfile handling is defined --- |
------------------------------------------------------------------------------- |
s_fifo_pop <= '1' WHEN s_first_time_reg = '0' AND |
(s_valid_out_byte = '1' OR |
s_fpga_state_reg = DO_FLUSH ) ELSE '0'; |
|
bitfifo : fifo_2kb |
PORT MAP ( clock => clock, |
reset => reset, |
-- push port |
push => push, |
push_data => push_data, |
push_size => last_byte, |
-- pop port |
pop => s_fifo_pop, |
pop_data => s_fifo_data, |
pop_size => s_fifo_last_byte, |
-- control port |
fifo_full => fifo_full, |
fifo_empty => s_fifo_empty ); |
|
|
------------------------------------------------------------------------------- |
--- Here the IOB flipflops are defined --- |
------------------------------------------------------------------------------- |
cclk_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => fpga_cclk, |
C => clock, |
D => s_cclk_reg ); |
n_prog_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => fpga_n_prog, |
C => clock, |
D => s_n_prog_reg ); |
n_cs_ff : FDE |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => fpga_n_cs, |
C => clock, |
CE => s_ena_out_ffs, |
D => s_n_cs_next ); |
rd_n_wr_ff : FDE |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => fpga_rd_n_wr, |
C => clock, |
CE => s_ena_out_ffs, |
D => s_rd_n_wr_reg ); |
n_init_ff : FDE |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_n_init, |
C => clock, |
CE => s_ena_in_ffs, |
D => fpga_n_init ); |
busy_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => s_busy, |
C => clock, |
CE => s_ena_in_ffs, |
D => fpga_busy ); |
done_ff : FDE |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => s_done, |
C => clock, |
CE => s_ena_in_ffs, |
D => fpga_done ); |
|
END no_platform_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/bitfile_interpreter-entity.vhdl
0,0 → 1,74
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY bitfile_interpreter IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
|
-- Here the handshake interface is defined |
start : IN std_logic; |
write_flash : IN std_logic; |
done : OUT std_logic; |
error_detected : OUT std_logic; |
|
-- Here the FX2 fifo interface is defined |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
fifo_empty : IN std_logic; |
|
-- Here the FPGA_IF fifo interface is defined |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
last_byte : OUT std_logic; |
fifo_full : IN std_logic; |
reset_fpga_if : OUT std_logic; |
|
-- Here the flash write fifo interface is defined |
bitfile_size : OUT std_logic_vector(31 DOWNTO 0 ); |
we_fifo : OUT std_logic; |
we_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
we_last : OUT std_logic; |
we_fifo_full : IN std_logic; |
start_write : OUT std_logic; |
size_error : IN std_logic; |
|
-- Here the debug vga interface is defined |
we_char : OUT std_logic; |
ascii_data : OUT std_logic_vector( 7 DOWNTO 0 )); |
END bitfile_interpreter; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/bitfile_interpreter-behavior.vhdl
0,0 → 1,430
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_platform_specific OF bitfile_interpreter IS |
|
TYPE INTERPRETER_STATES IS (IDLE , SIGNAL_DONE , INIT_GET_LENGTH , GET_LENGTH , |
MAKE_FIELD_DESC , INIT_DUMMY_READ , DUMMY_READ , |
GET_FIELD_CHAR , UPDATE_FIELD_ID , |
CHECK_FIELD_CHAR , FLUSH_FIFO , INIT_GET_B_LENGTH , |
GET_B_LENGTH , CHECK_B_LENGTH , INIT_WRITE_STR , |
WRITE_STR , COPY_BITSTREAM , SIGNAL_ERROR , |
EXECUTE_FLUSH_FIFO ); |
TYPE FIELD_TYPES IS (FIELD_1,FIELD_2,FIELD_3,FIELD_4,FIELD_5,FIELD_6, |
FIELD_7,RAW_DATA,HEADER_ERROR); |
|
SIGNAL s_interpreter_state_reg : INTERPRETER_STATES; |
SIGNAL s_current_field_reg : FIELD_TYPES; |
SIGNAL s_down_counter_reg : std_logic_vector( 16 DOWNTO 0 ); |
SIGNAL s_down_counter_load : std_logic; |
SIGNAL s_down_counter_ena : std_logic; |
SIGNAL s_down_counter_load_value : std_logic_vector( 16 DOWNTO 0 ); |
SIGNAL s_field_length_reg : std_logic_vector( 15 DOWNTO 0 ); |
SIGNAL s_pop_a_byte : std_logic; |
SIGNAL s_data_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_ena_data_reg : std_logic; |
SIGNAL s_we_char_reg : std_logic; |
SIGNAL s_bitstream_length_reg : std_logic_vector( 31 DOWNTO 0 ); |
SIGNAL s_push_reg : std_logic; |
SIGNAL s_bitstream_count_reg : std_logic_vector( 32 DOWNTO 0 ); |
SIGNAL s_bitstream_count_next : std_logic_vector( 32 DOWNTO 0 ); |
SIGNAL s_bitstream_count_ena : std_logic; |
SIGNAL s_error_reg : std_logic; |
SIGNAL s_watchdog_timer_reg : std_logic_vector( 11 DOWNTO 0 ); |
SIGNAL s_bitstream_size_reg : std_logic_vector( 31 DOWNTO 0 ); |
SIGNAL s_write_flash_reg : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
pop <= s_pop_a_byte; |
done <= '1' WHEN s_interpreter_state_reg = SIGNAL_DONE ELSE '0'; |
ascii_data <= s_data_reg WHEN s_we_char_reg = '1' ELSE (OTHERS => '0'); |
we_char <= s_we_char_reg; |
push <= s_push_reg AND NOT(s_write_flash_reg); |
push_data <= s_data_reg WHEN s_push_reg = '1' ELSE (OTHERS => '0'); |
last_byte <= s_bitstream_count_reg(32); |
error_detected <= s_error_reg WHEN s_interpreter_state_reg = SIGNAL_DONE ELSE '0'; |
reset_fpga_if <= reset OR s_error_reg; |
bitfile_size <= s_bitstream_size_reg; |
we_data <= s_data_reg; |
we_fifo <= s_push_reg AND s_write_flash_reg; |
we_last <= s_bitstream_count_reg(32) WHEN |
s_interpreter_state_reg = COPY_BITSTREAM ELSE '0'; |
start_write <= '1' WHEN s_interpreter_state_reg = CHECK_B_LENGTH AND |
s_write_flash_reg = '1' ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_pop_a_byte <= '1' WHEN |
((s_interpreter_state_reg = GET_LENGTH OR |
s_interpreter_state_reg = DUMMY_READ OR |
s_interpreter_state_reg = WRITE_STR OR |
s_interpreter_state_reg = GET_B_LENGTH) AND |
fifo_empty = '0' AND |
we_fifo_full = '0' AND |
s_down_counter_reg(16) = '0') OR |
(s_interpreter_state_reg = GET_FIELD_CHAR AND |
fifo_empty = '0' AND |
we_fifo_full = '0') OR |
(s_interpreter_state_reg = COPY_BITSTREAM AND |
fifo_empty = '0' AND |
fifo_full = '0' AND |
we_fifo_full = '0' AND |
s_bitstream_count_reg(32) = '0') OR |
(s_interpreter_state_reg = EXECUTE_FLUSH_FIFO AND |
fifo_empty = '0' AND |
s_bitstream_count_reg(32) = '0') |
ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the intermediate data buffer is defined --- |
-------------------------------------------------------------------------------- |
s_ena_data_reg <= s_pop_a_byte; |
|
make_data_reg : PROCESS( clock , reset , s_ena_data_reg , pop_data ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_data_reg <= X"FF"; |
ELSIF (s_ena_data_reg = '1') THEN s_data_reg <= pop_data; |
END IF; |
END IF; |
END PROCESS make_data_reg; |
|
make_we_char : PROCESS( clock , s_interpreter_state_reg , s_pop_a_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = WRITE_STR) THEN |
s_we_char_reg <= s_pop_a_byte; |
ELSE |
s_we_char_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_we_char; |
|
make_push_reg : PROCESS( clock , s_interpreter_state_reg , s_pop_a_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = COPY_BITSTREAM OR |
(s_interpreter_state_reg /= EXECUTE_FLUSH_FIFO AND |
s_write_flash_reg = '1')) THEN |
s_push_reg <= s_pop_a_byte; |
ELSE |
s_push_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_push_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the general purpose down counter is defined --- |
-------------------------------------------------------------------------------- |
s_down_counter_load <= '1' WHEN |
s_interpreter_state_reg = INIT_GET_LENGTH OR |
s_interpreter_state_reg = INIT_DUMMY_READ OR |
s_interpreter_state_reg = INIT_WRITE_STR OR |
s_interpreter_state_reg = INIT_GET_B_LENGTH |
ELSE '0'; |
s_down_counter_ena <= '1' WHEN |
((s_interpreter_state_reg = GET_LENGTH OR |
s_interpreter_state_reg = DUMMY_READ OR |
s_interpreter_state_reg = WRITE_STR OR |
s_interpreter_state_reg = GET_B_LENGTH) AND |
s_pop_a_byte = '1') |
ELSE '0'; |
|
make_down_counter_load_value : PROCESS( s_interpreter_state_reg , |
s_field_length_reg ) |
VARIABLE v_length : std_logic_vector( 16 DOWNTO 0 ); |
BEGIN |
CASE (s_interpreter_state_reg) IS |
WHEN INIT_GET_LENGTH => s_down_counter_load_value <= "0"&X"0001"; |
WHEN INIT_GET_B_LENGTH => s_down_counter_load_value <= "0"&X"0003"; |
WHEN OTHERS => v_length := "0"&s_field_length_reg; |
s_down_counter_load_value <= |
unsigned(v_length) - 1; |
END CASE; |
END PROCESS make_down_counter_load_value; |
|
make_down_counter : PROCESS( clock , s_down_counter_reg , |
s_down_counter_load , s_down_counter_ena , |
s_down_counter_load_value ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_down_counter_load = '1') THEN |
s_down_counter_reg <= s_down_counter_load_value; |
ELSIF (s_down_counter_ena = '1') THEN |
s_down_counter_reg <= unsigned(s_down_counter_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_down_counter; |
|
-------------------------------------------------------------------------------- |
--- Here the field length reg is defined --- |
-------------------------------------------------------------------------------- |
make_field_reg : PROCESS( clock , reset , s_interpreter_state_reg , pop_data , |
s_down_counter_reg , s_pop_a_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_field_length_reg <= (OTHERS => '0'); |
ELSIF (s_interpreter_state_reg = GET_LENGTH AND |
s_pop_a_byte = '1') THEN |
IF (s_down_counter_reg(0) = '1') THEN |
s_field_length_reg(15 DOWNTO 8) <= pop_data; |
ELSE |
s_field_length_reg( 7 DOWNTO 0) <= pop_data; |
END IF; |
END IF; |
END IF; |
END PROCESS make_field_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_state_machine : PROCESS( clock , reset , s_interpreter_state_reg , |
start , s_down_counter_reg , |
s_current_field_reg , |
s_bitstream_count_reg , s_watchdog_timer_reg ) |
VARIABLE v_next_state : INTERPRETER_STATES; |
BEGIN |
CASE (s_interpreter_state_reg) IS |
WHEN IDLE => IF (start = '1') THEN |
v_next_state := INIT_GET_LENGTH; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_GET_LENGTH => v_next_state := GET_LENGTH; |
WHEN GET_LENGTH => IF (s_down_counter_reg(16) = '1') THEN |
v_next_state := MAKE_FIELD_DESC; |
ELSE |
v_next_state := GET_LENGTH; |
END IF; |
WHEN MAKE_FIELD_DESC => CASE (s_current_field_reg) IS |
WHEN FIELD_1 => v_next_state := INIT_DUMMY_READ; |
WHEN FIELD_2 => v_next_state := GET_FIELD_CHAR; |
WHEN FIELD_3 | |
FIELD_4 | |
FIELD_5 | |
FIELD_6 => v_next_state := INIT_WRITE_STR; |
WHEN OTHERS => v_next_state := FLUSH_FIFO; |
END CASE; |
WHEN INIT_DUMMY_READ => v_next_state := DUMMY_READ; |
WHEN DUMMY_READ => IF (s_down_counter_reg(16) = '1') THEN |
v_next_state := INIT_GET_LENGTH; |
ELSE |
v_next_state := DUMMY_READ; |
END IF; |
WHEN GET_FIELD_CHAR => IF (s_pop_a_byte = '1') THEN |
v_next_state := UPDATE_FIELD_ID; |
ELSE |
v_next_state := GET_FIELD_CHAR; |
END IF; |
WHEN UPDATE_FIELD_ID => v_next_state := CHECK_FIELD_CHAR; |
WHEN CHECK_FIELD_CHAR => CASE (s_current_field_reg) IS |
WHEN HEADER_ERROR => v_next_state := FLUSH_FIFO; |
WHEN FIELD_7 => v_next_state := INIT_GET_B_LENGTH; |
WHEN OTHERS => v_next_state := INIT_GET_LENGTH; |
END CASE; |
WHEN INIT_GET_B_LENGTH => v_next_state := GET_B_LENGTH; |
WHEN GET_B_LENGTH => IF(s_down_counter_reg(16) = '1') THEN |
v_next_state := CHECK_B_LENGTH; |
ELSE |
v_next_state := GET_B_LENGTH; |
END IF; |
WHEN CHECK_B_LENGTH => v_next_state := COPY_BITSTREAM; |
WHEN COPY_BITSTREAM => IF (size_error = '1') THEN |
v_next_state := IDLE; |
ELSIF (s_bitstream_count_reg(32) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := COPY_BITSTREAM; |
END IF; |
WHEN INIT_WRITE_STR => v_next_state := WRITE_STR; |
WHEN WRITE_STR => IF (s_down_counter_reg(16) = '1') THEN |
v_next_state := GET_FIELD_CHAR; |
ELSE |
v_next_state := WRITE_STR; |
END IF; |
WHEN FLUSH_FIFO => v_next_state := EXECUTE_FLUSH_FIFO; |
WHEN SIGNAL_ERROR => v_next_state := SIGNAL_DONE; |
WHEN EXECUTE_FLUSH_FIFO => IF (pop_last = '1' AND |
s_pop_a_byte = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := EXECUTE_FLUSH_FIFO; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_interpreter_state_reg <= IDLE; |
ELSIF (s_watchdog_timer_reg(11) = '1') THEN |
s_interpreter_state_reg <= SIGNAL_ERROR; |
ELSE |
s_interpreter_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the current field identifier is defined --- |
-------------------------------------------------------------------------------- |
make_field_id : PROCESS( clock , s_interpreter_state_reg , s_data_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
CASE (s_interpreter_state_reg) IS |
WHEN IDLE => s_current_field_reg <= FIELD_1; |
WHEN INIT_DUMMY_READ => s_current_field_reg <= FIELD_2; |
WHEN UPDATE_FIELD_ID => CASE (s_data_reg) IS |
WHEN X"61" => s_current_field_reg <= FIELD_3; |
WHEN X"62" => s_current_field_reg <= FIELD_4; |
WHEN X"63" => s_current_field_reg <= FIELD_5; |
WHEN X"64" => s_current_field_reg <= FIELD_6; |
WHEN X"65" => s_current_field_reg <= FIELD_7; |
WHEN OTHERS=> s_current_field_reg <= HEADER_ERROR; |
END CASE; |
WHEN OTHERS => NULL; |
END CASE; |
END IF; |
END PROCESS make_field_id; |
|
-------------------------------------------------------------------------------- |
--- Here the bitstream length reg is defined --- |
-------------------------------------------------------------------------------- |
make_bitstream_length_reg : PROCESS( clock , s_interpreter_state_reg , |
s_pop_a_byte , s_down_counter_reg , |
pop_data ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = GET_B_LENGTH AND |
s_pop_a_byte = '1') THEN |
CASE (s_down_counter_reg(1 DOWNTO 0)) IS |
WHEN "11" => s_bitstream_length_reg( 31 DOWNTO 24 ) <= pop_data; |
WHEN "10" => s_bitstream_length_reg( 23 DOWNTO 16 ) <= pop_data; |
WHEN "01" => s_bitstream_length_reg( 15 DOWNTO 8 ) <= pop_data; |
WHEN OTHERS => s_bitstream_length_reg( 7 DOWNTO 0 ) <= pop_data; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_bitstream_length_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the bitstream counter is defined --- |
-------------------------------------------------------------------------------- |
s_bitstream_count_ena <= '1' WHEN (s_interpreter_state_reg = COPY_BITSTREAM OR |
s_interpreter_state_reg = EXECUTE_FLUSH_FIFO) AND |
s_pop_a_byte = '1' ELSE '0'; |
|
s_bitstream_count_next <= unsigned(s_bitstream_count_reg) - 1; |
|
make_bitstream_count_reg : PROCESS( clock , s_interpreter_state_reg , |
s_bitstream_count_ena , |
s_bitstream_count_next ) |
VARIABLE v_length : std_logic_vector( 32 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = GET_B_LENGTH AND |
s_pop_a_byte = '1') THEN |
CASE (s_down_counter_reg(1 DOWNTO 0)) IS |
WHEN "11" => s_bitstream_count_reg( 32 DOWNTO 24 ) <= "0"&pop_data; |
WHEN "10" => s_bitstream_count_reg( 23 DOWNTO 16 ) <= pop_data; |
WHEN "01" => s_bitstream_count_reg( 15 DOWNTO 8 ) <= pop_data; |
WHEN OTHERS => s_bitstream_count_reg( 7 DOWNTO 0 ) <= pop_data; |
END CASE; |
ELSIF (s_bitstream_count_ena = '1' OR |
s_interpreter_state_reg = CHECK_B_LENGTH) THEN |
s_bitstream_count_reg <= s_bitstream_count_next; |
END IF; |
END IF; |
END PROCESS make_bitstream_count_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the error reg is defined --- |
-------------------------------------------------------------------------------- |
make_error_reg : PROCESS( clock , s_interpreter_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = IDLE) THEN s_error_reg <= '0'; |
ELSIF (s_interpreter_state_reg = SIGNAL_ERROR) THEN s_error_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_error_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the watchdog timer is defined --- |
-------------------------------------------------------------------------------- |
make_watchdog_timer_reg : PROCESS( clock , s_interpreter_state_reg , |
s_pop_a_byte , s_watchdog_timer_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = IDLE OR |
s_interpreter_state_reg = SIGNAL_ERROR OR |
s_pop_a_byte = '1') THEN |
s_watchdog_timer_reg <= (11=>'0' , OTHERS => '1'); |
ELSIF (s_watchdog_timer_reg(11) = '0' AND |
msec_tick = '1') THEN |
s_watchdog_timer_reg <= unsigned(s_watchdog_timer_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_watchdog_timer_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the bitstream size count reg is defined --- |
-------------------------------------------------------------------------------- |
make_bitstream_size_reg : PROCESS( clock , s_pop_a_byte , |
s_interpreter_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_interpreter_state_reg = IDLE) THEN |
s_bitstream_size_reg <= (OTHERS => '0'); |
ELSIF (s_interpreter_state_reg /= COPY_BITSTREAM AND |
s_interpreter_state_reg /= FLUSH_FIFO AND |
s_pop_a_byte = '1') THEN |
s_bitstream_size_reg <= unsigned(s_bitstream_size_reg) + 1; |
ELSIF (s_interpreter_state_reg = CHECK_B_LENGTH) THEN |
s_bitstream_size_reg <= unsigned(s_bitstream_size_reg) + |
unsigned(s_bitstream_length_reg); |
END IF; |
END IF; |
END PROCESS make_bitstream_size_reg; |
|
make_write_flash_reg : PROCESS( clock , reset , start , write_flash ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_write_flash_reg <= '0'; |
ELSIF (start = '1') THEN s_write_flash_reg <= write_flash; |
END IF; |
END IF; |
END PROCESS make_write_flash_reg; |
|
END no_platform_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fpga_if/idreg_rom-entity.vhdl
0,0 → 1,40
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
ENTITY idreg_rom IS |
PORT( index : IN std_logic_vector( 4 DOWNTO 0 ); |
data : OUT std_logic_vector( 7 DOWNTO 0 ) ); |
END idreg_rom; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/flash/flash-behavior-xilinx.vhdl
0,0 → 1,1112
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF flash_if IS |
|
COMPONENT FDE |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
CE : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FDE_1 |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
CE : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FD |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT FD_1 |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT fifo_2kb |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_size : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT RAMB16_S9_S18 |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0 ); |
DOPA : OUT std_logic_vector( 0 DOWNTO 0 ); |
ADDRA : IN std_logic_vector(10 DOWNTO 0 ); |
CLKA : IN std_logic; |
DIA : IN std_logic_vector( 7 DOWNTO 0 ); |
DIPA : IN std_logic_vector( 0 DOWNTO 0 ); |
ENA : IN std_logic; |
SSRA : IN std_logic; |
WEA : IN std_logic; |
DOB : OUT std_logic_vector(15 DOWNTO 0 ); |
DOPB : OUT std_logic_vector( 1 DOWNTO 0 ); |
ADDRB : IN std_logic_vector( 9 DOWNTO 0 ); |
CLKB : IN std_logic; |
DIB : IN std_logic_vector(15 DOWNTO 0 ); |
DIPB : IN std_logic_vector( 1 DOWNTO 0 ); |
ENB : IN std_logic; |
SSRB : IN std_logic; |
WEB : IN std_logic ); |
END COMPONENT; |
|
TYPE FLASH_STATE_TYPE IS (RESET_STATE , SET_AUTOSELECT , READ_ID , IDLE , |
CHECK_ID , AUTO_NOP , RESET_AUTO , RESET_NOP , |
READ_HW , CHECK_HW , SIGNAL_DONE , INIT_ERASE_S1 , |
ERASE_S1 , WAIT_BUSY_LO , WAIT_BUSY_HI , NOP_READ, |
INIT_READ , COPY_PAYLOAD , CHECK_SIZE , PLAY_WRITE , |
SIGNAL_ERROR , RESET_FIFO , INIT_WRITE , DO_WRITE , |
WAIT_READY_LO , WAIT_READY_HI , WRITE_UPDATE , |
INIT_CHECK_EMPTY , CHECK_EMPTY , DO_PUD_WRITE , |
SET_PUD_SIZE_1 , SET_PUD_SIZE_2 , DO_PUD_READ , |
COPY_PUD_DATA , NEXT_SECTOR , SIGNAL_INIT ); |
|
CONSTANT c_vga_offset : std_logic_vector( 4 DOWNTO 0 ) := "10010"; |
|
SIGNAL s_flash_state_reg : FLASH_STATE_TYPE; |
SIGNAL s_delay_counter_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_player_count_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_command_byte : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_byte_address : std_logic_vector(20 DOWNTO 0 ); |
SIGNAL s_flash_data_in : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_data_out_next : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_tri_data_out : std_logic; |
SIGNAL s_flash_n_ce : std_logic; |
SIGNAL s_flash_n_oe : std_logic; |
SIGNAL s_flash_n_we : std_logic; |
SIGNAL s_state_tick : std_logic; |
|
SIGNAL s_sector_address_reg : std_logic_vector(20 DOWNTO 16); |
SIGNAL s_pud_sector_address : std_logic_vector(20 DOWNTO 16); |
SIGNAL s_in_sector_address_reg : std_logic_vector(15 DOWNTO 1); |
SIGNAL s_flash_mounted_reg : std_logic; |
SIGNAL s_flash_top_boot_reg : std_logic; |
SIGNAL s_flash_sec1_empty_reg : std_logic; |
SIGNAL s_next_address : std_logic; |
SIGNAL s_next_in_sector_addr : std_logic_vector(16 DOWNTO 1); |
|
SIGNAL s_word_data_reg : std_logic_vector(15 DOWNTO 0); |
SIGNAL s_word_bytes_valid_reg : std_logic_vector( 1 DOWNTO 0); |
SIGNAL s_latch_read_data : std_logic; |
SIGNAL s_fifo_read_info_reg : std_logic_vector( 2 DOWNTO 0); |
SIGNAL s_push_lo : std_logic; |
SIGNAL s_push_hi : std_logic; |
SIGNAL s_payload_size_cnt_reg : std_logic_vector(21 DOWNTO 0); |
SIGNAL s_payload_size_cnt_next : std_logic_vector(21 DOWNTO 0); |
|
SIGNAL s_fifo_empty : std_logic; |
SIGNAL s_fifo_pop : std_logic; |
SIGNAL s_fifo_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_fifo_pop_last : std_logic; |
SIGNAL s_fifo_word_reg : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_fifo_word_valid_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_invalid_size : std_logic; |
SIGNAL s_last_byte_reg : std_logic; |
SIGNAL s_fifo_reset : std_logic; |
|
SIGNAL s_write_idx_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_write_data_reg : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_write_size : std_logic; |
SIGNAL s_write_data : std_logic; |
SIGNAL s_done_reg : std_logic; |
SIGNAL s_write_done_reg : std_logic; |
SIGNAL s_empty_cnt_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_write_empty : std_logic; |
SIGNAL s_empty_size : std_logic; |
SIGNAL s_empty_data : std_logic_vector( 7 DOWNTO 0 ); |
|
SIGNAL s_start_pud_write : std_logic; |
SIGNAL s_start_pud_read : std_logic; |
SIGNAL s_is_pud_action_reg : std_logic; |
SIGNAL s_pud_word : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_write_pud : std_logic; |
SIGNAL s_we_pud_byte : std_logic; |
SIGNAL s_ena_pud_byte : std_logic; |
SIGNAL s_pud_byte_addr_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_ena_pud_word_read : std_logic; |
SIGNAL s_scpi_push : std_logic; |
SIGNAL s_scpi_n_reset : std_logic; |
SIGNAL s_pud_byte : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pud_size_value : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pud_word_address_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_we_pud_payload : std_logic; |
SIGNAL s_busy_pipe_reg : std_logic_vector( 3 DOWNTO 0 ); |
|
SIGNAL s_we_vga : std_logic; |
SIGNAL s_we_addr : std_logic_vector(10 DOWNTO 0); |
SIGNAL s_we_data : std_logic_vector( 7 DOWNTO 0); |
SIGNAL s_pud_hi_reg : std_logic; |
SIGNAL s_time_out_cnt_reg : std_logic_vector( 3 DOWNTO 0 ); |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
flash_n_byte <= '1'; |
flash_idle <= '1' WHEN s_flash_state_reg = IDLE ELSE '0'; |
flash_n_busy <= '0' WHEN s_flash_state_reg = INIT_CHECK_EMPTY OR |
s_flash_state_reg = CHECK_EMPTY OR |
s_flash_state_reg = INIT_ERASE_S1 OR |
s_flash_state_reg = ERASE_S1 OR |
s_flash_state_reg = WAIT_BUSY_LO OR |
s_flash_state_reg = WAIT_BUSY_HI OR |
s_flash_state_reg = NEXT_SECTOR OR |
s_flash_state_reg = INIT_WRITE OR |
s_flash_state_reg = PLAY_WRITE OR |
s_flash_state_reg = DO_WRITE OR |
s_flash_state_reg = WAIT_READY_LO OR |
s_flash_state_reg = WAIT_READY_HI OR |
s_flash_state_reg = WRITE_UPDATE OR |
reset = '1' ELSE '1'; |
done <= '1' WHEN s_flash_state_reg = SIGNAL_DONE OR |
s_done_reg = '1' ELSE '0'; |
flash_present <= s_flash_mounted_reg; |
flash_s1_empty <= s_flash_sec1_empty_reg; |
push <= ((s_push_lo OR s_push_hi) AND |
NOT(s_payload_size_cnt_reg(21))) OR s_write_empty; |
push_data <= s_word_data_reg( 7 DOWNTO 0 ) WHEN s_push_lo = '1' ELSE |
s_word_data_reg(15 DOWNTO 8 ) WHEN s_push_hi = '1' ELSE |
s_empty_data; |
push_last <= (s_push_lo OR s_push_hi) AND s_payload_size_cnt_next(21); |
push_size <= (NOT(s_fifo_read_info_reg(2)) AND |
(s_push_lo OR s_push_hi)) OR s_empty_size; |
size_error <= '1' WHEN s_flash_state_reg = SIGNAL_ERROR ELSE '0'; |
s_fifo_reset <= '1' WHEN reset = '1' OR |
s_flash_state_reg = RESET_FIFO ELSE '0'; |
scpi_pop <= s_we_pud_byte; |
scpi_push_data <= s_pud_size_value OR s_pud_byte; |
|
start_config <= '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_flash_n_ce <= '1' WHEN reset = '1' OR |
s_flash_state_reg = IDLE OR |
s_flash_state_reg = SIGNAL_DONE ELSE '0'; |
s_flash_n_oe <= '0' WHEN s_flash_state_reg = READ_ID OR |
s_flash_state_reg = RESET_NOP OR |
s_flash_state_reg = READ_HW OR |
s_flash_state_reg = NOP_READ OR |
s_flash_state_reg = INIT_READ OR |
s_flash_state_reg = CHECK_HW OR |
s_flash_state_reg = COPY_PAYLOAD OR |
s_flash_state_reg = INIT_CHECK_EMPTY OR |
s_flash_state_reg = CHECK_EMPTY OR |
s_flash_state_reg = COPY_PUD_DATA ELSE '1'; |
s_tri_data_out <= '0' WHEN s_flash_state_reg = SET_AUTOSELECT OR |
s_flash_state_reg = RESET_AUTO OR |
s_flash_state_reg = ERASE_S1 OR |
s_flash_state_reg = PLAY_WRITE OR |
s_flash_state_reg = DO_WRITE ELSE '1'; |
s_flash_n_we <= '0' WHEN (s_delay_counter_reg(1 DOWNTO 0) = "01" OR |
s_delay_counter_reg(1 DOWNTO 0) = "10") AND |
(s_flash_state_reg = SET_AUTOSELECT OR |
s_flash_state_reg = RESET_AUTO OR |
s_flash_state_reg = ERASE_S1 OR |
s_flash_state_reg = PLAY_WRITE OR |
s_flash_state_reg = DO_WRITE) ELSE '1'; |
s_state_tick <= s_delay_counter_reg(1) AND s_delay_counter_reg(0); |
s_next_address <= '1' WHEN (s_delay_counter_reg = "011" AND |
((s_word_bytes_valid_reg = "00" AND |
s_flash_state_reg = COPY_PAYLOAD) OR |
s_flash_state_reg = CHECK_HW OR |
s_flash_state_reg = COPY_PUD_DATA OR |
s_flash_state_reg = CHECK_EMPTY)) OR |
s_flash_state_reg = WRITE_UPDATE ELSE '0'; |
s_latch_read_data <= '1' WHEN s_word_bytes_valid_reg = "00" AND |
s_delay_counter_reg(2) = '1' AND |
s_flash_state_reg = COPY_PAYLOAD ELSE '0'; |
s_next_in_sector_addr <= unsigned("0"&s_in_sector_address_reg) + 1; |
s_invalid_size <= '1' WHEN bitfile_size(31 DOWNTO 21) /= "000"&X"00" OR |
bitfile_size(20 DOWNTO 16) = "11111" ELSE '0'; |
|
make_addr_data : PROCESS( s_player_count_reg , s_command_byte , |
s_sector_address_reg , s_in_sector_address_reg , |
s_write_data_reg ) |
BEGIN |
CASE (s_player_count_reg) IS |
WHEN "001" | |
"101" => s_byte_address <= "0"&X"00AAA"; |
s_data_out_next <= X"00AA"; |
WHEN "010" | |
"110" => s_byte_address <= "0"&X"00555"; |
s_data_out_next <= X"0055"; |
WHEN "011" => s_byte_address <= "0"&X"00AAA"; |
s_data_out_next <= X"00"&s_command_byte; |
WHEN "111" => s_byte_address <= s_sector_address_reg&X"0000"; |
s_data_out_next <= X"00"&s_command_byte; |
WHEN OTHERS => s_byte_address <= s_sector_address_reg& |
s_in_sector_address_reg&"0"; |
s_data_out_next <= s_write_data_reg; |
END CASE; |
END PROCESS make_addr_data; |
|
make_done_reg : PROCESS( clock , start_read ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
s_done_reg <= start_read; |
END IF; |
END PROCESS make_done_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the empty message is defined --- |
-------------------------------------------------------------------------------- |
s_write_empty <= '0' WHEN fifo_full = '1' OR |
s_empty_cnt_reg = "000" ELSE '1'; |
s_empty_size <= '1' WHEN s_empty_cnt_reg = "111" ELSE '0'; |
|
make_empty_data : PROCESS(s_empty_cnt_reg) |
BEGIN |
CASE (s_empty_cnt_reg) IS |
WHEN "111" => s_empty_data <= X"06"; |
WHEN "110" => s_empty_data <= X"45"; |
WHEN "101" => s_empty_data <= X"4D"; |
WHEN "100" => s_empty_data <= X"50"; |
WHEN "011" => s_empty_data <= X"54"; |
WHEN "010" => s_empty_data <= X"59"; |
WHEN "001" => s_empty_data <= X"0A"; |
WHEN OTHERS => s_empty_data <= X"00"; |
END CASE; |
END PROCESS make_empty_data; |
|
make_empty_cnt_reg : PROCESS( clock , reset , start_read , s_write_empty , |
s_empty_cnt_reg , s_flash_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_empty_cnt_reg <= "000"; |
ELSIF (start_read = '1' AND |
s_flash_sec1_empty_reg = '1' AND |
s_flash_state_reg = IDLE) THEN |
s_empty_cnt_reg <= "111"; |
ELSIF (s_write_empty = '1') THEN |
s_empty_cnt_reg <= unsigned(s_empty_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_empty_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_state_machine : PROCESS( clock , reset , s_flash_state_reg , |
s_state_tick , s_player_count_reg , start_erase, |
s_flash_sec1_empty_reg ) |
VARIABLE v_next_state : FLASH_STATE_TYPE; |
BEGIN |
CASE (s_flash_state_reg) IS |
WHEN RESET_STATE => IF (s_state_tick = '1') THEN |
v_next_state := SET_AUTOSELECT; |
ELSE |
v_next_state := RESET_STATE; |
END IF; |
WHEN SET_AUTOSELECT => IF (s_player_count_reg = "000" AND |
s_state_tick = '1') THEN |
v_next_state := AUTO_NOP; |
ELSE |
v_next_state := SET_AUTOSELECT; |
END IF; |
WHEN AUTO_NOP => IF (s_state_tick = '1') THEN |
v_next_state := READ_ID; |
ELSE |
v_next_state := AUTO_NOP; |
END IF; |
WHEN READ_ID => IF (s_state_tick = '1') THEN |
v_next_state := CHECK_ID; |
ELSE |
v_next_state := READ_ID; |
END IF; |
WHEN CHECK_ID => IF (s_state_tick = '1') THEN |
v_next_state := RESET_AUTO; |
ELSE |
v_next_state := CHECK_ID; |
END IF; |
WHEN RESET_AUTO => IF (s_state_tick = '1') THEN |
v_next_state := RESET_NOP; |
ELSE |
v_next_state := RESET_AUTO; |
END IF; |
WHEN RESET_NOP => IF (s_state_tick = '1') THEN |
v_next_state := READ_HW; |
ELSE |
v_next_state := RESET_NOP; |
END IF; |
WHEN READ_HW => IF (s_state_tick = '1') THEN |
v_next_state := CHECK_HW; |
ELSE |
v_next_state := READ_HW; |
END IF; |
WHEN CHECK_HW => IF (s_state_tick = '1') THEN |
IF (s_flash_mounted_reg = '1') THEN |
v_next_state := COPY_PUD_DATA; |
ELSE |
v_next_state := IDLE; |
END IF; |
ELSE |
v_next_state := CHECK_HW; |
END IF; |
WHEN COPY_PUD_DATA => IF (s_state_tick = '1' AND |
s_in_sector_address_reg(11) = '1') THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := COPY_PUD_DATA; |
END IF; |
WHEN IDLE => IF (s_start_pud_write = '1') THEN |
v_next_state := DO_PUD_WRITE; |
ELSIF (s_start_pud_read = '1') THEN |
v_next_state := SET_PUD_SIZE_1; |
ELSIF (start_erase = '1') THEN |
IF (s_flash_sec1_empty_reg = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := INIT_CHECK_EMPTY; |
END IF; |
ELSIF (start_read = '1' AND |
s_flash_sec1_empty_reg = '0') THEN |
v_next_state := NOP_READ; |
ELSIF (start_write = '1') THEN |
IF (s_flash_sec1_empty_reg = '0') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := CHECK_SIZE; |
END IF; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_CHECK_EMPTY => IF (s_delay_counter_reg(2) = '1') THEN |
v_next_state := CHECK_EMPTY; |
ELSE |
v_next_state := INIT_CHECK_EMPTY; |
END IF; |
WHEN CHECK_EMPTY => IF (s_state_tick = '1') THEN |
IF (s_sector_address_reg = |
s_pud_sector_address) THEN |
v_next_state := SIGNAL_DONE; |
ELSIF (s_flash_data_in = X"FFFF") THEN |
v_next_state := CHECK_EMPTY; |
ELSE |
v_next_state := INIT_ERASE_S1; |
END IF; |
ELSE |
v_next_state := CHECK_EMPTY; |
END IF; |
WHEN INIT_ERASE_S1 => IF (s_state_tick = '1') THEN |
v_next_state := ERASE_S1; |
ELSE |
v_next_state := INIT_ERASE_S1; |
END IF; |
WHEN ERASE_S1 => IF (s_player_count_reg = "000" AND |
s_state_tick = '1') THEN |
v_next_state := WAIT_BUSY_LO; |
ELSE |
v_next_state := ERASE_S1; |
END IF; |
WHEN WAIT_BUSY_LO => IF (s_time_out_cnt_reg(3) = '1') THEN |
v_next_state := INIT_ERASE_S1; |
ELSIF (s_busy_pipe_reg(3) = '0') THEN |
v_next_state := WAIT_BUSY_HI; |
ELSE |
v_next_state := WAIT_BUSY_LO; |
END IF; |
WHEN WAIT_BUSY_HI => IF (s_busy_pipe_reg(3) = '1') THEN |
IF (s_is_pud_action_reg = '1') THEN |
v_next_state := INIT_WRITE; |
ELSE |
v_next_state := NEXT_SECTOR; |
END IF; |
ELSE |
v_next_state := WAIT_BUSY_HI; |
END IF; |
WHEN NEXT_SECTOR => v_next_state := INIT_CHECK_EMPTY; |
WHEN NOP_READ => IF (s_delay_counter_reg(2) = '1') THEN |
v_next_state := INIT_READ; |
ELSE |
v_next_state := NOP_READ; |
END IF; |
WHEN INIT_READ => IF (s_delay_counter_reg(2) = '1') THEN |
v_next_state := COPY_PAYLOAD; |
ELSE |
v_next_state := INIT_READ; |
END IF; |
WHEN COPY_PAYLOAD => IF (s_payload_size_cnt_reg(21) = '1' AND |
s_delay_counter_reg = "011") THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := COPY_PAYLOAD; |
END IF; |
WHEN CHECK_SIZE => IF (s_invalid_size = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := INIT_WRITE; |
END IF; |
WHEN INIT_WRITE => IF (s_write_size = '1' OR |
s_write_data = '1' OR |
s_write_pud = '1') THEN |
v_next_state := PLAY_WRITE; |
ELSE |
v_next_state := INIT_WRITE; |
END IF; |
WHEN PLAY_WRITE => IF (s_player_count_reg = "000" AND |
s_state_tick = '1') THEN |
v_next_state := DO_WRITE; |
ELSE |
v_next_state := PLAY_WRITE; |
END IF; |
WHEN DO_WRITE => IF (s_state_tick = '1') THEN |
v_next_state := WAIT_READY_LO; |
ELSE |
v_next_state := DO_WRITE; |
END IF; |
WHEN WAIT_READY_LO => IF (s_busy_pipe_reg(3) = '0') THEN |
v_next_state := WAIT_READY_HI; |
ELSE |
v_next_state := WAIT_READY_LO; |
END IF; |
WHEN WAIT_READY_HI => IF (s_busy_pipe_reg(3) = '1') THEN |
v_next_state := WRITE_UPDATE; |
ELSE |
v_next_state := WAIT_READY_HI; |
END IF; |
WHEN WRITE_UPDATE => IF (s_write_done_reg = '1') THEN |
IF (s_is_pud_action_reg = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := SIGNAL_INIT; |
END IF; |
ELSE |
v_next_state := INIT_WRITE; |
END IF; |
WHEN SIGNAL_ERROR => v_next_state := RESET_FIFO; |
WHEN DO_PUD_WRITE => IF (s_we_pud_byte = '1' AND |
scpi_pop_last = '1') THEN |
IF (s_flash_mounted_reg = '1') THEN |
v_next_state := INIT_ERASE_S1; |
ELSE |
v_next_state := SIGNAL_DONE; |
END IF; |
ELSE |
v_next_state := DO_PUD_WRITE; |
END IF; |
WHEN SET_PUD_SIZE_1 => IF (s_scpi_push = '1') THEN |
v_next_state := SET_PUD_SIZE_2; |
ELSE |
v_next_state := SET_PUD_SIZE_1; |
END IF; |
WHEN SET_PUD_SIZE_2 => IF (s_scpi_push = '1') THEN |
v_next_state := DO_PUD_READ; |
ELSE |
v_next_state := SET_PUD_SIZE_2; |
END IF; |
WHEN DO_PUD_READ => IF (s_pud_byte_addr_reg(11) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := DO_PUD_READ; |
END IF; |
WHEN SIGNAL_INIT => v_next_state := SIGNAL_DONE; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_flash_state_reg <= RESET_STATE; |
ELSE s_flash_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
make_time_out_cnt_reg : PROCESS( clock , reset , s_flash_state_reg , |
msec_tick ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_time_out_cnt_reg <= X"F"; |
ELSIF (s_flash_state_reg = ERASE_S1) THEN |
s_time_out_cnt_reg <= X"7"; |
ELSIF (s_time_out_cnt_reg(3) = '0' AND |
msec_tick = '1') THEN |
s_time_out_cnt_reg <= unsigned(s_time_out_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_time_out_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the word to byte handling is defined --- |
-------------------------------------------------------------------------------- |
s_push_lo <= '1' WHEN fifo_full = '0' AND |
s_word_bytes_valid_reg(0) = '1' AND |
s_delay_counter_reg = "000" ELSE '0'; |
s_push_hi <= '1' WHEN fifo_full = '0' AND |
s_word_bytes_valid_reg = "10" AND |
s_delay_counter_reg = "010" ELSE '0'; |
s_payload_size_cnt_next <= unsigned(s_payload_size_cnt_reg) - 1; |
|
make_word_regs : PROCESS( clock , s_flash_state_reg , s_latch_read_data ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE) THEN |
s_word_data_reg <= (OTHERS => '0'); |
s_word_bytes_valid_reg <= (OTHERS => '0'); |
ELSIF (s_latch_read_data = '1') THEN |
s_word_data_reg <= s_flash_data_in; |
s_word_bytes_valid_reg <= "11"; |
ELSIF (s_push_lo = '1') THEN |
s_word_bytes_valid_reg(0) <= '0'; |
ELSIF (s_push_hi = '1') THEN |
s_word_bytes_valid_reg(1) <= '0'; |
END IF; |
END IF; |
END PROCESS make_word_regs; |
|
make_fifo_read_info_reg : PROCESS( clock , s_flash_state_reg , reset , |
s_push_lo , s_push_hi ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE OR |
reset = '1') THEN s_fifo_read_info_reg <= "000"; |
ELSIF ((s_push_lo = '1' OR |
s_push_hi = '1') AND |
s_fifo_read_info_reg(2) = '0') THEN |
s_fifo_read_info_reg <= unsigned(s_fifo_read_info_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_fifo_read_info_reg; |
|
make_payload_size_cnt_reg : PROCESS( clock , s_flash_state_reg , |
s_push_lo , s_push_hi , |
s_payload_size_cnt_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE) THEN |
s_payload_size_cnt_reg <= "01"&X"FFFFF"; |
ELSIF (s_push_lo = '1' OR |
s_push_hi = '1') THEN |
CASE (s_fifo_read_info_reg) IS |
WHEN "000" => s_payload_size_cnt_reg( 7 DOWNTO 0 ) <= |
s_word_data_reg( 7 DOWNTO 0 ); |
WHEN "001" => s_payload_size_cnt_reg( 15 DOWNTO 8 ) <= |
s_word_data_reg(15 DOWNTO 8 ); |
WHEN "010" => s_payload_size_cnt_reg( 21 DOWNTO 16 ) <= |
"0"&s_word_data_reg( 4 DOWNTO 0 ); |
WHEN OTHERS => s_payload_size_cnt_reg <= s_payload_size_cnt_next; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_payload_size_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the addresses are defined --- |
-------------------------------------------------------------------------------- |
s_pud_sector_address <= (OTHERS => '1') WHEN s_flash_top_boot_reg = '1' ELSE |
(OTHERS => '0'); |
|
make_sector_address : PROCESS( clock , s_flash_state_reg , |
s_flash_top_boot_reg , s_next_address , |
s_next_in_sector_addr ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = RESET_STATE) THEN |
s_sector_address_reg <= (OTHERS => '0'); |
ELSIF (s_flash_state_reg = RESET_AUTO OR |
s_flash_state_reg = IDLE) THEN |
s_sector_address_reg(20 DOWNTO 17) <= (OTHERS => '0'); |
s_sector_address_reg(16) <= NOT(s_flash_top_boot_reg); |
ELSIF ((s_flash_state_reg = INIT_ERASE_S1 AND |
s_is_pud_action_reg = '1') OR |
s_flash_state_reg = READ_HW) THEN |
s_sector_address_reg <= s_pud_sector_address; |
ELSIF ((s_next_address = '1' AND |
s_next_in_sector_addr(16) = '1') OR |
s_flash_state_reg = NEXT_SECTOR) THEN |
s_sector_address_reg <= unsigned(s_sector_address_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_sector_address; |
|
make_in_sector_address : PROCESS( clock , s_flash_state_reg , |
s_next_address , s_next_in_sector_addr ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = RESET_STATE) THEN |
s_in_sector_address_reg <= (1=>'1', OTHERS => '0'); |
ELSIF (s_flash_state_reg = RESET_AUTO OR |
s_flash_state_reg = IDLE OR |
s_flash_state_reg = INIT_ERASE_S1 OR |
s_flash_state_reg = READ_HW) THEN |
s_in_sector_address_reg <= (OTHERS => '0'); |
ELSIF (s_next_address = '1') THEN |
s_in_sector_address_reg <= s_next_in_sector_addr( 15 DOWNTO 1 ); |
END IF; |
END IF; |
END PROCESS make_in_sector_address; |
|
-------------------------------------------------------------------------------- |
--- Here the command player is defined --- |
-------------------------------------------------------------------------------- |
make_player_count_reg : PROCESS( clock , s_flash_state_reg , |
s_delay_counter_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = RESET_STATE OR |
s_flash_state_reg = INIT_ERASE_S1 OR |
s_flash_state_reg = INIT_WRITE) THEN |
s_player_count_reg <= "001"; |
ELSIF (s_flash_state_reg = CHECK_ID) THEN |
s_player_count_reg <= "011"; |
ELSIF (s_delay_counter_reg(2) = '1') THEN |
CASE (s_player_count_reg) IS |
WHEN "000" => NULL; |
WHEN "011" => IF (s_flash_state_reg = SET_AUTOSELECT OR |
s_flash_state_reg = RESET_AUTO OR |
s_flash_state_reg = PLAY_WRITE) THEN |
s_player_count_reg <= "000"; |
ELSE |
s_player_count_reg <= "101"; |
END IF; |
WHEN OTHERS => s_player_count_reg <= unsigned(s_player_count_reg) + 1; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_player_count_reg; |
|
make_command_byte : PROCESS( s_flash_state_reg , s_player_count_reg ) |
BEGIN |
CASE (s_flash_state_reg) IS |
WHEN SET_AUTOSELECT => s_command_byte <= X"90"; |
WHEN RESET_AUTO => s_command_byte <= X"F0"; |
WHEN ERASE_S1 => IF (s_player_count_reg(2) = '0') THEN |
s_command_byte <= X"80"; |
ELSE |
s_command_byte <= X"30"; |
END IF; |
WHEN PLAY_WRITE => s_command_byte <= X"A0"; |
WHEN OTHERS => s_command_byte <= X"00"; |
END CASE; |
END PROCESS make_command_byte; |
|
-------------------------------------------------------------------------------- |
--- Here the delay counter is defined --- |
-------------------------------------------------------------------------------- |
make_delay_counter : PROCESS( clock , reset , s_flash_state_reg , |
s_delay_counter_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE OR |
s_delay_counter_reg(2) = '1' OR |
reset = '1') THEN s_delay_counter_reg <= "000"; |
ELSE |
s_delay_counter_reg <= unsigned(s_delay_counter_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_delay_counter; |
|
-------------------------------------------------------------------------------- |
--- Here the flash id regs are defined --- |
-------------------------------------------------------------------------------- |
make_flash_mt_regs : PROCESS( clock , s_flash_state_reg , s_flash_data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_flash_mounted_reg <= '0'; |
s_flash_top_boot_reg <= '0'; |
ELSIF (s_flash_state_reg = CHECK_ID) THEN |
CASE (s_flash_data_in) IS |
WHEN X"22C4" => s_flash_mounted_reg <= '1'; |
s_flash_top_boot_reg <= '1'; |
WHEN X"2249" => s_flash_mounted_reg <= '1'; |
s_flash_top_boot_reg <= '0'; |
WHEN OTHERS => s_flash_mounted_reg <= '0'; |
s_flash_top_boot_reg <= '0'; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_flash_mt_regs; |
|
make_flash_sec1_empty_reg : PROCESS( clock , s_flash_state_reg , |
s_flash_data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
(s_flash_state_reg = WRITE_UPDATE AND |
s_is_pud_action_reg = '0')) THEN s_flash_sec1_empty_reg <= '0'; |
ELSIF (s_flash_state_reg = CHECK_HW) THEN |
IF (s_flash_data_in = X"FFFF") THEN s_flash_sec1_empty_reg <= '1'; |
ELSE s_flash_sec1_empty_reg <= '0'; |
END IF; |
ELSIF (s_flash_state_reg = INIT_ERASE_S1 AND |
s_is_pud_action_reg = '0') THEN |
s_flash_sec1_empty_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_flash_sec1_empty_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the write signals are defined --- |
-------------------------------------------------------------------------------- |
s_write_size <= '1' WHEN s_flash_state_reg = INIT_WRITE AND |
s_write_idx_reg(1) = '0' AND |
s_state_tick = '1' AND |
s_is_pud_action_reg = '0' ELSE '0'; |
s_write_data <= '1' WHEN s_flash_state_reg = INIT_WRITE AND |
s_write_idx_reg(1) = '1' AND |
s_state_tick = '1' AND |
s_fifo_word_valid_reg(1) = '1' AND |
s_is_pud_action_reg = '0' ELSE '0'; |
|
make_write_done_reg : PROCESS( clock , reset , s_write_data , |
s_flash_state_reg , s_last_byte_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = WRITE_UPDATE OR |
reset = '1') THEN s_write_done_reg <= '0'; |
ELSIF (s_write_data = '1') THEN s_write_done_reg <= s_last_byte_reg; |
ELSIF (s_write_pud = '1') THEN |
s_write_done_reg <= s_next_in_sector_addr(11); |
END IF; |
END IF; |
END PROCESS make_write_done_reg; |
|
|
make_write_idx_reg : PROCESS( clock , s_flash_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE) THEN |
s_write_idx_reg <= "00"; |
ELSIF (s_write_size = '1') THEN |
s_write_idx_reg <= unsigned(s_write_idx_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_write_idx_reg; |
|
make_write_data_reg : PROCESS( clock , s_fifo_pop , s_write_size , |
s_write_idx_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_is_pud_action_reg = '1') THEN s_write_data_reg <= s_pud_word; |
ELSIF (s_write_size = '1' OR |
s_write_data = '1') THEN |
CASE (s_write_idx_reg) IS |
WHEN "00" => s_write_data_reg <= bitfile_size(15 DOWNTO 0); |
WHEN "01" => s_write_data_reg <= bitfile_size(31 DOWNTO 16); |
WHEN OTHERS => s_write_data_reg <= s_fifo_word_reg; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_write_data_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the write fifo interface is defined --- |
-------------------------------------------------------------------------------- |
s_fifo_pop <= '1' WHEN s_fifo_empty = '0' AND |
s_fifo_word_valid_reg(1) = '0' AND |
s_last_byte_reg = '0' ELSE '0'; |
|
|
make_fifo_word_reg : PROCESS( clock , s_fifo_reset , s_fifo_pop , |
s_fifo_pop_data , s_fifo_word_valid_reg , |
s_write_data ) |
VARIABLE v_select : std_logic_vector( 2 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_fifo_reset = '1' OR |
s_write_data = '1') THEN s_fifo_word_valid_reg <= "00"; |
s_fifo_word_reg <= (OTHERS => '0'); |
ELSIF (s_fifo_pop = '1') THEN |
IF (s_fifo_word_valid_reg = "00" AND |
s_fifo_pop_last = '1') THEN |
s_fifo_word_valid_reg <= "11"; |
s_fifo_word_reg <= X"FF"&s_fifo_pop_data; |
ELSE |
s_fifo_word_reg <= s_fifo_pop_data&s_fifo_word_reg(15 DOWNTO 8); |
s_fifo_word_valid_reg <= s_fifo_word_valid_reg(0)&"1"; |
END IF; |
END IF; |
END IF; |
END PROCESS make_fifo_word_reg; |
|
make_last_byte_reg : PROCESS( clock , s_fifo_pop , |
s_fifo_pop_last , s_flash_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE) THEN s_last_byte_reg <= '0'; |
ELSIF (s_fifo_pop = '1' AND |
s_fifo_pop_last = '1') THEN s_last_byte_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_last_byte_reg; |
|
|
write_fifo : fifo_2kb |
PORT MAP ( clock => clock, |
reset => s_fifo_reset, |
-- push port |
push => we_fifo, |
push_data => we_data, |
push_size => we_last, |
-- pop port |
pop => s_fifo_pop, |
pop_data => s_fifo_pop_data, |
pop_size => s_fifo_pop_last, |
-- control port |
fifo_full => we_fifo_full, |
fifo_empty => s_fifo_empty ); |
|
-------------------------------------------------------------------------------- |
--- Here the PUD signals are defined --- |
-------------------------------------------------------------------------------- |
s_write_pud <= '1' WHEN s_flash_state_reg = INIT_WRITE AND |
s_state_tick = '1' AND |
s_is_pud_action_reg = '1' ELSE '0'; |
s_start_pud_write <= '1' WHEN start_command = '1' AND |
command_id = "0001101" ELSE '0'; |
s_start_pud_read <= '1' WHEN start_command = '1' AND |
command_id = "0001110" ELSE '0'; |
s_we_pud_byte <= '1' WHEN s_flash_state_reg = DO_PUD_WRITE AND |
scpi_empty = '0' ELSE '0'; |
s_ena_pud_byte <= '1' WHEN s_we_pud_byte = '1' OR |
(s_scpi_push = '1' AND |
s_flash_state_reg = DO_PUD_READ) ELSE '0'; |
s_ena_pud_word_read <= (NOT(s_we_pud_byte) AND s_is_pud_action_reg) OR |
s_we_pud_payload; |
s_scpi_push <= '1' WHEN scpi_full = '0' AND |
(s_flash_state_reg = SET_PUD_SIZE_1 OR |
s_flash_state_reg = SET_PUD_SIZE_2 OR |
(s_flash_state_reg = DO_PUD_READ AND |
s_pud_byte_addr_reg(11) = '0')) ELSE '0'; |
s_scpi_n_reset <= '0' WHEN s_flash_state_reg = DO_PUD_READ ELSE '1'; |
s_we_pud_payload <= '1' WHEN s_flash_state_reg = COPY_PUD_DATA AND |
s_delay_counter_reg = "000" ELSE '0'; |
|
make_scpi_push : PROCESS( clock , s_scpi_push ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
scpi_push <= s_scpi_push; |
IF (s_scpi_push = '1' AND |
s_flash_state_reg = SET_PUD_SIZE_2) THEN |
s_pud_size_value <= X"08"; |
ELSE |
s_pud_size_value <= X"00"; |
END IF; |
IF (s_scpi_push = '1' AND |
(s_flash_state_reg = SET_PUD_SIZE_1 OR |
s_flash_state_reg = SET_PUD_SIZE_2)) THEN |
scpi_push_size <= '1'; |
ELSE |
scpi_push_size <= '0'; |
END IF; |
END IF; |
END PROCESS make_scpi_push; |
|
make_is_pud_action_reg : PROCESS( clock , reset , s_start_pud_write , |
s_flash_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_start_pud_write = '1') THEN |
s_is_pud_action_reg <= '1'; |
ELSIF (reset = '1' OR |
s_flash_state_reg = IDLE) THEN s_is_pud_action_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_is_pud_action_reg; |
|
make_pud_byte_addr_reg : PROCESS( clock , reset , s_flash_state_reg , |
s_ena_pud_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE OR |
reset = '1') THEN s_pud_byte_addr_reg <= (OTHERS => '0'); |
ELSIF (s_ena_pud_byte = '1') THEN |
s_pud_byte_addr_reg <= unsigned(s_pud_byte_addr_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_pud_byte_addr_reg; |
|
make_pud_word_address_reg : PROCESS( clock , s_flash_state_reg , reset , |
s_next_address , s_next_in_sector_addr ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_flash_state_reg = IDLE OR |
reset = '1') THEN s_pud_word_address_reg <= (OTHERS => '0'); |
ELSIF (s_next_address = '1' AND |
s_is_pud_action_reg = '1') THEN |
s_pud_word_address_reg <= s_next_in_sector_addr( 10 DOWNTO 1 ); |
ELSIF (s_pud_hi_reg = '1') THEN |
s_pud_word_address_reg <= s_in_sector_address_reg( 10 DOWNTO 1 ); |
END IF; |
END IF; |
END PROCESS make_pud_word_address_reg; |
|
s_we_vga <= '1' WHEN (s_we_pud_byte = '1' AND |
unsigned(s_pud_byte_addr_reg( 10 DOWNTO 6)) > |
unsigned(c_vga_offset)) OR |
((s_pud_hi_reg = '1' OR |
s_we_pud_payload = '1') AND |
unsigned(s_pud_word_address_reg( 9 DOWNTO 5 )) > |
unsigned(c_vga_offset)) ELSE '0'; |
s_we_addr(10 DOWNTO 8) <= unsigned(s_pud_byte_addr_reg( 9 DOWNTO 7 )) - 1 |
WHEN s_we_pud_byte = '1' ELSE |
unsigned(s_pud_word_address_reg( 8 DOWNTO 6 )) - 1; |
s_we_addr(7) <= s_pud_byte_addr_reg(6) |
WHEN s_we_pud_byte = '1' ELSE |
s_pud_word_address_reg(5); |
s_we_addr(6) <= '1'; |
s_we_addr( 5 DOWNTO 0) <= s_pud_byte_addr_reg( 5 DOWNTO 0 ) |
WHEN s_we_pud_byte = '1' ELSE |
s_pud_word_address_reg(4 DOWNTO 0)&s_pud_hi_reg; |
s_we_data <= scpi_pop_data WHEN s_we_pud_byte = '1' ELSE |
s_flash_data_in( 7 DOWNTO 0) |
WHEN s_pud_hi_reg = '0' ELSE |
s_flash_data_in(15 DOWNTO 8) ; |
|
make_vga_signals : PROCESS( clock ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
we_char <= s_we_vga; |
we_ascii <= s_we_data; |
we_addr <= s_we_addr; |
END IF; |
END PROCESS make_vga_signals; |
|
make_pud_hi_reg : PROCESS( clock ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
s_pud_hi_reg <= s_we_pud_payload; |
END IF; |
END PROCESS make_pud_hi_reg; |
|
|
|
pud_buffer : RAMB16_S9_S18 |
PORT MAP ( DOA => s_pud_byte, |
DOPA => OPEN, |
ADDRA => s_pud_byte_addr_reg( 10 DOWNTO 0 ), |
CLKA => clock, |
DIA => scpi_pop_data, |
DIPA => "0", |
ENA => '1', |
SSRA => s_scpi_n_reset, |
WEA => s_we_pud_byte, |
DOB => s_pud_word, |
DOPB => OPEN, |
ADDRB => s_pud_word_address_reg, |
CLKB => clock, |
DIB => s_flash_data_in, |
DIPB => "00", |
ENB => s_ena_pud_word_read, |
SSRB => '0', |
WEB => s_we_pud_payload ); |
|
make_busy_pipe_reg : PROCESS( clock , reset , flash_ready_n_busy ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_busy_pipe_reg <= X"0"; |
ELSE |
s_busy_pipe_reg( 2 DOWNTO 0 ) <= s_busy_pipe_reg(1 DOWNTO 0)&flash_ready_n_busy; |
IF (s_busy_pipe_reg( 2 DOWNTO 0 ) = "000") THEN s_busy_pipe_reg(3) <= '0'; |
ELSIF (s_busy_pipe_reg( 2 DOWNTO 0 ) = "111") THEN s_busy_pipe_reg(3) <= '1'; |
END IF; |
END IF; |
END IF; |
END PROCESS make_busy_pipe_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the IOB flipflops are defined --- |
-------------------------------------------------------------------------------- |
address_ffs : FOR n IN 19 DOWNTO 0 GENERATE |
one_ff : FDE |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_address(n), |
C => clock, |
CE => s_delay_counter_reg(2), |
D => s_byte_address(n+1) ); |
END GENERATE address_ffs; |
|
data_in_out_ffs : FOR n IN 15 DOWNTO 0 GENERATE |
in_ff : FDE_1 |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => s_flash_data_in(n), |
C => clock, |
CE => s_delay_counter_reg(2), |
D => flash_data_in(n) ); |
out_ff : FDE |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_data_out(n), |
C => clock, |
CE => s_delay_counter_reg(2), |
D => s_data_out_next(n) ); |
oe_ff : FDE |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_data_oe(n), |
C => clock, |
CE => s_delay_counter_reg(2), |
D => s_tri_data_out ); |
END GENERATE data_in_out_ffs; |
|
nce_reg : FD |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_n_ce, |
C => clock, |
D => s_flash_n_ce ); |
noe_reg : FD |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_n_oe, |
C => clock, |
D => s_flash_n_oe ); |
nwe_reg : FD |
GENERIC MAP ( INIT => '1') |
PORT MAP ( Q => flash_n_we, |
C => clock, |
D => s_flash_n_we ); |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/flash/flash-entity.vhdl
0,0 → 1,96
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY flash_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
|
-- here the control interface is defined |
start_erase : IN std_logic; |
start_read : IN std_logic; |
start_write : IN std_logic; |
done : OUT std_logic; |
flash_present : OUT std_logic; |
flash_s1_empty : OUT std_logic; |
flash_idle : OUT std_logic; |
size_error : OUT std_logic; |
flash_n_busy : OUT std_logic; |
start_config : OUT std_logic; |
|
-- here the push fifo interface is defined |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_last : OUT std_logic; |
fifo_full : IN std_logic; |
|
-- here the write fifo is defined |
bitfile_size : IN std_logic_vector( 31 DOWNTO 0 ); |
we_fifo : IN std_logic; |
we_data : IN std_logic_vector( 7 DOWNTO 0 ); |
we_last : IN std_logic; |
we_fifo_full : OUT std_logic; |
|
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
scpi_pop : OUT std_logic; |
scpi_pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
scpi_pop_last : IN std_logic; |
scpi_empty : IN std_logic; |
scpi_push : OUT std_logic; |
scpi_push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
scpi_push_size : OUT std_logic; |
scpi_full : IN std_logic; |
|
-- Here the vga interface is defined |
we_char : OUT std_logic; |
we_ascii : OUT std_logic_vector( 7 DOWNTO 0 ); |
we_addr : OUT std_logic_vector( 10 DOWNTO 0 ); |
|
-- define the flash interface |
flash_address : OUT std_logic_vector( 19 DOWNTO 0 ); |
flash_data_in : IN std_logic_vector( 15 DOWNTO 0 ); |
flash_data_out : OUT std_logic_vector( 15 DOWNTO 0 ); |
flash_data_oe : OUT std_logic_vector( 15 DOWNTO 0 ); |
flash_n_byte : OUT std_logic; |
flash_n_ce : OUT std_logic; |
flash_n_oe : OUT std_logic; |
flash_n_we : OUT std_logic; |
flash_ready_n_busy : IN std_logic); |
END flash_if; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/flipflops/flip-flops_behavior_generic.vhdl
0,0 → 1,91
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_platform_specific OF DFF IS |
|
BEGIN |
make_ff : PROCESS( clock , D ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
Q <= D; |
END IF; |
END PROCESS make_ff; |
END no_platform_specific; |
|
ARCHITECTURE no_platform_specific OF DFF_E IS |
|
BEGIN |
make_ff : PROCESS( clock , D , enable ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (enable = '1') THEN Q <= D; |
END IF; |
END IF; |
END PROCESS make_ff; |
END no_platform_specific; |
|
ARCHITECTURE no_platform_specific OF DFF_AR IS |
|
BEGIN |
make_ff : PROCESS( clock , D , reset ) |
BEGIN |
IF (reset = '1') THEN Q <= '0'; |
ELSIF (clock'event AND (clock = '1')) THEN |
Q <= D; |
END IF; |
END PROCESS make_ff; |
END no_platform_specific; |
|
ARCHITECTURE no_platform_specific OF DFF_BUS IS |
|
BEGIN |
make_ff : PROCESS( clock , D ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
Q <= D; |
END IF; |
END PROCESS make_ff; |
END no_platform_specific; |
|
ARCHITECTURE no_platform_specific OF DFF_E_BUS IS |
|
BEGIN |
make_ff : PROCESS( clock , D , enable ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (enable = '1') THEN Q <= D; |
END IF; |
END IF; |
END PROCESS make_ff; |
END no_platform_specific; |
|
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/flipflops/flip-flops_entity.vhdl
0,0 → 1,87
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY DFF IS |
PORT ( clock : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END DFF; |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY DFF_E IS |
PORT ( clock : IN std_logic; |
enable : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END DFF_E; |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY DFF_AR IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END DFF_AR; |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY DFF_BUS IS |
GENERIC ( nr_of_bits : INTEGER ); |
PORT ( clock : IN std_logic; |
D : IN std_logic_vector( (nr_of_bits-1) DOWNTO 0 ); |
Q : OUT std_logic_vector( (nr_of_bits-1) DOWNTO 0 )); |
END DFF_BUS; |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY DFF_E_BUS IS |
GENERIC ( nr_of_bits : INTEGER ); |
PORT ( clock : IN std_logic; |
enable : IN std_logic; |
D : IN std_logic_vector( (nr_of_bits-1) DOWNTO 0 ); |
Q : OUT std_logic_vector( (nr_of_bits-1) DOWNTO 0 )); |
END DFF_E_BUS; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/reset_if/reset_if-entity.vhdl
0,0 → 1,54
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY reset_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
|
-- Here the fpga_interface is defined |
fpga_configured: IN std_logic; |
|
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
|
-- Here the system reset is defined |
n_reset_system : OUT std_logic; |
user_n_reset : OUT std_logic ); |
END reset_if; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/reset_if/reset_if-behavior.vhdl
0,0 → 1,99
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_target_specific OF reset_if IS |
|
SIGNAL s_reset_count_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_user_count_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_done_pending_reg: std_logic; |
|
BEGIN |
n_reset_system <= '0' WHEN s_reset_count_reg(4) = '0' ELSE 'Z'; |
user_n_reset <= '0' WHEN s_user_count_reg(4) = '0' ELSE '1'; |
command_done <= '1' WHEN (s_done_pending_reg = '1' AND |
s_reset_count_reg(4) = '1' AND |
s_user_count_reg(4) = '1') OR |
(start_command = '1' AND |
(command_id = "0001111" OR |
command_id = "0111010") AND |
fpga_configured = '0') ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the reset counter is defined --- |
-------------------------------------------------------------------------------- |
make_reset_count_reg : PROCESS( clock , reset , start_command , command_id , |
fpga_configured ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF ((start_command = '1' AND |
command_id = "0001111") OR |
fpga_configured = '0' OR |
reset = '1') THEN s_reset_count_reg <= "0"&X"A"; |
ELSIF (msec_tick = '1' AND |
s_reset_count_reg(4) = '0') THEN |
s_reset_count_reg <= unsigned(s_reset_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_reset_count_reg; |
|
make_user_count_reg : PROCESS( clock , reset , start_command , command_id , |
fpga_configured ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF ((start_command = '1' AND |
command_id = "0111010") OR |
fpga_configured = '0' OR |
reset = '1') THEN s_user_count_reg <= "0"&X"A"; |
ELSIF (msec_tick = '1' AND |
s_user_count_reg(4) = '0') THEN |
s_user_count_reg <= unsigned(s_user_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_user_count_reg; |
|
make_done_pending_reg : PROCESS( clock , reset , start_command , command_id , |
s_reset_count_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (start_command = '1' AND |
(command_id = "0001111" OR |
command_id = "0111010") AND |
fpga_configured = '1') THEN s_done_pending_reg <= '1'; |
ELSIF (reset = '1' OR |
(s_reset_count_reg(4) = '1' AND |
s_user_count_reg(4) = '1')) THEN s_done_pending_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_done_pending_reg; |
|
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/config/config-entity.vhdl
0,0 → 1,88
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
ENTITY config_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- here the flash interface is defined |
start_config : IN std_logic; |
flash_start_read : OUT std_logic; |
flash_done : IN std_logic; |
flash_present : IN std_logic; |
flash_s1_empty : IN std_logic; |
flash_idle : IN std_logic; |
|
flash_push : IN std_logic; |
flash_push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
flash_push_size : IN std_logic; |
flash_push_last : IN std_logic; |
flash_fifo_full : OUT std_logic; |
|
-- here the flash usbtmc interface is defined |
flash_u_start_read : IN std_logic; |
flash_u_done : OUT std_logic; |
flash_u_push : OUT std_logic; |
flash_u_push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
flash_u_push_size : OUT std_logic; |
flash_u_fifo_full : IN std_logic; |
|
-- here the bitfile interface is defined |
bitfile_start : OUT std_logic; |
bitfile_pop : IN std_logic; |
bitfile_pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
bitfile_last : OUT std_logic; |
bitfile_fifo_empty : OUT std_logic; |
|
-- here the bitfile usbtmc interface is defined |
bitfile_u_start : IN std_logic; |
bitfile_u_pop : OUT std_logic; |
bitfile_u_pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
bitfile_u_last : IN std_logic; |
bitfile_u_fifo_empty : IN std_logic; |
|
-- here the fpga interface is defined |
fpga_idle : IN std_logic; |
fpga_type : IN std_logic_vector( 2 DOWNTO 0 ); |
|
-- here the power interface is defined |
n_bus_power : IN std_logic; |
|
-- here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_error : OUT std_logic ); |
END config_if; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/config/config-behavior.vhdl
0,0 → 1,175
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_target_specific OF config_if IS |
|
COMPONENT fifo_2kb |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_size : IN std_logic; |
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END COMPONENT; |
|
TYPE CONFIG_STATE_TYPE IS (IDLE,SEND_START,WAIT_END,SIGNAL_ERROR); |
|
SIGNAL s_config_state_reg : CONFIG_STATE_TYPE; |
|
SIGNAL s_fifo_full : std_logic; |
SIGNAL s_push : std_logic; |
SIGNAL s_pop : std_logic; |
SIGNAL s_pop_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pop_last : std_logic; |
SIGNAL s_fifo_empty : std_logic; |
SIGNAL s_boot_up_config : std_logic; |
SIGNAL s_boot_up_reg : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
flash_start_read <= '1' WHEN s_config_state_reg = SEND_START OR |
(s_config_state_reg = IDLE AND |
flash_u_start_read = '1') ELSE '0'; |
flash_u_done <= flash_done WHEN s_config_state_reg = IDLE ELSE '0'; |
flash_u_push <= flash_push WHEN s_config_state_reg = IDLE ELSE '0'; |
flash_u_push_data<= flash_push_data WHEN s_config_state_reg = IDLE ELSE (OTHERS => '0'); |
flash_u_push_size<= flash_push_size WHEN s_config_state_reg = IDLE ELSE '0'; |
flash_fifo_full <= flash_u_fifo_full WHEN s_config_state_reg = IDLE ELSE s_fifo_full; |
bitfile_start <= '1' WHEN s_config_state_reg = SEND_START OR |
(s_config_state_reg = IDLE AND |
bitfile_u_start = '1') ELSE '0'; |
bitfile_u_pop <= bitfile_pop WHEN s_config_state_reg = IDLE ELSE '0'; |
bitfile_pop_data <= bitfile_u_pop_data WHEN s_config_state_reg = IDLE ELSE |
s_pop_data; |
bitfile_last <= bitfile_u_last WHEN s_config_state_reg = IDLE ELSE |
s_pop_last; |
bitfile_fifo_empty <= bitfile_u_fifo_empty WHEN s_config_state_reg = IDLE ELSE |
s_fifo_empty; |
command_error <= '1' WHEN s_config_state_reg = SIGNAL_ERROR ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_push <= '1' WHEN s_config_state_reg = WAIT_END AND |
flash_push = '1' AND |
flash_push_size = '0' ELSE '0'; |
s_pop <= bitfile_pop WHEN s_config_state_reg = WAIT_END ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_state_machine : PROCESS( clock , reset , s_config_state_reg ) |
VARIABLE v_next_state : CONFIG_STATE_TYPE; |
BEGIN |
CASE (s_config_state_reg) IS |
WHEN IDLE => IF (start_command = '1' AND |
command_id = "0011001") THEN |
IF (flash_present = '0' OR |
flash_s1_empty = '1' OR |
fpga_type = "111") THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := SEND_START; |
END IF; |
ELSIF (s_boot_up_config = '1' OR |
start_config = '1') THEN |
v_next_state := SEND_START; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN SEND_START => v_next_state := WAIT_END; |
WHEN WAIT_END => IF (s_pop = '1' AND |
s_pop_last = '1') THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := WAIT_END; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_config_state_reg <= IDLE; |
ELSE s_config_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the boot-up is defined --- |
-------------------------------------------------------------------------------- |
s_boot_up_config <= '1' WHEN s_boot_up_reg = '1' AND |
flash_present = '1' AND |
n_bus_power = '0' AND |
flash_s1_empty = '0' AND |
flash_idle = '1' AND |
fpga_idle = '1' AND |
fpga_type /= "111" ELSE '0'; |
|
make_boot_up_reg : PROCESS( clock , reset , start_command , s_boot_up_config) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_boot_up_reg <= '1'; |
ELSIF (start_command = '1' OR |
s_boot_up_config = '1') THEN s_boot_up_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_boot_up_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the components are defined --- |
-------------------------------------------------------------------------------- |
fifo : fifo_2kb |
PORT MAP ( clock => clock, |
reset => reset, |
-- push port |
push => s_push, |
push_data => flash_push_data, |
push_size => flash_push_last, |
-- pop port |
pop => s_pop, |
pop_data => s_pop_data, |
pop_size => s_pop_last, |
-- control port |
fifo_full => s_fifo_full, |
fifo_empty => s_fifo_empty ); |
|
|
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_4kb_16w_8r-entity.vhdl
0,0 → 1,56
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY fifo_4kb_16w_8r IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 15 DOWNTO 0 ); |
push_size : IN std_logic; |
|
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
|
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic; |
byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) ); |
END fifo_4kb_16w_8r; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_4kb_8w_16r-entity.vhdl
0,0 → 1,60
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
-- Important: This fifo allowes only a pop when at least 2 |
-- bytes are pushed. When only 1 byte is in the |
-- fifo, it cannot be poped! |
|
ENTITY fifo_4kb_8w_16r IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_last : IN std_logic; |
|
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 15 DOWNTO 0 ); |
pop_last : OUT std_logic_vector( 1 DOWNTO 0 ); |
|
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic; |
byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) ); |
END fifo_4kb_8w_16r; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_2kb_ef-entity.vhdl
0,0 → 1,57
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY fifo_2kb_ef IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
high_speed : IN std_logic; |
|
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_last : IN std_logic; |
|
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_last : OUT std_logic; |
|
-- control port |
fifo_full : OUT std_logic; |
early_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END fifo_2kb_ef; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_2kb-behavior-xilinx.vhdl
0,0 → 1,158
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF fifo_2kb IS |
|
COMPONENT RAMB16_S9_S9 |
GENERIC ( WRITE_MODE_A : string := "READ_FIRST"; |
WRITE_MODE_B : string := "READ_FIRST" ); |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRA : IN std_logic_vector(10 DOWNTO 0); |
DIA : IN std_logic_vector( 7 DOWNTO 0); |
ENA : IN std_ulogic; |
WEA : IN std_ulogic; |
DOPA : OUT std_logic_vector( 0 DOWNTO 0); |
CLKA : IN std_ulogic; |
DIPA : IN std_logic_vector( 0 DOWNTO 0); |
SSRA : IN std_ulogic; |
DOPB : OUT std_logic_vector( 0 DOWNTO 0); |
CLKB : IN std_ulogic; |
DIPB : IN std_logic_vector( 0 DOWNTO 0); |
SSRB : IN std_ulogic; |
DOB : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRB : IN std_logic_vector(10 DOWNTO 0); |
DIB : IN std_logic_vector( 7 DOWNTO 0); |
ENB : IN std_ulogic; |
WEB : IN std_ulogic ); |
END COMPONENT; |
|
CONSTANT c_threshold : std_logic_vector(11 DOWNTO 0 ) := X"7FD"; |
|
SIGNAL s_write_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_write_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_next : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_full : std_logic; |
SIGNAL s_empty : std_logic; |
SIGNAL s_execute_push : std_logic; |
SIGNAL s_execute_pop : std_logic; |
SIGNAL s_n_clock : std_logic; |
|
BEGIN |
-- Assign outputs |
fifo_full <= s_full; |
fifo_empty <= s_empty; |
|
-- Assign control signals |
s_read_address_next <= unsigned(s_read_address_reg) + 1; |
s_write_address_next <= unsigned(s_write_address_reg) + 1; |
s_nr_of_bytes_next <= unsigned(s_nr_of_bytes_reg) - 1 |
WHEN s_execute_pop = '1' AND |
s_execute_push = '0' ELSE |
unsigned(s_nr_of_bytes_reg) + 1 |
WHEN s_execute_pop = '0' AND |
s_execute_push = '1' ELSE |
s_nr_of_bytes_reg; |
|
s_execute_push <= push AND NOT(s_nr_of_bytes_reg(11)); |
s_execute_pop <= pop AND NOT(s_empty); |
s_n_clock <= NOT(clock); |
s_full <= '1' WHEN unsigned(s_nr_of_bytes_reg) > |
unsigned(c_threshold) ELSE '0'; |
s_empty <= '1' WHEN s_nr_of_bytes_reg = "000000000000" ELSE '0'; |
|
-- define processes |
make_read_address_reg : PROCESS( clock , reset , s_execute_pop , |
s_read_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_read_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_pop = '1') THEN |
s_read_address_reg <= s_read_address_next; |
END IF; |
END IF; |
END PROCESS make_read_address_reg; |
|
make_write_address_reg : PROCESS( clock , reset , s_execute_push , |
s_write_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_write_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_push = '1') THEN |
s_write_address_reg <= s_write_address_next; |
END IF; |
END IF; |
END PROCESS make_write_address_reg; |
|
make_nr_of_bytes_reg : PROCESS( clock , reset , s_nr_of_bytes_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_nr_of_bytes_reg <= (OTHERS => '0'); |
ELSE s_nr_of_bytes_reg <= s_nr_of_bytes_next; |
END IF; |
END IF; |
END PROCESS make_nr_of_bytes_reg; |
|
-- map components |
ram1 : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg, |
DIA => push_data, |
ENA => s_execute_push, |
WEA => s_execute_push, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0) => push_size, |
SSRA => '0', |
DOPB(0) => pop_size, |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => pop_data, |
ADDRB => s_read_address_reg, |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_2kb-entity.vhdl
0,0 → 1,55
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY fifo_2kb IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- push port |
push : IN std_logic; |
push_data : IN std_logic_vector( 7 DOWNTO 0 ); |
push_size : IN std_logic; |
|
-- pop port |
pop : IN std_logic; |
pop_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
pop_size : OUT std_logic; |
|
-- control port |
fifo_full : OUT std_logic; |
fifo_empty : OUT std_logic ); |
END fifo_2kb; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_4kb_16w_8r-behavior-xilinx.vhdl
0,0 → 1,194
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF fifo_4kb_16w_8r IS |
|
COMPONENT RAMB16_S9_S9 |
GENERIC ( WRITE_MODE_A : string := "READ_FIRST"; |
WRITE_MODE_B : string := "READ_FIRST" ); |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRA : IN std_logic_vector(10 DOWNTO 0); |
DIA : IN std_logic_vector( 7 DOWNTO 0); |
ENA : IN std_ulogic; |
WEA : IN std_ulogic; |
DOPA : OUT std_logic_vector( 0 DOWNTO 0); |
CLKA : IN std_ulogic; |
DIPA : IN std_logic_vector( 0 DOWNTO 0); |
SSRA : IN std_ulogic; |
DOPB : OUT std_logic_vector( 0 DOWNTO 0); |
CLKB : IN std_ulogic; |
DIPB : IN std_logic_vector( 0 DOWNTO 0); |
SSRB : IN std_ulogic; |
DOB : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRB : IN std_logic_vector(10 DOWNTO 0); |
DIB : IN std_logic_vector( 7 DOWNTO 0); |
ENB : IN std_ulogic; |
WEB : IN std_ulogic ); |
END COMPONENT; |
|
CONSTANT c_threshold : std_logic_vector(12 DOWNTO 0 ) := "0"&X"FFD"; |
|
SIGNAL s_write_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_write_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_read_address_next : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_reg : std_logic_vector(12 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_next : std_logic_vector(12 DOWNTO 0 ); |
SIGNAL s_full : std_logic; |
SIGNAL s_empty : std_logic; |
SIGNAL s_execute_push : std_logic; |
SIGNAL s_execute_pop : std_logic; |
SIGNAL s_n_clock : std_logic; |
SIGNAL s_pop_data_lo : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pop_data_hi : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_pop_size_lo : std_logic; |
SIGNAL s_pop_size_hi : std_logic; |
|
BEGIN |
-- Assign outputs |
fifo_full <= s_full; |
fifo_empty <= s_empty; |
pop_data <= s_pop_data_lo WHEN s_read_address_reg(0) = '0' ELSE s_pop_data_hi; |
pop_size <= s_pop_size_lo WHEN s_read_address_reg(0) = '0' ELSE s_pop_size_hi; |
byte_cnt <= s_nr_of_bytes_reg; |
|
-- Assign control signals |
s_read_address_next <= unsigned(s_read_address_reg) + 1; |
s_write_address_next <= unsigned(s_write_address_reg) + 1; |
|
s_execute_push <= push AND NOT(s_nr_of_bytes_reg(12)); |
s_execute_pop <= pop AND NOT(s_empty); |
s_n_clock <= NOT(clock); |
s_full <= s_nr_of_bytes_reg(12); |
s_empty <= '1' WHEN s_nr_of_bytes_reg = "0000000000000" ELSE '0'; |
|
-- define processes |
make_nr_of_bytes_next : PROCESS( s_execute_push , s_execute_pop , |
s_nr_of_bytes_reg ) |
VARIABLE v_add : std_logic_vector(12 DOWNTO 0 ); |
VARIABLE v_sel : std_logic_vector( 1 DOWNTO 0 ); |
BEGIN |
v_sel := s_execute_push&s_execute_pop; |
CASE (v_sel) IS |
WHEN "00" => v_add := "0"&X"000"; |
WHEN "01" => v_add := "1"&X"FFF"; |
WHEN "10" => v_add := "0"&X"002"; |
WHEN OTHERS => v_add := "0"&X"001"; |
END CASE; |
s_nr_of_bytes_next <= unsigned(s_nr_of_bytes_reg)+ |
unsigned(v_add); |
END PROCESS make_nr_of_bytes_next; |
|
make_read_address_reg : PROCESS( clock , reset , s_execute_pop , |
s_read_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_read_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_pop = '1') THEN |
s_read_address_reg <= s_read_address_next; |
END IF; |
END IF; |
END PROCESS make_read_address_reg; |
|
make_write_address_reg : PROCESS( clock , reset , s_execute_push , |
s_write_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_write_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_push = '1') THEN |
s_write_address_reg <= s_write_address_next; |
END IF; |
END IF; |
END PROCESS make_write_address_reg; |
|
make_nr_of_bytes_reg : PROCESS( clock , reset , s_nr_of_bytes_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_nr_of_bytes_reg <= (OTHERS => '0'); |
ELSE s_nr_of_bytes_reg <= s_nr_of_bytes_next; |
END IF; |
END IF; |
END PROCESS make_nr_of_bytes_reg; |
|
-- map components |
ram1 : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg, |
DIA => push_data( 7 DOWNTO 0 ), |
ENA => s_execute_push, |
WEA => s_execute_push, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0) => push_size, |
SSRA => '0', |
DOPB(0) => s_pop_size_lo, |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => s_pop_data_lo, |
ADDRB => s_read_address_reg(11 DOWNTO 1), |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
ram2 : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg, |
DIA => push_data(15 DOWNTO 8 ), |
ENA => s_execute_push, |
WEA => s_execute_push, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0) => push_size, |
SSRA => '0', |
DOPB(0) => s_pop_size_hi, |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => s_pop_data_hi, |
ADDRB => s_read_address_reg(11 DOWNTO 1), |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_4kb_8w_16r-behavior-xilinx.vhdl
0,0 → 1,192
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF fifo_4kb_8w_16r IS |
|
COMPONENT RAMB16_S9_S9 |
GENERIC ( WRITE_MODE_A : string := "READ_FIRST"; |
WRITE_MODE_B : string := "READ_FIRST" ); |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRA : IN std_logic_vector(10 DOWNTO 0); |
DIA : IN std_logic_vector( 7 DOWNTO 0); |
ENA : IN std_ulogic; |
WEA : IN std_ulogic; |
DOPA : OUT std_logic_vector( 0 DOWNTO 0); |
CLKA : IN std_ulogic; |
DIPA : IN std_logic_vector( 0 DOWNTO 0); |
SSRA : IN std_ulogic; |
DOPB : OUT std_logic_vector( 0 DOWNTO 0); |
CLKB : IN std_ulogic; |
DIPB : IN std_logic_vector( 0 DOWNTO 0); |
SSRB : IN std_ulogic; |
DOB : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRB : IN std_logic_vector(10 DOWNTO 0); |
DIB : IN std_logic_vector( 7 DOWNTO 0); |
ENB : IN std_ulogic; |
WEB : IN std_ulogic ); |
END COMPONENT; |
|
CONSTANT c_threshold : std_logic_vector(12 DOWNTO 0 ) := "0"&X"FFD"; |
|
SIGNAL s_write_address_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_write_address_next : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_read_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_reg : std_logic_vector(12 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_next : std_logic_vector(12 DOWNTO 0 ); |
SIGNAL s_full : std_logic; |
SIGNAL s_empty : std_logic; |
SIGNAL s_execute_push : std_logic; |
SIGNAL s_execute_pop : std_logic; |
SIGNAL s_n_clock : std_logic; |
SIGNAL s_we_lo : std_logic; |
SIGNAL s_we_hi : std_logic; |
|
BEGIN |
-- Assign outputs |
fifo_full <= s_full; |
fifo_empty <= s_empty; |
byte_cnt <= s_nr_of_bytes_reg; |
|
-- Assign control signals |
s_read_address_next <= unsigned(s_read_address_reg) + 1; |
s_write_address_next <= unsigned(s_write_address_reg) + 1; |
|
s_execute_push <= push AND NOT(s_nr_of_bytes_reg(12)); |
s_execute_pop <= pop AND NOT(s_empty); |
s_n_clock <= NOT(clock); |
s_full <= s_nr_of_bytes_reg(12); |
s_empty <= '1' WHEN s_nr_of_bytes_reg(12 DOWNTO 1) = X"000" ELSE '0'; |
s_we_lo <= s_execute_push AND NOT(s_write_address_reg(0)); |
s_we_hi <= s_execute_push AND s_write_address_reg(0); |
|
-- define processes |
make_nr_of_bytes_next : PROCESS( s_execute_push , s_execute_pop , |
s_nr_of_bytes_reg ) |
VARIABLE v_add : std_logic_vector(12 DOWNTO 0 ); |
VARIABLE v_sel : std_logic_vector( 1 DOWNTO 0 ); |
BEGIN |
v_sel := s_execute_push&s_execute_pop; |
CASE (v_sel) IS |
WHEN "00" => v_add := "0"&X"000"; |
WHEN "01" => v_add := "1"&X"FFE"; |
WHEN "10" => v_add := "0"&X"001"; |
WHEN OTHERS => v_add := "1"&X"FFF"; |
END CASE; |
s_nr_of_bytes_next <= unsigned(s_nr_of_bytes_reg)+ |
unsigned(v_add); |
END PROCESS make_nr_of_bytes_next; |
|
make_read_address_reg : PROCESS( clock , reset , s_execute_pop , |
s_read_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_read_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_pop = '1') THEN |
s_read_address_reg <= s_read_address_next; |
END IF; |
END IF; |
END PROCESS make_read_address_reg; |
|
make_write_address_reg : PROCESS( clock , reset , s_execute_push , |
s_write_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_write_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_push = '1') THEN |
s_write_address_reg <= s_write_address_next; |
END IF; |
END IF; |
END PROCESS make_write_address_reg; |
|
make_nr_of_bytes_reg : PROCESS( clock , reset , s_nr_of_bytes_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_nr_of_bytes_reg <= (OTHERS => '0'); |
ELSE s_nr_of_bytes_reg <= s_nr_of_bytes_next; |
END IF; |
END IF; |
END PROCESS make_nr_of_bytes_reg; |
|
-- map components |
ram1 : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg(11 DOWNTO 1), |
DIA => push_data, |
ENA => s_we_lo, |
WEA => s_we_lo, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0) => push_last, |
SSRA => '0', |
DOPB(0) => pop_last(0), |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => pop_data( 7 DOWNTO 0 ), |
ADDRB => s_read_address_reg, |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
ram2 : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg(11 DOWNTO 1), |
DIA => push_data, |
ENA => s_we_hi, |
WEA => s_we_hi, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0) => push_last, |
SSRA => '0', |
DOPB(0) => pop_last(1), |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => pop_data( 15 DOWNTO 8 ), |
ADDRB => s_read_address_reg, |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/fifos/fifo_2kb_ef-behavior-xilinx.vhdl
0,0 → 1,161
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF fifo_2kb_ef IS |
|
COMPONENT RAMB16_S9_S9 |
GENERIC ( WRITE_MODE_A : string := "READ_FIRST"; |
WRITE_MODE_B : string := "READ_FIRST" ); |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRA : IN std_logic_vector(10 DOWNTO 0); |
DIA : IN std_logic_vector( 7 DOWNTO 0); |
ENA : IN std_ulogic; |
WEA : IN std_ulogic; |
DOPA : OUT std_logic_vector(0 DOWNTO 0); |
CLKA : IN std_ulogic; |
DIPA : IN std_logic_vector(0 DOWNTO 0); |
SSRA : IN std_ulogic; |
DOPB : OUT std_logic_vector(0 DOWNTO 0); |
CLKB : IN std_ulogic; |
DIPB : IN std_logic_vector(0 DOWNTO 0); |
SSRB : IN std_ulogic; |
DOB : OUT std_logic_vector( 7 DOWNTO 0); |
ADDRB : IN std_logic_vector(10 DOWNTO 0); |
DIB : IN std_logic_vector( 7 DOWNTO 0); |
ENB : IN std_ulogic; |
WEB : IN std_ulogic ); |
END COMPONENT; |
|
CONSTANT c_threshold_full : std_logic_vector(11 DOWNTO 0 ) := X"7BF"; |
CONSTANT c_threshold_high : std_logic_vector(11 DOWNTO 0 ) := X"5FF"; |
|
SIGNAL s_write_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_write_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_reg : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_read_address_next : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_nr_of_bytes_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_full : std_logic; |
SIGNAL s_empty : std_logic; |
SIGNAL s_execute_push : std_logic; |
SIGNAL s_execute_pop : std_logic; |
SIGNAL s_n_clock : std_logic; |
SIGNAL s_current_threshold : std_logic_vector(11 DOWNTO 0); |
|
BEGIN |
-- Assign outputs |
fifo_full <= s_full; |
fifo_empty <= s_empty; |
early_full <= '1' WHEN unsigned(s_nr_of_bytes_reg) > |
unsigned(s_current_threshold) ELSE '0'; |
|
-- Assign control signals |
s_read_address_next <= unsigned(s_read_address_reg) + 1; |
s_write_address_next <= unsigned(s_write_address_reg) + 1; |
s_execute_push <= push AND NOT(s_full); |
s_execute_pop <= pop AND NOT(s_empty); |
s_n_clock <= NOT(clock); |
s_current_threshold <= c_threshold_full WHEN high_speed = '0' ELSE |
c_threshold_high; |
s_full <= s_nr_of_bytes_reg(11); |
s_empty <= '1' WHEN s_nr_of_bytes_reg = "000000000000" ELSE '0'; |
|
-- define processes |
make_read_address_reg : PROCESS( clock , reset , s_execute_pop , |
s_read_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_read_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_pop = '1') THEN |
s_read_address_reg <= s_read_address_next; |
END IF; |
END IF; |
END PROCESS make_read_address_reg; |
|
make_write_address_reg : PROCESS( clock , reset , s_execute_push , |
s_write_address_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_write_address_reg <= (OTHERS => '0'); |
ELSIF (s_execute_push = '1') THEN |
s_write_address_reg <= s_write_address_next; |
END IF; |
END IF; |
END PROCESS make_write_address_reg; |
|
make_nr_of_bytes_reg : PROCESS( clock , reset , s_execute_push , |
s_execute_pop ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_nr_of_bytes_reg <= (OTHERS => '0'); |
ELSIF (s_execute_push = '1' AND |
s_execute_pop = '0') THEN |
s_nr_of_bytes_reg <= unsigned(s_nr_of_bytes_reg) + 1; |
ELSIF (s_execute_push = '0' AND |
s_execute_pop = '1') THEN |
s_nr_of_bytes_reg <= unsigned(s_nr_of_bytes_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_nr_of_bytes_reg; |
|
-- map components |
ram : RAMB16_S9_S9 |
GENERIC MAP ( WRITE_MODE_A => "READ_FIRST", |
WRITE_MODE_B => "READ_FIRST" ) |
PORT MAP ( DOA => OPEN, |
ADDRA => s_write_address_reg, |
DIA => push_data, |
ENA => s_execute_push, |
WEA => s_execute_push, |
DOPA => OPEN, |
CLKA => clock, |
DIPA(0)=> push_last, |
SSRA => '0', |
DOPB(0)=> pop_last, |
CLKB => s_n_clock, |
DIPB => "0", |
SSRB => '0', |
DOB => pop_data, |
ADDRB => s_read_address_reg, |
DIB => X"00", |
ENB => '1', |
WEB => '0' ); |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/bus_if/bus_if-behavior-xilinx.vhdl
0,0 → 1,242
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
-- In case of start of transmission: |
-- data(15) => read_n_write |
-- data(14 DOWNTO 6) => burst_size |
-- data( 5 DOWNTO 0) => address |
|
ARCHITECTURE xilinx OF bus_if IS |
|
COMPONENT FD |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
SIGNAL s_n_force_bus_reg : std_logic; |
SIGNAL s_bus_reset : std_logic; |
SIGNAL s_data_in : std_logic_vector( 15 DOWNTO 0 ); |
SIGNAL s_data_n_valid_in : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_n_start : std_logic; |
SIGNAL s_n_end_in : std_logic; |
SIGNAL s_n_error : std_logic; |
SIGNAL s_n_start_send : std_logic; |
SIGNAL s_n_end_out : std_logic; |
SIGNAL s_bus_n_end_transmission : std_logic; |
SIGNAL s_bus_n_end_tri : std_logic; |
SIGNAL s_n_valid_out : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_bus_n_data_valid : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_bus_n_data_tri : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_bus_data_addr_cntrl : std_logic_vector(15 DOWNTO 0 ); |
SIGNAL s_bus_data_addr_tri : std_logic_vector(15 DOWNTO 0 ); |
|
BEGIN |
|
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
b_n_reset <= NOT(s_bus_reset); |
bus_n_end_transmission <= s_bus_n_end_transmission |
WHEN s_bus_n_end_tri = '0' ELSE 'Z'; |
|
make_n_start_reg : PROCESS( clock , s_n_start , s_bus_reset , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_bus_reset = '1' OR |
reset = '1') THEN b_n_start_transmission <= '1'; |
ELSE b_n_start_transmission <= s_n_start; |
END IF; |
END IF; |
END PROCESS make_n_start_reg; |
|
make_control_regs : PROCESS( clock , s_n_start , s_bus_reset , reset , |
s_data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_bus_reset = '1' OR |
reset = '1') THEN read_n_write <= '1'; |
burst_size <= (OTHERS => '0'); |
address <= (OTHERS => '0'); |
ELSIF (s_n_start = '0') THEN read_n_write <= s_data_in(15); |
burst_size <= s_data_in(14 DOWNTO 6); |
address <= s_data_in( 5 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_control_regs; |
|
make_data_regs : PROCESS( clock , s_bus_reset , reset , s_data_n_valid_in , |
s_data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_bus_reset = '1' OR |
reset = '1') THEN data_out <= (OTHERS => '0'); |
b_n_data_valid_out <= "11"; |
b_n_end_transmission_out <= '1'; |
ELSE |
b_n_data_valid_out <= s_data_n_valid_in; |
b_n_end_transmission_out <= s_n_end_in; |
IF (s_data_n_valid_in /= "11") THEN |
data_out <= s_data_in; |
END IF; |
END IF; |
END IF; |
END PROCESS make_data_regs; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_n_error <= '0' WHEN s_bus_reset = '0' AND |
reset = '0' AND |
(n_bus_error = '0' OR |
(s_n_start = '0' AND |
s_data_in(4) = '1')) -- Only vga and fifo for the moment |
ELSE '1'; |
s_n_start_send <= '0' WHEN s_bus_reset = '0' AND |
reset = '0' AND |
n_start_send = '0' ELSE '1'; |
s_n_end_out <= '0' WHEN s_bus_reset = '0' AND |
reset = '0' AND |
b_n_end_transmission_in = '0' ELSE '1'; |
s_n_valid_out <= "11" WHEN s_bus_reset = '1' OR |
reset = '1' ELSE b_n_data_valid_in; |
|
-------------------------------------------------------------------------------- |
--- Here the three state control is defined --- |
-------------------------------------------------------------------------------- |
make_n_force_bus_reg : PROCESS( clock , reset , s_bus_reset , |
s_n_start , s_data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_n_error = '0' OR |
s_n_end_out = '0' OR |
s_bus_reset = '1') THEN s_n_force_bus_reg <= '1'; |
ELSIF (s_n_start = '0' AND |
s_data_in(15) = '1') THEN s_n_force_bus_reg <= '0'; |
END IF; |
END IF; |
END PROCESS make_n_force_bus_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the IOB ffs are defined --- |
-------------------------------------------------------------------------------- |
reset_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_reset, |
C => clock, |
D => bus_reset ); |
make_data_ffs : FOR n IN 15 DOWNTO 0 GENERATE |
bus_data_addr_cntrl(n) <= s_bus_data_addr_cntrl(n) |
WHEN s_bus_data_addr_tri(n) = '0' ELSE |
'Z'; |
din_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_data_in(n), |
C => clock, |
D => bus_data_addr_cntrl(n)); |
dout_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_data_addr_cntrl(n), |
C => clock, |
D => data_in(n) ); |
tri_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_data_addr_tri(n), |
C => clock, |
D => s_n_force_bus_reg ); |
END GENERATE make_data_ffs; |
|
make_data_valid_ffs : FOR n IN 1 DOWNTO 0 GENERATE |
bus_n_data_valid(n) <= s_bus_n_data_valid(n) |
WHEN s_bus_n_data_tri(n) = '0' ELSE |
'Z'; |
in_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_data_n_valid_in(n), |
C => clock, |
D => bus_n_data_valid(n) ); |
out_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_n_data_valid(n), |
C => clock, |
D => s_n_valid_out(n) ); |
tri_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_n_data_tri(n), |
C => clock, |
D => s_n_force_bus_reg ); |
END GENERATE make_data_valid_ffs; |
|
end_in_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_n_end_in, |
C => clock, |
D => bus_n_end_transmission ); |
end_out_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_n_end_transmission, |
C => clock, |
D => s_n_end_out ); |
end_tri_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_bus_n_end_tri, |
C => clock, |
D => s_n_force_bus_reg ); |
|
start_trans_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => s_n_start, |
C => clock, |
D => bus_n_start_transmission ); |
n_error_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => bus_n_error, |
C => clock, |
D => s_n_error ); |
n_send_ff : FD |
GENERIC MAP ( INIT => '1' ) |
PORT MAP ( Q => bus_n_start_send, |
C => clock, |
D => s_n_start_send ); |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/bus_if/bus_if-entity.vhdl
0,0 → 1,64
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
ENTITY bus_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- Here the IOB interface is defined |
bus_reset : IN std_logic; |
bus_n_start_transmission : IN std_logic; |
bus_n_end_transmission : INOUT std_logic; |
bus_n_data_valid : INOUT std_logic_vector( 1 DOWNTO 0 ); |
bus_data_addr_cntrl : INOUT std_logic_vector(15 DOWNTO 0 ); |
bus_n_start_send : OUT std_logic; |
bus_n_error : OUT std_logic; |
|
-- Here the FPGA internal interface is defined |
b_n_reset : OUT std_logic; |
b_n_start_transmission : OUT std_logic; |
b_n_end_transmission_out : OUT std_logic; |
b_n_end_transmission_in : IN std_logic; |
b_n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
b_n_data_valid_in : IN std_logic_vector( 1 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
data_in : IN std_logic_vector(15 DOWNTO 0 ); |
read_n_write : OUT std_logic; |
burst_size : OUT std_logic_vector( 8 DOWNTO 0 ); |
address : OUT std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : IN std_logic; |
n_bus_error : IN std_logic); |
END bus_if; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/scpi_if/scpi_if-entity.vhdl
0,0 → 1,98
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
-- The vendor commands are directly send to the main FPGA without |
-- interpretation of the ieee488.2 controler |
|
ENTITY SCPI_INTERFACE IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- The command interface |
transparent_mode : IN std_logic; |
start_command : OUT std_logic; |
command_id : OUT std_logic_vector( 6 DOWNTO 0 ); |
cmd_gen_respons : OUT std_logic; |
command_done : IN std_logic; |
command_error : IN std_logic; |
unknown_command : OUT std_logic; |
slave_pop : IN std_logic; |
|
-- USBTMC fifo interface |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_empty : IN std_logic; |
pop_last : IN std_logic); |
END SCPI_INTERFACE; |
|
-- Command ID <=> Command |
-- 0x02 <=> "*CLS" |
-- 0x06 <=> "*ESE" |
-- 0x07 <=> "*ESE?" |
-- 0x08 <=> "*ESR?" |
-- 0x09 <=> "*IDN?" |
-- 0x0A <=> "*IST?" |
-- 0x0B <=> "*OPC" |
-- 0x0C <=> "*OPC?" |
-- 0x0D <=> "*PUD" |
-- 0x0E <=> "*PUD?" |
-- 0x0F <=> "*RST" |
-- 0x10 <=> "*SRE" |
-- 0x11 <=> "*SRE?" |
-- 0x12 <=> "*STB?" |
-- 0x14 <=> "*TST?" |
-- 0x15 <=> "*WAI" |
-- 0x16 <=> "BITFLASH" |
-- 0x17 <=> "BITFLASH?" |
-- 0x18 <=> "BOARD?" |
-- 0x19 <=> "CONFIG" |
-- 0x1A <=> "ERASE" |
-- 0x1B <=> "FIFO" |
-- 0x1C <=> "FIFO?" |
-- 0x1D <=> "FPGA" |
-- 0x1E <=> "FPGA?" |
-- 0x23 <=> "HEXSWITCH" |
-- 0x24 <=> "HEXSWITCH?" |
-- 0x25 <=> "IDENTIFY" |
-- 0x33 <=> "TRANS" |
-- 0x3A <=> "USERRESET" |
-- 0x3B <=> "VGA:BGCOL" |
-- 0x3C <=> "VGA:CLEAR" |
-- 0x3D <=> "VGA:CURSOR" |
-- 0x3E <=> "VGA:CURSOR?" |
-- 0x3F <=> "VGA:FGCOL" |
-- 0x40 <=> "VGA:PUTSTR" |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/scpi_if/scpi_if-behavior-xilinx.vhdl
0,0 → 1,630
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF SCPI_INTERFACE IS |
|
COMPONENT RAM16X1S |
GENERIC ( INIT : bit_vector(15 DOWNTO 0 ) ); |
PORT ( O : OUT std_ulogic; |
A0 : IN std_ulogic; |
A1 : IN std_ulogic; |
A2 : IN std_ulogic; |
A3 : IN std_ulogic; |
D : IN std_ulogic; |
WCLK : IN std_ulogic; |
WE : IN std_ulogic ); |
END COMPONENT; |
|
COMPONENT RAMB16_S9 |
GENERIC ( INIT_00 : bit_vector; |
INIT_01 : bit_vector; |
INIT_02 : bit_vector; |
INIT_03 : bit_vector; |
INIT_04 : bit_vector; |
INIT_05 : bit_vector; |
INIT_06 : bit_vector; |
INIT_07 : bit_vector; |
INIT_08 : bit_vector; |
INIT_09 : bit_vector; |
INIT_0A : bit_vector; |
INIT_0B : bit_vector; |
INIT_0C : bit_vector; |
INIT_0D : bit_vector; |
INIT_0E : bit_vector; |
INIT_0F : bit_vector; |
INIT_10 : bit_vector; |
INIT_11 : bit_vector; |
INIT_12 : bit_vector; |
INIT_13 : bit_vector; |
INIT_14 : bit_vector; |
INIT_15 : bit_vector; |
INIT_16 : bit_vector; |
INIT_17 : bit_vector; |
INIT_18 : bit_vector; |
INIT_19 : bit_vector; |
INIT_1A : bit_vector; |
INIT_1B : bit_vector; |
INIT_1C : bit_vector; |
INIT_1D : bit_vector; |
INIT_1E : bit_vector; |
INIT_1F : bit_vector; |
INIT_20 : bit_vector; |
INIT_21 : bit_vector; |
INIT_22 : bit_vector; |
INIT_23 : bit_vector; |
INIT_24 : bit_vector; |
INIT_25 : bit_vector; |
INIT_26 : bit_vector; |
INIT_27 : bit_vector; |
INIT_28 : bit_vector; |
INIT_29 : bit_vector; |
INIT_2A : bit_vector; |
INIT_2B : bit_vector; |
INIT_2C : bit_vector; |
INIT_2D : bit_vector; |
INIT_2E : bit_vector; |
INIT_2F : bit_vector; |
INIT_30 : bit_vector; |
INIT_31 : bit_vector; |
INIT_32 : bit_vector; |
INIT_33 : bit_vector; |
INIT_34 : bit_vector; |
INIT_35 : bit_vector; |
INIT_36 : bit_vector; |
INIT_37 : bit_vector; |
INIT_38 : bit_vector; |
INIT_39 : bit_vector; |
INIT_3A : bit_vector; |
INIT_3B : bit_vector; |
INIT_3C : bit_vector; |
INIT_3D : bit_vector; |
INIT_3E : bit_vector; |
INIT_3F : bit_vector); |
PORT ( DO : OUT std_logic_vector( 7 DOWNTO 0 ); |
DOP : OUT std_logic_vector( 0 DOWNTO 0 ); |
ADDR : IN std_logic_vector( 10 DOWNTO 0 ); |
DI : IN std_logic_vector( 7 DOWNTO 0 ); |
DIP : IN std_logic_vector( 0 DOWNTO 0 ); |
EN : IN std_logic; |
WE : IN std_logic; |
CLK : IN std_logic; |
SSR : IN std_logic ); |
END COMPONENT; |
|
TYPE SCPI_STATES IS (IDLE,INIT_COMMAND_READ,READ_ONE_COMMAND, |
FLUSH_MESSAGE,SIGNAL_ERROR, |
INIT_COMMAND_SEARCH_7 , COMMAND_SEARCH_7 , |
INIT_COMMAND_SEARCH_6 , COMMAND_SEARCH_6 , |
INIT_COMMAND_SEARCH_5 , COMMAND_SEARCH_5 , |
INIT_COMMAND_SEARCH_4 , COMMAND_SEARCH_4 , |
INIT_COMMAND_SEARCH_3 , COMMAND_SEARCH_3 , |
INIT_COMMAND_SEARCH_2 , COMMAND_SEARCH_2 , |
INIT_COMMAND_SEARCH_1 , COMMAND_SEARCH_1 , |
INIT_COMMAND_SEARCH_0 , COMMAND_SEARCH_0 , |
FETCH_COMMAND_ID , WAIT_FOR_DONE ); |
CONSTANT c_small_a_1 : std_logic_vector( 7 DOWNTO 0 ) := X"60"; |
CONSTANT c_small_z_1 : std_logic_vector( 7 DOWNTO 0 ) := X"7B"; |
|
SIGNAL s_scpi_state_machine : SCPI_STATES; |
SIGNAL s_n_clock : std_logic; |
SIGNAL s_pop_byte : std_logic; |
SIGNAL s_upcased_char : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_is_lower_case : std_logic; |
SIGNAL s_is_command_seperator : std_logic; |
SIGNAL s_command_buffer_address_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_write_byte : std_logic; |
SIGNAL s_command_too_long : std_logic; |
SIGNAL s_command_stored : std_logic; |
SIGNAL s_command_byte : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_command_char : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_command_rom_search_addr : std_logic_vector( 10 DOWNTO 0 ); |
SIGNAL s_command_rom_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_rom_data_zero : std_logic; |
SIGNAL s_buffer_data_zero : std_logic; |
SIGNAL s_command_match : std_logic; |
SIGNAL s_command_smaller : std_logic; |
SIGNAL s_command_bigger : std_logic; |
SIGNAL s_search_command : std_logic; |
SIGNAL s_cmd_gen_respons_reg : std_logic; |
SIGNAL s_message_in_progress_reg : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
pop <= s_pop_byte OR slave_pop; |
unknown_command <= '1' WHEN s_scpi_state_machine = COMMAND_SEARCH_0 AND |
(s_command_smaller = '1' OR |
s_command_bigger = '1') ELSE '0'; |
make_command : PROCESS( clock , reset , s_scpi_state_machine , |
s_command_rom_data , s_cmd_gen_respons_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN start_command <= '0'; |
command_id <= (OTHERS => '0'); |
cmd_gen_respons <= '0'; |
ELSE |
IF (s_scpi_state_machine = FETCH_COMMAND_ID) THEN |
start_command <= '1'; |
command_id <= s_command_rom_data( 6 DOWNTO 0 ); |
cmd_gen_respons <= s_cmd_gen_respons_reg; |
ELSE |
start_command <= '0'; |
cmd_gen_respons <= '0'; |
END IF; |
END IF; |
END IF; |
END PROCESS make_command; |
|
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_scpi_state_machine : PROCESS( clock , reset , s_scpi_state_machine , |
transparent_mode , pop_empty, |
s_command_too_long , |
s_command_stored , s_command_match , |
s_command_bigger , s_command_smaller ) |
VARIABLE v_next_state : SCPI_STATES; |
BEGIN |
CASE (s_scpi_state_machine) IS |
WHEN IDLE => IF (transparent_mode = '0' AND |
pop_empty = '0') THEN |
v_next_state := INIT_COMMAND_READ; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_COMMAND_READ => v_next_state := READ_ONE_COMMAND; |
WHEN READ_ONE_COMMAND => IF (s_command_too_long = '1') THEN |
v_next_state := FLUSH_MESSAGE; |
ELSIF (s_command_stored = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_7; |
ELSIF (pop_last = '1' AND |
pop_empty = '0') THEN |
v_next_state := SIGNAL_ERROR; |
ELSE |
v_next_state := READ_ONE_COMMAND; |
END IF; |
WHEN INIT_COMMAND_SEARCH_7 => v_next_state := COMMAND_SEARCH_7; |
WHEN COMMAND_SEARCH_7 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_6; |
ELSE |
v_next_state := COMMAND_SEARCH_7; |
END IF; |
WHEN INIT_COMMAND_SEARCH_6 => v_next_state := COMMAND_SEARCH_6; |
WHEN COMMAND_SEARCH_6 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_5; |
ELSE |
v_next_state := COMMAND_SEARCH_6; |
END IF; |
WHEN INIT_COMMAND_SEARCH_5 => v_next_state := COMMAND_SEARCH_5; |
WHEN COMMAND_SEARCH_5 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_4; |
ELSE |
v_next_state := COMMAND_SEARCH_5; |
END IF; |
WHEN INIT_COMMAND_SEARCH_4 => v_next_state := COMMAND_SEARCH_4; |
WHEN COMMAND_SEARCH_4 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_3; |
ELSE |
v_next_state := COMMAND_SEARCH_4; |
END IF; |
WHEN INIT_COMMAND_SEARCH_3 => v_next_state := COMMAND_SEARCH_3; |
WHEN COMMAND_SEARCH_3 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_2; |
ELSE |
v_next_state := COMMAND_SEARCH_3; |
END IF; |
WHEN INIT_COMMAND_SEARCH_2 => v_next_state := COMMAND_SEARCH_2; |
WHEN COMMAND_SEARCH_2 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_1; |
ELSE |
v_next_state := COMMAND_SEARCH_2; |
END IF; |
WHEN INIT_COMMAND_SEARCH_1 => v_next_state := COMMAND_SEARCH_1; |
WHEN COMMAND_SEARCH_1 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := INIT_COMMAND_SEARCH_0; |
ELSE |
v_next_state := COMMAND_SEARCH_1; |
END IF; |
WHEN INIT_COMMAND_SEARCH_0 => v_next_state := COMMAND_SEARCH_0; |
WHEN COMMAND_SEARCH_0 => IF (s_command_match = '1') THEN |
v_next_state := FETCH_COMMAND_ID; |
ELSIF (s_command_smaller = '1' OR |
s_command_bigger = '1') THEN |
v_next_state := FLUSH_MESSAGE; |
ELSE |
v_next_state := COMMAND_SEARCH_0; |
END IF; |
WHEN FETCH_COMMAND_ID => v_next_state := WAIT_FOR_DONE; |
WHEN WAIT_FOR_DONE => IF (command_error = '1') THEN |
v_next_state := FLUSH_MESSAGE; |
ELSIF (command_done = '1') THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := WAIT_FOR_DONE; |
END IF; |
WHEN FLUSH_MESSAGE => IF (s_message_in_progress_reg = '1') THEN |
v_next_state := FLUSH_MESSAGE; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_scpi_state_machine <= IDLE; |
ELSE s_scpi_state_machine <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_scpi_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the message in progress reg is defined --- |
-------------------------------------------------------------------------------- |
make_message_in_progress_reg : PROCESS( clock , reset , |
s_scpi_state_machine ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
(pop_last = '1' AND |
(s_pop_byte = '1' OR |
slave_pop = '1'))) THEN s_message_in_progress_reg <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_READ) THEN |
s_message_in_progress_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_message_in_progress_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the input fifo handling is defined --- |
-------------------------------------------------------------------------------- |
s_pop_byte <= '1' WHEN (s_scpi_state_machine = READ_ONE_COMMAND OR |
(s_scpi_state_machine = FLUSH_MESSAGE AND |
s_message_in_progress_reg = '1')) AND |
pop_empty = '0' |
ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the command buffer handling is defined --- |
-------------------------------------------------------------------------------- |
s_n_clock <= NOT( clock ); |
s_upcased_char(7 DOWNTO 6) <= pop_data(7 DOWNTO 6); |
s_upcased_char( 5) <= pop_data(5) XOR s_is_lower_case; |
s_upcased_char(4 DOWNTO 0) <= pop_data(4 DOWNTO 0); |
s_command_rom_search_addr( 3 DOWNTO 0 ) <= s_command_buffer_address_reg; |
|
|
s_is_lower_case <= '1' WHEN |
(unsigned(pop_data) > unsigned(c_small_a_1)) AND |
(unsigned(pop_data) < unsigned(c_small_z_1)) ELSE '0'; |
s_is_command_seperator <= '1' WHEN pop_data = X"0A" OR |
pop_data = X"20" OR |
pop_data = X"3B" ELSE '0'; |
s_write_byte <= '1' WHEN |
(s_is_command_seperator = '0' AND |
s_pop_byte = '1' AND |
s_scpi_state_machine = READ_ONE_COMMAND) OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_7 ELSE '0'; |
s_command_too_long <= '1' WHEN s_is_command_seperator = '0' AND |
pop_empty = '0' AND |
s_command_buffer_address_reg = X"F" |
ELSE '0'; |
s_command_stored <= '1' WHEN |
(s_pop_byte = '1' AND |
s_is_command_seperator = '1' AND |
s_command_buffer_address_reg /= X"0") |
ELSE '0'; |
s_command_byte <= X"00" WHEN s_scpi_state_machine = INIT_COMMAND_SEARCH_7 |
ELSE s_upcased_char; |
s_rom_data_zero <= '1' WHEN s_command_rom_data = X"00" ELSE '0'; |
s_buffer_data_zero <= '1' WHEN s_command_char = X"00" ELSE '0'; |
s_command_match <= s_rom_data_zero AND s_buffer_data_zero; |
s_command_smaller <= '1' WHEN unsigned(s_command_char) < |
unsigned(s_command_rom_data) ELSE '0'; |
s_command_bigger <= '1' WHEN unsigned(s_command_char) > |
unsigned(s_command_rom_data) ELSE '0'; |
s_search_command <= '1' WHEN |
s_scpi_state_machine = COMMAND_SEARCH_7 OR |
s_scpi_state_machine = COMMAND_SEARCH_6 OR |
s_scpi_state_machine = COMMAND_SEARCH_5 OR |
s_scpi_state_machine = COMMAND_SEARCH_4 OR |
s_scpi_state_machine = COMMAND_SEARCH_3 OR |
s_scpi_state_machine = COMMAND_SEARCH_2 OR |
s_scpi_state_machine = COMMAND_SEARCH_1 OR |
s_scpi_state_machine = COMMAND_SEARCH_0 |
ELSE '0'; |
|
make_cmd_gen_respons_reg : PROCESS( clock , reset , s_scpi_state_machine , |
s_command_byte , s_write_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_READ OR |
reset = '1') THEN s_cmd_gen_respons_reg <= '0'; |
ELSIF (s_write_byte = '1' AND |
s_command_byte = X"3F") THEN |
s_cmd_gen_respons_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_cmd_gen_respons_reg; |
|
make_command_rom_search_addr_7 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(10) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_7 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(10) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_7; |
|
make_command_rom_search_addr_6 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(9) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_6) THEN |
s_command_rom_search_addr(9) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_6 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(9) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_6; |
|
make_command_rom_search_addr_5 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(8) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_5) THEN |
s_command_rom_search_addr(8) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_5 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(8) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_5; |
|
make_command_rom_search_addr_4 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(7) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_4) THEN |
s_command_rom_search_addr(7) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_4 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(7) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_4; |
|
make_command_rom_search_addr_3 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(6) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_3) THEN |
s_command_rom_search_addr(6) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_3 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(6) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_3; |
|
make_command_rom_search_addr_2 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
reset = '1') THEN s_command_rom_search_addr(5) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_2) THEN |
s_command_rom_search_addr(5) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_2 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(5) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_2; |
|
make_command_rom_search_addr_1 : PROCESS( clock , reset , |
s_scpi_state_machine , |
s_command_smaller ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_0 OR |
reset = '1') THEN s_command_rom_search_addr(4) <= '0'; |
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_1) THEN |
s_command_rom_search_addr(4) <= '1'; |
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_1 AND |
s_command_smaller = '1') THEN |
s_command_rom_search_addr(4) <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_rom_search_addr_1; |
|
make_command_buffer_address_reg : PROCESS( clock , reset , s_write_byte , |
s_scpi_state_machine , |
s_search_command ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scpi_state_machine = INIT_COMMAND_READ OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_6 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_5 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_4 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_3 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_2 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_1 OR |
s_scpi_state_machine = INIT_COMMAND_SEARCH_0 OR |
reset = '1') THEN s_command_buffer_address_reg <= (OTHERS => '0'); |
ELSIF (s_write_byte = '1' OR |
s_search_command = '1') THEN |
s_command_buffer_address_reg <= unsigned(s_command_buffer_address_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_command_buffer_address_reg; |
|
command_buffer : FOR n IN 7 DOWNTO 0 GENERATE |
one_bit : RAM16X1S |
GENERIC MAP ( INIT => X"0000" ) |
PORT MAP ( O => s_command_char(n), |
A0 => s_command_buffer_address_reg(0), |
A1 => s_command_buffer_address_reg(1), |
A2 => s_command_buffer_address_reg(2), |
A3 => s_command_buffer_address_reg(3), |
D => s_command_byte(n), |
WCLK => clock, |
WE => s_write_byte ); |
END GENERATE command_buffer; |
|
command_rom : RAMB16_S9 |
GENERIC MAP ( INIT_00 => X"FFFFFFFFFFFFFFFFFFFF06004553452AFFFFFFFFFFFFFFFFFFFF0200534C432A", |
INIT_01 => X"FFFFFFFFFFFFFFFFFF08003F5253452AFFFFFFFFFFFFFFFFFF07003F4553452A", |
INIT_02 => X"FFFFFFFFFFFFFFFFFF0A003F5453492AFFFFFFFFFFFFFFFFFF09003F4E44492A", |
INIT_03 => X"FFFFFFFFFFFFFFFFFF0C003F43504F2AFFFFFFFFFFFFFFFFFFFF0B0043504F2A", |
INIT_04 => X"FFFFFFFFFFFFFFFFFF0E003F4455502AFFFFFFFFFFFFFFFFFFFF0D004455502A", |
INIT_05 => X"FFFFFFFFFFFFFFFFFFFF10004552532AFFFFFFFFFFFFFFFFFFFF0F005453522A", |
INIT_06 => X"FFFFFFFFFFFFFFFFFF12003F4254532AFFFFFFFFFFFFFFFFFF11003F4552532A", |
INIT_07 => X"FFFFFFFFFFFFFFFFFFFF15004941572AFFFFFFFFFFFFFFFFFF14003F5453542A", |
INIT_08 => X"FFFFFFFFFF17003F4853414C46544942FFFFFFFFFFFF16004853414C46544942", |
INIT_09 => X"FFFFFFFFFFFFFFFF19004749464E4F43FFFFFFFFFFFFFFFF18003F4452414F42", |
INIT_0A => X"FFFFFFFFFFFFFFFFFFFF1B004F464946FFFFFFFFFFFFFFFFFF1A004553415245", |
INIT_0B => X"FFFFFFFFFFFFFFFFFFFF1D0041475046FFFFFFFFFFFFFFFFFF1C003F4F464946", |
INIT_0C => X"FFFFFFFFFF2300484354495753584548FFFFFFFFFFFFFFFFFF1E003F41475046", |
INIT_0D => X"FFFFFFFFFFFF2500594649544E454449FFFFFFFF24003F484354495753584548", |
INIT_0E => X"FFFFFFFFFF3A00544553455252455355FFFFFFFFFFFFFFFFFF3300534E415254", |
INIT_0F => X"FFFFFFFFFF3C005241454C433A414756FFFFFFFFFF3B004C4F4347423A414756", |
INIT_10 => X"FFFFFF3E003F524F535255433A414756FFFFFFFF3D00524F535255433A414756", |
INIT_11 => X"FFFFFFFF40005254535455503A414756FFFFFFFFFF3F004C4F4347463A414756", |
INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_13 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_14 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_15 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_16 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_18 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_19 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_20 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_22 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_23 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_25 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_26 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_28 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_29 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_2F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_30 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_31 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_32 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_33 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_34 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_35 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_36 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_37 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_38 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE", |
INIT_3F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE") |
PORT MAP ( DO => s_command_rom_data, |
DOP => OPEN, |
ADDR => s_command_rom_search_addr, |
DI => X"00", |
DIP => "0", |
EN => '1', |
WE => '0', |
CLK => s_n_clock, |
SSR => '0' ); |
|
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/spi-entity.vhdl
0,0 → 1,51
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY spi_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
read_request : IN std_logic; |
write_request : IN std_logic; |
i2c_write_done : IN std_logic; |
address : IN std_logic_vector( 11 DOWNTO 0 ); |
data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
|
done : OUT std_logic; |
busy : OUT std_logic ); |
END spi_if; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/edge_detector-entity.vhdl
0,0 → 1,45
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
ENTITY edge_detector IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
data_in : IN std_logic; |
pos_edge : OUT std_logic; |
neg_edge : OUT std_logic; |
data_out : OUT std_logic ); |
END edge_detector; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/edge_detector-behavior.vhdl
0,0 → 1,68
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_platform_specific OF edge_detector IS |
|
SIGNAL s_pipe_regs : std_logic_vector( 3 DOWNTO 0 ); |
|
BEGIN |
|
make_pipe_regs : PROCESS( clock , reset , data_in ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_pipe_regs <= (OTHERS => '1'); |
ELSE |
s_pipe_regs <= s_pipe_regs( 2 DOWNTO 0 )& data_in; |
END IF; |
END IF; |
END PROCESS make_pipe_regs; |
|
make_output_regs : PROCESS( clock , reset , s_pipe_regs ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN data_out <= '1'; |
pos_edge <= '0'; |
neg_edge <= '0'; |
ELSE data_out <= s_pipe_regs(1); |
pos_edge <= NOT(s_pipe_regs(3)) AND |
NOT(s_pipe_regs(2)) AND |
s_pipe_regs(1) AND |
s_pipe_regs(0); |
neg_edge <= NOT(s_pipe_regs(0)) AND |
NOT(s_pipe_regs(1)) AND |
s_pipe_regs(2) AND |
s_pipe_regs(3); |
END IF; |
END IF; |
END PROCESS make_output_regs; |
END no_platform_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/24LC32A_emu-entity.vhdl
0,0 → 1,47
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY eeprom_emu IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
button : IN std_logic; |
|
SDA_in : IN std_logic; |
SCL_in : IN std_logic; |
SDA_out : OUT std_logic ); |
END eeprom_emu; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/24LC32A_emu-behavior.vhdl
0,0 → 1,316
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE xilinx OF eeprom_emu IS |
|
COMPONENT edge_detector |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
data_in : IN std_logic; |
pos_edge : OUT std_logic; |
neg_edge : OUT std_logic; |
data_out : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT spi_if |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
read_request : IN std_logic; |
write_request : IN std_logic; |
i2c_write_done : IN std_logic; |
address : IN std_logic_vector( 11 DOWNTO 0 ); |
data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
data_out : OUT std_logic_vector( 7 DOWNTO 0 ); |
done : OUT std_logic; |
busy : OUT std_logic ); |
END COMPONENT; |
|
TYPE state_type IS (IDLE,GET_CONTROL,CHECK_CONTROL,SEND_CONTROL_ACK, |
GET_HI_ADDRESS,SEND_HI_ADDR_ACK,GET_LO_ADDRESS, |
SEND_LO_ADDR_ACK,GET_DATA,SEND_DATA_ACK, |
LATCH_DATA_OUT,WRITE_DATA, SAMPLE_DATA_ACK ); |
|
SIGNAL s_scl_neg_edge : std_logic; |
SIGNAL s_scl_pos_edge : std_logic; |
SIGNAL s_scl_value : std_logic; |
SIGNAL s_sda_neg_edge : std_logic; |
SIGNAL s_sda_pos_edge : std_logic; |
SIGNAL s_sda_value : std_logic; |
SIGNAL s_start_condition : std_logic; |
SIGNAL s_stop_condition : std_logic; |
SIGNAL s_shift_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_bit_count_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_state_reg : state_type; |
SIGNAL s_next_state : state_type; |
SIGNAL s_sda_out_next : std_logic; |
SIGNAL s_address_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_shift_next : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_spi_busy : std_logic; |
SIGNAL s_i2c_write_done : std_logic; |
SIGNAL s_read_request : std_logic; |
SIGNAL s_write_request : std_logic; |
SIGNAL s_read_request_reg : std_logic; |
SIGNAL s_write_request_reg: std_logic; |
|
BEGIN |
-- Assign outputs |
make_SDA_out : PROCESS( clock , reset , s_sda_out_next , s_scl_neg_edge ) |
VARIABLE v_enable_reg : std_logic; |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN SDA_out <= '1'; |
v_enable_reg := '0'; |
ELSE |
IF (v_enable_reg = '1') THEN SDA_out <= s_sda_out_next; |
END IF; |
v_enable_reg := s_scl_neg_edge; |
END IF; |
END IF; |
END PROCESS make_SDA_out; |
|
-- Define control signals |
s_read_request <= '1' WHEN s_start_condition = '1' OR |
(s_state_reg = LATCH_DATA_OUT AND |
s_scl_neg_edge = '1') ELSE '0'; |
s_write_request <= '1' WHEN (s_state_reg = SEND_DATA_ACK AND |
s_scl_pos_edge = '1') ELSE '0'; |
s_i2c_write_done <= s_start_condition OR s_stop_condition; |
s_start_condition <= s_scl_value AND s_sda_neg_edge; |
s_stop_condition <= s_scl_value AND s_sda_pos_edge; |
s_sda_out_next <= '0' |
WHEN s_state_reg = SEND_CONTROL_ACK OR |
s_state_reg = SEND_HI_ADDR_ACK OR |
s_state_reg = SEND_LO_ADDR_ACK OR |
s_state_reg = SEND_DATA_ACK |
ELSE |
s_shift_reg(7) OR NOT(button) |
WHEN s_state_reg = WRITE_DATA |
ELSE '1'; |
|
-- Define processes |
make_regs : PROCESS( clock , reset , s_read_request , s_write_request ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_read_request_reg <= '0'; |
s_write_request_reg <= '0'; |
ELSE s_read_request_reg <= s_read_request; |
s_write_request_reg <= s_write_request; |
END IF; |
END IF; |
END PROCESS make_regs; |
|
make_shift_reg : PROCESS( clock , s_state_reg , s_sda_value , s_scl_pos_edge ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_scl_pos_edge = '1' AND |
(s_state_reg = GET_CONTROL OR |
s_state_reg = GET_DATA)) THEN |
s_shift_reg <= s_shift_reg(6 DOWNTO 0)&s_sda_value; |
ELSIF (s_scl_neg_edge = '1' AND |
s_state_reg = LATCH_DATA_OUT) THEN |
s_shift_reg <= s_shift_next; |
ELSIF (s_scl_neg_edge = '1' AND |
s_state_reg = WRITE_DATA) THEN |
s_shift_reg <= s_shift_reg(6 DOWNTO 0)&"1"; |
END IF; |
END IF; |
END PROCESS make_shift_reg; |
|
make_bit_count_reg : PROCESS( clock , s_state_reg , s_scl_pos_edge , |
s_start_condition ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_state_reg = IDLE OR |
s_state_reg = SEND_CONTROL_ACK OR |
s_state_reg = SEND_HI_ADDR_ACK OR |
s_state_reg = SEND_LO_ADDR_ACK OR |
s_state_reg = SEND_DATA_ACK OR |
s_start_condition = '1') THEN s_bit_count_reg <= X"0"; |
ELSIF (s_state_reg = LATCH_DATA_OUT) THEN s_bit_count_reg <= X"1"; |
ELSIF (((s_state_reg = GET_CONTROL OR |
s_state_reg = GET_HI_ADDRESS OR |
s_state_reg = GET_LO_ADDRESS OR |
s_state_reg = GET_DATA)AND |
s_scl_pos_edge = '1') OR |
(s_state_reg = WRITE_DATA AND |
s_scl_neg_edge = '1')) THEN |
s_bit_count_reg <= unsigned(s_bit_count_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_bit_count_reg; |
|
make_address_reg : PROCESS( clock , s_state_reg , s_sda_value , |
s_scl_pos_edge , reset , s_scl_neg_edge ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_address_reg <= (OTHERS => '0'); |
ELSIF (s_scl_pos_edge = '1') THEN |
CASE (s_state_reg) IS |
WHEN GET_HI_ADDRESS => s_address_reg <= |
s_address_reg(10 DOWNTO 8)&s_sda_value& |
s_address_reg( 7 DOWNTO 0); |
WHEN GET_LO_ADDRESS => s_address_reg <= |
s_address_reg(11 DOWNTO 8)& |
s_address_reg( 6 DOWNTO 0)&s_sda_value; |
WHEN OTHERS => NULL; |
END CASE; |
ELSIF (s_scl_pos_edge = '1' AND |
s_state_reg = SEND_DATA_ACK) OR |
(s_scl_neg_edge = '1' AND |
s_state_reg = LATCH_DATA_OUT) THEN |
s_address_reg <= unsigned(s_address_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_address_reg; |
|
make_next_state : PROCESS( s_state_reg , s_stop_condition , |
s_start_condition , s_bit_count_reg , s_shift_reg , |
s_scl_neg_edge , s_scl_pos_edge , s_spi_busy ) |
BEGIN |
CASE (s_state_reg) IS |
WHEN GET_CONTROL => IF (s_bit_count_reg(3) = '1') THEN |
s_next_state <= CHECK_CONTROL; |
ELSE |
s_next_state <= GET_CONTROL; |
END IF; |
WHEN CHECK_CONTROL => IF (s_shift_reg(7 DOWNTO 1) /= "1010001" OR |
s_spi_busy = '1') THEN |
s_next_state <= IDLE; |
ELSIF (s_scl_neg_edge = '1') THEN |
s_next_state <= SEND_CONTROL_ACK; |
ELSE |
s_next_state <= CHECK_CONTROL; |
END IF; |
WHEN SEND_CONTROL_ACK => IF (s_scl_pos_edge = '1') THEN |
IF (s_shift_reg(0) = '0') THEN |
s_next_state <= GET_HI_ADDRESS; |
ELSE |
s_next_state <= LATCH_DATA_OUT; |
END IF; |
ELSE |
s_next_state <= SEND_CONTROL_ACK; |
END IF; |
WHEN GET_HI_ADDRESS => IF (s_bit_count_reg(3) = '1') THEN |
s_next_state <= SEND_HI_ADDR_ACK; |
ELSE |
s_next_state <= GET_HI_ADDRESS; |
END IF; |
WHEN SEND_HI_ADDR_ACK => IF (s_scl_pos_edge = '1') THEN |
s_next_state <= GET_LO_ADDRESS; |
ELSE |
s_next_state <= SEND_HI_ADDR_ACK; |
END IF; |
WHEN GET_LO_ADDRESS => IF (s_bit_count_reg(3) = '1') THEN |
s_next_state <= SEND_LO_ADDR_ACK; |
ELSE |
s_next_state <= GET_LO_ADDRESS; |
END IF; |
WHEN SEND_LO_ADDR_ACK => IF (s_scl_pos_edge = '1') THEN |
s_next_state <= GET_DATA; |
ELSE |
s_next_state <= SEND_LO_ADDR_ACK; |
END IF; |
WHEN GET_DATA => IF (s_bit_count_reg(3) = '1') THEN |
s_next_state <= SEND_DATA_ACK; |
ELSE |
s_next_state <= GET_DATA; |
END IF; |
WHEN SEND_DATA_ACK => IF (s_scl_pos_edge = '1') THEN |
s_next_state <= GET_DATA; |
ELSE |
s_next_state <= SEND_DATA_ACK; |
END IF; |
WHEN LATCH_DATA_OUT => IF (s_scl_neg_edge = '1') THEN |
s_next_state <= WRITE_DATA; |
ELSE |
s_next_state <= LATCH_DATA_OUT; |
END IF; |
WHEN WRITE_DATA => IF (s_bit_count_reg(3) = '1' AND |
s_scl_pos_edge = '1') THEN |
s_next_state <= SAMPLE_DATA_ACK; |
ELSE |
s_next_state <= WRITE_DATA; |
END IF; |
WHEN SAMPLE_DATA_ACK => IF (s_scl_pos_edge = '1') THEN |
IF (s_sda_value = '0') THEN |
s_next_state <= LATCH_DATA_OUT; |
ELSE |
s_next_state <= IDLE; |
END IF; |
ELSE |
s_next_state <= SAMPLE_DATA_ACK; |
END IF; |
WHEN OTHERS => s_next_state <= IDLE; |
END CASE; |
END PROCESS make_next_state; |
|
make_state_reg : PROCESS( clock , reset , s_stop_condition , |
s_start_condition , s_next_state ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_stop_condition = '1') THEN s_state_reg <= IDLE; |
ELSIF (s_start_condition = '1') THEN s_state_reg <= GET_CONTROL; |
ELSE s_state_reg <= s_next_state; |
END IF; |
END IF; |
END PROCESS make_state_reg; |
|
-- Map components |
scl_det : edge_detector |
PORT MAP ( clock => clock, |
reset => reset, |
data_in => SCL_in, |
pos_edge => s_scl_pos_edge, |
neg_edge => s_scl_neg_edge, |
data_out => s_scl_value ); |
sda_det : edge_detector |
PORT MAP ( clock => clock, |
reset => reset, |
data_in => SDA_in, |
pos_edge => s_sda_pos_edge, |
neg_edge => s_sda_neg_edge, |
data_out => s_sda_value ); |
spi : spi_if |
PORT MAP ( clock => clock, |
reset => reset, |
read_request => s_read_request_reg, |
write_request => s_write_request_reg, |
i2c_write_done => s_i2c_write_done, |
address => s_address_reg, |
data_in => s_shift_reg, |
data_out => s_shift_next, |
done => OPEN, |
busy => s_spi_busy ); |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/i2c/spi-behavior-xilinx.vhdl
0,0 → 1,305
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
library UNISIM; |
use UNISIM.VComponents.all; |
|
ARCHITECTURE xilinx OF spi_if IS |
|
TYPE STATE_TYPE IS (IDLE,INIT_READ,WAIT_READ,ALL_DONE, |
INIT_PAGE_LOAD,WAIT_I2C_DONE,INIT_STATE_REG_1, |
POLL_STATE_REG_1,INIT_WRITE,WAIT_WRITE, INIT_WRITE_BACK , |
WAIT_WRITE_BACK,INIT_STATE_REG_2,POLL_STATE_REG_2); |
|
COMPONENT SPI_ACCESS |
GENERIC ( SIM_DEVICE : string ); |
PORT( MISO : OUT std_ulogic; |
CLK : IN std_ulogic; |
CSB : IN std_ulogic; |
MOSI : IN std_ulogic ); |
END COMPONENT; |
|
COMPONENT RAM32X1S |
PORT ( O : OUT std_logic; |
A0 : IN std_logic; |
A1 : IN std_logic; |
A2 : IN std_logic; |
A3 : IN std_logic; |
A4 : IN std_logic; |
D : IN std_logic; |
WCLK : IN std_logic; |
WE : IN std_logic); |
END COMPONENT; |
|
SIGNAL s_state_reg : STATE_TYPE; |
SIGNAL s_spi_shift_reg : std_logic_vector(31 DOWNTO 0 ); |
SIGNAL s_spi_shift_next : std_logic_vector(31 DOWNTO 0 ); |
SIGNAL s_spi_shift_load : std_logic_vector(31 DOWNTO 0 ); |
SIGNAL s_n_ena_spi : std_logic; |
SIGNAL s_spi_miso : std_logic; |
SIGNAL s_spi_count_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_spi_count_load : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_start_spi_action : std_logic; |
SIGNAL s_spi_clk_reg : std_logic; |
SIGNAL s_spi_mosi : std_logic; |
SIGNAL s_spi_ram_index_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_spi_size_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_spi_address_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_load_data_byte : std_logic; |
SIGNAL s_buffer_data : std_logic_vector( 7 DOWNTO 0 ); |
|
BEGIN |
-- Assign outputs |
data_out <= s_spi_shift_reg( 7 DOWNTO 0 ); |
done <= '1' WHEN s_state_reg = ALL_DONE ELSE '0'; |
busy <= '0' WHEN s_state_reg = IDLE OR |
s_state_reg = INIT_READ OR |
s_state_reg = WAIT_READ OR |
s_state_reg = ALL_DONE ELSE '1'; |
|
-- Assign control signals |
s_start_spi_action <= '1' WHEN s_state_reg = INIT_READ OR |
s_state_reg = INIT_PAGE_LOAD OR |
s_state_reg = INIT_STATE_REG_1 OR |
s_state_reg = INIT_WRITE OR |
s_state_reg = INIT_WRITE_BACK OR |
s_state_reg = INIT_STATE_REG_2 ELSE '0'; |
|
s_n_ena_spi <= s_spi_count_reg(9) AND NOT(s_spi_count_reg(0)); |
s_load_data_byte <= '1' WHEN s_state_reg = WAIT_WRITE AND |
s_spi_count_reg( 2 DOWNTO 0 ) = "000" AND |
s_spi_clk_reg = '1' ELSE '0'; |
s_spi_shift_next <= s_spi_shift_load |
WHEN s_start_spi_action = '1' ELSE |
s_spi_shift_reg WHEN s_n_ena_spi = '1' OR |
s_spi_clk_reg = '0' ELSE |
s_spi_shift_reg(30 DOWNTO 7)&s_buffer_data |
WHEN s_load_data_byte = '1' ELSE |
s_spi_shift_reg(30 DOWNTO 0)&s_spi_miso; |
|
-- map processes |
make_spi_load_values : PROCESS( s_state_reg , address , |
s_spi_address_reg ) |
VARIABLE v_select : std_logic_vector( 1 DOWNTO 0 ); |
VARIABLE v_add : std_logic_vector( 5 DOWNTO 0 ); |
BEGIN |
CASE (s_state_reg) IS |
WHEN INIT_READ => s_spi_shift_load <= X"030F"&"111"& |
s_spi_address_reg(11 DOWNTO 8)&"0"& |
s_spi_address_reg(7 DOWNTO 0); |
s_spi_count_load <= "0000100111"; |
WHEN INIT_PAGE_LOAD => s_spi_shift_load <= X"530F"&"111"& |
s_spi_address_reg(11 DOWNTO 8)&"0"& |
X"00"; |
s_spi_count_load <= "0000011111"; |
WHEN INIT_STATE_REG_1 | |
INIT_STATE_REG_2=> s_spi_shift_load <= X"D7000000"; |
s_spi_count_load <= "0000001111"; |
WHEN INIT_WRITE => s_spi_shift_load <= X"840000"&s_spi_address_reg(7 DOWNTO 0); |
v_add := unsigned(s_spi_size_reg) + 3; |
s_spi_count_load <= "0"&v_add&"111"; |
WHEN INIT_WRITE_BACK => s_spi_shift_load <= X"830F"&"111"& |
s_spi_address_reg(11 DOWNTO 8)&"0"& |
X"00"; |
s_spi_count_load <= "0000011111"; |
WHEN OTHERS => s_spi_shift_load <= X"00000000"; |
s_spi_count_load <= "1111111110"; |
END CASE; |
END PROCESS make_spi_load_values; |
|
make_state_machine : PROCESS( clock , reset , s_state_reg , |
read_request , s_spi_count_reg , |
write_request , i2c_write_done , |
s_spi_shift_reg ) |
VARIABLE v_next_state : STATE_TYPE; |
BEGIN |
CASE (s_state_reg) IS |
WHEN IDLE => IF (read_request = '1') THEN |
v_next_state := INIT_READ; |
ELSIF (write_request = '1') THEN |
v_next_state := INIT_PAGE_LOAD; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_READ => v_next_state := WAIT_READ; |
WHEN WAIT_READ => IF (s_spi_count_reg(9) = '1') THEN |
v_next_state := ALL_DONE; |
ELSE |
v_next_state := WAIT_READ; |
END IF; |
WHEN INIT_PAGE_LOAD => v_next_state := WAIT_I2C_DONE; |
WHEN WAIT_I2C_DONE => IF (i2c_write_done = '1') THEN |
v_next_state := INIT_STATE_REG_1; |
ELSE |
v_next_state := WAIT_I2C_DONE; |
END IF; |
WHEN INIT_STATE_REG_1 => v_next_state := POLL_STATE_REG_1; |
WHEN POLL_STATE_REG_1 => IF (s_spi_count_reg(9) = '1' AND |
s_spi_count_reg(0) = '0') THEN |
IF (s_spi_shift_reg(7) = '0') THEN |
v_next_state := INIT_STATE_REG_1; |
ELSE |
v_next_state := INIT_WRITE; |
END IF; |
ELSE |
v_next_state := POLL_STATE_REG_1; |
END IF; |
WHEN INIT_WRITE => v_next_state := WAIT_WRITE; |
WHEN WAIT_WRITE => IF (s_spi_count_reg(9) = '1' AND |
s_spi_count_reg(0) = '0') THEN |
v_next_state := INIT_WRITE_BACK; |
ELSE |
v_next_state := WAIT_WRITE; |
END IF; |
WHEN INIT_WRITE_BACK => v_next_state := WAIT_WRITE_BACK; |
WHEN WAIT_WRITE_BACK => IF (s_spi_count_reg(9) = '1' AND |
s_spi_count_reg(0) = '0') THEN |
v_next_state := INIT_STATE_REG_2; |
ELSE |
v_next_state := WAIT_WRITE_BACK; |
END IF; |
WHEN INIT_STATE_REG_2 => v_next_state := POLL_STATE_REG_2; |
WHEN POLL_STATE_REG_2 => IF (s_spi_count_reg(9) = '1' AND |
s_spi_count_reg(0) = '0') THEN |
IF (s_spi_shift_reg(7) = '0') THEN |
v_next_state := INIT_STATE_REG_2; |
ELSE |
v_next_state := ALL_DONE; |
END IF; |
ELSE |
v_next_state := POLL_STATE_REG_2; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_state_reg <= IDLE; |
ELSE s_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
|
make_spi_count_reg : PROCESS( clock , reset , s_spi_count_reg , |
s_start_spi_action ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_spi_count_reg <= (0 => '0' , OTHERS => '1'); |
ELSIF (s_start_spi_action = '1') THEN s_spi_count_reg <= s_spi_count_load; |
ELSIF ((s_spi_count_reg(9) = '0' OR |
s_spi_count_reg(0) = '1') AND |
(s_spi_clk_reg = '0' OR |
(s_spi_count_reg(9) = '1' AND |
s_spi_count_reg(0) = '1'))) THEN |
s_spi_count_reg <= unsigned(s_spi_count_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_spi_count_reg; |
|
make_spi_shift_reg : PROCESS( clock , s_spi_shift_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
s_spi_shift_reg <= s_spi_shift_next; |
END IF; |
END PROCESS make_spi_shift_reg; |
|
make_spi_clock_reg : PROCESS( clock , s_spi_count_reg , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_spi_count_reg(9) = '1') THEN s_spi_clk_reg <= '1'; |
ELSE s_spi_clk_reg <= NOT(s_spi_clk_reg); |
END IF; |
END IF; |
END PROCESS make_spi_clock_reg; |
|
make_spi_mosi : PROCESS( clock , s_spi_clk_reg , s_spi_shift_reg , |
reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_spi_clk_reg = '1') THEN s_spi_mosi <= s_spi_shift_reg(31); |
END IF; |
END IF; |
END PROCESS make_spi_mosi; |
|
make_spi_ram_index_reg : PROCESS( clock , reset , s_state_reg , |
write_request , s_load_data_byte ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
s_state_reg = ALL_DONE OR |
s_state_reg = INIT_WRITE) THEN s_spi_ram_index_reg <= (OTHERS => '0'); |
IF (s_state_reg /= INIT_WRITE) THEN |
s_spi_size_reg <= (OTHERS => '0'); |
END IF; |
ELSIF (write_request = '1' OR |
s_load_data_byte = '1') THEN |
s_spi_ram_index_reg <= unsigned(s_spi_ram_index_reg) + 1; |
IF (s_spi_size_reg(5) = '0') THEN |
s_spi_size_reg <= unsigned(s_spi_size_reg) + 1; |
END IF; |
END IF; |
END IF; |
END PROCESS make_spi_ram_index_reg; |
|
make_spi_address_reg : PROCESS( clock , s_state_reg , write_request , |
address , read_request ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF ((write_request = '1' AND |
s_state_reg = IDLE) OR |
read_request = '1') THEN |
s_spi_address_reg <= address; |
END IF; |
END IF; |
END PROCESS make_spi_address_reg; |
|
-- map components |
spiif: SPI_ACCESS |
GENERIC MAP ( SIM_DEVICE => "3S200AN" ) |
PORT MAP ( MISO => s_spi_miso, |
CLK => s_spi_clk_reg, |
CSB => s_n_ena_spi, |
MOSI => s_spi_mosi ); |
write_buffer : FOR n IN 7 DOWNTO 0 GENERATE |
bufbit : RAM32X1S |
PORT MAP ( O => s_buffer_data(n), |
A0 => s_spi_ram_index_reg(0), |
A1 => s_spi_ram_index_reg(1), |
A2 => s_spi_ram_index_reg(2), |
A3 => s_spi_ram_index_reg(3), |
A4 => s_spi_ram_index_reg(4), |
D => data_in(n), |
WCLK => clock, |
WE => write_request); |
END GENERATE write_buffer; |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/vga/vga_leds_buttons_bus-entity.vhdl
0,0 → 1,109
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- IMPORTANT: This core is single byte writable/readable only! |
-- In case of a burst size > 1 a bus_error is generated |
-- |
-- Address map: |
-- 0x20 -> read/write fg color |
-- 0x21 -> read/write bg color |
-- 0x22 -> read/write cursor x position |
-- 0x23 -> read/write cursor y position |
-- 0x24 -> write ascii data at cursor position |
-- 0x25 -> write dummy for clear screen |
-- 0x26 -> read buttons |
-- 0x27 -> read hexswitch |
-- 0x28 -> read/write LED0 mode |
-- 0x29 -> read/write LED1 mode |
-- 0x2A -> read/write LED2 mode |
-- 0x2B -> read/write LED3 mode |
-- 0x2C -> read/write LED4 mode |
-- 0x2D -> read/write LED5 mode |
-- 0x2E -> read/write LED6 mode |
-- 0x2F -> read/write LED7 mode |
|
-- Definition of the led mode reg: |
-- bit 3 -> 1 => fast blinking/toggle (8Hz) |
-- 0 => slow blinking/toggle (1Hz) |
-- bit 2..0 => 000 LED off |
-- 001 LED off |
-- 010 LED Red |
-- 011 LED Green |
-- 100 LED Red blinking |
-- 101 LED Green blinking |
-- 110 LED Red/Green toggling |
-- 111 LED Red/Green toggling |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY vga_bus IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
msec_tick : IN std_logic; |
|
-- Here the bus signals are defined |
n_bus_reset : IN std_logic; |
n_start_transmission : IN std_logic; |
n_end_transmission_in : IN std_logic; |
n_end_transmission_out : OUT std_logic; |
n_data_valid_in : IN std_logic; -- Only for low byte! |
n_data_valid_out : OUT std_logic_vector( 1 DOWNTO 0 ); |
data_in : IN std_logic_vector( 7 DOWNTO 0 ); |
data_out : OUT std_logic_vector(15 DOWNTO 0 ); |
read_n_write : IN std_logic; |
burst_size : IN std_logic_vector( 8 DOWNTO 0 ); |
bus_address : IN std_logic_vector( 5 DOWNTO 0 ); |
n_start_send : OUT std_logic; |
n_bus_error : OUT std_logic; |
|
-- Here the button interface is defined |
n_button_1 : IN std_logic; |
n_button_2 : IN std_logic; |
n_button_3 : IN std_logic; |
hexswitch : IN std_logic_vector( 3 DOWNTO 0 ); |
|
-- Here the LED interface is defined |
leds_a : OUT std_logic_vector( 7 DOWNTO 0 ); |
leds_k : OUT std_logic_vector( 7 DOWNTO 0 ); |
|
-- Here the VGA interface is defined |
cursor_pos : OUT std_logic_vector( 10 DOWNTO 0 ); |
screen_offset : OUT std_logic_vector( 4 DOWNTO 0 ); |
fg_color : OUT std_logic_vector( 2 DOWNTO 0 ); |
bg_color : OUT std_logic_vector( 2 DOWNTO 0 ); |
write_address : OUT std_logic_vector( 10 DOWNTO 0 ); |
ascii_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
we : OUT std_logic); |
END vga_bus; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/vga/vga_controller-behavior-xilinx.vhdl
0,0 → 1,1012
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF vga_controller IS |
|
COMPONENT FDC |
GENERIC ( INIT : bit ); |
PORT ( Q : OUT std_logic; |
C : IN std_logic; |
CLR : IN std_logic; |
D : IN std_logic ); |
END COMPONENT; |
|
COMPONENT DFF |
PORT ( clock : IN std_logic; |
D : IN std_logic; |
Q : OUT std_logic ); |
END COMPONENT; |
|
COMPONENT DFF_BUS |
GENERIC ( nr_of_bits : INTEGER ); |
PORT ( clock : IN std_logic; |
D : IN std_logic_vector( (nr_of_bits-1) DOWNTO 0 ); |
Q : OUT std_logic_vector( (nr_of_bits-1) DOWNTO 0 )); |
END COMPONENT; |
|
COMPONENT RAMB16_S9_S9 |
PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0 ); |
DOPA : OUT std_logic_vector( 0 DOWNTO 0 ); |
ADDRA : IN std_logic_vector(10 DOWNTO 0 ); |
CLKA : IN std_logic; |
DIA : IN std_logic_vector( 7 DOWNTO 0 ); |
DIPA : IN std_logic_vector( 0 DOWNTO 0 ); |
ENA : IN std_logic; |
SSRA : IN std_logic; |
WEA : IN std_logic; |
DOB : OUT std_logic_vector( 7 DOWNTO 0 ); |
DOPB : OUT std_logic_vector( 0 DOWNTO 0 ); |
ADDRB : IN std_logic_vector(10 DOWNTO 0 ); |
CLKB : IN std_logic; |
DIB : IN std_logic_vector( 7 DOWNTO 0 ); |
DIPB : IN std_logic_vector( 0 DOWNTO 0 ); |
ENB : IN std_logic; |
SSRB : IN std_logic; |
WEB : IN std_logic); |
END COMPONENT; |
|
COMPONENT RAMB16_S1 |
PORT ( DO : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); |
ADDR : IN STD_LOGIC_VECTOR (13 DOWNTO 0); |
CLK : IN STD_ULOGIC; |
DI : IN STD_LOGIC_VECTOR (0 DOWNTO 0); |
EN : IN STD_ULOGIC; |
SSR : IN STD_ULOGIC; |
WE : IN STD_ULOGIC ); |
END COMPONENT; |
|
TYPE HCOUNT_TYPE IS ( HORIZONTAL_FRONT_PORCH , HORIZONTAL_SYNC , HORIZONTAL_BACK_PORCH , HORIZONTAL_PIXELS ); |
TYPE VCOUNT_TYPE IS ( VERTICAL_FRONT_PORCH , VERTICAL_SYNC , VERTICAL_BACK_PORCH , VERTICAL_ACTIVE ); |
TYPE USBTMC_STATE_TYPE IS (IDLE,INIT_CLEAR_SCREEN,CLEAR_SCREEN,SIGNAL_DONE, |
GET_BG_COLOR,SET_BG_COLOR,SIGNAL_ERROR, |
GET_FG_COLOR,SET_FG_COLOR,WRITE_CHAR,NEW_LINE, |
INIT_CLEAR_LINE,CLEAR_LINE,CLEAR_NOP, |
INIT_CURSOR_SEND,SEND_CURSOR,INIT_GET_CURSOR, |
GET_X_CHAR,MULT_10_X,GET_Y_CHAR,MULT_10_Y, |
UPDATE_CURSOR); |
|
CONSTANT H_FRONT_PORCH_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0000010111"; |
CONSTANT H_SYNC_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0010000111"; |
CONSTANT H_BACK_PORCH_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0010001111"; |
CONSTANT H_PIXEL_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "1111111111"; |
CONSTANT V_FRONT_PORCH_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0000000010"; |
CONSTANT V_SYNC_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0000000101"; |
CONSTANT V_BACK_PORCH_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "0000011100"; |
CONSTANT V_ACTIVE_COUNT : std_logic_vector( 9 DOWNTO 0 ) := "1011111111"; |
CONSTANT HIGH_RELOAD : std_logic_vector(12 DOWNTO 0 ) := "1"&X"D4B"; --(=7499) |
CONSTANT LOW_RELOAD : std_logic_vector(12 DOWNTO 0 ) := "1"&X"387"; --(=4999) |
CONSTANT c_ten : std_logic_vector( 4 DOWNTO 0 ) := "01010"; |
CONSTANT c_31 : std_logic_vector( 6 DOWNTO 0 ) := "0011111"; |
|
SIGNAL s_horiz_count_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_horiz_load_value : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_horiz_count_is_zero : std_logic; |
SIGNAL s_horiz_state_reg : HCOUNT_TYPE; |
SIGNAL s_next_line : std_logic; |
SIGNAL s_next_line_reg : std_logic; |
SIGNAL s_vert_count_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_vert_load_value : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_vert_count_is_zero : std_logic; |
SIGNAL s_vert_state_reg : VCOUNT_TYPE; |
SIGNAL s_vsync : std_logic; |
SIGNAL s_hsync : std_logic; |
SIGNAL s_n_blank : std_logic; |
SIGNAL s_red : std_logic; |
SIGNAL s_green : std_logic; |
SIGNAL s_blue : std_logic; |
SIGNAL s_new_screen : std_logic; |
SIGNAL s_new_screen_reg : std_logic; |
SIGNAL s_req_line : std_logic; |
SIGNAL s_req_line_reg : std_logic; |
SIGNAL s_line_counter_reg : std_logic_vector( 9 DOWNTO 0 ); |
SIGNAL s_lookup_address : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_is_fpga_cursor_pos : std_logic; |
SIGNAL s_fpga_lookup_address : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_usbtmc_lookup_address : std_logic_vector(10 DOWNTO 0 ); |
|
SIGNAL s_ascii_data_1 : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_ascii_data_2 : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_ascii_data_3 : std_logic_vector( 7 DOWNTO 0 ); |
|
SIGNAL s_stage_1_data_sel_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_stage_1_line_index_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_stage_1_pixel_index_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_stage_1_fg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_stage_1_bg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_stage_1_hsync_reg : std_logic; |
SIGNAL s_stage_1_vsync_reg : std_logic; |
SIGNAL s_stage_1_n_blank_reg : std_logic; |
SIGNAL s_stage_1_cursor_reg : std_logic; |
SIGNAL s_stage_1_draw_line_reg : std_logic; |
|
SIGNAL s_stage_1_ascii_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_rom_index : std_logic_vector(13 DOWNTO 0 ); |
SIGNAL s_rom_value_0 : std_logic_vector( 0 DOWNTO 0 ); |
|
SIGNAL s_stage_2_fg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_stage_2_bg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_stage_2_hsync_reg : std_logic; |
SIGNAL s_stage_2_vsync_reg : std_logic; |
SIGNAL s_stage_2_n_blank_reg : std_logic; |
SIGNAL s_stage_2_cursor_reg : std_logic; |
SIGNAL s_stage_2_pixel_inv_reg : std_logic; |
|
SIGNAL s_stage_2_pixel_set : std_logic; |
|
SIGNAL s_stage_1_counter_reg : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_stage_1_counter_next : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_stage_1_counter_zero : std_logic; |
SIGNAL s_stage_1_counter_tick_reg : std_logic; |
SIGNAL s_stage_1_counter_tick_next : std_logic; |
SIGNAL s_stage_2_counter_reg : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_stage_2_counter_next : std_logic_vector( 12 DOWNTO 0 ); |
SIGNAL s_stage_2_counter_zero : std_logic; |
SIGNAL s_stage_2_counter_tick_reg : std_logic; |
SIGNAL s_stage_2_counter_tick_next : std_logic; |
SIGNAL s_blink_reg : std_logic; |
SIGNAL s_blink_next : std_logic; |
SIGNAL s_draw_hor_line : std_logic; |
|
SIGNAL s_usbtmc_screen_offset_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_usbtmc_cursor_x_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_usbtmc_cursor_y_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_usbtmc_cursor_x_bcd_reg : std_logic_vector( 6 DOWNTO 0 ); |
SIGNAL s_usbtmc_cursor_y_bcd_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_usbtmc_fg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_usbtmc_bg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_is_usbtmc_cursor : std_logic; |
SIGNAL s_usbtmc_write_address : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_usbtmc_write_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_usbtmc_write_enable : std_logic; |
SIGNAL s_usbtmc_state_reg : USBTMC_STATE_TYPE; |
SIGNAL s_clear_counter_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_pop_data : std_logic; |
SIGNAL s_pop_data_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_next_cursor_xpos : std_logic_vector( 6 DOWNTO 0 ); |
SIGNAL s_next_cursor_ypos : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_valid_char : std_logic; |
SIGNAL s_last_char_reg : std_logic; |
SIGNAL s_push_cnt_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_push : std_logic; |
SIGNAL s_new_cursor_x_pos_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_new_cursor_y_pos_reg : std_logic_vector( 4 DOWNTO 0 ); |
|
BEGIN |
|
-- Assign control signals |
s_horiz_count_is_zero <= '1' WHEN s_horiz_count_reg = "0000000000" ELSE '0'; |
s_vert_count_is_zero <= '1' WHEN s_vert_count_reg = "0000000000" ELSE '0'; |
s_next_line <= '1' WHEN s_horiz_count_is_zero = '1' AND |
s_horiz_state_reg = HORIZONTAL_PIXELS ELSE '0'; |
s_n_blank <= '1' WHEN s_horiz_state_reg = HORIZONTAL_PIXELS AND |
s_vert_state_reg = VERTICAL_ACTIVE ELSE '0'; |
s_red <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE |
s_stage_2_fg_color_reg(2) WHEN s_stage_2_pixel_set = '1' ELSE |
s_stage_2_bg_color_reg(2); |
s_green <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE |
s_stage_2_fg_color_reg(1) WHEN s_stage_2_pixel_set = '1' ELSE |
s_stage_2_bg_color_reg(1); |
s_blue <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE |
s_stage_2_fg_color_reg(0) WHEN s_stage_2_pixel_set = '1' ELSE |
s_stage_2_bg_color_reg(0); |
s_new_screen <= '1' WHEN s_horiz_count_is_zero = '1' AND |
s_vert_count_is_zero = '1' AND |
s_horiz_state_reg = HORIZONTAL_PIXELS AND |
s_vert_state_reg = VERTICAL_FRONT_PORCH ELSE '0'; |
s_req_line <= '1' WHEN (s_horiz_count_is_zero = '1' AND |
s_horiz_state_reg = HORIZONTAL_PIXELS AND |
s_vert_state_reg = VERTICAL_ACTIVE) ELSE '0'; |
s_lookup_address <= s_line_counter_reg(7 DOWNTO 4)&NOT(s_horiz_count_reg(9 DOWNTO 3)); |
s_fpga_lookup_address( 5 DOWNTO 0 ) <= NOT(s_horiz_count_reg(8 DOWNTO 3)); |
s_fpga_lookup_address(10 DOWNTO 6 ) <= unsigned(screen_offset)+ |
unsigned(s_line_counter_reg(9)& |
s_line_counter_reg(7 DOWNTO 4)); |
s_usbtmc_lookup_address( 5 DOWNTO 0 ) <= NOT(s_horiz_count_reg(8 DOWNTO 3)); |
s_usbtmc_lookup_address(10 DOWNTO 6 ) <= unsigned(s_usbtmc_screen_offset_reg)+ |
unsigned(s_line_counter_reg(9)& |
s_line_counter_reg(7 DOWNTO 4)); |
s_hsync <= '1' WHEN s_horiz_state_reg = HORIZONTAL_SYNC ELSE '0'; |
s_vsync <= '1' WHEN s_vert_state_reg = VERTICAL_SYNC ELSE '0'; |
s_is_fpga_cursor_pos <= '1' WHEN cursor_pos(10 DOWNTO 6) = s_line_counter_reg(9)&s_line_counter_reg(7 DOWNTO 4) AND |
cursor_pos( 5 DOWNTO 0) = NOT(s_horiz_count_reg( 8 DOWNTO 3)) ELSE '0'; |
s_is_usbtmc_cursor <= '1' WHEN s_usbtmc_cursor_y_reg = s_line_counter_reg(9)&s_line_counter_reg(7 DOWNTO 4) AND |
s_usbtmc_cursor_x_reg = NOT(s_horiz_count_reg( 8 DOWNTO 3)) ELSE '0'; |
s_draw_hor_line <= '1' WHEN s_horiz_count_reg(8 DOWNTO 0) = "0"&X"00" OR |
s_horiz_count_reg(8 DOWNTO 0) = "1"&X"FF" ELSE '0'; |
s_rom_index(13 DOWNTO 7 ) <= s_stage_1_ascii_data( 6 DOWNTO 0 ); |
s_rom_index( 6 DOWNTO 3 ) <= s_stage_1_line_index_reg; |
s_rom_index( 2 DOWNTO 0 ) <= s_stage_1_pixel_index_reg; |
s_stage_2_pixel_set <= (s_rom_value_0(0) XOR s_stage_2_cursor_reg) XOR s_stage_2_pixel_inv_reg; |
s_stage_1_counter_zero <= '1' WHEN s_stage_1_counter_reg = "0"&X"000" ELSE '0'; |
s_stage_2_counter_zero <= s_stage_1_counter_tick_reg WHEN s_stage_2_counter_reg = "0"&X"000" ELSE '0'; |
|
-- Here the update logic is defined |
s_stage_1_counter_next <= HIGH_RELOAD WHEN s_stage_1_counter_zero = '1' OR |
vga_off = '1' ELSE |
unsigned(s_stage_1_counter_reg) - 1; |
s_stage_1_counter_tick_next <= s_stage_1_counter_zero OR vga_off; |
s_stage_2_counter_next <= LOW_RELOAD WHEN s_stage_2_counter_zero = '1' OR |
vga_off = '1' ELSE |
unsigned(s_stage_2_counter_reg) - 1 WHEN s_stage_1_counter_tick_reg = '1' ELSE |
s_stage_2_counter_reg; |
s_stage_2_counter_tick_next <= s_stage_2_counter_zero OR vga_off; |
s_blink_next <= '0' WHEN vga_off = '1' ELSE |
NOT(s_blink_reg) WHEN s_stage_2_counter_tick_reg = '1' ELSE s_blink_reg; |
|
-- Here the flipflops are instantiated |
stage_1_counter_reg : DFF_BUS |
GENERIC MAP ( nr_of_bits => 13 ) |
PORT MAP ( clock => clock_75MHz, |
D => s_stage_1_counter_next, |
Q => s_stage_1_counter_reg ); |
stage_1_counter_tick_reg : DFF |
PORT MAP ( clock => clock_75MHz, |
D => s_stage_1_counter_tick_next, |
Q => s_stage_1_counter_tick_reg ); |
stage_2_counter_reg : DFF_BUS |
GENERIC MAP ( nr_of_bits => 13 ) |
PORT MAP ( clock => clock_75MHz, |
D => s_stage_2_counter_next, |
Q => s_stage_2_counter_reg ); |
stage_2_counter_tick_reg : DFF |
PORT MAP ( clock => clock_75MHz, |
D => s_stage_2_counter_tick_next, |
Q => s_stage_2_counter_tick_reg ); |
blink_reg : DFF |
PORT MAP ( clock => clock_75MHz, |
D => s_blink_next, |
Q => s_blink_reg ); |
|
-- Map processes |
|
make_horiz_count_reg : PROCESS( clock_75MHz , vga_off , |
s_horiz_count_is_zero , s_horiz_load_value ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_horiz_count_reg <= H_FRONT_PORCH_COUNT; |
ELSIF (s_horiz_count_is_zero = '1') THEN |
s_horiz_count_reg <= s_horiz_load_value; |
ELSE |
s_horiz_count_reg <= unsigned( s_horiz_count_reg ) - 1; |
END IF; |
END IF; |
END PROCESS make_horiz_count_reg; |
|
make_horiz_load_value : PROCESS( s_horiz_state_reg ) |
BEGIN |
CASE (s_horiz_state_reg) IS |
WHEN HORIZONTAL_FRONT_PORCH => s_horiz_load_value <= H_SYNC_COUNT; |
WHEN HORIZONTAL_SYNC => s_horiz_load_value <= H_BACK_PORCH_COUNT; |
WHEN HORIZONTAL_BACK_PORCH => s_horiz_load_value <= H_PIXEL_COUNT; |
WHEN OTHERS => s_horiz_load_value <= H_FRONT_PORCH_COUNT; |
END CASE; |
END PROCESS make_horiz_load_value; |
|
make_horiz_state_reg : PROCESS( clock_75MHz , s_horiz_state_reg , |
vga_off , s_horiz_count_is_zero ) |
VARIABLE v_next_state : HCOUNT_TYPE; |
BEGIN |
CASE (s_horiz_state_reg) IS |
WHEN HORIZONTAL_FRONT_PORCH => v_next_state := HORIZONTAL_SYNC; |
WHEN HORIZONTAL_SYNC => v_next_state := HORIZONTAL_BACK_PORCH; |
WHEN HORIZONTAL_BACK_PORCH => v_next_state := HORIZONTAL_PIXELS; |
WHEN OTHERS => v_next_state := HORIZONTAL_FRONT_PORCH; |
END CASE; |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_horiz_state_reg <= HORIZONTAL_FRONT_PORCH; |
ELSIF (s_horiz_count_is_zero = '1') THEN s_horiz_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_horiz_state_reg; |
|
make_vert_count_reg : PROCESS( clock_75MHz , vga_off , s_next_line_reg , |
s_vert_count_is_zero , s_vert_load_value ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_vert_count_reg <= V_FRONT_PORCH_COUNT; |
ELSIF (s_next_line_reg = '1') THEN |
IF (s_vert_count_is_zero = '1') THEN |
s_vert_count_reg <= s_vert_load_value; |
ELSE |
s_vert_count_reg <= unsigned( s_vert_count_reg ) - 1; |
END IF; |
END IF; |
END IF; |
END PROCESS make_vert_count_reg; |
|
make_vert_load_value : PROCESS( s_vert_state_reg ) |
BEGIN |
CASE (s_vert_state_reg) IS |
WHEN VERTICAL_FRONT_PORCH => s_vert_load_value <= V_SYNC_COUNT; |
WHEN VERTICAL_SYNC => s_vert_load_value <= V_BACK_PORCH_COUNT; |
WHEN VERTICAL_BACK_PORCH => s_vert_load_value <= V_ACTIVE_COUNT; |
WHEN OTHERS => s_vert_load_value <= V_FRONT_PORCH_COUNT; |
END CASE; |
END PROCESS make_vert_load_value; |
|
make_vert_state_reg : PROCESS( clock_75MHz , s_vert_state_reg , s_next_line_reg , |
vga_off , s_vert_count_is_zero ) |
VARIABLE v_next_state : VCOUNT_TYPE; |
BEGIN |
CASE ( s_vert_state_reg ) IS |
WHEN VERTICAL_FRONT_PORCH => v_next_state := VERTICAL_SYNC; |
WHEN VERTICAL_SYNC => v_next_state := VERTICAL_BACK_PORCH; |
WHEN VERTICAL_BACK_PORCH => v_next_state := VERTICAL_ACTIVE; |
WHEN OTHERS => v_next_state := VERTICAL_FRONT_PORCH; |
END CASE; |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_vert_state_reg <= VERTICAL_FRONT_PORCH; |
ELSIF (s_next_line_reg = '1' AND |
s_vert_count_is_zero = '1') THEN s_vert_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_vert_state_reg; |
|
make_next_line_reg : PROCESS( clock_75MHz , vga_off , s_next_line ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_next_line_reg <= '0'; |
ELSE s_next_line_reg <= s_next_line; |
END IF; |
END IF; |
END PROCESS make_next_line_reg; |
|
make_new_screen_reg : PROCESS( clock_75MHz , vga_off , s_new_screen , s_req_line ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN s_new_screen_reg <= '0'; |
s_req_line_reg <= '0'; |
ELSE s_new_screen_reg <= s_new_screen; |
s_req_line_reg <= s_req_line; |
END IF; |
END IF; |
END PROCESS make_new_screen_reg; |
|
make_line_counter_reg : PROCESS( clock_75MHz , s_new_screen_reg , s_req_line_reg ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (s_new_screen_reg = '1') THEN s_line_counter_reg <= (OTHERS => '0'); |
ELSIF (s_req_line_reg = '1') THEN s_line_counter_reg <= unsigned(s_line_counter_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_line_counter_reg; |
|
make_stage_1_regs : PROCESS( clock_75MHz , vga_off , s_line_counter_reg , |
fg_color , bg_color , s_hsync , s_vsync , s_n_blank , |
s_is_fpga_cursor_pos , s_draw_hor_line , |
s_vert_count_is_zero , s_is_usbtmc_cursor ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN |
s_stage_1_data_sel_reg <= "00"; |
s_stage_1_line_index_reg <= X"0"; |
s_stage_1_pixel_index_reg <= "000"; |
s_stage_1_fg_color_reg <= "000"; |
s_stage_1_bg_color_reg <= "000"; |
s_stage_1_hsync_reg <= '0'; |
s_stage_1_vsync_reg <= '0'; |
s_stage_1_n_blank_reg <= '0'; |
s_stage_1_cursor_reg <= '0'; |
s_stage_1_draw_line_reg <= '0'; |
ELSE |
CASE (s_line_counter_reg(9 DOWNTO 8)) IS |
WHEN "00" => s_stage_1_data_sel_reg <= "00"; |
IF (s_horiz_count_reg(9) = '0' AND |
(s_line_counter_reg(7 DOWNTO 4) /= X"0" AND |
s_line_counter_reg(7 DOWNTO 4) /= X"E" AND |
s_line_counter_reg(7 DOWNTO 4) /= X"F")) THEN |
s_stage_1_fg_color_reg <= "111"; |
s_stage_1_bg_color_reg <= "000"; |
ELSE |
s_stage_1_fg_color_reg <= "110"; |
s_stage_1_bg_color_reg <= "001"; |
END IF; |
s_stage_1_draw_line_reg<= s_draw_hor_line; |
s_stage_1_cursor_reg <= '0'; |
WHEN OTHERS => s_stage_1_data_sel_reg <= "1"&s_horiz_count_reg(9); |
IF (s_horiz_count_reg(9) = '1') THEN |
s_stage_1_fg_color_reg <= s_usbtmc_fg_color_reg; |
s_stage_1_bg_color_reg <= s_usbtmc_bg_color_reg; |
s_stage_1_cursor_reg <= s_is_usbtmc_cursor; |
ELSE |
s_stage_1_fg_color_reg <= fg_color; |
s_stage_1_bg_color_reg <= bg_color; |
s_stage_1_cursor_reg <= s_is_fpga_cursor_pos; |
END IF; |
s_stage_1_draw_line_reg <= s_draw_hor_line OR |
s_vert_count_is_zero; |
END CASE; |
s_stage_1_line_index_reg <= s_line_counter_reg( 3 DOWNTO 0 ); |
s_stage_1_pixel_index_reg <= s_horiz_count_reg( 2 DOWNTO 0 ); |
s_stage_1_hsync_reg <= s_hsync; |
s_stage_1_vsync_reg <= s_vsync; |
s_stage_1_n_blank_reg <= s_n_blank; |
END IF; |
END IF; |
END PROCESS make_stage_1_regs; |
|
make_stage_1_data : PROCESS( s_stage_1_data_sel_reg , |
s_ascii_data_1 , s_ascii_data_2 , s_ascii_data_3 ) |
BEGIN |
CASE (s_stage_1_data_sel_reg) IS |
WHEN "00" => s_stage_1_ascii_data <= s_ascii_data_1; |
WHEN "11" => s_stage_1_ascii_data <= s_ascii_data_2; |
WHEN OTHERS => s_stage_1_ascii_data <= s_ascii_data_3; |
END CASE; |
END PROCESS make_stage_1_data; |
|
make_stage_2_regs : PROCESS( clock_75MHz , vga_off , s_stage_1_fg_color_reg , s_stage_1_bg_color_reg , |
s_stage_1_hsync_reg , s_stage_1_vsync_reg , s_stage_1_n_blank_reg , |
s_stage_1_cursor_reg , s_stage_1_ascii_data , |
s_blink_reg , s_stage_1_draw_line_reg ) |
BEGIN |
IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN |
IF (vga_off = '1') THEN |
s_stage_2_fg_color_reg <= "000"; |
s_stage_2_bg_color_reg <= "000"; |
s_stage_2_hsync_reg <= '0'; |
s_stage_2_vsync_reg <= '0'; |
s_stage_2_n_blank_reg <= '0'; |
s_stage_2_cursor_reg <= '0'; |
s_stage_2_pixel_inv_reg <= '0'; |
ELSE |
IF (s_stage_1_draw_line_reg = '1') THEN |
s_stage_2_fg_color_reg <= "001"; |
s_stage_2_bg_color_reg <= "001"; |
ELSE |
s_stage_2_fg_color_reg <= s_stage_1_fg_color_reg; |
s_stage_2_bg_color_reg <= s_stage_1_bg_color_reg; |
END IF; |
s_stage_2_hsync_reg <= s_stage_1_hsync_reg; |
s_stage_2_vsync_reg <= s_stage_1_vsync_reg; |
s_stage_2_n_blank_reg <= s_stage_1_n_blank_reg; |
s_stage_2_cursor_reg <= s_stage_1_cursor_reg AND s_blink_reg; |
s_stage_2_pixel_inv_reg <= s_stage_1_ascii_data(7); |
END IF; |
END IF; |
END PROCESS make_stage_2_regs; |
|
-------------------------------------------------------------------------------- |
--- Here the usbtmc handling is defined --- |
-------------------------------------------------------------------------------- |
command_done <= '1' WHEN s_usbtmc_state_reg = SIGNAL_DONE OR |
s_usbtmc_state_reg = SIGNAL_ERROR ELSE '0'; |
command_error <= '1' WHEN s_usbtmc_state_reg = SIGNAL_ERROR ELSE '0'; |
pop <= s_pop_data; |
push <= s_push; |
push_size <= '1' WHEN s_push_cnt_reg = X"6" ELSE '0'; |
|
s_usbtmc_write_address( 10 DOWNTO 6 ) <= unsigned(s_usbtmc_cursor_y_reg)+ |
unsigned(s_usbtmc_screen_offset_reg)+ |
unsigned(s_clear_counter_reg(10 DOWNTO 6)); |
s_usbtmc_write_address( 5 DOWNTO 0 ) <= unsigned(s_usbtmc_cursor_x_reg)+ |
unsigned(s_clear_counter_reg( 5 DOWNTO 0)); |
s_usbtmc_write_data <= X"20" WHEN s_clear_counter_reg(11) = '0' |
ELSE pop_data; |
s_usbtmc_write_enable <= '1' WHEN s_clear_counter_reg(11) = '0' OR |
s_valid_char = '1' ELSE '0'; |
s_pop_data <= '1' WHEN (s_usbtmc_state_reg = GET_BG_COLOR OR |
s_usbtmc_state_reg = GET_FG_COLOR OR |
(s_usbtmc_state_reg = WRITE_CHAR AND |
s_last_char_reg = '0') OR |
s_usbtmc_state_reg = GET_X_CHAR OR |
s_usbtmc_state_reg = GET_Y_CHAR) AND |
pop_empty = '0' ELSE '0'; |
s_next_cursor_xpos <= "1000000" WHEN s_pop_data = '1' AND |
pop_data = X"0A" AND |
s_usbtmc_state_reg = WRITE_CHAR ELSE |
unsigned("0"&s_usbtmc_cursor_x_reg) + 1 |
WHEN s_valid_char = '1' ELSE |
"0"&s_usbtmc_cursor_x_reg; |
s_next_cursor_ypos <= unsigned("0"&s_usbtmc_cursor_y_reg)+1; |
s_push <= '1' WHEN s_usbtmc_state_reg = SEND_CURSOR AND |
push_full = '0' AND |
s_push_cnt_reg(3) = '0' ELSE '0'; |
s_valid_char <= '1' WHEN s_pop_data = '1' AND |
s_usbtmc_state_reg = WRITE_CHAR AND |
(unsigned(pop_data(6 DOWNTO 0)) > |
unsigned(c_31)) ELSE '0'; |
|
make_usbtmc_screen_offset_reg : PROCESS( clock , reset , s_usbtmc_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_usbtmc_screen_offset_reg <= (OTHERS => '0'); |
ELSIF (s_next_cursor_ypos(5) = '1' AND |
s_usbtmc_state_reg = NEW_LINE) THEN |
s_usbtmc_screen_offset_reg <= unsigned(s_usbtmc_screen_offset_reg)+1; |
END IF; |
END IF; |
END PROCESS make_usbtmc_screen_offset_reg; |
|
make_usbtmc_cursor_x_reg : PROCESS( clock , reset , s_usbtmc_state_reg , |
s_new_cursor_x_pos_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_usbtmc_cursor_x_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = UPDATE_CURSOR) THEN |
s_usbtmc_cursor_x_reg <= s_new_cursor_x_pos_reg; |
ELSE |
s_usbtmc_cursor_x_reg <= s_next_cursor_xpos(5 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_usbtmc_cursor_x_reg; |
|
make_usbtmc_cursor_y_reg : PROCESS( clock , reset , s_usbtmc_state_reg , |
s_next_cursor_ypos , |
s_new_cursor_y_pos_reg) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_usbtmc_cursor_y_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = NEW_LINE AND |
s_next_cursor_ypos(5) = '0') THEN |
s_usbtmc_cursor_y_reg <= s_next_cursor_ypos( 4 DOWNTO 0 ); |
ELSIF (s_usbtmc_state_reg = UPDATE_CURSOR) THEN |
s_usbtmc_cursor_y_reg <= s_new_cursor_y_pos_reg; |
END IF; |
END IF; |
END PROCESS make_usbtmc_cursor_y_reg; |
|
make_usbtmc_fg_color_reg : PROCESS( clock , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_usbtmc_fg_color_reg <= "111"; |
ELSIF (s_usbtmc_state_reg = SET_FG_COLOR) THEN |
s_usbtmc_fg_color_reg <= s_pop_data_reg( 2 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_usbtmc_fg_color_reg; |
|
make_usbtmc_bg_color_reg : PROCESS( clock , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_usbtmc_bg_color_reg <= "000"; |
ELSIF (s_usbtmc_state_reg = SET_BG_COLOR) THEN |
s_usbtmc_bg_color_reg <= s_pop_data_reg( 2 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_usbtmc_bg_color_reg; |
|
make_pop_data_reg : PROCESS( clock , reset , s_pop_data , pop_data ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_pop_data_reg <= X"00"; |
ELSIF (s_pop_data = '1') THEN s_pop_data_reg <= pop_data; |
END IF; |
END IF; |
END PROCESS make_pop_data_reg; |
|
make_clear_counter_reg : PROCESS( clock , reset , s_usbtmc_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN) THEN |
s_clear_counter_reg <= "011111111111"; |
ELSIF (s_usbtmc_state_reg = INIT_CLEAR_LINE) THEN |
s_clear_counter_reg <= "000000111111"; |
ELSIF (s_clear_counter_reg(11) = '0' AND |
reset = '0') THEN |
s_clear_counter_reg <= unsigned(s_clear_counter_reg) - 1; |
ELSIF (reset = '1' OR |
s_clear_counter_reg(11) = '1') THEN |
s_clear_counter_reg <= "100000000000"; |
END IF; |
END IF; |
END PROCESS make_clear_counter_reg; |
|
make_last_char_reg : PROCESS( clock , reset , s_usbtmc_state_reg , |
s_pop_data , pop_last ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = IDLE OR |
reset = '1') THEN s_last_char_reg <= '0'; |
ELSIF (s_usbtmc_state_reg = WRITE_CHAR AND |
s_pop_data = '1' AND |
pop_last = '1') THEN s_last_char_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_last_char_reg; |
|
make_usbtmc_cursor_x_bcd_reg : PROCESS( clock , s_usbtmc_cursor_x_reg ) |
VARIABLE v_sub1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_rest_1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_rest_2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub3 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_rest_3 : std_logic_vector( 3 DOWNTO 0 ); |
BEGIN |
v_sub1 := unsigned("0"&s_usbtmc_cursor_x_reg(5 DOWNTO 2)) - |
unsigned(c_ten); |
IF (v_sub1(4) = '0') THEN v_rest_1 := v_sub1(3 DOWNTO 0)& |
s_usbtmc_cursor_x_reg(1); |
ELSE v_rest_1 := s_usbtmc_cursor_x_reg(5 DOWNTO 1); |
END IF; |
v_sub2 := unsigned(v_rest_1) - unsigned(c_ten); |
IF (v_sub2(4) = '0') THEN v_rest_2 := v_sub2(3 DOWNTO 0)& |
s_usbtmc_cursor_x_reg(0); |
ELSE v_rest_2 := v_rest_1(3 DOWNTO 0)& |
s_usbtmc_cursor_x_reg(0); |
END IF; |
v_sub3 := unsigned(v_rest_2) - unsigned(c_ten); |
IF (v_sub3(4) = '0') THEN v_rest_3 := v_sub3( 3 DOWNTO 0 ); |
ELSE v_rest_3 := v_rest_2( 3 DOWNTO 0 ); |
END IF; |
IF (clock'event AND (clock = '1')) THEN |
s_usbtmc_cursor_x_bcd_reg(6) <= NOT(v_sub1(4)); |
s_usbtmc_cursor_x_bcd_reg(5) <= NOT(v_sub2(4)); |
s_usbtmc_cursor_x_bcd_reg(4) <= NOT(v_sub3(4)); |
s_usbtmc_cursor_x_bcd_reg(3 DOWNTO 0) <= v_rest_3; |
END IF; |
END PROCESS make_usbtmc_cursor_x_bcd_reg; |
|
make_usbtmc_cursor_y_bcd_reg : PROCESS( clock , s_usbtmc_cursor_y_reg ) |
VARIABLE v_sub1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_rest_1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_rest_2 : std_logic_vector( 3 DOWNTO 0 ); |
BEGIN |
v_sub1 := unsigned("0"&s_usbtmc_cursor_y_reg(4 DOWNTO 1)) - |
unsigned(c_ten); |
IF (v_sub1(4) = '0') THEN v_rest_1 := v_sub1(3 DOWNTO 0)& |
s_usbtmc_cursor_y_reg(0); |
ELSE v_rest_1 := s_usbtmc_cursor_y_reg(4 DOWNTO 0); |
END IF; |
v_sub2 := unsigned(v_rest_1) - unsigned(c_ten); |
IF (v_sub2(4) = '0') THEN v_rest_2 := v_sub2(3 DOWNTO 0); |
ELSE v_rest_2 := v_rest_1(3 DOWNTO 0); |
END IF; |
IF (clock'event AND (clock = '1')) THEN |
s_usbtmc_cursor_y_bcd_reg(5) <= NOT(v_sub1(4)); |
s_usbtmc_cursor_y_bcd_reg(4) <= NOT(v_sub2(4)); |
s_usbtmc_cursor_y_bcd_reg(3 DOWNTO 0) <= v_rest_2; |
END IF; |
END PROCESS make_usbtmc_cursor_y_bcd_reg; |
|
make_push_data : PROCESS( s_push_cnt_reg , s_usbtmc_cursor_x_bcd_reg , |
s_usbtmc_cursor_y_bcd_reg) |
BEGIN |
CASE (s_push_cnt_reg) IS |
WHEN X"6" => IF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000" AND |
s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN |
push_data <= X"04"; |
ELSIF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000" OR |
s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN |
push_data <= X"05"; |
ELSE |
push_data <= X"06"; |
END IF; |
WHEN X"5" => push_data <= X"3"&"0"&s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4); |
WHEN X"4" => push_data <= X"3"&s_usbtmc_cursor_x_bcd_reg(3 DOWNTO 0); |
WHEN X"3" => push_data <= X"2C"; |
WHEN X"2" => push_data <= X"3"&"00"&s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4); |
WHEN X"1" => push_data <= X"3"&s_usbtmc_cursor_y_bcd_reg(3 DOWNTO 0); |
WHEN X"0" => push_data <= X"0A"; |
WHEN OTHERS => push_data <= X"00"; |
END CASE; |
END PROCESS make_push_data; |
|
make_push_cnt_reg : PROCESS( clock , reset , s_usbtmc_cursor_x_bcd_reg , |
s_usbtmc_cursor_y_bcd_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_push_cnt_reg <= (OTHERS => '1'); |
ELSIF (s_usbtmc_state_reg = INIT_CURSOR_SEND) THEN |
s_push_cnt_reg <= X"6"; |
ELSIF (s_push = '1') THEN |
CASE (s_push_cnt_reg) IS |
WHEN X"6" => IF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000") THEN |
s_push_cnt_reg <= X"4"; |
ELSE |
s_push_cnt_reg <= X"5"; |
END IF; |
WHEN X"3" => IF (s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN |
s_push_cnt_reg <= X"1"; |
ELSE |
s_push_cnt_reg <= X"2"; |
END IF; |
WHEN OTHERS => s_push_cnt_reg <= unsigned(s_push_cnt_reg) - 1; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_push_cnt_reg; |
|
make_new_cursor_x_pos_reg : PROCESS( clock , reset , s_usbtmc_state_reg , |
s_pop_data_reg ) |
VARIABLE v_add_1 : std_logic_vector( 5 DOWNTO 0 ); |
VARIABLE v_add_2 : std_logic_vector( 5 DOWNTO 0 ); |
VARIABLE v_add_3 : std_logic_vector( 5 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_GET_CURSOR OR |
reset = '1') THEN |
s_new_cursor_x_pos_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = MULT_10_X) THEN |
v_add_1 := s_new_cursor_x_pos_reg(2 DOWNTO 0)&"000"; |
v_add_2 := s_new_cursor_x_pos_reg(4 DOWNTO 0)&"0"; |
v_add_3 := "00"&s_pop_data_reg(3 DOWNTO 0); |
s_new_cursor_x_pos_reg <= unsigned(v_add_1) + |
unsigned(v_add_2) + |
unsigned(v_add_3); |
END IF; |
END IF; |
END PROCESS make_new_cursor_x_pos_reg; |
|
make_new_cursor_y_pos_reg : PROCESS( clock , reset , s_usbtmc_state_reg , |
s_pop_data_reg ) |
VARIABLE v_add_1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_add_2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_add_3 : std_logic_vector( 4 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_usbtmc_state_reg = INIT_GET_CURSOR OR |
reset = '1') THEN |
s_new_cursor_y_pos_reg <= (OTHERS => '0'); |
ELSIF (s_usbtmc_state_reg = MULT_10_Y) THEN |
v_add_1 := s_new_cursor_y_pos_reg( 1 DOWNTO 0 )&"000"; |
v_add_2 := s_new_cursor_y_pos_reg( 3 DOWNTO 0 )&"0"; |
v_add_3 := "0"&s_pop_data_reg( 3 DOWNTO 0 ); |
s_new_cursor_y_pos_reg <= unsigned(v_add_1) + |
unsigned(v_add_2) + |
unsigned(v_add_3); |
END IF; |
END IF; |
END PROCESS make_new_cursor_y_pos_reg; |
|
make_state_reg : PROCESS( clock , reset , s_usbtmc_state_reg , start_command , |
command_id , s_clear_counter_reg ) |
VARIABLE v_next_state : USBTMC_STATE_TYPE; |
BEGIN |
CASE (s_usbtmc_state_reg) IS |
WHEN IDLE => IF (start_command = '1') THEN |
CASE (command_id) IS |
WHEN "0111011" => v_next_state := GET_BG_COLOR; |
WHEN "0111100" => v_next_state := INIT_CLEAR_SCREEN; |
WHEN "0111101" => v_next_state := INIT_GET_CURSOR; |
WHEN "0111110" => v_next_state := INIT_CURSOR_SEND; |
WHEN "0111111" => v_next_state := GET_FG_COLOR; |
WHEN "1000000" => v_next_state := WRITE_CHAR; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_CLEAR_SCREEN => v_next_state := CLEAR_SCREEN; |
WHEN CLEAR_SCREEN => IF (s_clear_counter_reg(11) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := CLEAR_SCREEN; |
END IF; |
WHEN GET_BG_COLOR => IF (s_pop_data = '1') THEN |
IF (pop_data(7 DOWNTO 4) = X"3") THEN |
v_next_state := SET_BG_COLOR; |
ELSIF (pop_data = X"20" AND |
pop_last = '0') THEN |
v_next_state := GET_BG_COLOR; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_BG_COLOR; |
END IF; |
WHEN SET_BG_COLOR => v_next_state := SIGNAL_DONE; |
WHEN GET_FG_COLOR => IF (s_pop_data = '1') THEN |
IF (pop_data(7 DOWNTO 4) = X"3") THEN |
v_next_state := SET_FG_COLOR; |
ELSIF (pop_data = X"20" AND |
pop_last = '0') THEN |
v_next_state := GET_FG_COLOR; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_FG_COLOR; |
END IF; |
WHEN SET_FG_COLOR => v_next_state := SIGNAL_DONE; |
WHEN WRITE_CHAR => IF (s_last_char_reg = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSIF (s_next_cursor_xpos(6) = '1') THEN |
v_next_state := NEW_LINE; |
ELSE |
v_next_state := WRITE_CHAR; |
END IF; |
WHEN NEW_LINE => IF (s_next_cursor_ypos(5) = '1') THEN |
v_next_state := INIT_CLEAR_LINE; |
ELSE |
v_next_state := WRITE_CHAR; |
END IF; |
WHEN INIT_CLEAR_LINE => v_next_state := CLEAR_LINE; |
WHEN CLEAR_LINE => IF (s_clear_counter_reg(11) = '1') THEN |
v_next_state := CLEAR_NOP; |
ELSE |
v_next_state := CLEAR_LINE; |
END IF; |
WHEN CLEAR_NOP => v_next_state := WRITE_CHAR; |
WHEN INIT_CURSOR_SEND => v_next_state := SEND_CURSOR; |
WHEN SEND_CURSOR => IF (s_push_cnt_reg(3) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := SEND_CURSOR; |
END IF; |
WHEN INIT_GET_CURSOR => v_next_state := GET_X_CHAR; |
WHEN GET_X_CHAR => IF (s_pop_data = '1') THEN |
IF (pop_data = X"20" AND |
pop_last = '0') THEN |
v_next_state := GET_X_CHAR; |
ELSIF (pop_data = X"2C" AND |
pop_last = '0') THEN |
v_next_state := GET_Y_CHAR; |
ELSIF (pop_data(7 DOWNTO 4) = X"3" AND |
pop_last = '0') THEN |
v_next_state := MULT_10_X; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_X_CHAR; |
END IF; |
WHEN MULT_10_X => v_next_state := GET_X_CHAR; |
WHEN GET_Y_CHAR => IF (s_pop_data = '1') THEN |
IF (pop_data = X"20" AND |
pop_last = '0') THEN |
v_next_state := GET_Y_CHAR; |
ELSIF (pop_data = X"0A" AND |
pop_last = '1') THEN |
v_next_state := UPDATE_CURSOR; |
ELSIF (pop_data(7 DOWNTO 4) = X"3" AND |
pop_last = '0') THEN |
v_next_state := MULT_10_Y; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_Y_CHAR; |
END IF; |
WHEN MULT_10_Y => v_next_state := GET_Y_CHAR; |
WHEN UPDATE_CURSOR => v_next_state := SIGNAL_DONE; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_usbtmc_state_reg <= IDLE; |
ELSE s_usbtmc_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_reg; |
|
-- map components |
hsync_ff : FDC |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => vga_hsync, |
C => clock_75MHz, |
CLR => vga_off, |
D => s_stage_2_hsync_reg ); |
|
vsync_ff : FDC |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => vga_vsync, |
C => clock_75MHz, |
CLR => vga_off, |
D => s_stage_2_vsync_reg ); |
red_ff : FDC |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => vga_red, |
C => clock_75MHz, |
CLR => vga_off, |
D => s_red ); |
|
green_ff : FDC |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => vga_green, |
C => clock_75MHz, |
CLR => vga_off, |
D => s_green ); |
|
blue_ff : FDC |
GENERIC MAP ( INIT => '0' ) |
PORT MAP ( Q => vga_blue, |
C => clock_75MHz, |
CLR => vga_off, |
D => s_blue ); |
|
usbtmc_buf : RAMB16_S9_S9 |
PORT MAP ( DOA => s_ascii_data_2, |
DOPA => OPEN, |
ADDRA => s_usbtmc_lookup_address, |
CLKA => clock_75MHz, |
DIA => X"00", |
DIPA => "0", |
ENA => s_n_blank, |
SSRA => '0', |
WEA => '0', |
DOB => OPEN, |
DOPB => OPEN, |
ADDRB => s_usbtmc_write_address, |
CLKB => clock, |
DIB => s_usbtmc_write_data, |
DIPB => "1", |
ENB => s_usbtmc_write_enable, |
SSRB => '0', |
WEB => s_usbtmc_write_enable); |
|
fpga_buf : RAMB16_S9_S9 |
PORT MAP ( DOA => s_ascii_data_3, |
DOPA => OPEN, |
ADDRA => s_fpga_lookup_address, |
CLKA => clock_75MHz, |
DIA => X"00", |
DIPA => "0", |
ENA => s_n_blank, |
SSRA => '0', |
WEA => '0', |
DOB => OPEN, |
DOPB => OPEN, |
ADDRB => write_address, |
CLKB => clock, |
DIB => ascii_data, |
DIPB => "1", |
ENB => we, |
SSRB => '0', |
WEB => we); |
|
ascii_buf0 : RAMB16_S9_S9 |
PORT MAP ( DOA => s_ascii_data_1, |
DOPA => OPEN, |
ADDRA => s_lookup_address, |
CLKA => clock_75MHz, |
DIA => X"00", |
DIPA => "0", |
ENA => s_n_blank, |
SSRA => '0', |
WEA => '0', |
DOB => OPEN, |
DOPB => OPEN, |
ADDRB => we_addr, |
CLKB => clock, |
DIB => we_ascii, |
DIPB => "1", |
ENB => we_char, |
SSRB => '0', |
WEB => we_char); |
rom_lo : RAMB16_S1 |
PORT MAP ( DO => s_rom_value_0, |
ADDR => s_rom_index(13 DOWNTO 0), |
CLK => clock_75MHz, |
DI => s_rom_value_0, |
EN => '1', |
SSR => '0', |
WE => '0'); |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/vga/vga_leds_buttons_bus-behavior.vhdl
0,0 → 1,698
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_target_specific OF vga_bus IS |
TYPE VGA_STATE_TYPE IS (IDLE , INIT_CLEAR_SCREEN , CLEAR_SCREEN , |
INIT_CLEAR_LINE ); |
|
SIGNAL s_led_0_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_1_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_2_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_3_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_4_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_5_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_6_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_7_mode_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_led_delay_cnt_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_led_blink_cnt_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_my_write_burst_active_reg : std_logic; |
SIGNAL s_n_bus_error_reg : std_logic; |
SIGNAL s_n_bus_error_next : std_logic; |
SIGNAL s_n_data_valid_reg : std_logic; |
SIGNAL s_fg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_bg_color_reg : std_logic_vector( 2 DOWNTO 0 ); |
SIGNAL s_cursor_x_pos_reg : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_cursor_y_pos_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_screen_offset_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_clear_screen_cnt_reg : std_logic_vector(11 DOWNTO 0 ); |
SIGNAL s_vga_state_reg : VGA_STATE_TYPE; |
SIGNAL s_we_ascii : std_logic; |
SIGNAL s_next_x_pos : std_logic_vector( 6 DOWNTO 0 ); |
SIGNAL s_next_y_pos : std_logic_vector( 5 DOWNTO 0 ); |
SIGNAL s_write_pending_reg : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
n_start_send <= '0' WHEN (n_start_transmission = '0' AND |
bus_address(5 DOWNTO 4) = "10" AND |
read_n_write = '0' AND |
s_n_bus_error_next = '1' AND |
s_vga_state_reg = IDLE) OR |
(s_write_pending_reg = '1' AND |
s_vga_state_reg = IDLE) ELSE '1'; |
n_bus_error <= s_n_bus_error_reg; |
n_end_transmission_out <= '0' WHEN s_n_bus_error_reg = '0' OR |
s_n_data_valid_reg = '0' ELSE '1'; |
n_data_valid_out <= "1"&s_n_data_valid_reg; |
fg_color <= s_fg_color_reg; |
bg_color <= s_bg_color_reg; |
cursor_pos <= s_cursor_y_pos_reg&s_cursor_x_pos_reg; |
write_address(5 DOWNTO 0) <= unsigned(s_cursor_x_pos_reg)+ |
unsigned(s_clear_screen_cnt_reg( 5 DOWNTO 0 )); |
write_address(10 DOWNTO 6) <= unsigned(s_screen_offset_reg) + |
unsigned(s_cursor_y_pos_reg) + |
unsigned(s_clear_screen_cnt_reg(10 DOWNTO 6)); |
screen_offset <= s_screen_offset_reg; |
ascii_data <= data_in WHEN s_clear_screen_cnt_reg(11) = '1' ELSE X"20"; |
we <= '1' WHEN s_clear_screen_cnt_reg(11) = '0' OR |
(s_we_ascii = '1' AND |
data_in /= X"0A") ELSE '0'; |
|
-------------------------------------------------------------------------------- |
--- Here the data out is defined --- |
-------------------------------------------------------------------------------- |
make_data_out : PROCESS( bus_address , n_button_1 , n_button_2 , n_button_3 , |
hexswitch , clock , s_fg_color_reg , s_bg_color_reg, |
s_led_0_mode_reg , s_led_1_mode_reg , s_led_2_mode_reg , |
s_led_3_mode_reg , s_led_4_mode_reg , s_led_5_mode_reg , |
s_led_6_mode_reg , s_led_7_mode_reg , |
s_cursor_x_pos_reg , s_cursor_y_pos_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (bus_address(5 DOWNTO 4) = "10") THEN |
CASE (bus_address(3 DOWNTO 0)) IS |
WHEN X"0" => data_out <= X"000"&"0"&s_fg_color_reg; |
WHEN X"1" => data_out <= X"000"&"0"&s_bg_color_reg; |
WHEN X"2" => data_out <= X"00"&"00"&s_cursor_x_pos_reg; |
WHEN X"3" => data_out <= X"00"&"000"&s_cursor_y_pos_reg; |
WHEN X"6" => data_out(15 DOWNTO 3) <= (OTHERS => '0'); |
data_out(2) <= NOT(n_button_3); |
data_out(1) <= NOT(n_button_2); |
data_out(0) <= NOT(n_button_1); |
WHEN X"7" => data_out <= X"000"&hexswitch; |
WHEN X"8" => data_out <= X"000"&s_led_0_mode_reg; |
WHEN X"9" => data_out <= X"000"&s_led_1_mode_reg; |
WHEN X"A" => data_out <= X"000"&s_led_2_mode_reg; |
WHEN X"B" => data_out <= X"000"&s_led_3_mode_reg; |
WHEN X"C" => data_out <= X"000"&s_led_4_mode_reg; |
WHEN X"D" => data_out <= X"000"&s_led_5_mode_reg; |
WHEN X"E" => data_out <= X"000"&s_led_6_mode_reg; |
WHEN X"F" => data_out <= X"000"&s_led_7_mode_reg; |
WHEN OTHERS => data_out <= X"FFFF"; |
END CASE; |
ELSE |
data_out <= X"0000"; |
END IF; |
END IF; |
END PROCESS make_data_out; |
|
-------------------------------------------------------------------------------- |
--- Here the bus control signals are defined --- |
-------------------------------------------------------------------------------- |
s_n_bus_error_next <= '0' WHEN bus_address(5 DOWNTO 4) = "10" AND |
n_start_transmission = '0' AND |
(burst_size /= "000000000" OR |
(read_n_write = '1' AND -- Write only regs |
(bus_address(3 DOWNTO 0) = X"4" OR |
bus_address(3 DOWNTO 0) = X"5")) OR |
(read_n_write = '0' AND -- Read only regs |
(bus_address(3 DOWNTO 0) = X"6" OR |
bus_address(3 DOWNTO 0) = X"7"))) ELSE '1'; |
|
make_my_write_burst_active_reg : PROCESS( clock , reset , bus_address , |
n_start_transmission , |
n_end_transmission_in , |
n_bus_reset , s_n_bus_error_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (n_end_transmission_in = '0' OR |
reset = '1' OR |
n_bus_reset = '0') THEN s_my_write_burst_active_reg <= '0'; |
ELSIF (n_start_transmission = '0' AND |
bus_address(5 DOWNTO 4) = "10" AND |
read_n_write = '0' AND |
s_n_bus_error_next = '1') THEN |
s_my_write_burst_active_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_my_write_burst_active_reg; |
|
|
make_n_bus_error_reg : PROCESS( clock , s_n_bus_error_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
s_n_bus_error_reg <= s_n_bus_error_next; |
END IF; |
END PROCESS make_n_bus_error_reg; |
|
make_n_data_valid_reg : PROCESS( clock , bus_address , n_start_transmission , |
burst_size , read_n_write , |
s_n_bus_error_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (bus_address(5 DOWNTO 4) = "10" AND |
n_start_transmission = '0' AND |
burst_size = "000000000") THEN |
s_n_data_valid_reg <= NOT(read_n_write) OR NOT(s_n_bus_error_next); |
ELSE s_n_data_valid_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_n_data_valid_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the vga controller is defined --- |
-------------------------------------------------------------------------------- |
s_we_ascii <= '1' WHEN n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address( 3 DOWNTO 0 ) = X"4" ELSE '0'; |
s_next_x_pos <= "0"&s_cursor_x_pos_reg WHEN s_we_ascii = '0' ELSE |
"1000000" WHEN data_in = X"0A" ELSE |
unsigned("0"&s_cursor_x_pos_reg) + 1; |
s_next_y_pos <= unsigned("0"&s_cursor_y_pos_reg) + 1; |
|
make_write_pending_reg : PROCESS( clock , reset , n_end_transmission_in , |
s_vga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_vga_state_reg = IDLE OR |
n_end_transmission_in = '0' OR |
reset = '1') THEN s_write_pending_reg <= '0'; |
ELSIF (n_start_transmission = '0' AND |
bus_address(5 DOWNTO 4) = "10" AND |
read_n_write = '0' AND |
s_n_bus_error_next = '1' AND |
s_vga_state_reg /= IDLE) THEN |
s_write_pending_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_write_pending_reg; |
|
make_fg_color_reg : PROCESS( clock , reset , n_bus_reset , data_in , |
n_data_valid_in , s_my_write_burst_active_reg , |
bus_address ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (n_bus_reset = '0' OR |
reset = '1') THEN s_fg_color_reg <= "100"; |
ELSIF (n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address( 3 DOWNTO 0 ) = X"0") THEN |
s_fg_color_reg <= data_in( 2 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_fg_color_reg; |
|
make_bg_color_reg : PROCESS( clock , reset , n_bus_reset , data_in , |
n_data_valid_in , s_my_write_burst_active_reg , |
bus_address ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (n_bus_reset = '0' OR |
reset = '1') THEN s_bg_color_reg <= "000"; |
ELSIF (n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address( 3 DOWNTO 0 ) = X"1") THEN |
s_bg_color_reg <= data_in( 2 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_bg_color_reg; |
|
make_cursor_x_pos_reg : PROCESS( clock , reset , data_in , s_next_x_pos , |
n_data_valid_in , s_my_write_burst_active_reg , |
bus_address , s_vga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_cursor_x_pos_reg <= (OTHERS => '0'); |
ELSIF (n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address( 3 DOWNTO 0 ) = X"2") THEN |
s_cursor_x_pos_reg <= data_in( 5 DOWNTO 0 ); |
ELSE |
s_cursor_x_pos_reg <= s_next_x_pos( 5 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_cursor_x_pos_reg; |
|
make_cursor_y_pos_reg : PROCESS( clock , reset , data_in , s_vga_state_reg , |
n_data_valid_in , s_my_write_burst_active_reg , |
bus_address ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_cursor_y_pos_reg <= (OTHERS => '0'); |
ELSIF (n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address( 3 DOWNTO 0 ) = X"3") THEN |
s_cursor_y_pos_reg <= data_in( 4 DOWNTO 0 ); |
ELSIF (s_next_x_pos(6) = '1' AND |
s_next_y_pos(5) = '0') THEN |
s_cursor_y_pos_reg <= s_next_y_pos( 4 DOWNTO 0 ); |
END IF; |
END IF; |
END PROCESS make_cursor_y_pos_reg; |
|
make_screen_offset_reg : PROCESS( clock , reset , s_vga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR |
reset = '1') THEN s_screen_offset_reg <= (OTHERS => '0'); |
ELSIF (s_next_x_pos(6) = '1' AND |
s_next_y_pos(5) = '1') THEN |
s_screen_offset_reg <= unsigned(s_screen_offset_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_screen_offset_reg; |
|
make_clear_screen_cnt_reg : PROCESS( clock , reset , s_vga_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_vga_state_reg = INIT_CLEAR_SCREEN) THEN |
s_clear_screen_cnt_reg <= (11 => '0' , OTHERS => '1'); |
ELSIF (s_vga_state_reg = INIT_CLEAR_LINE) THEN |
s_clear_screen_cnt_reg <= "000000111111"; |
ELSIF (s_clear_screen_cnt_reg(11) = '1' OR |
reset = '1') THEN |
s_clear_screen_cnt_reg <= "100000000000"; |
ELSIF (s_clear_screen_cnt_reg(11) = '0') THEN |
s_clear_screen_cnt_reg <= unsigned(s_clear_screen_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_clear_screen_cnt_reg; |
|
make_vga_state_machine : PROCESS( clock , reset , s_vga_state_reg ) |
VARIABLE v_next_state : VGA_STATE_TYPE; |
BEGIN |
CASE (s_vga_state_reg) IS |
WHEN IDLE => IF (n_data_valid_in = '0' AND |
s_my_write_burst_active_reg = '1' AND |
bus_address(3 DOWNTO 0) = X"5") THEN |
v_next_state := INIT_CLEAR_SCREEN; |
ELSIF (s_next_x_pos(6) = '1' AND |
s_next_y_pos(5) = '1') THEN |
v_next_state := INIT_CLEAR_LINE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN INIT_CLEAR_SCREEN => v_next_state := CLEAR_SCREEN; |
WHEN CLEAR_SCREEN => IF (s_clear_screen_cnt_reg(11) = '1') THEN |
v_next_state := IDLE; |
ELSE |
v_next_state := CLEAR_SCREEN; |
END IF; |
WHEN INIT_CLEAR_LINE => v_next_state := CLEAR_SCREEN; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_vga_state_reg <= IDLE; |
ELSE s_vga_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_vga_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the led control is defined --- |
-------------------------------------------------------------------------------- |
make_led_0_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_0_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"8" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_0_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_0_mode_reg; |
|
make_led_1_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_1_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"9" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_1_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_1_mode_reg; |
|
make_led_2_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_2_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"A" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_2_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_2_mode_reg; |
|
make_led_3_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_3_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"B" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_3_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_3_mode_reg; |
|
make_led_4_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_4_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"C" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_4_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_4_mode_reg; |
|
make_led_5_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_5_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"D" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_5_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_5_mode_reg; |
|
make_led_6_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_6_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"E" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_6_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_6_mode_reg; |
|
make_led_7_mode_reg : PROCESS( clock , reset , bus_address , data_in , |
n_data_valid_in , s_my_write_burst_active_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1' OR |
n_bus_reset = '0') THEN s_led_7_mode_reg <= X"0"; |
ELSIF (n_data_valid_in = '0' AND |
bus_address( 3 DOWNTO 0) = X"F" AND |
s_my_write_burst_active_reg = '1') THEN |
s_led_7_mode_reg <= data_in(3 DOWNTO 0); |
END IF; |
END IF; |
END PROCESS make_led_7_mode_reg; |
|
make_led_delay_cnt_reg : PROCESS( clock , reset , msec_tick ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF ((msec_tick = '1' AND |
s_led_delay_cnt_reg = X"00") OR |
reset = '1') THEN s_led_delay_cnt_reg <= X"7C"; |
ELSIF (msec_tick = '1') THEN |
s_led_delay_cnt_reg <= unsigned(s_led_delay_cnt_reg) - 1; |
END IF; |
END IF; |
END PROCESS make_led_delay_cnt_reg; |
|
make_led_blink_cnt_reg : PROCESS( clock , reset , msec_tick , |
s_led_delay_cnt_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_led_blink_cnt_reg <= "000"; |
ELSIF (msec_tick = '1' AND |
s_led_delay_cnt_reg = X"00") THEN |
s_led_blink_cnt_reg <= unsigned(s_led_blink_cnt_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_led_blink_cnt_reg; |
|
make_led_0 : PROCESS( s_led_0_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_0_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(0) <= '0'; |
leds_k(0) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(0) <= '1'; |
leds_k(0) <= '0'; |
WHEN X"4" => leds_a(0) <= '0'; |
leds_k(0) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(0) <= s_led_blink_cnt_reg(2); |
leds_k(0) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(0) <= s_led_blink_cnt_reg(2); |
leds_k(0) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(0) <= '0'; |
leds_k(0) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(0) <= s_led_blink_cnt_reg(0); |
leds_k(0) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(0) <= s_led_blink_cnt_reg(0); |
leds_k(0) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(0) <= '0'; |
leds_k(0) <= '0'; |
END CASE; |
END PROCESS make_led_0; |
|
make_led_1 : PROCESS( s_led_1_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_1_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(1) <= '0'; |
leds_k(1) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(1) <= '1'; |
leds_k(1) <= '0'; |
WHEN X"4" => leds_a(1) <= '0'; |
leds_k(1) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(1) <= s_led_blink_cnt_reg(2); |
leds_k(1) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(1) <= s_led_blink_cnt_reg(2); |
leds_k(1) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(1) <= '0'; |
leds_k(1) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(1) <= s_led_blink_cnt_reg(0); |
leds_k(1) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(1) <= s_led_blink_cnt_reg(0); |
leds_k(1) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(1) <= '0'; |
leds_k(1) <= '0'; |
END CASE; |
END PROCESS make_led_1; |
|
make_led_2 : PROCESS( s_led_2_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_2_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(2) <= '0'; |
leds_k(2) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(2) <= '1'; |
leds_k(2) <= '0'; |
WHEN X"4" => leds_a(2) <= '0'; |
leds_k(2) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(2) <= s_led_blink_cnt_reg(2); |
leds_k(2) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(2) <= s_led_blink_cnt_reg(2); |
leds_k(2) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(2) <= '0'; |
leds_k(2) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(2) <= s_led_blink_cnt_reg(0); |
leds_k(2) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(2) <= s_led_blink_cnt_reg(0); |
leds_k(2) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(2) <= '0'; |
leds_k(2) <= '0'; |
END CASE; |
END PROCESS make_led_2; |
|
make_led_3 : PROCESS( s_led_3_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_3_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(3) <= '0'; |
leds_k(3) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(3) <= '1'; |
leds_k(3) <= '0'; |
WHEN X"4" => leds_a(3) <= '0'; |
leds_k(3) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(3) <= s_led_blink_cnt_reg(2); |
leds_k(3) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(3) <= s_led_blink_cnt_reg(2); |
leds_k(3) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(3) <= '0'; |
leds_k(3) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(3) <= s_led_blink_cnt_reg(0); |
leds_k(3) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(3) <= s_led_blink_cnt_reg(0); |
leds_k(3) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(3) <= '0'; |
leds_k(3) <= '0'; |
END CASE; |
END PROCESS make_led_3; |
|
make_led_4 : PROCESS( s_led_4_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_4_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(4) <= '0'; |
leds_k(4) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(4) <= '1'; |
leds_k(4) <= '0'; |
WHEN X"4" => leds_a(4) <= '0'; |
leds_k(4) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(4) <= s_led_blink_cnt_reg(2); |
leds_k(4) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(4) <= s_led_blink_cnt_reg(2); |
leds_k(4) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(4) <= '0'; |
leds_k(4) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(4) <= s_led_blink_cnt_reg(0); |
leds_k(4) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(4) <= s_led_blink_cnt_reg(0); |
leds_k(4) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(4) <= '0'; |
leds_k(4) <= '0'; |
END CASE; |
END PROCESS make_led_4; |
|
make_led_5 : PROCESS( s_led_5_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_5_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(5) <= '0'; |
leds_k(5) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(5) <= '1'; |
leds_k(5) <= '0'; |
WHEN X"4" => leds_a(5) <= '0'; |
leds_k(5) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(5) <= s_led_blink_cnt_reg(2); |
leds_k(5) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(5) <= s_led_blink_cnt_reg(2); |
leds_k(5) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(5) <= '0'; |
leds_k(5) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(5) <= s_led_blink_cnt_reg(0); |
leds_k(5) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(5) <= s_led_blink_cnt_reg(0); |
leds_k(5) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(5) <= '0'; |
leds_k(5) <= '0'; |
END CASE; |
END PROCESS make_led_5; |
|
make_led_6 : PROCESS( s_led_6_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_6_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(6) <= '0'; |
leds_k(6) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(6) <= '1'; |
leds_k(6) <= '0'; |
WHEN X"4" => leds_a(6) <= '0'; |
leds_k(6) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(6) <= s_led_blink_cnt_reg(2); |
leds_k(6) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(6) <= s_led_blink_cnt_reg(2); |
leds_k(6) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(6) <= '0'; |
leds_k(6) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(6) <= s_led_blink_cnt_reg(0); |
leds_k(6) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(6) <= s_led_blink_cnt_reg(0); |
leds_k(6) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(6) <= '0'; |
leds_k(6) <= '0'; |
END CASE; |
END PROCESS make_led_6; |
|
make_led_7 : PROCESS( s_led_7_mode_reg , s_led_blink_cnt_reg ) |
BEGIN |
CASE (s_led_7_mode_reg) IS |
WHEN X"2" | |
X"A" => leds_a(7) <= '0'; |
leds_k(7) <= '1'; |
WHEN X"3" | |
X"B" => leds_a(7) <= '1'; |
leds_k(7) <= '0'; |
WHEN X"4" => leds_a(7) <= '0'; |
leds_k(7) <= s_led_blink_cnt_reg(2); |
WHEN X"5" => leds_a(7) <= s_led_blink_cnt_reg(2); |
leds_k(7) <= '0'; |
WHEN X"6" | |
X"7" => leds_a(7) <= s_led_blink_cnt_reg(2); |
leds_k(7) <= NOT(s_led_blink_cnt_reg(2)); |
WHEN X"C" => leds_a(7) <= '0'; |
leds_k(7) <= s_led_blink_cnt_reg(0); |
WHEN X"D" => leds_a(7) <= s_led_blink_cnt_reg(0); |
leds_k(7) <= '0'; |
WHEN X"E" | |
X"F" => leds_a(7) <= s_led_blink_cnt_reg(0); |
leds_k(7) <= NOT(s_led_blink_cnt_reg(0)); |
WHEN OTHERS => leds_a(7) <= '0'; |
leds_k(7) <= '0'; |
END CASE; |
END PROCESS make_led_7; |
|
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/vga/vga_controller-entity.vhdl
0,0 → 1,90
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
-- Color definition: |
-- 0 => black |
-- 1 => blue |
-- 2 => green |
-- 3 => cyan |
-- 4 => red |
-- 5 => magenta |
-- 6 => yellow |
-- 7 => white |
|
ENTITY vga_controller IS |
PORT ( clock_75MHz : IN std_logic; |
reset : IN std_logic; |
vga_off : IN std_logic; |
clock : IN std_logic; |
|
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
command_error : OUT std_logic; |
|
-- Here the usbtmc fifo interface is defined |
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic; |
|
-- Here the PUD interface is defined |
we_char : IN std_logic; |
we_ascii : IN std_logic_vector( 7 DOWNTO 0 ); |
we_addr : IN std_logic_vector( 10 DOWNTO 0 ); |
|
-- Here the fpga interface is defined |
cursor_pos : IN std_logic_vector( 10 DOWNTO 0 ); |
screen_offset : IN std_logic_vector( 4 DOWNTO 0 ); |
fg_color : IN std_logic_vector( 2 DOWNTO 0 ); |
bg_color : IN std_logic_vector( 2 DOWNTO 0 ); |
write_address : IN std_logic_vector( 10 DOWNTO 0 ); |
ascii_data : IN std_logic_vector( 7 DOWNTO 0 ); |
we : IN std_logic; |
|
vga_red : OUT std_logic; |
vga_green : OUT std_logic; |
vga_blue : OUT std_logic; |
vga_hsync : OUT std_logic; |
vga_vsync : OUT std_logic ); |
END vga_controller; |
|
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/ieee488.2_status/ieee488.2_status-entity.vhdl
0,0 → 1,70
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY status_controller IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
fpga_configured : IN std_logic; |
|
-- Here the fx2 interface is defined |
status_nibble : OUT std_logic_vector( 3 DOWNTO 0 ); |
|
-- Here the external status if is defined |
ESB_bit : IN std_logic; |
STATUS3_bit : IN std_logic; |
|
-- Here the scpi interface is defined |
start : IN std_logic; |
command : IN std_logic_vector( 6 DOWNTO 0 ); |
cmd_error : OUT std_logic; |
command_error : IN std_logic; |
execution_error : IN std_logic; |
done : OUT std_logic; |
transparent : OUT std_logic; |
|
pop : OUT std_logic; |
pop_data : IN std_logic_vector( 7 DOWNTO 0 ); |
pop_last : IN std_logic; |
pop_empty : IN std_logic; |
|
push : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
push_size : OUT std_logic; |
push_full : IN std_logic; |
push_empty : IN std_logic ); |
END status_controller; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/ieee488.2_status/ieee488.2_status-behavior.vhdl
0,0 → 1,440
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
ARCHITECTURE no_target_specific OF status_controller IS |
|
TYPE STATUS_STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,CLEAR, |
GET_VALUE,STORE_VALUE,LATCH_RESULT,SET_OPC, |
CALC_100,CALC_10,INIT_SEND,DO_SEND, |
SET_TRANSPARENT); |
|
CONSTANT c_100 : std_logic_vector( 6 DOWNTO 0 ) := "1100100"; |
CONSTANT c_10 : std_logic_vector( 3 DOWNTO 0 ) := X"A"; |
|
SIGNAL s_command_state_reg : STATUS_STATE_TYPE; |
SIGNAL s_standard_event_status_register : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_standard_event_status_next : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_standard_event_status_enable_register : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_service_request_enable_register : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_status_byte_register : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_transparent_reg : std_logic; |
SIGNAL s_pop : std_logic; |
SIGNAL s_valid_data : std_logic; |
SIGNAL s_value_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_overflow : std_logic; |
SIGNAL s_result_reg : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_100_remain_reg : std_logic_vector( 6 DOWNTO 0 ); |
SIGNAL s_100_div_reg : std_logic_vector( 1 DOWNTO 0 ); |
SIGNAL s_10_remain_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_10_div_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_send_cnt_reg : std_logic_vector( 3 DOWNTO 0 ); |
SIGNAL s_push : std_logic; |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
cmd_error <= '1' WHEN s_command_state_reg = SIGNAL_ERROR ELSE '0'; |
done <= '1' WHEN s_command_state_reg = SIGNAL_DONE ELSE '0'; |
pop <= s_pop; |
push <= s_push; |
push_size <= '1' WHEN s_send_cnt_reg = X"4" ELSE '0'; |
transparent <= s_transparent_reg; |
status_nibble <= s_status_byte_register( 5 DOWNTO 2 ); |
|
make_push_data : PROCESS( s_send_cnt_reg , s_10_div_reg , s_100_div_reg , |
s_10_remain_reg ) |
BEGIN |
CASE (s_send_cnt_reg) IS |
WHEN X"4" => IF (s_10_div_reg = X"0" AND |
s_100_div_reg = "00") THEN |
push_data <= X"02"; |
ELSIF (s_100_div_reg = "00") THEN |
push_data <= X"03"; |
ELSE |
push_data <= X"04"; |
END IF; |
WHEN X"3" => push_data <= X"3"&"00"&s_100_div_reg; |
WHEN X"2" => push_data <= X"3"&s_10_div_reg; |
WHEN X"1" => push_data <= X"3"&s_10_remain_reg; |
WHEN X"0" => push_data <= X"0A"; |
WHEN OTHERS => push_data <= X"00"; |
END CASE; |
END PROCESS make_push_data; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_pop <= '1' WHEN s_command_state_reg = GET_VALUE AND |
pop_empty = '0' ELSE '0'; |
s_push <= '1' WHEN s_send_cnt_reg(3) = '0' AND |
push_full = '0' ELSE '0'; |
s_valid_data <= '1' WHEN (pop_data = X"30" OR |
pop_data = X"31" OR |
pop_data = X"32" OR |
pop_data = X"33" OR |
pop_data = X"34" OR |
pop_data = X"35" OR |
pop_data = X"36" OR |
pop_data = X"37" OR |
pop_data = X"38" OR |
pop_data = X"39") AND |
s_pop = '1' ELSE '0'; |
|
s_status_byte_register(7) <= '0'; |
s_status_byte_register(6) <= (s_service_request_enable_register(7) AND |
s_status_byte_register(7)) |
OR |
(s_service_request_enable_register(5) AND |
s_status_byte_register(5)) |
OR |
(s_service_request_enable_register(4) AND |
s_status_byte_register(4)) |
OR |
(s_service_request_enable_register(3) AND |
s_status_byte_register(3)) |
OR |
(s_service_request_enable_register(2) AND |
s_status_byte_register(2)) |
OR |
(s_service_request_enable_register(1) AND |
s_status_byte_register(1)) |
OR |
(s_service_request_enable_register(0) AND |
s_status_byte_register(0)); |
s_status_byte_register(5) <= ((s_standard_event_status_register(0) AND |
s_standard_event_status_enable_register(0)) |
OR |
(s_standard_event_status_register(1) AND |
s_standard_event_status_enable_register(1)) |
OR |
(s_standard_event_status_register(2) AND |
s_standard_event_status_enable_register(2)) |
OR |
(s_standard_event_status_register(3) AND |
s_standard_event_status_enable_register(3)) |
OR |
(s_standard_event_status_register(4) AND |
s_standard_event_status_enable_register(4)) |
OR |
(s_standard_event_status_register(5) AND |
s_standard_event_status_enable_register(5)) |
OR |
(s_standard_event_status_register(6) AND |
s_standard_event_status_enable_register(6)) |
OR |
(s_standard_event_status_register(7) AND |
s_standard_event_status_enable_register(7))) |
WHEN s_transparent_reg = '0' ELSE |
ESB_bit; |
s_status_byte_register(4) <= NOT(push_empty); -- MAV bit |
s_status_byte_register(3) <= STATUS3_bit WHEN s_transparent_reg = '1' ELSE |
fpga_configured; |
s_status_byte_register(2) <= s_transparent_reg; |
s_status_byte_register(1) <= '0'; |
s_status_byte_register(0) <= '0'; |
|
s_standard_event_status_next(0) <= '1' WHEN s_command_state_reg = SET_OPC ELSE |
s_standard_event_status_register(0); |
s_standard_event_status_next(1) <= s_standard_event_status_register(1); |
s_standard_event_status_next(2) <= s_standard_event_status_register(2); |
s_standard_event_status_next(3) <= s_standard_event_status_register(3); |
s_standard_event_status_next(4) <= s_standard_event_status_register(4) OR |
execution_error; |
s_standard_event_status_next(5) <= s_standard_event_status_register(5) OR |
command_error; |
s_standard_event_status_next(6) <= s_standard_event_status_register(6); |
s_standard_event_status_next(7) <= s_standard_event_status_register(7); |
-------------------------------------------------------------------------------- |
--- Here the state machine is defined --- |
-------------------------------------------------------------------------------- |
make_state_machine : PROCESS( clock , reset , s_command_state_reg , start , |
command ) |
VARIABLE v_next_state : STATUS_STATE_TYPE; |
BEGIN |
CASE (s_command_state_reg) IS |
WHEN IDLE => IF (start = '1') THEN |
CASE (command) IS |
WHEN "0000010" => v_next_state := CLEAR; |
WHEN "0000110" | |
"0010000" => v_next_state := GET_VALUE; |
WHEN "0000111" | |
"0001000" | |
"0010001" | |
"0010010" | |
"0001100" | |
"0010100" | |
"0001010" => v_next_state := LATCH_RESULT; |
WHEN "0001011" => v_next_state := SET_OPC; |
WHEN "0010101" => v_next_state := SIGNAL_DONE; |
WHEN "0110011" => v_next_state := SET_TRANSPARENT; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
ELSE |
v_next_state := IDLE; |
END IF; |
WHEN CLEAR => v_next_state := SIGNAL_DONE; |
WHEN GET_VALUE => IF (s_overflow = '1') THEN |
v_next_state := SIGNAL_ERROR; |
ELSIF (s_pop = '1') THEN |
IF (pop_data = X"0A" OR |
pop_data = X"3B" OR |
(pop_last = '1' AND |
(s_valid_data = '1' OR |
pop_data = X"20"))) THEN |
v_next_state := STORE_VALUE; |
ELSIF (pop_last = '0' AND |
(s_valid_data = '1' OR |
pop_data = X"20")) THEN |
v_next_state := GET_VALUE; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
ELSE |
v_next_state := GET_VALUE; |
END IF; |
WHEN STORE_VALUE => v_next_state := SIGNAL_DONE; |
WHEN LATCH_RESULT => v_next_state := CALC_100; |
WHEN CALC_100 => v_next_state := CALC_10; |
WHEN CALC_10 => v_next_state := INIT_SEND; |
WHEN INIT_SEND => v_next_state := DO_SEND; |
WHEN DO_SEND => IF (s_send_cnt_reg(3) = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := DO_SEND; |
END IF; |
WHEN SET_OPC => v_next_state := SIGNAL_DONE; |
WHEN SET_TRANSPARENT => IF (fpga_configured = '1') THEN |
v_next_state := SIGNAL_DONE; |
ELSE |
v_next_state := SIGNAL_ERROR; |
END IF; |
WHEN OTHERS => v_next_state := IDLE; |
END CASE; |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_command_state_reg <= IDLE; |
ELSE s_command_state_reg <= v_next_state; |
END IF; |
END IF; |
END PROCESS make_state_machine; |
|
-------------------------------------------------------------------------------- |
--- Here the value handling is defined --- |
-------------------------------------------------------------------------------- |
make_value_reg : PROCESS( clock , s_command_state_reg , pop_data , |
s_valid_data ) |
VARIABLE v_add_1 : std_logic_vector(11 DOWNTO 0 ); |
VARIABLE v_add_2 : std_logic_vector(11 DOWNTO 0 ); |
VARIABLE v_add_3 : std_logic_vector(11 DOWNTO 0 ); |
VARIABLE v_sum : std_logic_vector(11 DOWNTO 0 ); |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_command_state_reg = IDLE) THEN |
s_value_reg <= X"00"; |
s_overflow <= '0'; |
ELSIF (s_valid_data = '1') THEN |
v_add_1 := X"00"&pop_data( 3 DOWNTO 0 ); |
v_add_2 := "000"&s_value_reg&"0"; |
v_add_3 := "0"&s_value_reg&"000"; |
v_sum := unsigned(v_add_1) + unsigned(v_add_2) + unsigned(v_add_3); |
s_value_reg <= v_sum( 7 DOWNTO 0 ); |
s_overflow <= v_sum(8) OR v_sum(9) OR v_sum(10) OR v_sum(11); |
END IF; |
END IF; |
END PROCESS make_value_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the query handling is defined --- |
-------------------------------------------------------------------------------- |
make_result_reg : PROCESS( clock , s_command_state_reg , reset ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_result_reg <= X"00"; |
ELSIF (s_command_state_reg = LATCH_RESULT) THEN |
CASE (command) IS |
WHEN "0000111" => s_result_reg <= s_standard_event_status_enable_register; |
WHEN "0001000" => s_result_reg <= s_standard_event_status_register; |
WHEN "0010001" => s_result_reg <= s_service_request_enable_register; |
WHEN "0010010" => s_result_reg <= s_status_byte_register; |
WHEN "0001100" => s_result_reg <= X"01"; |
WHEN OTHERS => s_result_reg <= X"00"; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_result_reg; |
|
make_100_regs : PROCESS( clock , s_result_reg ) |
VARIABLE v_sub_1_1 : std_logic_vector( 8 DOWNTO 0 ); |
VARIABLE v_sub_1_2 : std_logic_vector( 8 DOWNTO 0 ); |
VARIABLE v_sub_1 : std_logic_vector( 8 DOWNTO 0 ); |
VARIABLE v_sub_2_1 : std_logic_vector( 7 DOWNTO 0 ); |
VARIABLE v_sub_2_2 : std_logic_vector( 7 DOWNTO 0 ); |
VARIABLE v_sub_2 : std_logic_vector( 7 DOWNTO 0 ); |
BEGIN |
v_sub_1_1 := "0"&s_result_reg; |
v_sub_1_2 := "0"&c_100&"0"; |
v_sub_1 := unsigned(v_sub_1_1)-unsigned(v_sub_1_2); |
IF (v_sub_1(8) = '0') THEN v_sub_2_1 := v_sub_1( 7 DOWNTO 0 ); |
ELSE v_sub_2_1 := s_result_reg; |
END IF; |
v_sub_2_2 := "0"&c_100; |
v_sub_2 := unsigned(v_sub_2_1) - unsigned(v_sub_2_2); |
IF (clock'event AND (clock = '1')) THEN |
IF (v_sub_2(7) = '0') THEN s_100_remain_reg <= v_sub_2( 6 DOWNTO 0 ); |
ELSE s_100_remain_reg <= v_sub_2_1( 6 DOWNTO 0 ); |
END IF; |
s_100_div_reg(1) <= NOT(v_sub_1(8)); |
s_100_div_reg(0) <= NOT(v_sub_2(7)); |
END IF; |
END PROCESS make_100_regs; |
|
make_10_regs : PROCESS( clock , s_100_remain_reg ) |
VARIABLE v_sub_1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_remain_1 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub_2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_remain_2 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub_3 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_remain_3 : std_logic_vector( 4 DOWNTO 0 ); |
VARIABLE v_sub_4 : std_logic_vector( 4 DOWNTO 0 ); |
BEGIN |
v_sub_1 := unsigned("0"&s_100_remain_reg(6 DOWNTO 3)) - |
unsigned("0"&c_10); |
IF (v_sub_1(4) = '0') THEN |
v_remain_1 := v_sub_1(3 DOWNTO 0)&s_100_remain_reg(2); |
ELSE |
v_remain_1 := s_100_remain_reg(6 DOWNTO 2); |
END IF; |
v_sub_2 := unsigned(v_remain_1) - unsigned("0"&c_10); |
IF (v_sub_2(4) = '0') THEN |
v_remain_2 := v_sub_2(3 DOWNTO 0)&s_100_remain_reg(1); |
ELSE |
v_remain_2 := v_remain_1(3 DOWNTO 0)&s_100_remain_reg(1); |
END IF; |
v_sub_3 := unsigned(v_remain_2) - unsigned("0"&c_10); |
IF (v_sub_3(4) = '0') THEN |
v_remain_3 := v_sub_3(3 DOWNTO 0)&s_100_remain_reg(0); |
ELSE |
v_remain_3 := v_remain_2(3 DOWNTO 0)&s_100_remain_reg(0); |
END IF; |
v_sub_4 := unsigned(v_remain_3) - unsigned("0"&c_10); |
IF (clock'event AND (clock = '1')) THEN |
IF (v_sub_4(4) = '0') THEN s_10_remain_reg <= v_sub_4(3 DOWNTO 0); |
ELSE s_10_remain_reg <= v_remain_3(3 DOWNTO 0); |
END IF; |
s_10_div_reg(3) <= NOT(v_sub_1(4)); |
s_10_div_reg(2) <= NOT(v_sub_2(4)); |
s_10_div_reg(1) <= NOT(v_sub_3(4)); |
s_10_div_reg(0) <= NOT(v_sub_4(4)); |
END IF; |
END PROCESS make_10_regs; |
|
-------------------------------------------------------------------------------- |
--- Here the data sending is defined --- |
-------------------------------------------------------------------------------- |
make_send_cnt_reg : PROCESS( clock , reset , s_command_state_reg , s_push ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_send_cnt_reg <= (OTHERS => '1'); |
ELSIF (s_command_state_reg = INIT_SEND) THEN |
s_send_cnt_reg <= X"4"; |
ELSIF (s_push = '1') THEN |
CASE (s_send_cnt_reg) IS |
WHEN X"4" => IF (s_10_div_reg = X"0" AND |
s_100_div_reg = "00") THEN |
s_send_cnt_reg <= X"1"; |
ELSIF (s_100_div_reg = "00") THEN |
s_send_cnt_reg <= X"2"; |
ELSE |
s_send_cnt_reg <= X"3"; |
END IF; |
WHEN OTHERS => s_send_cnt_reg <= unsigned(s_send_cnt_reg) - 1; |
END CASE; |
END IF; |
END IF; |
END PROCESS make_send_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here all registers are defined --- |
-------------------------------------------------------------------------------- |
make_seser : PROCESS( clock , reset , s_command_state_reg , |
command , s_value_reg) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_standard_event_status_enable_register <= X"00"; |
ELSIF (s_command_state_reg = STORE_VALUE AND |
command = "0000110" ) THEN |
s_standard_event_status_enable_register <= s_value_reg; |
END IF; |
END IF; |
END PROCESS make_seser; |
|
make_sesr : PROCESS( clock , reset , s_command_state_reg , |
s_standard_event_status_next ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_standard_event_status_register <= X"80"; |
ELSIF (s_command_state_reg = CLEAR OR |
(s_command_state_reg = LATCH_RESULT AND |
command = "0001000")) THEN |
s_standard_event_status_register <= X"00"; |
ELSE |
s_standard_event_status_register <= s_standard_event_status_next; |
END IF; |
END IF; |
END PROCESS make_sesr; |
|
make_srer : PROCESS( clock , reset , s_command_state_reg , |
command , s_value_reg) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_service_request_enable_register <= X"00"; |
ELSIF (s_command_state_reg = STORE_VALUE AND |
command = "0010000" ) THEN |
s_service_request_enable_register <= s_value_reg; |
END IF; |
END IF; |
END PROCESS make_srer; |
|
make_transparent_reg : PROCESS( clock , reset , s_command_state_reg ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_command_state_reg = CLEAR OR |
reset = '1') THEN s_transparent_reg <= '0'; |
ELSIF (s_command_state_reg = SET_TRANSPARENT AND |
fpga_configured = '1') THEN |
s_transparent_reg <= '1'; |
END IF; |
END IF; |
END PROCESS make_transparent_reg; |
|
END no_target_specific; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_18_1e_if/cmd_18_1e_if-behavior-xilinx.vhdl
0,0 → 1,266
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- The unisim library is used for simulation of the xilinx specific components |
-- For generic usage please use: |
-- LIBRARY work; |
-- USE work.xilinx_generic.all; |
-- And use the xilinx generic package found in the xilinx generic module |
LIBRARY unisim; |
USE unisim.all; |
|
ARCHITECTURE xilinx OF cmd_18_1e_if IS |
|
COMPONENT RAMB16_S9 |
GENERIC ( INIT_00 : bit_vector; |
INIT_01 : bit_vector; |
INIT_02 : bit_vector; |
INIT_03 : bit_vector; |
INIT_04 : bit_vector; |
INIT_05 : bit_vector; |
INIT_06 : bit_vector; |
INIT_07 : bit_vector; |
INIT_08 : bit_vector; |
INIT_09 : bit_vector; |
INIT_0A : bit_vector; |
INIT_0B : bit_vector; |
INIT_0C : bit_vector; |
INIT_0D : bit_vector; |
INIT_0E : bit_vector; |
INIT_0F : bit_vector; |
INIT_10 : bit_vector; |
INIT_11 : bit_vector; |
INIT_12 : bit_vector; |
INIT_13 : bit_vector; |
INIT_14 : bit_vector; |
INIT_15 : bit_vector; |
INIT_16 : bit_vector; |
INIT_17 : bit_vector; |
INIT_18 : bit_vector; |
INIT_19 : bit_vector; |
INIT_1A : bit_vector; |
INIT_1B : bit_vector; |
INIT_1C : bit_vector; |
INIT_1D : bit_vector; |
INIT_1E : bit_vector; |
INIT_1F : bit_vector; |
INIT_20 : bit_vector; |
INIT_21 : bit_vector; |
INIT_22 : bit_vector; |
INIT_23 : bit_vector; |
INIT_24 : bit_vector; |
INIT_25 : bit_vector; |
INIT_26 : bit_vector; |
INIT_27 : bit_vector; |
INIT_28 : bit_vector; |
INIT_29 : bit_vector; |
INIT_2A : bit_vector; |
INIT_2B : bit_vector; |
INIT_2C : bit_vector; |
INIT_2D : bit_vector; |
INIT_2E : bit_vector; |
INIT_2F : bit_vector; |
INIT_30 : bit_vector; |
INIT_31 : bit_vector; |
INIT_32 : bit_vector; |
INIT_33 : bit_vector; |
INIT_34 : bit_vector; |
INIT_35 : bit_vector; |
INIT_36 : bit_vector; |
INIT_37 : bit_vector; |
INIT_38 : bit_vector; |
INIT_39 : bit_vector; |
INIT_3A : bit_vector; |
INIT_3B : bit_vector; |
INIT_3C : bit_vector; |
INIT_3D : bit_vector; |
INIT_3E : bit_vector; |
INIT_3F : bit_vector); |
PORT ( DO : OUT std_logic_vector( 7 DOWNTO 0 ); |
DOP : OUT std_logic_vector( 0 DOWNTO 0 ); |
ADDR : IN std_logic_vector( 10 DOWNTO 0 ); |
DI : IN std_logic_vector( 7 DOWNTO 0 ); |
DIP : IN std_logic_vector( 0 DOWNTO 0 ); |
EN : IN std_logic; |
WE : IN std_logic; |
CLK : IN std_logic; |
SSR : IN std_logic ); |
END COMPONENT; |
|
SIGNAL s_n_clock : std_logic; |
SIGNAL s_string_data : std_logic_vector( 7 DOWNTO 0 ); |
SIGNAL s_string_index : std_logic_vector(10 DOWNTO 0 ); |
SIGNAL s_push : std_logic; |
SIGNAL s_valid_command : std_logic; |
SIGNAL s_string_select_reg : std_logic_vector( 4 DOWNTO 0 ); |
SIGNAL s_string_cnt_reg : std_logic_vector( 5 DOWNTO 0 ); |
|
BEGIN |
-------------------------------------------------------------------------------- |
--- Here the outputs are defined --- |
-------------------------------------------------------------------------------- |
push_size <= s_string_data(7); |
push_data <= "0"&s_string_data(6 DOWNTO 0); |
push <= s_push; |
|
-------------------------------------------------------------------------------- |
--- Here the control signals are defined --- |
-------------------------------------------------------------------------------- |
s_n_clock <= NOT(clock); |
s_push <= '0' WHEN s_string_data = X"00" OR |
fifo_full = '1' ELSE '1'; |
s_valid_command <= '1' WHEN start_command = '1' AND |
(command_id = "0011000" OR |
command_id = "0011110") ELSE '0'; |
s_string_index <= s_string_select_reg&s_string_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the processes are defined --- |
-------------------------------------------------------------------------------- |
make_command_done : PROCESS( clock , s_push , s_string_data ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (s_push = '1' AND |
s_string_data = X"0A") THEN command_done <= '1'; |
ELSE command_done <= '0'; |
END IF; |
END IF; |
END PROCESS make_command_done; |
|
make_string_select_reg : PROCESS( clock , reset , s_valid_command , |
command_id , n_usb_power , n_usb_charge , |
n_bus_power , fpga_configured , |
fpga_type , flash_empty ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_string_select_reg <= (OTHERS => '0'); |
ELSIF (s_valid_command = '1') THEN |
IF (command_id = "0011000") THEN |
s_string_select_reg <= "1"&flash_empty&n_usb_power&n_usb_charge&n_bus_power; |
ELSE |
s_string_select_reg <= "0"&fpga_configured&fpga_type; |
END IF; |
END IF; |
END IF; |
END PROCESS make_string_select_reg; |
|
make_string_cnt_reg : PROCESS( clock , reset , s_valid_command , s_push ) |
BEGIN |
IF (clock'event AND (clock = '1')) THEN |
IF (reset = '1') THEN s_string_cnt_reg <= (OTHERS => '1'); |
ELSIF (s_valid_command = '1') THEN s_string_cnt_reg <= (OTHERS => '0'); |
ELSIF (s_push = '1') THEN |
s_string_cnt_reg <= unsigned(s_string_cnt_reg) + 1; |
END IF; |
END IF; |
END PROCESS make_string_cnt_reg; |
|
-------------------------------------------------------------------------------- |
--- Here the string rom is defined --- |
-------------------------------------------------------------------------------- |
string_rom : RAMB16_S9 |
GENERIC MAP ( INIT_00 => X"36373647474630303031533343582033206E61747261705320786E696C6958B0", |
INIT_01 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C", |
INIT_02 => X"36373647474630303531533343582033206E61747261705320786E696C6958B0", |
INIT_03 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C", |
INIT_04 => X"36373647474630303032533343582033206E61747261705320786E696C6958B0", |
INIT_05 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C", |
INIT_06 => X"36373647474630303034533343582033206E61747261705320786E696C6958B0", |
INIT_07 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C", |
INIT_08 => X"36373647474630303035533343582033206E61747261705320786E696C6958B0", |
INIT_09 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C", |
INIT_0A => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_0B => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_0C => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_0D => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_0E => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_0F => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_10 => X"36373647474630303031533343582033206E61747261705320786E696C6958A9", |
INIT_11 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C", |
INIT_12 => X"36373647474630303531533343582033206E61747261705320786E696C6958A9", |
INIT_13 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C", |
INIT_14 => X"36373647474630303032533343582033206E61747261705320786E696C6958A9", |
INIT_15 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C", |
INIT_16 => X"36373647474630303034533343582033206E61747261705320786E696C6958A9", |
INIT_17 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C", |
INIT_18 => X"36373647474630303035533343582033206E61747261705320786E696C6958A9", |
INIT_19 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C", |
INIT_1A => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_1B => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_1C => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_1D => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_1E => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5", |
INIT_1F => X"00000000000000000000000000000000000000000000000000000A6570797420", |
INIT_20 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_21 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_22 => X"7265776F70202C6465696C7070757320425355203A6E69616D344F4B434547B9", |
INIT_23 => X"0000000000000A64656D6D6172676F7270206873616C46202C53554220676E69", |
INIT_24 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_25 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_26 => X"6873616C46202C6465696C7070757320425355203A6E69616D344F4B434547AB", |
INIT_27 => X"00000000000000000000000000000000000000000A64656D6D6172676F727020", |
INIT_28 => X"6F70202C6465696C7070757320314F494E4547203A6E69616D344F4B434547BC", |
INIT_29 => X"0000000A64656D6D6172676F7270206873616C46202C53554220676E69726577", |
INIT_2A => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_2B => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_2C => X"6C46202C6465696C7070757320314F494E4547203A6E69616D344F4B434547AE", |
INIT_2D => X"00000000000000000000000000000000000A64656D6D6172676F727020687361", |
INIT_2E => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_2F => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_30 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_31 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_32 => X"7265776F70202C6465696C7070757320425355203A6E69616D344F4B434547B4", |
INIT_33 => X"00000000000000000000000A7974706D65206873616C46202C53554220676E69", |
INIT_34 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_35 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_36 => X"6873616C46202C6465696C7070757320425355203A6E69616D344F4B434547A6", |
INIT_37 => X"000000000000000000000000000000000000000000000000000A7974706D6520", |
INIT_38 => X"6F70202C6465696C7070757320314F494E4547203A6E69616D344F4B434547B7", |
INIT_39 => X"00000000000000000A7974706D65206873616C46202C53554220676E69726577", |
INIT_3A => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_3B => X"0000000000000000000000000000000000000000000000000000000A3F6D656C", |
INIT_3C => X"6C46202C6465696C7070757320314F494E4547203A6E69616D344F4B434547A9", |
INIT_3D => X"000000000000000000000000000000000000000000000A7974706D6520687361", |
INIT_3E => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4", |
INIT_3F => X"0000000000000000000000000000000000000000000000000000000A3F6D656C") |
PORT MAP ( DO => s_string_data, |
DOP => OPEN, |
ADDR => s_string_index, |
DI => X"00", |
DIP => "0", |
EN => '1', |
WE => '0', |
CLK => s_n_clock, |
SSR => '0' ); |
|
END xilinx; |
/gecko4/trunk/GECKO4com/spartan200_an/vhdl/cmd_18_1e_if/cmd_18_1e_if-entity.vhdl
0,0 → 1,64
-------------------------------------------------------------------------------- |
-- _ _ __ ____ -- |
-- / / | | / _| | __| -- |
-- | |_| | _ _ / / | |_ -- |
-- | _ | | | | | | | | _| -- |
-- | | | | | |_| | \ \_ | |__ -- |
-- |_| |_| \_____| \__| |____| microLab -- |
-- -- |
-- Bern University of Applied Sciences (BFH) -- |
-- Quellgasse 21 -- |
-- Room HG 4.33 -- |
-- 2501 Biel/Bienne -- |
-- Switzerland -- |
-- -- |
-- http://www.microlab.ch -- |
-------------------------------------------------------------------------------- |
-- GECKO4com |
-- |
-- 2010/2011 Dr. Theo Kluter |
-- |
-- This VHDL code is free code: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This VHDL code is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- You should have received a copy of the GNU General Public License |
-- along with these sources. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
|
ENTITY cmd_18_1e_if IS |
PORT ( clock : IN std_logic; |
reset : IN std_logic; |
|
-- Here the scpi interface is defined |
start_command : IN std_logic; |
command_id : IN std_logic_vector( 6 DOWNTO 0 ); |
command_done : OUT std_logic; |
|
-- Here the tx_fifo is defined |
push : OUT std_logic; |
push_size : OUT std_logic; |
push_data : OUT std_logic_vector( 7 DOWNTO 0 ); |
fifo_full : IN std_logic; |
|
-- Here the fpga_if is defined |
fpga_type : IN std_logic_vector( 2 DOWNTO 0 ); |
fpga_configured : IN std_logic; |
|
-- Here the flash if is defined |
flash_empty : IN std_logic; |
|
-- Here the board interface is defined |
n_usb_power : IN std_logic; |
n_bus_power : IN std_logic; |
n_usb_charge : IN std_logic); |
END cmd_18_1e_if; |
/gecko4/trunk/GECKO4com/spartan200_an/Makefile
0,0 → 1,137
################################################################################ |
## _ _ __ ____ ## |
## / / | | / _| | __| ## |
## | |_| | _ _ / / | |_ ## |
## | _ | | | | | | | | _| ## |
## | | | | | |_| | \ \_ | |__ ## |
## |_| |_| \_____| \__| |____| microLab ## |
## ## |
## Bern University of Applied Sciences (BFH) ## |
## Quellgasse 21 ## |
## Room HG 4.33 ## |
## 2501 Biel/Bienne ## |
## Switzerland ## |
## ## |
## http://www.microlab.ch ## |
################################################################################ |
PROJECT_TOP=config/project.toplevel |
PROJECT_LIST=config/project.files |
PROJECT_FORCE=config/project.force |
PROJECT_DEVICE=config/project.device |
PROJECT_OPTIONS=config/project.options |
PROJECT_UCF=config/project.ucf |
PROJECT_XILINX=config/project.xilinx |
|
REL_PATH=. |
TOPLEVEL := $(shell cat $(REL_PATH)/$(PROJECT_TOP)) |
PROJECT_EDF=sandbox/$(TOPLEVEL).edf |
|
.PHONY: default clean sim % |
|
define do_modelsim |
if test ! -f $(PROJECT_LIST); then\ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_LIST) found!"; else\ |
if test ! -f $(PROJECT_FORCE); then \ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_FORCE) found!"; else\ |
echo "INFO: Performing automated simulation...";\ |
mkdir -p sandbox;\ |
cd sandbox;\ |
echo "PROJECT_LIST=$(PROJECT_LIST)" >> Makefile.modelsim;\ |
echo "PROJECT_FORCE=$(PROJECT_FORCE)" >> Makefile.modelsim;\ |
echo "REL_PATH=.." >> Makefile.modelsim;\ |
cat ../Makefile.modelsim >> Makefile.modelsim;\ |
$(MAKE) -f Makefile.modelsim;\ |
fi; fi |
endef #do modelsim |
|
define do_synth |
if test ! -f $(PROJECT_TOP); then\ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_TOP) found!"; else\ |
if test ! -f $(PROJECT_LIST); then\ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_LIST) found!"; else\ |
if test ! -f $(PROJECT_DEVICE); then \ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_DEVICE) found!"; else\ |
echo "INFO: Performing automated synthesis...";\ |
mkdir -p sandbox;\ |
cd sandbox;\ |
echo "PROJECT_TOP=$(PROJECT_TOP)" > Makefile.synthesis;\ |
echo "PROJECT_LIST=$(PROJECT_LIST)" >> Makefile.synthesis;\ |
echo "PROJECT_OPTIONS=$(PROJECT_OPTIONS)" >> Makefile.synthesis;\ |
echo "PROJECT_DEVICE=$(PROJECT_DEVICE)" >> Makefile.synthesis;\ |
echo "REL_PATH=.." >> Makefile.synthesis;\ |
cat ../Makefile.synthesis >> Makefile.synthesis;\ |
$(MAKE) -f Makefile.synthesis;\ |
fi; fi ; fi |
endef |
|
define make_xilinx_bit |
if test ! -f $(PROJECT_TOP); then\ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_TOP) found!"; else\ |
if test ! -f $(PROJECT_UCF); then\ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_UCF) found!"; else\ |
if test ! -f $(PROJECT_DEVICE); then \ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_DEVICE) found!"; else\ |
if test ! -f $(PROJECT_XILINX); then \ |
echo ""; echo ""; echo "ERROR: No file $(PROJECT_XILINX) found!"; else\ |
echo "INFO: Performing automated xilinx bitfile generation...";\ |
mkdir -p sandbox;\ |
cd sandbox;\ |
echo "PROJECT_TOP=$(PROJECT_TOP)" > Makefile.xilinx;\ |
echo "PROJECT_UCF=$(PROJECT_UCF)" >> Makefile.xilinx;\ |
echo "PROJECT_XILINX=$(PROJECT_XILINX)" >> Makefile.xilinx;\ |
echo "PROJECT_DEVICE=$(PROJECT_DEVICE)" >> Makefile.xilinx;\ |
echo "REL_PATH=.." >> Makefile.xilinx;\ |
cat ../Makefile.xilinx >> Makefile.xilinx;\ |
$(MAKE) -f Makefile.xilinx;\ |
fi; fi ; fi ; fi |
endef |
|
define make_template |
mkdir -p c_sources |
mkdir -p config |
mkdir -p doc |
mkdir -p sandbox |
mkdir -p scripts |
mkdir -p vhdl |
endef |
|
default: |
@echo "===========================================================" |
@echo " Possible make targets are:" |
@echo "" |
@echo " clean: Remove all temporary files" |
@echo "" |
@echo " sim: Perform an automated simulation. The files" |
@echo " project.files and project.force in the directory" |
@echo " config/ must exist for this command to work" |
@echo "" |
@echo " synth: Perform an automated synthesis. The files" |
@echo " project.files, project.device, and project.toplevel" |
@echo " in the directory config/ must exist for this " |
@echo " command to work" |
@echo "" |
@echo " xilinx_bit: Generate a Xilinx bitfile for download. The" |
@echo " files project.ucf, project.device," |
@echo " project.toplevel, and project.xilinx" |
@echo " in the directory config/ must exist for this " |
@echo " command to work" |
@echo "" |
@echo "===========================================================" |
|
clean: |
@cd sandbox; find -type d | grep -v svn | grep "/" | xargs rm -rf ; find -type f | grep -v svn | xargs rm -f |
|
sim: |
@$(do_modelsim) |
|
synth: |
@$(do_synth) |
|
xilinx_bit: $(PROJECT_EDF) |
@$(make_xilinx_bit) |
|
template: |
@$(make_template) |
|
$(PROJECT_EDF) : |
@$(do_synth) |
/gecko4/trunk/GECKO4com/spartan200_an/README
0,0 → 1,8
Here the sources for the spartan 3 200AN FPGA are stored. To automatically |
generate the bitfile you require that: |
1) You have synplify_pro or synplify_premier_dp in your path and have a license |
2) You have Xilinx ISE 11.x and up in your path with the required license |
|
To generate the bitfile simply type: make xilinx_bit |
|
A pre-generated bitfile can be found in the bitfile directory. |
/gecko4/trunk/GECKO4com/spartan200_an/bitfile/xc3s200an_top.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
gecko4/trunk/GECKO4com/spartan200_an/bitfile/xc3s200an_top.bit
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property