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trunk/doc/hwlu_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sw/gen_hw_looping.c =================================================================== --- trunk/sw/gen_hw_looping.c (revision 4) +++ trunk/sw/gen_hw_looping.c (nonexistent) @@ -1,331 +0,0 @@ -/* Filename: gen_hw_looping.c */ -/* Description: Generates top-level module for the hw_looping unit */ -/* Author: Nikos Kavvadias, */ -/* Date: Friday, 09/04/2004 */ - -#include -#include -#include - -#define PRINT_DEBUG - - -// FUNCTION PROTOTYPES -void write_file_hw_looping(FILE *outfile); - -FILE *file_hw_looping; /* VHDL source for the top-level module of the - * hw_looping unit (hw_looping.vhd) */ - -char hw_looping_file_name[32]; -int nlp; -time_t t; - - -int main(int argc, char **argv) -{ - int i; - int gen_hw_looping_file; - char nlp_s[3]; - - gen_hw_looping_file = 0; - - if( argc < 3 ) - { - printf("Usage: gen_hw_looping \n"); - printf("where:\n"); - printf("num loops = give number of supported loops\n"); - printf("output base = output file base name. The generated files will be named:\n"); - printf(" \"_top.vhd\" for the top-level module\n"); - // - printf("\n"); - // - return -1; - } - - // Acquire number of supported loops - strcpy(nlp_s,argv[1]); - nlp = atoi(nlp_s); - - // Generate hw_looping_file_name - // (indicating the number of loops supported) - - // Filenames for the requested VHDL source files - //strcpy(hw_looping_file_name,argv[2]); - //strcat(hw_looping_file_name,nlp_s); - //strcat(hw_looping_file_name,"_top.vhd"); - sprintf(hw_looping_file_name,"%s_loops%s%s", argv[2], nlp_s, "_top.vhd"); - gen_hw_looping_file = 1; - - // DEBUG OUTPUT - #ifdef PRINT_DEBUG - printf("\n"); - // - printf("nlp = %d\n",nlp); - printf("hw_looping_file_name = %s\n", hw_looping_file_name); - // - #endif - - - /*************************************************************/ - /* Generate VHDL source for the top-level unit of hw_looping */ - /*************************************************************/ - if (gen_hw_looping_file == 1) - { - file_hw_looping = fopen(hw_looping_file_name,"w"); - write_file_hw_looping(file_hw_looping); - fclose(file_hw_looping); - } - - return 0; - -} - - -void write_file_hw_looping( - FILE *outfile // Name for the output file - ) -{ - unsigned i; - - // Get current time - time(&t); - - /* Generate interface for the VHDL file */ - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Filename: %s ----\n", hw_looping_file_name); - fprintf(outfile,"---- Module description: Top-level file for the hw_looping unit. ----\n"); - fprintf(outfile,"---- Also implements input and output ----\n"); - fprintf(outfile,"---- wrapping operations. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically ----\n"); - fprintf(outfile,"---- with the use of the \"gen_hw_looping\" tool ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- To Do: ----\n"); - fprintf(outfile,"---- Considered stable for the time being ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Copyright (C) 2004 Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nick-kavi.8m.com ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- nick_ka_vi@hotmail.com ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source file may be used and distributed without ----\n"); - fprintf(outfile,"---- restriction provided that this copyright statement is not ----\n"); - fprintf(outfile,"---- removed from the file and that any derivative work contains ----\n"); - fprintf(outfile,"---- the original copyright notice and the associated disclaimer. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source file is free software; you can redistribute it ----\n"); - fprintf(outfile,"---- and/or modify it under the terms of the GNU Lesser General ----\n"); - fprintf(outfile,"---- Public License as published by the Free Software Foundation; ----\n"); - fprintf(outfile,"---- either version 2.1 of the License, or (at your option) any ----\n"); - fprintf(outfile,"---- later version. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source is distributed in the hope that it will be ----\n"); - fprintf(outfile,"---- useful, but WITHOUT ANY WARRANTY; without even the implied ----\n"); - fprintf(outfile,"---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----\n"); - fprintf(outfile,"---- PURPOSE. See the GNU Lesser General Public License for more ----\n"); - fprintf(outfile,"---- details. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- You should have received a copy of the GNU Lesser General ----\n"); - fprintf(outfile,"---- Public License along with this source; if not, download it ----\n"); - fprintf(outfile,"---- from ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"--\n"); - fprintf(outfile,"-- CVS Revision History\n"); - fprintf(outfile,"--\n"); - fprintf(outfile,"\n"); - - /* Code generation for library inclusions */ - fprintf(outfile,"library IEEE;\n"); - fprintf(outfile,"use IEEE.std_logic_1164.all;\n"); - fprintf(outfile,"\n"); - - /* Generate entity declaration */ - fprintf(outfile,"entity hw_looping is\n"); - fprintf(outfile,"\tgeneric (\n"); - fprintf(outfile,"\t\tDW : integer := 8;\n"); - fprintf(outfile,"\t\tNLP : integer := %d\n", nlp); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"\tport (\n"); - fprintf(outfile, "\t\tclk : in std_logic;\n"); - fprintf(outfile, "\t\treset : in std_logic;\n"); - fprintf(outfile, "\t\ttask_loop%d_end : in std_logic;\n", nlp); - // - for (i=1; i<=nlp; i++) - fprintf(outfile,"\t\tloop%d_count : in std_logic_vector(DW-1 downto 0);\n", i); - // - for (i=1; i<=nlp; i++) - { - fprintf(outfile,"\t\tindex%d : out std_logic_vector(DW-1 downto 0);\n", i); - } - // - fprintf(outfile, "\t\tloops_end : out std_logic\n"); - // - fprintf(outfile,"\t);\n"); - fprintf(outfile,"end hw_looping;\n"); - fprintf(outfile,"\n"); - - /* Generate architecture declaration */ - fprintf(outfile,"architecture structural of hw_looping is\n"); - - /* Add component declarations here if needed */ - fprintf(outfile,"--\n"); - fprintf(outfile,"-- Component declarations\n"); - fprintf(outfile,"component cmpeq\n"); - fprintf(outfile,"\tgeneric (\n"); - fprintf(outfile,"\t\tDW : integer := 8\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"\tport (\n"); - fprintf(outfile,"\t\ta : in std_logic_vector(DW-1 downto 0);\n"); - fprintf(outfile,"\t\tb : in std_logic_vector(DW-1 downto 0);\n"); - fprintf(outfile,"\t\treset : in std_logic;\n"); - fprintf(outfile,"\t\ta_eq_b : out std_logic\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"end component;\n"); - // - fprintf(outfile,"--\n"); - fprintf(outfile,"component index_inc\n"); - fprintf(outfile,"\tgeneric (\n"); - fprintf(outfile,"\t\tDW : integer := 8\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"\tport (\n"); - fprintf(outfile,"\t\tclk : in std_logic;\n"); - fprintf(outfile,"\t\treset : in std_logic;\n"); - fprintf(outfile,"\t\tinc_en : in std_logic;\n"); - fprintf(outfile,"\t\tindex_plus_one : out std_logic_vector(DW-1 downto 0);\n"); - fprintf(outfile,"\t\tindex_out : out std_logic_vector(DW-1 downto 0)\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"end component;\n"); - // - fprintf(outfile,"--\n"); - fprintf(outfile,"component priority_encoder\n"); - fprintf(outfile,"\tgeneric (\n"); - fprintf(outfile,"\t\tNLP : integer := 5\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"\tport (\n"); - fprintf(outfile,"\t\tflag : in std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp); - fprintf(outfile,"\t\tincl : out std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\treset_vct : out std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\tloops_end : out std_logic\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"end component;\n"); - - /* Add signal declarations here if needed */ - fprintf(outfile,"--\n"); - fprintf(outfile,"-- Signal declarations\n"); - // flag - fprintf(outfile,"signal flag : std_logic_vector(NLP-1 downto 0);\n"); - // incl - fprintf(outfile,"signal incl : std_logic_vector(NLP-1 downto 0);\n"); - // temp_loop_count - fprintf(outfile,"signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0);\n"); - // temp_index - fprintf(outfile,"signal temp_index : std_logic_vector(NLP*DW-1 downto 0);\n"); - // temp_index_plus_one - fprintf(outfile,"signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);\n"); - // temp_vct_penc - fprintf(outfile,"signal reset_vct_penc : std_logic_vector(NLP-1 downto 0);\n"); - // temp_index - fprintf(outfile,"signal reset_vct_ix : std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"--\n"); - - /* Continue with the rest of the architecture declaration */ - fprintf(outfile,"begin\n"); - fprintf(outfile,"\n"); - - /***************************************/ - /* GENERATE INPUT WRAPPING ASSIGNMENTS */ - /***************************************/ - - /* Iterate through all loops */ - for (i=1; i<=nlp; i++) - { - /* Generate assignment code */ - fprintf(outfile,"\ttemp_loop_count( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) ) <= loop%d_count;\n", - i-1, i, i); - } - fprintf(outfile,"\n"); - - /***************************************/ - /* GENERATE INTERNAL HW_LOOPING MODULE */ - /***************************************/ - - // Generate cmpeq modules - fprintf(outfile,"\tGEN_COMPARATORS: for i in 0 to NLP-1 generate\n"); - fprintf(outfile,"\t\tU_cmp : cmpeq\n"); - fprintf(outfile,"\t\t\tgeneric map (\n"); - fprintf(outfile,"\t\t\t\tDW => DW\n"); - fprintf(outfile,"\t\t\t)\n"); - fprintf(outfile,"\t\t\tport map (\n"); - fprintf(outfile,"\t\t\t\ta => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n"); - fprintf(outfile,"\t\t\t\tb => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),\n"); - fprintf(outfile,"\t\t\t\treset => reset,\n"); - fprintf(outfile,"\t\t\t\ta_eq_b => flag(i)\n"); - fprintf(outfile,"\t\t\t);\n"); - fprintf(outfile,"\tend generate GEN_COMPARATORS;\n"); - fprintf(outfile,"\n"); - - // Generate priority encoder - fprintf(outfile,"\tU_priority_enc : priority_encoder\n"); - fprintf(outfile,"\t\tgeneric map (\n"); - fprintf(outfile,"\t\t\tNLP => NLP\n"); - fprintf(outfile,"\t\t)\n"); - fprintf(outfile,"\t\tport map (\n"); - fprintf(outfile,"\t\t\tflag => flag,\n"); - fprintf(outfile,"\t\t\ttask_loop5_end => task_loop5_end,\n"); - fprintf(outfile,"\t\t\tincl => incl,\n"); - fprintf(outfile,"\t\t\treset_vct => reset_vct_penc,\n"); - fprintf(outfile,"\t\t\tloops_end => loops_end\n"); - fprintf(outfile,"\t\t);\n"); - fprintf(outfile,"\n"); - - // Generate reset_vct_ix - fprintf(outfile,"\tGEN_RESET_SEL: for i in 0 to NLP-1 generate\n"); - fprintf(outfile,"\t\treset_vct_ix(i) <= reset_vct_penc(i) or reset;\n"); - fprintf(outfile,"\tend generate GEN_RESET_SEL;\n"); - fprintf(outfile,"\n"); - - // Generate index_inc modules - fprintf(outfile,"\tGEN_INC_IX: for i in 0 to NLP-1 generate\n"); - fprintf(outfile,"\t\tU_inc_ix1 : index_inc\n"); - fprintf(outfile,"\t\t\tgeneric map (\n"); - fprintf(outfile,"\t\t\t\tDW => DW\n"); - fprintf(outfile,"\t\t\t)\n"); - fprintf(outfile,"\t\t\tport map (\n"); - fprintf(outfile,"\t\t\t\tclk => clk,\n"); - fprintf(outfile,"\t\t\t\treset => reset_vct_ix(i),\n"); - fprintf(outfile,"\t\t\t\tinc_en => incl(i),\n"); - fprintf(outfile,"\t\t\t\tindex_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n"); - fprintf(outfile,"\t\t\t\tindex_out => temp_index( ((i+1)*DW-1) downto (i*DW) )\n"); - fprintf(outfile,"\t\t\t);\n"); - fprintf(outfile,"\tend generate GEN_INC_IX;\n"); - fprintf(outfile,"\n"); - - /****************************************/ - /* GENERATE OUTPUT WRAPPING ASSIGNMENTS */ - /****************************************/ - - /* Iterate through all loops */ - for (i=1; i<=nlp; i++) - { - /* Generate assignment code */ - fprintf(outfile,"\tindex%d <= temp_index( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) );\n", i, i-1, i); - } - fprintf(outfile,"\n"); - - // - fprintf(outfile,"end structural;\n"); - -} - \ No newline at end of file Index: trunk/sw/gen_priority_encoder.c =================================================================== --- trunk/sw/gen_priority_encoder.c (revision 4) +++ trunk/sw/gen_priority_encoder.c (nonexistent) @@ -1,424 +0,0 @@ -/* Filename: gen_priority_encoder.c */ -/* Description: Generates priority_encoder module */ -/* Author: Nikos Kavvadias, */ -/* Date: Friday, 09/04/2004 */ - -#include -#include -#include - -#define PRINT_DEBUG - - -// FUNCTION PROTOTYPES -void write_file_priority_encoder(FILE *outfile); -unsigned dectobin(unsigned bin_data, int num_bits); -unsigned ipow(unsigned x, unsigned y); -unsigned log2(unsigned operand); -void print_binary_value(FILE *outfile, int i); -void print_binary_value_fbone(FILE *outfile, int i); - - -FILE *file_priority_encoder; /* VHDL source for the priority_encoder module of the - * hw_looping unit (priority_encoder.vhd) */ - -char priority_encoder_file_name[32]; -int nlp; -time_t t; - - -int main(int argc, char **argv) -{ - int i; - int gen_priority_encoder_file; - char nlp_s[3]; - - gen_priority_encoder_file = 0; - - if( argc < 3 ) - { - printf("Usage: gen_priority_encoder \n"); - printf("where:\n"); - printf("num loops = give number of supported loops\n"); - printf("output base = output file base name. The generated files will be named:\n"); - printf(" \".vhd\" for the module\n"); - // - printf("\n"); - // - return -1; - } - - // Acquire number of supported loops - strcpy(nlp_s,argv[1]); - nlp = atoi(nlp_s); - - // Filenames for the requested VHDL source files - sprintf(priority_encoder_file_name,"%s_loops%s%s", argv[2], nlp_s, ".vhd"); - gen_priority_encoder_file = 1; - - - // DEBUG OUTPUT - #ifdef PRINT_DEBUG - printf("\n"); - // - printf("nlp = %d\n",nlp); - printf("priority_encoder_file_name = %s\n", priority_encoder_file_name); - // - #endif - - - /******************************************************/ - /* Generate VHDL source for the priority_encoder unit */ - /******************************************************/ - if (gen_priority_encoder_file == 1) - { - file_priority_encoder = fopen(priority_encoder_file_name,"w"); - write_file_priority_encoder(file_priority_encoder); - fclose(file_priority_encoder); - } - - return 0; - -} - - -void write_file_priority_encoder( - FILE *outfile // Name for the output file -- e.g. mbloop_merger.vhd - ) -{ - int i; - - // Get current time - time(&t); - - /* Generate interface for the VHDL file */ - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Filename: %s ----\n", priority_encoder_file_name); - fprintf(outfile,"---- Module description: Priority encoder unit. Obtains ----\n"); - fprintf(outfile,"---- increment and reset decisions for the loop indices. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically ----\n"); - fprintf(outfile,"---- with the use of the \"gen_priority_encoder\" tool ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- To Do: ----\n"); - fprintf(outfile,"---- Considered stable for the time being ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- Copyright (C) 2004 Nikolaos Kavvadias ----\n"); - fprintf(outfile,"---- nick-kavi.8m.com ----\n"); - fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); - fprintf(outfile,"---- nick_ka_vi@hotmail.com ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source file may be used and distributed without ----\n"); - fprintf(outfile,"---- restriction provided that this copyright statement is not ----\n"); - fprintf(outfile,"---- removed from the file and that any derivative work contains ----\n"); - fprintf(outfile,"---- the original copyright notice and the associated disclaimer. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source file is free software; you can redistribute it ----\n"); - fprintf(outfile,"---- and/or modify it under the terms of the GNU Lesser General ----\n"); - fprintf(outfile,"---- Public License as published by the Free Software Foundation; ----\n"); - fprintf(outfile,"---- either version 2.1 of the License, or (at your option) any ----\n"); - fprintf(outfile,"---- later version. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- This source is distributed in the hope that it will be ----\n"); - fprintf(outfile,"---- useful, but WITHOUT ANY WARRANTY; without even the implied ----\n"); - fprintf(outfile,"---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----\n"); - fprintf(outfile,"---- PURPOSE. See the GNU Lesser General Public License for more ----\n"); - fprintf(outfile,"---- details. ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"---- You should have received a copy of the GNU Lesser General ----\n"); - fprintf(outfile,"---- Public License along with this source; if not, download it ----\n"); - fprintf(outfile,"---- from ----\n"); - fprintf(outfile,"---- ----\n"); - fprintf(outfile,"----==============================================================----\n"); - fprintf(outfile,"--\n"); - fprintf(outfile,"-- CVS Revision History\n"); - fprintf(outfile,"--\n"); - fprintf(outfile,"\n"); - - /* Code generation for library inclusions */ - fprintf(outfile,"library IEEE;\n"); - fprintf(outfile,"use IEEE.std_logic_1164.all;\n"); - fprintf(outfile,"use IEEE.std_logic_unsigned.all;\n"); - fprintf(outfile,"\n"); - - /* Generate entity declaration */ - fprintf(outfile,"entity priority_encoder is\n"); - fprintf(outfile,"\tgeneric (\n"); - fprintf(outfile,"\t\tNLP : integer := %d\n", nlp); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"\tport (\n"); - fprintf(outfile,"\t\tflag : in std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp); - fprintf(outfile,"\t\tincl : out std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\treset_vct : out std_logic_vector(NLP-1 downto 0);\n"); - fprintf(outfile,"\t\tloops_end : out std_logic\n"); - fprintf(outfile,"\t);\n"); - fprintf(outfile,"end priority_encoder;\n"); - fprintf(outfile,"\n"); - - /* Generate architecture declaration */ - fprintf(outfile,"architecture rtl of priority_encoder is\n"); - - /* Add component declarations here if needed */ - - /* Add signal declarations here if needed */ - - /* Continue with the rest of the architecture declaration */ - fprintf(outfile,"begin\n"); - fprintf(outfile,"\n"); - - fprintf(outfile,"\t-- Fully-nested loop structure with %d loops\n", nlp); - fprintf(outfile,"\t-- From outer to inner: "); - // - i = nlp-1; - fprintf(outfile,"%d", nlp-1); - // - if (nlp>=2) - { - for (i=nlp-2; i>=0; i--) - fprintf(outfile,"-> %d",i); - } - // - fprintf(outfile,"\n"); - - // Loop counter - i = nlp-1; - - /********************/ - /* GENERATE process */ - /********************/ - - fprintf(outfile,"\tprocess (flag, task_loop5_end)\n"); - fprintf(outfile,"\tbegin\n"); - fprintf(outfile,"\t\t--\n"); - fprintf(outfile,"\t\t-- if loop%d is terminating:\n", i); - fprintf(outfile,"\t\t-- reset loops %d-%d to initial index\n", i, 0); - // - fprintf(outfile,"\t\tif (flag(%d downto 0) = \"", i); - print_binary_value_fbone( outfile, ipow(2,i+1)-1 ); - fprintf(outfile,"\") then\n"); - // - fprintf(outfile,"\t\t\tincl <= \""); - print_binary_value( outfile, 0 ); - fprintf(outfile,"\";\n"); - // - fprintf(outfile,"\t\t\treset_vct <= \""); - print_binary_value( outfile, ipow(2,i+1)-1 ); - fprintf(outfile,"\";\n"); - // - fprintf(outfile,"\t\t\tloops_end <= '1';\n"); - - // Loop on all "elsif" cases: i=2 -> i=nlp - for (i=nlp-2; i>=0; i--) - { - fprintf(outfile,"\t\t-- else if loop%d is terminating:\n", i); - fprintf(outfile,"\t\t-- 1. increment loop%d index\n", i+1); - fprintf(outfile,"\t\t-- 2. reset loop%d to initial index\n", i); - // - fprintf(outfile,"\t\telsif (flag(%d downto 0) = \"", i); - print_binary_value_fbone( outfile, ipow(2,i+1)-1 ); - fprintf(outfile,"\") then\n"); - // - fprintf(outfile,"\t\t\tincl <= \""); - print_binary_value( outfile, ipow(2,i+1) ); - fprintf(outfile,"\";\n"); - // - fprintf(outfile,"\t\t\treset_vct <= \""); - print_binary_value( outfile, ipow(2,i+1)-1 ); - fprintf(outfile,"\";\n"); - // - fprintf(outfile,"\t\t\tloops_end <= '0';\n"); - } - - // Else increment inner loop - fprintf(outfile,"\t\t-- else increment loop%d index\n", i); - fprintf(outfile,"\t\telse\n"); - // - fprintf(outfile,"\t\t\treset_vct <= \""); - print_binary_value( outfile, 0 ); - fprintf(outfile,"\";\n"); - // - fprintf(outfile,"\t\t\tloops_end <= '0';\n"); - // - fprintf(outfile,"\t\t\tif (task_loop%d_end = '1') then\n", nlp); - fprintf(outfile,"\t\t\t\tincl <= \""); - print_binary_value( outfile, ipow(2,i+1) ); - fprintf(outfile,"\";\n"); - fprintf(outfile,"\t\t\telse\n"); - fprintf(outfile,"\t\t\t\tincl <= \""); - print_binary_value( outfile, 0 ); - fprintf(outfile,"\";\n"); - fprintf(outfile,"\t\t\tend if;\n"); - // - fprintf(outfile,"\t\tend if;\n"); - fprintf(outfile,"\tend process;\n"); - fprintf(outfile,"\n"); - // - fprintf(outfile,"end rtl;\n"); - -} - - -unsigned dectobin(unsigned bin_data, int num_bits) -{ - int count; - unsigned MASK; - unsigned result; - unsigned result_arr[100]; - - count = num_bits; - MASK = 1<<(count-1); - - result = 0; - - for (count=num_bits-1; count>-1; count--) - { - result_arr[count] = (( bin_data & MASK ) ? 1 : 0 ); - bin_data <<= 1; - } - - for (count=num_bits-1; count>-1; count--) - result = ipow(10,count)*result_arr[count] + result; - - return result; -} - - -unsigned ipow(unsigned x, unsigned y) -{ - unsigned i; - unsigned result; - - result = 1; - - for (i=1; i<=y; i++) - result = result*x; - - return result; -} - - -/* log2 function for integers: unsigned log2(unsigned operand) */ -unsigned log2(unsigned operand) -{ - unsigned temp; - unsigned log_val; - - temp = operand-1; - //temp = operand; - log_val = 0; - - while (temp > 0) - { - temp = temp/2; - log_val = log_val + 1; - } - - return log_val; -} - -void print_binary_value(FILE *outfile, int i) -{ - // Print integer value - switch (nlp) - { - case 1: - fprintf(outfile,"%d",dectobin( i, nlp )); - break; - case 2: - fprintf(outfile,"%02d",dectobin( i, nlp )); - break; - case 3: - fprintf(outfile,"%03d",dectobin( i, nlp )); - break; - case 4: - fprintf(outfile,"%04d",dectobin( i, nlp )); - break; - case 5: - fprintf(outfile,"%05d",dectobin( i, nlp )); - break; - case 6: - fprintf(outfile,"%06d",dectobin( i, nlp )); - break; - case 7: - fprintf(outfile,"%07d",dectobin( i, nlp )); - break; - case 8: - fprintf(outfile,"%08d",dectobin( i, nlp )); - break; - case 9: - fprintf(outfile,"%09d",dectobin( i, nlp )); - break; - case 10: - fprintf(outfile,"%10d",dectobin( i, nlp )); - break; - case 11: - fprintf(outfile,"%11d",dectobin( i, nlp )); - break; - case 12: - fprintf(outfile,"%12d",dectobin( i, nlp )); - break; - case 13: - fprintf(outfile,"%13d",dectobin( i, nlp )); - break; - case 14: - fprintf(outfile,"%14d",dectobin( i, nlp )); - break; - case 15: - fprintf(outfile,"%15d",dectobin( i, nlp )); - break; - case 16: - fprintf(outfile,"%16d",dectobin( i, nlp )); - break; - default: - break; - } -} - -// Print binary value -- First bit is "one". -void print_binary_value_fbone(FILE *outfile, int i) -{ - // Print integer value - switch ( log2(i) ) - { - // i = 1 - case 0: - fprintf(outfile,"%d",dectobin( i, i )); - break; - // i = 2:3 - case 1: - fprintf(outfile,"%d",dectobin( i, log2(i) )); - break; - // i = 4:7 - case 2: - fprintf(outfile,"%02d",dectobin( i, log2(i) )); - break; - // i = 8:15 - case 3: - fprintf(outfile,"%03d",dectobin( i, log2(i) )); - break; - // i = 16:31 - case 4: - fprintf(outfile,"%04d",dectobin( i, log2(i) )); - break; - // i = 32:63 - case 5: - fprintf(outfile,"%05d",dectobin( i, log2(i) )); - break; - default: - break; - } -} - - - \ No newline at end of file Index: trunk/syn/leonardo/bin/hwlu_5_csadder.scr =================================================================== --- trunk/syn/leonardo/bin/hwlu_5_csadder.scr (revision 4) +++ trunk/syn/leonardo/bin/hwlu_5_csadder.scr (nonexistent) @@ -1,45 +0,0 @@ -# Leonardo synthesis script -# Author: Nikolaos Kavvadias -# Details: -# Uses a carry-select implementation for the index incrementer -# This is the public release of the carry-select adder -# (not using tachnology-specific cells and optimizations) -# Only applicable for DW = 8 - -# Loading Target Technology -load_library tsmc018 - -# Setting operating conditions -set temp 80 -set process typical -set voltage 1.8 - -# Setting Design Rule Conditions -set max_fanout_load 16 -set max_cap_load 4 -set max_transition 0.0 - -# Set global timing constraints -set input2register 2.5 -set register2register 2.5 -set register2output 2.5 -set input2output 2.5 - -# Read complete design -read -technology "tsmc018" { ../../../rtl/vhdl/fa.vhd ../../../rtl/vhdl/mux2_1.vhd ../../../rtl/vhdl/csa8.vhd ../../../rtl/vhdl/reg_dw.vhd ../../../rtl/vhdl/cmpeq.vhd ../../../rtl/vhdl/index_inc.vhd ../../../rtl/vhdl/prenc_loops5.vhd ../../../rtl/vhdl/hw_loops5_top.vhd } -elaborate hw_looping -architecture structural -single_level -generic {DW=8 NLP=5} - -# Set timing constraints -clock_cycle 2.5 clk - -# Design optimizations -set asic_auto_dissolve_limit 600 -pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize -optimize .work.hw_looping.structural -target tsmc018 -macro -area -effort quick -hierarchy auto -report_area -cell_usage -all_leafs > hwlu_5_csadder_area.rpt -set report_delay_slack_threshold 0 -report_delay -num_paths 1 -critical_paths -clock_frequency > hwlu_5_csadder_delay.rpt - -#Save design -write hwlu_5_csadder.xdb -write -format VHDL hwlu_5_csadder_net.vhd Index: trunk/syn/leonardo/bin/hwlu_5_generic.scr =================================================================== --- trunk/syn/leonardo/bin/hwlu_5_generic.scr (revision 4) +++ trunk/syn/leonardo/bin/hwlu_5_generic.scr (nonexistent) @@ -1,43 +0,0 @@ -# Leonardo synthesis script -# Author: Nikolaos Kavvadias -# Details: -# Uses a generic adder implementation (determined by synthesis tool) -# Applicable for any DW - -# Loading Target Technology -load_library tsmc018 - -# Setting operating conditions -set temp 80 -set process typical -set voltage 1.8 - -# Setting Design Rule Conditions -set max_fanout_load 16 -set max_cap_load 4 -set max_transition 0.0 - -# Set global timing constraints -set input2register 2.5 -set register2register 2.5 -set register2output 2.5 -set input2output 2.5 - -# Read complete design -read -technology "tsmc018" { ../../../rtl/vhdl/add_dw.vhd ../../../rtl/vhdl/reg_dw.vhd ../../../rtl/vhdl/cmpeq.vhd ../../../rtl/vhdl/index_inc.vhd ../../../rtl/vhdl/prenc_loops5.vhd ../../../rtl/vhdl/hw_loops5_top.vhd } -elaborate hw_looping -architecture structural -single_level -generic {DW=8 NLP=5} - -# Set timing constraints -clock_cycle 2.5 clk - -# Design optimizations -set asic_auto_dissolve_limit 600 -pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize -optimize .work.hw_looping.structural -target tsmc018 -macro -area -effort quick -hierarchy auto -report_area -cell_usage -all_leafs > hwlu_5_generic_area.rpt -set report_delay_slack_threshold 0 -report_delay -num_paths 1 -critical_paths -clock_frequency > hwlu_5_generic_delay.rpt - -#Save design -write hwlu_5_generic.xdb -write -format VHDL hwlu_5_generic_net.vhd Index: trunk/bench/vhdl/hw_loops5_top_tb.vhd =================================================================== --- trunk/bench/vhdl/hw_loops5_top_tb.vhd (revision 4) +++ trunk/bench/vhdl/hw_loops5_top_tb.vhd (nonexistent) @@ -1,197 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: hw_loops5_top_tb.vhd ---- ----- Module description: Simple testbench for the "hw_loops5_top" ---- ----- top-level module ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- 1. Should be improved. A more thorough testbench is ---- ----- needed. ---- ----- 2. The testbench file for the top-level module will ---- ----- be generated by corresponding C tool. ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_arith.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_textio.all; -use STD.textio.all; - - -entity hwloop_top_tb is - generic ( - DW : integer := 8; - NLP : integer := 5 - ); -end hwloop_top_tb; - - -architecture tb_architecture of hwloop_top_tb is --- --- Component declaration of the DUT -component hw_looping is - generic ( - DW : integer := 8; - NLP : integer := 5 - ); - port ( - clk : in std_logic; - reset : in std_logic; - task_loop5_end : in std_logic; - loop1_count : in std_logic_vector(DW-1 downto 0); - loop2_count : in std_logic_vector(DW-1 downto 0); - loop3_count : in std_logic_vector(DW-1 downto 0); - loop4_count : in std_logic_vector(DW-1 downto 0); - loop5_count : in std_logic_vector(DW-1 downto 0); - index1 : out std_logic_vector(DW-1 downto 0); - index2 : out std_logic_vector(DW-1 downto 0); - index3 : out std_logic_vector(DW-1 downto 0); - index4 : out std_logic_vector(DW-1 downto 0); - index5 : out std_logic_vector(DW-1 downto 0); - loops_end : out std_logic - ); -end component; --- --- Signal declarations --- Stimulus signals - signals mapped to the I/IO ports of tested entity -signal clk : std_logic; -signal reset : std_logic; -signal task_loop5_end : std_logic; -signal loop1_count : std_logic_vector(DW-1 downto 0); -signal loop2_count : std_logic_vector(DW-1 downto 0); -signal loop3_count : std_logic_vector(DW-1 downto 0); -signal loop4_count : std_logic_vector(DW-1 downto 0); -signal loop5_count : std_logic_vector(DW-1 downto 0); --- Signals mapped to the output ports of tested entity -signal index1 : std_logic_vector(DW-1 downto 0); -signal index2 : std_logic_vector(DW-1 downto 0); -signal index3 : std_logic_vector(DW-1 downto 0); -signal index4 : std_logic_vector(DW-1 downto 0); -signal index5 : std_logic_vector(DW-1 downto 0); -signal loops_end : std_logic; --- --- Constant declarations -constant CLK_PERIOD : time := 10 ns; - -begin - - -- Unit Under Test port map - UUT : hw_looping - generic map ( - DW => DW, - NLP => NLP - ) - port map ( - clk => clk, - reset => reset, - task_loop5_end => task_loop5_end, - loop1_count => loop1_count, - loop2_count => loop2_count, - loop3_count => loop3_count, - loop4_count => loop4_count, - loop5_count => loop5_count, - index1 => index1, - index2 => index2, - index3 => index3, - index4 => index4, - index5 => index5, - loops_end => loops_end - ); - -CLK_GEN_PROC: process(clk) -begin - if (clk = 'U') then - clk <= '1'; - else - clk <= not clk after CLK_PERIOD/2; - end if; -end process CLK_GEN_PROC; - -DATA_STIM: process -begin - reset <= '0'; - task_loop5_end <= '0'; - loop1_count <= X"00"; - loop2_count <= X"00"; - loop3_count <= X"00"; - loop4_count <= X"00"; - loop5_count <= X"00"; - wait for CLK_PERIOD; - -- - reset <= '1'; - task_loop5_end <= '0'; - loop1_count <= X"00"; - loop2_count <= X"00"; - loop3_count <= X"00"; - loop4_count <= X"00"; - loop5_count <= X"00"; - wait for CLK_PERIOD; - -- - reset <= '0'; - task_loop5_end <= '1'; - loop1_count <= X"04"; - loop2_count <= X"06"; - loop3_count <= X"02"; - loop4_count <= X"04"; - loop5_count <= X"03"; - wait for CLK_PERIOD; - -- - -- Apply same inputs (written in some kind of - -- configuration memory) for large amount of time, - -- e.g. 1000 clock periods - wait for 1000*CLK_PERIOD; - -- -end process DATA_STIM; - -end tb_architecture; - - -configuration TESTBENCH_FOR_hw_looping of hwloop_top_tb is - for tb_architecture - for UUT : hw_looping - use entity work.hw_looping(structural); - end for; - end for; -end TESTBENCH_FOR_hw_looping; Index: trunk/rtl/vhdl/mux2_1.vhd =================================================================== --- trunk/rtl/vhdl/mux2_1.vhd (revision 4) +++ trunk/rtl/vhdl/mux2_1.vhd (nonexistent) @@ -1,79 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: mux2_1.vhd ---- ----- Module description: 2-to-1 DW-bit multiplexer ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - - -entity mux2_1 is - generic ( - DW : integer := 8 - ); - port ( - in0 : in std_logic_vector(DW-1 downto 0); - in1 : in std_logic_vector(DW-1 downto 0); - sel : in std_logic; - mout : out std_logic_vector(DW-1 downto 0) - ); -end mux2_1; - - -architecture rtl of mux2_1 is -begin - process (sel, in0, in1) - begin - case sel is - when '0' => mout <= in0; - when others => mout <= in1; - end case; - end process; - -- -end rtl; Index: trunk/rtl/vhdl/csa8.vhd =================================================================== --- trunk/rtl/vhdl/csa8.vhd (revision 4) +++ trunk/rtl/vhdl/csa8.vhd (nonexistent) @@ -1,155 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: csa8.vhd ---- ----- Module description: Top-level module of 8-bit carry-select ---- ----- adder ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Add a parameterized version of a fast adder ---- ----- (probably a carry select adder). ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - - -entity add is - generic ( - DW : integer := 8 - ); - port ( - a : in std_logic_vector(DW-1 downto 0); - b : in std_logic_vector(DW-1 downto 0); - sum : out std_logic_vector(DW-1 downto 0) - ); -end add; - -architecture structural of add is --- Component declarations -component fa - port ( - a : in std_logic; - b : in std_logic; - ci : in std_logic; - s : out std_logic; - co : out std_logic - ); -end component; --- -component mux2_1 - generic ( - DW : integer := 8 - ); - port ( - in0 : in std_logic_vector(DW-1 downto 0); - in1 : in std_logic_vector(DW-1 downto 0); - sel : in std_logic; - mout : out std_logic_vector(DW-1 downto 0) - ); -end component; --- --- Constant declarations -constant zero_1b : std_logic := '0'; -constant one_1b : std_logic := '1'; --- --- Signal declarations -signal carry : std_logic_vector(4 downto 0); -signal c_up_ci0 : std_logic_vector(4 downto 0); -signal c_up_ci1 : std_logic_vector(4 downto 0); -signal s_up_ci0 : std_logic_vector(3 downto 0); -signal s_up_ci1 : std_logic_vector(3 downto 0); --- -begin - - carry(0) <= '0'; - -- - - U_fa0_3_cells : for i in 0 to 3 generate - U_fa : fa - port map ( - a => a(i), - b => b(i), - ci => carry(i), - s => sum(i), - co => carry(i+1) - ); - end generate U_fa0_3_cells; - - c_up_ci0(0) <= zero_1b; - c_up_ci1(0) <= one_1b; - - U_fa4_7_ci0_cells : for i in 0 to 3 generate - U_fa : fa - port map ( - a => a(i+4), - b => b(i+4), - ci => c_up_ci0(i), - s => s_up_ci0(i), - co => c_up_ci0(i+1) - ); - end generate U_fa4_7_ci0_cells; - - U_fa4_7_ci1_cells : for i in 0 to 3 generate - U_fa : fa - port map ( - a => a(i+4), - b => b(i+4), - ci => c_up_ci1(i), - s => s_up_ci1(i), - co => c_up_ci1(i+1) - ); - end generate U_fa4_7_ci1_cells; - - U_mux_s_up : mux2_1 - generic map ( - DW => 4 - ) - port map ( - in0 => s_up_ci0(3 downto 0), - in1 => s_up_ci1(3 downto 0), - sel => carry(4), - mout => sum(7 downto 4) - ); - -end structural; Index: trunk/rtl/vhdl/index_inc.vhd =================================================================== --- trunk/rtl/vhdl/index_inc.vhd (revision 4) +++ trunk/rtl/vhdl/index_inc.vhd (nonexistent) @@ -1,131 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: index_inc.vhd ---- ----- Module description: Index increment-by-one unit ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -use IEEE.std_logic_arith.all; - - -entity index_inc is - generic ( - DW : integer := 8 - ); - port ( - clk : in std_logic; - reset : in std_logic; - inc_en : in std_logic; - index_plus_one : out std_logic_vector(Dw-1 downto 0); - index_out : out std_logic_vector(DW-1 downto 0) - ); -end index_inc; - -architecture rtl of index_inc is --- --- Component declarations -component add - generic ( - DW : integer := 8 - ); - port ( - a : in std_logic_vector(DW-1 downto 0); - b : in std_logic_vector(DW-1 downto 0); - sum : out std_logic_vector(DW-1 downto 0) - ); -end component; --- -component reg_dw - generic ( - DW : integer := 8 - ); - port ( - clk : in std_logic; - reset : in std_logic; - load : in std_logic; - d : in std_logic_vector(DW-1 downto 0); - q : out std_logic_vector(DW-1 downto 0) - ); -end component; --- --- Constant declarations -constant one_dw : std_logic_vector(DW-1 downto 0) := conv_std_logic_vector(1,DW); --- --- Signal declarations -signal index_rin, index_r : std_logic_vector(DW-1 downto 0); --- -begin - - U_adder : add - generic map ( - DW => DW - ) - port map ( - a => index_r, - b => one_dw, - sum => index_rin - ); - - U_reg_dw : reg_dw - generic map ( - DW => DW - ) - port map ( - clk => clk, - reset => reset, - load => inc_en, - d => index_rin, - q => index_r - ); - - index_out <= index_r; - index_plus_one <= index_rin; - -end rtl; Index: trunk/rtl/vhdl/hw_loops5_top.vhd =================================================================== --- trunk/rtl/vhdl/hw_loops5_top.vhd (revision 4) +++ trunk/rtl/vhdl/hw_loops5_top.vhd (nonexistent) @@ -1,187 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: hw_loops5_top.vhd ---- ----- Module description: Top-level file for the hw_looping unit. ---- ----- Also implements input and output ---- ----- wrapping operations. ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Part of the hwlu OPENCORES project generated automatically ---- ----- with the use of the "gen_hw_looping" tool ---- ----- ---- ----- To Do: ---- ----- Considered stable for the time being ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - -entity hw_looping is - generic ( - DW : integer := 8; - NLP : integer := 5 - ); - port ( - clk : in std_logic; - reset : in std_logic; - task_loop5_end : in std_logic; - loop1_count : in std_logic_vector(DW-1 downto 0); - loop2_count : in std_logic_vector(DW-1 downto 0); - loop3_count : in std_logic_vector(DW-1 downto 0); - loop4_count : in std_logic_vector(DW-1 downto 0); - loop5_count : in std_logic_vector(DW-1 downto 0); - index1 : out std_logic_vector(DW-1 downto 0); - index2 : out std_logic_vector(DW-1 downto 0); - index3 : out std_logic_vector(DW-1 downto 0); - index4 : out std_logic_vector(DW-1 downto 0); - index5 : out std_logic_vector(DW-1 downto 0); - loops_end : out std_logic - ); -end hw_looping; - -architecture structural of hw_looping is --- --- Component declarations -component cmpeq - generic ( - DW : integer := 8 - ); - port ( - a : in std_logic_vector(DW-1 downto 0); - b : in std_logic_vector(DW-1 downto 0); - reset : in std_logic; - a_eq_b : out std_logic - ); -end component; --- -component index_inc - generic ( - DW : integer := 8 - ); - port ( - clk : in std_logic; - reset : in std_logic; - inc_en : in std_logic; - index_plus_one : out std_logic_vector(DW-1 downto 0); - index_out : out std_logic_vector(DW-1 downto 0) - ); -end component; --- -component priority_encoder - generic ( - NLP : integer := 5 - ); - port ( - flag : in std_logic_vector(NLP-1 downto 0); - task_loop5_end : in std_logic; - incl : out std_logic_vector(NLP-1 downto 0); - reset_vct : out std_logic_vector(NLP-1 downto 0); - loops_end : out std_logic - ); -end component; --- --- Signal declarations -signal flag : std_logic_vector(NLP-1 downto 0); -signal incl : std_logic_vector(NLP-1 downto 0); -signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0); -signal temp_index : std_logic_vector(NLP*DW-1 downto 0); -signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0); -signal reset_vct_penc : std_logic_vector(NLP-1 downto 0); -signal reset_vct_ix : std_logic_vector(NLP-1 downto 0); --- -begin - - temp_loop_count( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ) <= loop1_count; - temp_loop_count( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ) <= loop2_count; - temp_loop_count( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ) <= loop3_count; - temp_loop_count( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ) <= loop4_count; - temp_loop_count( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ) <= loop5_count; - - GEN_COMPARATORS: for i in 0 to NLP-1 generate - U_cmp : cmpeq - generic map ( - DW => DW - ) - port map ( - a => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ), - b => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ), - reset => reset, - a_eq_b => flag(i) - ); - end generate GEN_COMPARATORS; - - U_priority_enc : priority_encoder - generic map ( - NLP => NLP - ) - port map ( - flag => flag, - task_loop5_end => task_loop5_end, - incl => incl, - reset_vct => reset_vct_penc, - loops_end => loops_end - ); - - GEN_RESET_SEL: for i in 0 to NLP-1 generate - reset_vct_ix(i) <= reset_vct_penc(i) or reset; - end generate GEN_RESET_SEL; - - GEN_INC_IX: for i in 0 to NLP-1 generate - U_inc_ix1 : index_inc - generic map ( - DW => DW - ) - port map ( - clk => clk, - reset => reset_vct_ix(i), - inc_en => incl(i), - index_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ), - index_out => temp_index( ((i+1)*DW-1) downto (i*DW) ) - ); - end generate GEN_INC_IX; - - index1 <= temp_index( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ); - index2 <= temp_index( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ); - index3 <= temp_index( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ); - index4 <= temp_index( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ); - index5 <= temp_index( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ); - -end structural; Index: trunk/rtl/vhdl/add_dw.vhd =================================================================== --- trunk/rtl/vhdl/add_dw.vhd (revision 4) +++ trunk/rtl/vhdl/add_dw.vhd (nonexistent) @@ -1,78 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: add_dw.vhd ---- ----- Module description: Generic DW-bit binary adder ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - - -entity add is - generic ( - DW : integer := 8 - ); - port ( - a : in std_logic_vector(DW-1 downto 0); - b : in std_logic_vector(DW-1 downto 0); - sum : out std_logic_vector(DW-1 downto 0) - ); -end add; - - -architecture structural of add is -signal temp_sum : std_logic_vector(DW downto 0); -begin - -- - temp_sum <= (a(DW-1) & a) + (b(DW-1) & b); - sum <= temp_sum(DW-1 downto 0); - -- -end structural; - - Index: trunk/rtl/vhdl/cmpeq.vhd =================================================================== --- trunk/rtl/vhdl/cmpeq.vhd (revision 4) +++ trunk/rtl/vhdl/cmpeq.vhd (nonexistent) @@ -1,73 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: cmpeq.vhd ---- ----- Module description: Equality comparator ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - - -entity cmpeq is - generic ( - DW : integer := 8 - ); - port ( - a : in std_logic_vector(DW-1 downto 0); - b : in std_logic_vector(DW-1 downto 0); - reset : in std_logic; - a_eq_b : out std_logic - ); -end cmpeq; - -architecture rtl of cmpeq is -begin - -- - a_eq_b <= '1' when (a = b and reset = '0') else '0'; - -- -end rtl; Index: trunk/rtl/vhdl/fa.vhd =================================================================== --- trunk/rtl/vhdl/fa.vhd (revision 4) +++ trunk/rtl/vhdl/fa.vhd (nonexistent) @@ -1,73 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: fa.vhd ---- ----- Module description: Full-adder module ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - - -entity fa is - port ( - a : in std_logic; - b : in std_logic; - ci : in std_logic; - s : out std_logic; - co : out std_logic - ); -end fa; - - -architecture structural of fa is -begin - -- - s <= a xor b xor ci; - co <= ((a xor b) and ci) or (a and b); - -- -end structural; Index: trunk/rtl/vhdl/reg_dw.vhd =================================================================== --- trunk/rtl/vhdl/reg_dw.vhd (revision 4) +++ trunk/rtl/vhdl/reg_dw.vhd (nonexistent) @@ -1,85 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: reg_dw.vhd ---- ----- Module description: DW-bit D-type register with synchronous ---- ----- reset and load enable ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- ----- ---- ----- To Do: ---- ----- Probably remains as current ---- ----- (to promote as stable version) ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; - - -entity reg_dw is - generic ( - DW : integer := 8 - ); - port ( - clk : in std_logic; - reset : in std_logic; - load : in std_logic; - d : in std_logic_vector(DW-1 downto 0); - q : out std_logic_vector(DW-1 downto 0) - ); -end reg_dw; - - -architecture rtl of reg_dw is -begin - process (clk, reset, load, d) - begin - if (clk'event and clk = '1') then - -- synchronous reset - if (reset = '1') then - q <= (others => '0'); - elsif (load = '1') then - q <= d; - end if; -- reset, load - end if; -- clk - end process; - -- -end rtl; Index: trunk/rtl/vhdl/prenc_loops5.vhd =================================================================== --- trunk/rtl/vhdl/prenc_loops5.vhd (revision 4) +++ trunk/rtl/vhdl/prenc_loops5.vhd (nonexistent) @@ -1,124 +0,0 @@ -----==============================================================---- ----- ---- ----- Filename: prenc_loops5.vhd ---- ----- Module description: Priority encoder unit. Obtains ---- ----- increment and reset decisions for the loop indices. ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- ----- ---- ----- Part of the hwlu OPENCORES project generated automatically ---- ----- with the use of the "gen_priority_encoder" tool ---- ----- ---- ----- To Do: ---- ----- Considered stable for the time being ---- ----- ---- ----- Author: Nikolaos Kavvadias ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- ---- -----==============================================================---- ----- ---- ----- Copyright (C) 2004 Nikolaos Kavvadias ---- ----- nick-kavi.8m.com ---- ----- nkavv@skiathos.physics.auth.gr ---- ----- nick_ka_vi@hotmail.com ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from ---- ----- ---- -----==============================================================---- --- --- CVS Revision History --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity priority_encoder is - generic ( - NLP : integer := 5 - ); - port ( - flag : in std_logic_vector(NLP-1 downto 0); - task_loop5_end : in std_logic; - incl : out std_logic_vector(NLP-1 downto 0); - reset_vct : out std_logic_vector(NLP-1 downto 0); - loops_end : out std_logic - ); -end priority_encoder; - -architecture rtl of priority_encoder is -begin - - -- Fully-nested loop structure with 5 loops - -- From outer to inner: 4-> 3-> 2-> 1-> 0 - process (flag, task_loop5_end) - begin - -- - -- if loop4 is terminating: - -- reset loops 4-0 to initial index - if (flag(4 downto 0) = "11111") then - incl <= "00000"; - reset_vct <= "11111"; - loops_end <= '1'; - -- else if loop3 is terminating: - -- 1. increment loop4 index - -- 2. reset loop3 to initial index - elsif (flag(3 downto 0) = "1111") then - incl <= "10000"; - reset_vct <= "01111"; - loops_end <= '0'; - -- else if loop2 is terminating: - -- 1. increment loop3 index - -- 2. reset loop2 to initial index - elsif (flag(2 downto 0) = "111") then - incl <= "01000"; - reset_vct <= "00111"; - loops_end <= '0'; - -- else if loop1 is terminating: - -- 1. increment loop2 index - -- 2. reset loop1 to initial index - elsif (flag(1 downto 0) = "11") then - incl <= "00100"; - reset_vct <= "00011"; - loops_end <= '0'; - -- else if loop0 is terminating: - -- 1. increment loop1 index - -- 2. reset loop0 to initial index - elsif (flag(0 downto 0) = "1") then - incl <= "00010"; - reset_vct <= "00001"; - loops_end <= '0'; - -- else increment loop-1 index - else - reset_vct <= "00000"; - loops_end <= '0'; - if (task_loop5_end = '1') then - incl <= "00001"; - else - incl <= "00000"; - end if; - end if; - end process; - -end rtl; Index: hwlu/trunk/rtl/vhdl/csa8.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/csa8.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/csa8.vhd (revision 5) @@ -0,0 +1,155 @@ +----==============================================================---- +---- ---- +---- Filename: csa8.vhd ---- +---- Module description: Top-level module of 8-bit carry-select ---- +---- adder ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Add a parameterized version of a fast adder ---- +---- (probably a carry select adder). ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity add is + generic ( + DW : integer := 8 + ); + port ( + a : in std_logic_vector(DW-1 downto 0); + b : in std_logic_vector(DW-1 downto 0); + sum : out std_logic_vector(DW-1 downto 0) + ); +end add; + +architecture structural of add is +-- Component declarations +component fa + port ( + a : in std_logic; + b : in std_logic; + ci : in std_logic; + s : out std_logic; + co : out std_logic + ); +end component; +-- +component mux2_1 + generic ( + DW : integer := 8 + ); + port ( + in0 : in std_logic_vector(DW-1 downto 0); + in1 : in std_logic_vector(DW-1 downto 0); + sel : in std_logic; + mout : out std_logic_vector(DW-1 downto 0) + ); +end component; +-- +-- Constant declarations +constant zero_1b : std_logic := '0'; +constant one_1b : std_logic := '1'; +-- +-- Signal declarations +signal carry : std_logic_vector(4 downto 0); +signal c_up_ci0 : std_logic_vector(4 downto 0); +signal c_up_ci1 : std_logic_vector(4 downto 0); +signal s_up_ci0 : std_logic_vector(3 downto 0); +signal s_up_ci1 : std_logic_vector(3 downto 0); +-- +begin + + carry(0) <= '0'; + -- + + U_fa0_3_cells : for i in 0 to 3 generate + U_fa : fa + port map ( + a => a(i), + b => b(i), + ci => carry(i), + s => sum(i), + co => carry(i+1) + ); + end generate U_fa0_3_cells; + + c_up_ci0(0) <= zero_1b; + c_up_ci1(0) <= one_1b; + + U_fa4_7_ci0_cells : for i in 0 to 3 generate + U_fa : fa + port map ( + a => a(i+4), + b => b(i+4), + ci => c_up_ci0(i), + s => s_up_ci0(i), + co => c_up_ci0(i+1) + ); + end generate U_fa4_7_ci0_cells; + + U_fa4_7_ci1_cells : for i in 0 to 3 generate + U_fa : fa + port map ( + a => a(i+4), + b => b(i+4), + ci => c_up_ci1(i), + s => s_up_ci1(i), + co => c_up_ci1(i+1) + ); + end generate U_fa4_7_ci1_cells; + + U_mux_s_up : mux2_1 + generic map ( + DW => 4 + ) + port map ( + in0 => s_up_ci0(3 downto 0), + in1 => s_up_ci1(3 downto 0), + sel => carry(4), + mout => sum(7 downto 4) + ); + +end structural; Index: hwlu/trunk/rtl/vhdl/index_inc.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/index_inc.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/index_inc.vhd (revision 5) @@ -0,0 +1,131 @@ +----==============================================================---- +---- ---- +---- Filename: index_inc.vhd ---- +---- Module description: Index increment-by-one unit ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; + + +entity index_inc is + generic ( + DW : integer := 8 + ); + port ( + clk : in std_logic; + reset : in std_logic; + inc_en : in std_logic; + index_plus_one : out std_logic_vector(Dw-1 downto 0); + index_out : out std_logic_vector(DW-1 downto 0) + ); +end index_inc; + +architecture rtl of index_inc is +-- +-- Component declarations +component add + generic ( + DW : integer := 8 + ); + port ( + a : in std_logic_vector(DW-1 downto 0); + b : in std_logic_vector(DW-1 downto 0); + sum : out std_logic_vector(DW-1 downto 0) + ); +end component; +-- +component reg_dw + generic ( + DW : integer := 8 + ); + port ( + clk : in std_logic; + reset : in std_logic; + load : in std_logic; + d : in std_logic_vector(DW-1 downto 0); + q : out std_logic_vector(DW-1 downto 0) + ); +end component; +-- +-- Constant declarations +constant one_dw : std_logic_vector(DW-1 downto 0) := conv_std_logic_vector(1,DW); +-- +-- Signal declarations +signal index_rin, index_r : std_logic_vector(DW-1 downto 0); +-- +begin + + U_adder : add + generic map ( + DW => DW + ) + port map ( + a => index_r, + b => one_dw, + sum => index_rin + ); + + U_reg_dw : reg_dw + generic map ( + DW => DW + ) + port map ( + clk => clk, + reset => reset, + load => inc_en, + d => index_rin, + q => index_r + ); + + index_out <= index_r; + index_plus_one <= index_rin; + +end rtl; Index: hwlu/trunk/rtl/vhdl/hw_loops5_top.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/hw_loops5_top.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/hw_loops5_top.vhd (revision 5) @@ -0,0 +1,187 @@ +----==============================================================---- +---- ---- +---- Filename: hw_loops5_top.vhd ---- +---- Module description: Top-level file for the hw_looping unit. ---- +---- Also implements input and output ---- +---- wrapping operations. ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Part of the hwlu OPENCORES project generated automatically ---- +---- with the use of the "gen_hw_looping" tool ---- +---- ---- +---- To Do: ---- +---- Considered stable for the time being ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +entity hw_looping is + generic ( + DW : integer := 8; + NLP : integer := 5 + ); + port ( + clk : in std_logic; + reset : in std_logic; + task_loop5_end : in std_logic; + loop1_count : in std_logic_vector(DW-1 downto 0); + loop2_count : in std_logic_vector(DW-1 downto 0); + loop3_count : in std_logic_vector(DW-1 downto 0); + loop4_count : in std_logic_vector(DW-1 downto 0); + loop5_count : in std_logic_vector(DW-1 downto 0); + index1 : out std_logic_vector(DW-1 downto 0); + index2 : out std_logic_vector(DW-1 downto 0); + index3 : out std_logic_vector(DW-1 downto 0); + index4 : out std_logic_vector(DW-1 downto 0); + index5 : out std_logic_vector(DW-1 downto 0); + loops_end : out std_logic + ); +end hw_looping; + +architecture structural of hw_looping is +-- +-- Component declarations +component cmpeq + generic ( + DW : integer := 8 + ); + port ( + a : in std_logic_vector(DW-1 downto 0); + b : in std_logic_vector(DW-1 downto 0); + reset : in std_logic; + a_eq_b : out std_logic + ); +end component; +-- +component index_inc + generic ( + DW : integer := 8 + ); + port ( + clk : in std_logic; + reset : in std_logic; + inc_en : in std_logic; + index_plus_one : out std_logic_vector(DW-1 downto 0); + index_out : out std_logic_vector(DW-1 downto 0) + ); +end component; +-- +component priority_encoder + generic ( + NLP : integer := 5 + ); + port ( + flag : in std_logic_vector(NLP-1 downto 0); + task_loop5_end : in std_logic; + incl : out std_logic_vector(NLP-1 downto 0); + reset_vct : out std_logic_vector(NLP-1 downto 0); + loops_end : out std_logic + ); +end component; +-- +-- Signal declarations +signal flag : std_logic_vector(NLP-1 downto 0); +signal incl : std_logic_vector(NLP-1 downto 0); +signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0); +signal temp_index : std_logic_vector(NLP*DW-1 downto 0); +signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0); +signal reset_vct_penc : std_logic_vector(NLP-1 downto 0); +signal reset_vct_ix : std_logic_vector(NLP-1 downto 0); +-- +begin + + temp_loop_count( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ) <= loop1_count; + temp_loop_count( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ) <= loop2_count; + temp_loop_count( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ) <= loop3_count; + temp_loop_count( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ) <= loop4_count; + temp_loop_count( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ) <= loop5_count; + + GEN_COMPARATORS: for i in 0 to NLP-1 generate + U_cmp : cmpeq + generic map ( + DW => DW + ) + port map ( + a => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ), + b => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ), + reset => reset, + a_eq_b => flag(i) + ); + end generate GEN_COMPARATORS; + + U_priority_enc : priority_encoder + generic map ( + NLP => NLP + ) + port map ( + flag => flag, + task_loop5_end => task_loop5_end, + incl => incl, + reset_vct => reset_vct_penc, + loops_end => loops_end + ); + + GEN_RESET_SEL: for i in 0 to NLP-1 generate + reset_vct_ix(i) <= reset_vct_penc(i) or reset; + end generate GEN_RESET_SEL; + + GEN_INC_IX: for i in 0 to NLP-1 generate + U_inc_ix1 : index_inc + generic map ( + DW => DW + ) + port map ( + clk => clk, + reset => reset_vct_ix(i), + inc_en => incl(i), + index_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ), + index_out => temp_index( ((i+1)*DW-1) downto (i*DW) ) + ); + end generate GEN_INC_IX; + + index1 <= temp_index( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ); + index2 <= temp_index( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ); + index3 <= temp_index( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ); + index4 <= temp_index( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ); + index5 <= temp_index( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ); + +end structural; Index: hwlu/trunk/rtl/vhdl/add_dw.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/add_dw.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/add_dw.vhd (revision 5) @@ -0,0 +1,78 @@ +----==============================================================---- +---- ---- +---- Filename: add_dw.vhd ---- +---- Module description: Generic DW-bit binary adder ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + + +entity add is + generic ( + DW : integer := 8 + ); + port ( + a : in std_logic_vector(DW-1 downto 0); + b : in std_logic_vector(DW-1 downto 0); + sum : out std_logic_vector(DW-1 downto 0) + ); +end add; + + +architecture structural of add is +signal temp_sum : std_logic_vector(DW downto 0); +begin + -- + temp_sum <= (a(DW-1) & a) + (b(DW-1) & b); + sum <= temp_sum(DW-1 downto 0); + -- +end structural; + + Index: hwlu/trunk/rtl/vhdl/cmpeq.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/cmpeq.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/cmpeq.vhd (revision 5) @@ -0,0 +1,73 @@ +----==============================================================---- +---- ---- +---- Filename: cmpeq.vhd ---- +---- Module description: Equality comparator ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cmpeq is + generic ( + DW : integer := 8 + ); + port ( + a : in std_logic_vector(DW-1 downto 0); + b : in std_logic_vector(DW-1 downto 0); + reset : in std_logic; + a_eq_b : out std_logic + ); +end cmpeq; + +architecture rtl of cmpeq is +begin + -- + a_eq_b <= '1' when (a = b and reset = '0') else '0'; + -- +end rtl; Index: hwlu/trunk/rtl/vhdl/fa.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/fa.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/fa.vhd (revision 5) @@ -0,0 +1,73 @@ +----==============================================================---- +---- ---- +---- Filename: fa.vhd ---- +---- Module description: Full-adder module ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity fa is + port ( + a : in std_logic; + b : in std_logic; + ci : in std_logic; + s : out std_logic; + co : out std_logic + ); +end fa; + + +architecture structural of fa is +begin + -- + s <= a xor b xor ci; + co <= ((a xor b) and ci) or (a and b); + -- +end structural; Index: hwlu/trunk/rtl/vhdl/reg_dw.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/reg_dw.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/reg_dw.vhd (revision 5) @@ -0,0 +1,85 @@ +----==============================================================---- +---- ---- +---- Filename: reg_dw.vhd ---- +---- Module description: DW-bit D-type register with synchronous ---- +---- reset and load enable ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity reg_dw is + generic ( + DW : integer := 8 + ); + port ( + clk : in std_logic; + reset : in std_logic; + load : in std_logic; + d : in std_logic_vector(DW-1 downto 0); + q : out std_logic_vector(DW-1 downto 0) + ); +end reg_dw; + + +architecture rtl of reg_dw is +begin + process (clk, reset, load, d) + begin + if (clk'event and clk = '1') then + -- synchronous reset + if (reset = '1') then + q <= (others => '0'); + elsif (load = '1') then + q <= d; + end if; -- reset, load + end if; -- clk + end process; + -- +end rtl; Index: hwlu/trunk/rtl/vhdl/prenc_loops5.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/prenc_loops5.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/prenc_loops5.vhd (revision 5) @@ -0,0 +1,124 @@ +----==============================================================---- +---- ---- +---- Filename: prenc_loops5.vhd ---- +---- Module description: Priority encoder unit. Obtains ---- +---- increment and reset decisions for the loop indices. ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Part of the hwlu OPENCORES project generated automatically ---- +---- with the use of the "gen_priority_encoder" tool ---- +---- ---- +---- To Do: ---- +---- Considered stable for the time being ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity priority_encoder is + generic ( + NLP : integer := 5 + ); + port ( + flag : in std_logic_vector(NLP-1 downto 0); + task_loop5_end : in std_logic; + incl : out std_logic_vector(NLP-1 downto 0); + reset_vct : out std_logic_vector(NLP-1 downto 0); + loops_end : out std_logic + ); +end priority_encoder; + +architecture rtl of priority_encoder is +begin + + -- Fully-nested loop structure with 5 loops + -- From outer to inner: 4-> 3-> 2-> 1-> 0 + process (flag, task_loop5_end) + begin + -- + -- if loop4 is terminating: + -- reset loops 4-0 to initial index + if (flag(4 downto 0) = "11111") then + incl <= "00000"; + reset_vct <= "11111"; + loops_end <= '1'; + -- else if loop3 is terminating: + -- 1. increment loop4 index + -- 2. reset loop3 to initial index + elsif (flag(3 downto 0) = "1111") then + incl <= "10000"; + reset_vct <= "01111"; + loops_end <= '0'; + -- else if loop2 is terminating: + -- 1. increment loop3 index + -- 2. reset loop2 to initial index + elsif (flag(2 downto 0) = "111") then + incl <= "01000"; + reset_vct <= "00111"; + loops_end <= '0'; + -- else if loop1 is terminating: + -- 1. increment loop2 index + -- 2. reset loop1 to initial index + elsif (flag(1 downto 0) = "11") then + incl <= "00100"; + reset_vct <= "00011"; + loops_end <= '0'; + -- else if loop0 is terminating: + -- 1. increment loop1 index + -- 2. reset loop0 to initial index + elsif (flag(0 downto 0) = "1") then + incl <= "00010"; + reset_vct <= "00001"; + loops_end <= '0'; + -- else increment loop-1 index + else + reset_vct <= "00000"; + loops_end <= '0'; + if (task_loop5_end = '1') then + incl <= "00001"; + else + incl <= "00000"; + end if; + end if; + end process; + +end rtl; Index: hwlu/trunk/rtl/vhdl/mux2_1.vhd =================================================================== --- hwlu/trunk/rtl/vhdl/mux2_1.vhd (nonexistent) +++ hwlu/trunk/rtl/vhdl/mux2_1.vhd (revision 5) @@ -0,0 +1,79 @@ +----==============================================================---- +---- ---- +---- Filename: mux2_1.vhd ---- +---- Module description: 2-to-1 DW-bit multiplexer ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- Probably remains as current ---- +---- (to promote as stable version) ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity mux2_1 is + generic ( + DW : integer := 8 + ); + port ( + in0 : in std_logic_vector(DW-1 downto 0); + in1 : in std_logic_vector(DW-1 downto 0); + sel : in std_logic; + mout : out std_logic_vector(DW-1 downto 0) + ); +end mux2_1; + + +architecture rtl of mux2_1 is +begin + process (sel, in0, in1) + begin + case sel is + when '0' => mout <= in0; + when others => mout <= in1; + end case; + end process; + -- +end rtl; Index: hwlu/trunk/syn/leonardo/bin/hwlu_5_generic.scr =================================================================== --- hwlu/trunk/syn/leonardo/bin/hwlu_5_generic.scr (nonexistent) +++ hwlu/trunk/syn/leonardo/bin/hwlu_5_generic.scr (revision 5) @@ -0,0 +1,43 @@ +# Leonardo synthesis script +# Author: Nikolaos Kavvadias +# Details: +# Uses a generic adder implementation (determined by synthesis tool) +# Applicable for any DW + +# Loading Target Technology +load_library tsmc018 + +# Setting operating conditions +set temp 80 +set process typical +set voltage 1.8 + +# Setting Design Rule Conditions +set max_fanout_load 16 +set max_cap_load 4 +set max_transition 0.0 + +# Set global timing constraints +set input2register 2.5 +set register2register 2.5 +set register2output 2.5 +set input2output 2.5 + +# Read complete design +read -technology "tsmc018" { ../../../rtl/vhdl/add_dw.vhd ../../../rtl/vhdl/reg_dw.vhd ../../../rtl/vhdl/cmpeq.vhd ../../../rtl/vhdl/index_inc.vhd ../../../rtl/vhdl/prenc_loops5.vhd ../../../rtl/vhdl/hw_loops5_top.vhd } +elaborate hw_looping -architecture structural -single_level -generic {DW=8 NLP=5} + +# Set timing constraints +clock_cycle 2.5 clk + +# Design optimizations +set asic_auto_dissolve_limit 600 +pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize +optimize .work.hw_looping.structural -target tsmc018 -macro -area -effort quick -hierarchy auto +report_area -cell_usage -all_leafs > hwlu_5_generic_area.rpt +set report_delay_slack_threshold 0 +report_delay -num_paths 1 -critical_paths -clock_frequency > hwlu_5_generic_delay.rpt + +#Save design +write hwlu_5_generic.xdb +write -format VHDL hwlu_5_generic_net.vhd Index: hwlu/trunk/syn/leonardo/bin/hwlu_5_csadder.scr =================================================================== --- hwlu/trunk/syn/leonardo/bin/hwlu_5_csadder.scr (nonexistent) +++ hwlu/trunk/syn/leonardo/bin/hwlu_5_csadder.scr (revision 5) @@ -0,0 +1,45 @@ +# Leonardo synthesis script +# Author: Nikolaos Kavvadias +# Details: +# Uses a carry-select implementation for the index incrementer +# This is the public release of the carry-select adder +# (not using tachnology-specific cells and optimizations) +# Only applicable for DW = 8 + +# Loading Target Technology +load_library tsmc018 + +# Setting operating conditions +set temp 80 +set process typical +set voltage 1.8 + +# Setting Design Rule Conditions +set max_fanout_load 16 +set max_cap_load 4 +set max_transition 0.0 + +# Set global timing constraints +set input2register 2.5 +set register2register 2.5 +set register2output 2.5 +set input2output 2.5 + +# Read complete design +read -technology "tsmc018" { ../../../rtl/vhdl/fa.vhd ../../../rtl/vhdl/mux2_1.vhd ../../../rtl/vhdl/csa8.vhd ../../../rtl/vhdl/reg_dw.vhd ../../../rtl/vhdl/cmpeq.vhd ../../../rtl/vhdl/index_inc.vhd ../../../rtl/vhdl/prenc_loops5.vhd ../../../rtl/vhdl/hw_loops5_top.vhd } +elaborate hw_looping -architecture structural -single_level -generic {DW=8 NLP=5} + +# Set timing constraints +clock_cycle 2.5 clk + +# Design optimizations +set asic_auto_dissolve_limit 600 +pre_optimize -common_logic -unused_logic -boundary -xor_comparator_optimize +optimize .work.hw_looping.structural -target tsmc018 -macro -area -effort quick -hierarchy auto +report_area -cell_usage -all_leafs > hwlu_5_csadder_area.rpt +set report_delay_slack_threshold 0 +report_delay -num_paths 1 -critical_paths -clock_frequency > hwlu_5_csadder_delay.rpt + +#Save design +write hwlu_5_csadder.xdb +write -format VHDL hwlu_5_csadder_net.vhd Index: hwlu/trunk/bench/vhdl/hw_loops5_top_tb.vhd =================================================================== --- hwlu/trunk/bench/vhdl/hw_loops5_top_tb.vhd (nonexistent) +++ hwlu/trunk/bench/vhdl/hw_loops5_top_tb.vhd (revision 5) @@ -0,0 +1,197 @@ +----==============================================================---- +---- ---- +---- Filename: hw_loops5_top_tb.vhd ---- +---- Module description: Simple testbench for the "hw_loops5_top" ---- +---- top-level module ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +---- ---- +---- Downloaded from: http://wwww.opencores.org/cores/hwlu ---- +---- ---- +---- To Do: ---- +---- 1. Should be improved. A more thorough testbench is ---- +---- needed. ---- +---- 2. The testbench file for the top-level module will ---- +---- be generated by corresponding C tool. ---- +---- ---- +---- Author: Nikolaos Kavvadias ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- ---- +----==============================================================---- +---- ---- +---- Copyright (C) 2004 Nikolaos Kavvadias ---- +---- nick-kavi.8m.com ---- +---- nkavv@skiathos.physics.auth.gr ---- +---- nick_ka_vi@hotmail.com ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from ---- +---- ---- +----==============================================================---- +-- +-- CVS Revision History +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use IEEE.std_logic_textio.all; +use STD.textio.all; + + +entity hwloop_top_tb is + generic ( + DW : integer := 8; + NLP : integer := 5 + ); +end hwloop_top_tb; + + +architecture tb_architecture of hwloop_top_tb is +-- +-- Component declaration of the DUT +component hw_looping is + generic ( + DW : integer := 8; + NLP : integer := 5 + ); + port ( + clk : in std_logic; + reset : in std_logic; + task_loop5_end : in std_logic; + loop1_count : in std_logic_vector(DW-1 downto 0); + loop2_count : in std_logic_vector(DW-1 downto 0); + loop3_count : in std_logic_vector(DW-1 downto 0); + loop4_count : in std_logic_vector(DW-1 downto 0); + loop5_count : in std_logic_vector(DW-1 downto 0); + index1 : out std_logic_vector(DW-1 downto 0); + index2 : out std_logic_vector(DW-1 downto 0); + index3 : out std_logic_vector(DW-1 downto 0); + index4 : out std_logic_vector(DW-1 downto 0); + index5 : out std_logic_vector(DW-1 downto 0); + loops_end : out std_logic + ); +end component; +-- +-- Signal declarations +-- Stimulus signals - signals mapped to the I/IO ports of tested entity +signal clk : std_logic; +signal reset : std_logic; +signal task_loop5_end : std_logic; +signal loop1_count : std_logic_vector(DW-1 downto 0); +signal loop2_count : std_logic_vector(DW-1 downto 0); +signal loop3_count : std_logic_vector(DW-1 downto 0); +signal loop4_count : std_logic_vector(DW-1 downto 0); +signal loop5_count : std_logic_vector(DW-1 downto 0); +-- Signals mapped to the output ports of tested entity +signal index1 : std_logic_vector(DW-1 downto 0); +signal index2 : std_logic_vector(DW-1 downto 0); +signal index3 : std_logic_vector(DW-1 downto 0); +signal index4 : std_logic_vector(DW-1 downto 0); +signal index5 : std_logic_vector(DW-1 downto 0); +signal loops_end : std_logic; +-- +-- Constant declarations +constant CLK_PERIOD : time := 10 ns; + +begin + + -- Unit Under Test port map + UUT : hw_looping + generic map ( + DW => DW, + NLP => NLP + ) + port map ( + clk => clk, + reset => reset, + task_loop5_end => task_loop5_end, + loop1_count => loop1_count, + loop2_count => loop2_count, + loop3_count => loop3_count, + loop4_count => loop4_count, + loop5_count => loop5_count, + index1 => index1, + index2 => index2, + index3 => index3, + index4 => index4, + index5 => index5, + loops_end => loops_end + ); + +CLK_GEN_PROC: process(clk) +begin + if (clk = 'U') then + clk <= '1'; + else + clk <= not clk after CLK_PERIOD/2; + end if; +end process CLK_GEN_PROC; + +DATA_STIM: process +begin + reset <= '0'; + task_loop5_end <= '0'; + loop1_count <= X"00"; + loop2_count <= X"00"; + loop3_count <= X"00"; + loop4_count <= X"00"; + loop5_count <= X"00"; + wait for CLK_PERIOD; + -- + reset <= '1'; + task_loop5_end <= '0'; + loop1_count <= X"00"; + loop2_count <= X"00"; + loop3_count <= X"00"; + loop4_count <= X"00"; + loop5_count <= X"00"; + wait for CLK_PERIOD; + -- + reset <= '0'; + task_loop5_end <= '1'; + loop1_count <= X"04"; + loop2_count <= X"06"; + loop3_count <= X"02"; + loop4_count <= X"04"; + loop5_count <= X"03"; + wait for CLK_PERIOD; + -- + -- Apply same inputs (written in some kind of + -- configuration memory) for large amount of time, + -- e.g. 1000 clock periods + wait for 1000*CLK_PERIOD; + -- +end process DATA_STIM; + +end tb_architecture; + + +configuration TESTBENCH_FOR_hw_looping of hwloop_top_tb is + for tb_architecture + for UUT : hw_looping + use entity work.hw_looping(structural); + end for; + end for; +end TESTBENCH_FOR_hw_looping; Index: hwlu/trunk/doc/hwlu_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: hwlu/trunk/doc/hwlu_spec.pdf =================================================================== --- hwlu/trunk/doc/hwlu_spec.pdf (nonexistent) +++ hwlu/trunk/doc/hwlu_spec.pdf (revision 5)

hwlu/trunk/doc/hwlu_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: hwlu/trunk/sw/gen_hw_looping.c =================================================================== --- hwlu/trunk/sw/gen_hw_looping.c (nonexistent) +++ hwlu/trunk/sw/gen_hw_looping.c (revision 5) @@ -0,0 +1,331 @@ +/* Filename: gen_hw_looping.c */ +/* Description: Generates top-level module for the hw_looping unit */ +/* Author: Nikos Kavvadias, */ +/* Date: Friday, 09/04/2004 */ + +#include +#include +#include + +#define PRINT_DEBUG + + +// FUNCTION PROTOTYPES +void write_file_hw_looping(FILE *outfile); + +FILE *file_hw_looping; /* VHDL source for the top-level module of the + * hw_looping unit (hw_looping.vhd) */ + +char hw_looping_file_name[32]; +int nlp; +time_t t; + + +int main(int argc, char **argv) +{ + int i; + int gen_hw_looping_file; + char nlp_s[3]; + + gen_hw_looping_file = 0; + + if( argc < 3 ) + { + printf("Usage: gen_hw_looping \n"); + printf("where:\n"); + printf("num loops = give number of supported loops\n"); + printf("output base = output file base name. The generated files will be named:\n"); + printf(" \"_top.vhd\" for the top-level module\n"); + // + printf("\n"); + // + return -1; + } + + // Acquire number of supported loops + strcpy(nlp_s,argv[1]); + nlp = atoi(nlp_s); + + // Generate hw_looping_file_name + // (indicating the number of loops supported) + + // Filenames for the requested VHDL source files + //strcpy(hw_looping_file_name,argv[2]); + //strcat(hw_looping_file_name,nlp_s); + //strcat(hw_looping_file_name,"_top.vhd"); + sprintf(hw_looping_file_name,"%s_loops%s%s", argv[2], nlp_s, "_top.vhd"); + gen_hw_looping_file = 1; + + // DEBUG OUTPUT + #ifdef PRINT_DEBUG + printf("\n"); + // + printf("nlp = %d\n",nlp); + printf("hw_looping_file_name = %s\n", hw_looping_file_name); + // + #endif + + + /*************************************************************/ + /* Generate VHDL source for the top-level unit of hw_looping */ + /*************************************************************/ + if (gen_hw_looping_file == 1) + { + file_hw_looping = fopen(hw_looping_file_name,"w"); + write_file_hw_looping(file_hw_looping); + fclose(file_hw_looping); + } + + return 0; + +} + + +void write_file_hw_looping( + FILE *outfile // Name for the output file + ) +{ + unsigned i; + + // Get current time + time(&t); + + /* Generate interface for the VHDL file */ + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Filename: %s ----\n", hw_looping_file_name); + fprintf(outfile,"---- Module description: Top-level file for the hw_looping unit. ----\n"); + fprintf(outfile,"---- Also implements input and output ----\n"); + fprintf(outfile,"---- wrapping operations. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically ----\n"); + fprintf(outfile,"---- with the use of the \"gen_hw_looping\" tool ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- To Do: ----\n"); + fprintf(outfile,"---- Considered stable for the time being ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Copyright (C) 2004 Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nick-kavi.8m.com ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- nick_ka_vi@hotmail.com ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source file may be used and distributed without ----\n"); + fprintf(outfile,"---- restriction provided that this copyright statement is not ----\n"); + fprintf(outfile,"---- removed from the file and that any derivative work contains ----\n"); + fprintf(outfile,"---- the original copyright notice and the associated disclaimer. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source file is free software; you can redistribute it ----\n"); + fprintf(outfile,"---- and/or modify it under the terms of the GNU Lesser General ----\n"); + fprintf(outfile,"---- Public License as published by the Free Software Foundation; ----\n"); + fprintf(outfile,"---- either version 2.1 of the License, or (at your option) any ----\n"); + fprintf(outfile,"---- later version. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source is distributed in the hope that it will be ----\n"); + fprintf(outfile,"---- useful, but WITHOUT ANY WARRANTY; without even the implied ----\n"); + fprintf(outfile,"---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----\n"); + fprintf(outfile,"---- PURPOSE. See the GNU Lesser General Public License for more ----\n"); + fprintf(outfile,"---- details. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- You should have received a copy of the GNU Lesser General ----\n"); + fprintf(outfile,"---- Public License along with this source; if not, download it ----\n"); + fprintf(outfile,"---- from ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"--\n"); + fprintf(outfile,"-- CVS Revision History\n"); + fprintf(outfile,"--\n"); + fprintf(outfile,"\n"); + + /* Code generation for library inclusions */ + fprintf(outfile,"library IEEE;\n"); + fprintf(outfile,"use IEEE.std_logic_1164.all;\n"); + fprintf(outfile,"\n"); + + /* Generate entity declaration */ + fprintf(outfile,"entity hw_looping is\n"); + fprintf(outfile,"\tgeneric (\n"); + fprintf(outfile,"\t\tDW : integer := 8;\n"); + fprintf(outfile,"\t\tNLP : integer := %d\n", nlp); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"\tport (\n"); + fprintf(outfile, "\t\tclk : in std_logic;\n"); + fprintf(outfile, "\t\treset : in std_logic;\n"); + fprintf(outfile, "\t\ttask_loop%d_end : in std_logic;\n", nlp); + // + for (i=1; i<=nlp; i++) + fprintf(outfile,"\t\tloop%d_count : in std_logic_vector(DW-1 downto 0);\n", i); + // + for (i=1; i<=nlp; i++) + { + fprintf(outfile,"\t\tindex%d : out std_logic_vector(DW-1 downto 0);\n", i); + } + // + fprintf(outfile, "\t\tloops_end : out std_logic\n"); + // + fprintf(outfile,"\t);\n"); + fprintf(outfile,"end hw_looping;\n"); + fprintf(outfile,"\n"); + + /* Generate architecture declaration */ + fprintf(outfile,"architecture structural of hw_looping is\n"); + + /* Add component declarations here if needed */ + fprintf(outfile,"--\n"); + fprintf(outfile,"-- Component declarations\n"); + fprintf(outfile,"component cmpeq\n"); + fprintf(outfile,"\tgeneric (\n"); + fprintf(outfile,"\t\tDW : integer := 8\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"\tport (\n"); + fprintf(outfile,"\t\ta : in std_logic_vector(DW-1 downto 0);\n"); + fprintf(outfile,"\t\tb : in std_logic_vector(DW-1 downto 0);\n"); + fprintf(outfile,"\t\treset : in std_logic;\n"); + fprintf(outfile,"\t\ta_eq_b : out std_logic\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"end component;\n"); + // + fprintf(outfile,"--\n"); + fprintf(outfile,"component index_inc\n"); + fprintf(outfile,"\tgeneric (\n"); + fprintf(outfile,"\t\tDW : integer := 8\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"\tport (\n"); + fprintf(outfile,"\t\tclk : in std_logic;\n"); + fprintf(outfile,"\t\treset : in std_logic;\n"); + fprintf(outfile,"\t\tinc_en : in std_logic;\n"); + fprintf(outfile,"\t\tindex_plus_one : out std_logic_vector(DW-1 downto 0);\n"); + fprintf(outfile,"\t\tindex_out : out std_logic_vector(DW-1 downto 0)\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"end component;\n"); + // + fprintf(outfile,"--\n"); + fprintf(outfile,"component priority_encoder\n"); + fprintf(outfile,"\tgeneric (\n"); + fprintf(outfile,"\t\tNLP : integer := 5\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"\tport (\n"); + fprintf(outfile,"\t\tflag : in std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp); + fprintf(outfile,"\t\tincl : out std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\treset_vct : out std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\tloops_end : out std_logic\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"end component;\n"); + + /* Add signal declarations here if needed */ + fprintf(outfile,"--\n"); + fprintf(outfile,"-- Signal declarations\n"); + // flag + fprintf(outfile,"signal flag : std_logic_vector(NLP-1 downto 0);\n"); + // incl + fprintf(outfile,"signal incl : std_logic_vector(NLP-1 downto 0);\n"); + // temp_loop_count + fprintf(outfile,"signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0);\n"); + // temp_index + fprintf(outfile,"signal temp_index : std_logic_vector(NLP*DW-1 downto 0);\n"); + // temp_index_plus_one + fprintf(outfile,"signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);\n"); + // temp_vct_penc + fprintf(outfile,"signal reset_vct_penc : std_logic_vector(NLP-1 downto 0);\n"); + // temp_index + fprintf(outfile,"signal reset_vct_ix : std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"--\n"); + + /* Continue with the rest of the architecture declaration */ + fprintf(outfile,"begin\n"); + fprintf(outfile,"\n"); + + /***************************************/ + /* GENERATE INPUT WRAPPING ASSIGNMENTS */ + /***************************************/ + + /* Iterate through all loops */ + for (i=1; i<=nlp; i++) + { + /* Generate assignment code */ + fprintf(outfile,"\ttemp_loop_count( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) ) <= loop%d_count;\n", + i-1, i, i); + } + fprintf(outfile,"\n"); + + /***************************************/ + /* GENERATE INTERNAL HW_LOOPING MODULE */ + /***************************************/ + + // Generate cmpeq modules + fprintf(outfile,"\tGEN_COMPARATORS: for i in 0 to NLP-1 generate\n"); + fprintf(outfile,"\t\tU_cmp : cmpeq\n"); + fprintf(outfile,"\t\t\tgeneric map (\n"); + fprintf(outfile,"\t\t\t\tDW => DW\n"); + fprintf(outfile,"\t\t\t)\n"); + fprintf(outfile,"\t\t\tport map (\n"); + fprintf(outfile,"\t\t\t\ta => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n"); + fprintf(outfile,"\t\t\t\tb => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),\n"); + fprintf(outfile,"\t\t\t\treset => reset,\n"); + fprintf(outfile,"\t\t\t\ta_eq_b => flag(i)\n"); + fprintf(outfile,"\t\t\t);\n"); + fprintf(outfile,"\tend generate GEN_COMPARATORS;\n"); + fprintf(outfile,"\n"); + + // Generate priority encoder + fprintf(outfile,"\tU_priority_enc : priority_encoder\n"); + fprintf(outfile,"\t\tgeneric map (\n"); + fprintf(outfile,"\t\t\tNLP => NLP\n"); + fprintf(outfile,"\t\t)\n"); + fprintf(outfile,"\t\tport map (\n"); + fprintf(outfile,"\t\t\tflag => flag,\n"); + fprintf(outfile,"\t\t\ttask_loop5_end => task_loop5_end,\n"); + fprintf(outfile,"\t\t\tincl => incl,\n"); + fprintf(outfile,"\t\t\treset_vct => reset_vct_penc,\n"); + fprintf(outfile,"\t\t\tloops_end => loops_end\n"); + fprintf(outfile,"\t\t);\n"); + fprintf(outfile,"\n"); + + // Generate reset_vct_ix + fprintf(outfile,"\tGEN_RESET_SEL: for i in 0 to NLP-1 generate\n"); + fprintf(outfile,"\t\treset_vct_ix(i) <= reset_vct_penc(i) or reset;\n"); + fprintf(outfile,"\tend generate GEN_RESET_SEL;\n"); + fprintf(outfile,"\n"); + + // Generate index_inc modules + fprintf(outfile,"\tGEN_INC_IX: for i in 0 to NLP-1 generate\n"); + fprintf(outfile,"\t\tU_inc_ix1 : index_inc\n"); + fprintf(outfile,"\t\t\tgeneric map (\n"); + fprintf(outfile,"\t\t\t\tDW => DW\n"); + fprintf(outfile,"\t\t\t)\n"); + fprintf(outfile,"\t\t\tport map (\n"); + fprintf(outfile,"\t\t\t\tclk => clk,\n"); + fprintf(outfile,"\t\t\t\treset => reset_vct_ix(i),\n"); + fprintf(outfile,"\t\t\t\tinc_en => incl(i),\n"); + fprintf(outfile,"\t\t\t\tindex_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n"); + fprintf(outfile,"\t\t\t\tindex_out => temp_index( ((i+1)*DW-1) downto (i*DW) )\n"); + fprintf(outfile,"\t\t\t);\n"); + fprintf(outfile,"\tend generate GEN_INC_IX;\n"); + fprintf(outfile,"\n"); + + /****************************************/ + /* GENERATE OUTPUT WRAPPING ASSIGNMENTS */ + /****************************************/ + + /* Iterate through all loops */ + for (i=1; i<=nlp; i++) + { + /* Generate assignment code */ + fprintf(outfile,"\tindex%d <= temp_index( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) );\n", i, i-1, i); + } + fprintf(outfile,"\n"); + + // + fprintf(outfile,"end structural;\n"); + +} + \ No newline at end of file Index: hwlu/trunk/sw/gen_priority_encoder.c =================================================================== --- hwlu/trunk/sw/gen_priority_encoder.c (nonexistent) +++ hwlu/trunk/sw/gen_priority_encoder.c (revision 5) @@ -0,0 +1,424 @@ +/* Filename: gen_priority_encoder.c */ +/* Description: Generates priority_encoder module */ +/* Author: Nikos Kavvadias, */ +/* Date: Friday, 09/04/2004 */ + +#include +#include +#include + +#define PRINT_DEBUG + + +// FUNCTION PROTOTYPES +void write_file_priority_encoder(FILE *outfile); +unsigned dectobin(unsigned bin_data, int num_bits); +unsigned ipow(unsigned x, unsigned y); +unsigned log2(unsigned operand); +void print_binary_value(FILE *outfile, int i); +void print_binary_value_fbone(FILE *outfile, int i); + + +FILE *file_priority_encoder; /* VHDL source for the priority_encoder module of the + * hw_looping unit (priority_encoder.vhd) */ + +char priority_encoder_file_name[32]; +int nlp; +time_t t; + + +int main(int argc, char **argv) +{ + int i; + int gen_priority_encoder_file; + char nlp_s[3]; + + gen_priority_encoder_file = 0; + + if( argc < 3 ) + { + printf("Usage: gen_priority_encoder \n"); + printf("where:\n"); + printf("num loops = give number of supported loops\n"); + printf("output base = output file base name. The generated files will be named:\n"); + printf(" \".vhd\" for the module\n"); + // + printf("\n"); + // + return -1; + } + + // Acquire number of supported loops + strcpy(nlp_s,argv[1]); + nlp = atoi(nlp_s); + + // Filenames for the requested VHDL source files + sprintf(priority_encoder_file_name,"%s_loops%s%s", argv[2], nlp_s, ".vhd"); + gen_priority_encoder_file = 1; + + + // DEBUG OUTPUT + #ifdef PRINT_DEBUG + printf("\n"); + // + printf("nlp = %d\n",nlp); + printf("priority_encoder_file_name = %s\n", priority_encoder_file_name); + // + #endif + + + /******************************************************/ + /* Generate VHDL source for the priority_encoder unit */ + /******************************************************/ + if (gen_priority_encoder_file == 1) + { + file_priority_encoder = fopen(priority_encoder_file_name,"w"); + write_file_priority_encoder(file_priority_encoder); + fclose(file_priority_encoder); + } + + return 0; + +} + + +void write_file_priority_encoder( + FILE *outfile // Name for the output file -- e.g. mbloop_merger.vhd + ) +{ + int i; + + // Get current time + time(&t); + + /* Generate interface for the VHDL file */ + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Filename: %s ----\n", priority_encoder_file_name); + fprintf(outfile,"---- Module description: Priority encoder unit. Obtains ----\n"); + fprintf(outfile,"---- increment and reset decisions for the loop indices. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically ----\n"); + fprintf(outfile,"---- with the use of the \"gen_priority_encoder\" tool ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- To Do: ----\n"); + fprintf(outfile,"---- Considered stable for the time being ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- Copyright (C) 2004 Nikolaos Kavvadias ----\n"); + fprintf(outfile,"---- nick-kavi.8m.com ----\n"); + fprintf(outfile,"---- nkavv@skiathos.physics.auth.gr ----\n"); + fprintf(outfile,"---- nick_ka_vi@hotmail.com ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source file may be used and distributed without ----\n"); + fprintf(outfile,"---- restriction provided that this copyright statement is not ----\n"); + fprintf(outfile,"---- removed from the file and that any derivative work contains ----\n"); + fprintf(outfile,"---- the original copyright notice and the associated disclaimer. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source file is free software; you can redistribute it ----\n"); + fprintf(outfile,"---- and/or modify it under the terms of the GNU Lesser General ----\n"); + fprintf(outfile,"---- Public License as published by the Free Software Foundation; ----\n"); + fprintf(outfile,"---- either version 2.1 of the License, or (at your option) any ----\n"); + fprintf(outfile,"---- later version. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- This source is distributed in the hope that it will be ----\n"); + fprintf(outfile,"---- useful, but WITHOUT ANY WARRANTY; without even the implied ----\n"); + fprintf(outfile,"---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----\n"); + fprintf(outfile,"---- PURPOSE. See the GNU Lesser General Public License for more ----\n"); + fprintf(outfile,"---- details. ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"---- You should have received a copy of the GNU Lesser General ----\n"); + fprintf(outfile,"---- Public License along with this source; if not, download it ----\n"); + fprintf(outfile,"---- from ----\n"); + fprintf(outfile,"---- ----\n"); + fprintf(outfile,"----==============================================================----\n"); + fprintf(outfile,"--\n"); + fprintf(outfile,"-- CVS Revision History\n"); + fprintf(outfile,"--\n"); + fprintf(outfile,"\n"); + + /* Code generation for library inclusions */ + fprintf(outfile,"library IEEE;\n"); + fprintf(outfile,"use IEEE.std_logic_1164.all;\n"); + fprintf(outfile,"use IEEE.std_logic_unsigned.all;\n"); + fprintf(outfile,"\n"); + + /* Generate entity declaration */ + fprintf(outfile,"entity priority_encoder is\n"); + fprintf(outfile,"\tgeneric (\n"); + fprintf(outfile,"\t\tNLP : integer := %d\n", nlp); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"\tport (\n"); + fprintf(outfile,"\t\tflag : in std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp); + fprintf(outfile,"\t\tincl : out std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\treset_vct : out std_logic_vector(NLP-1 downto 0);\n"); + fprintf(outfile,"\t\tloops_end : out std_logic\n"); + fprintf(outfile,"\t);\n"); + fprintf(outfile,"end priority_encoder;\n"); + fprintf(outfile,"\n"); + + /* Generate architecture declaration */ + fprintf(outfile,"architecture rtl of priority_encoder is\n"); + + /* Add component declarations here if needed */ + + /* Add signal declarations here if needed */ + + /* Continue with the rest of the architecture declaration */ + fprintf(outfile,"begin\n"); + fprintf(outfile,"\n"); + + fprintf(outfile,"\t-- Fully-nested loop structure with %d loops\n", nlp); + fprintf(outfile,"\t-- From outer to inner: "); + // + i = nlp-1; + fprintf(outfile,"%d", nlp-1); + // + if (nlp>=2) + { + for (i=nlp-2; i>=0; i--) + fprintf(outfile,"-> %d",i); + } + // + fprintf(outfile,"\n"); + + // Loop counter + i = nlp-1; + + /********************/ + /* GENERATE process */ + /********************/ + + fprintf(outfile,"\tprocess (flag, task_loop5_end)\n"); + fprintf(outfile,"\tbegin\n"); + fprintf(outfile,"\t\t--\n"); + fprintf(outfile,"\t\t-- if loop%d is terminating:\n", i); + fprintf(outfile,"\t\t-- reset loops %d-%d to initial index\n", i, 0); + // + fprintf(outfile,"\t\tif (flag(%d downto 0) = \"", i); + print_binary_value_fbone( outfile, ipow(2,i+1)-1 ); + fprintf(outfile,"\") then\n"); + // + fprintf(outfile,"\t\t\tincl <= \""); + print_binary_value( outfile, 0 ); + fprintf(outfile,"\";\n"); + // + fprintf(outfile,"\t\t\treset_vct <= \""); + print_binary_value( outfile, ipow(2,i+1)-1 ); + fprintf(outfile,"\";\n"); + // + fprintf(outfile,"\t\t\tloops_end <= '1';\n"); + + // Loop on all "elsif" cases: i=2 -> i=nlp + for (i=nlp-2; i>=0; i--) + { + fprintf(outfile,"\t\t-- else if loop%d is terminating:\n", i); + fprintf(outfile,"\t\t-- 1. increment loop%d index\n", i+1); + fprintf(outfile,"\t\t-- 2. reset loop%d to initial index\n", i); + // + fprintf(outfile,"\t\telsif (flag(%d downto 0) = \"", i); + print_binary_value_fbone( outfile, ipow(2,i+1)-1 ); + fprintf(outfile,"\") then\n"); + // + fprintf(outfile,"\t\t\tincl <= \""); + print_binary_value( outfile, ipow(2,i+1) ); + fprintf(outfile,"\";\n"); + // + fprintf(outfile,"\t\t\treset_vct <= \""); + print_binary_value( outfile, ipow(2,i+1)-1 ); + fprintf(outfile,"\";\n"); + // + fprintf(outfile,"\t\t\tloops_end <= '0';\n"); + } + + // Else increment inner loop + fprintf(outfile,"\t\t-- else increment loop%d index\n", i); + fprintf(outfile,"\t\telse\n"); + // + fprintf(outfile,"\t\t\treset_vct <= \""); + print_binary_value( outfile, 0 ); + fprintf(outfile,"\";\n"); + // + fprintf(outfile,"\t\t\tloops_end <= '0';\n"); + // + fprintf(outfile,"\t\t\tif (task_loop%d_end = '1') then\n", nlp); + fprintf(outfile,"\t\t\t\tincl <= \""); + print_binary_value( outfile, ipow(2,i+1) ); + fprintf(outfile,"\";\n"); + fprintf(outfile,"\t\t\telse\n"); + fprintf(outfile,"\t\t\t\tincl <= \""); + print_binary_value( outfile, 0 ); + fprintf(outfile,"\";\n"); + fprintf(outfile,"\t\t\tend if;\n"); + // + fprintf(outfile,"\t\tend if;\n"); + fprintf(outfile,"\tend process;\n"); + fprintf(outfile,"\n"); + // + fprintf(outfile,"end rtl;\n"); + +} + + +unsigned dectobin(unsigned bin_data, int num_bits) +{ + int count; + unsigned MASK; + unsigned result; + unsigned result_arr[100]; + + count = num_bits; + MASK = 1<<(count-1); + + result = 0; + + for (count=num_bits-1; count>-1; count--) + { + result_arr[count] = (( bin_data & MASK ) ? 1 : 0 ); + bin_data <<= 1; + } + + for (count=num_bits-1; count>-1; count--) + result = ipow(10,count)*result_arr[count] + result; + + return result; +} + + +unsigned ipow(unsigned x, unsigned y) +{ + unsigned i; + unsigned result; + + result = 1; + + for (i=1; i<=y; i++) + result = result*x; + + return result; +} + + +/* log2 function for integers: unsigned log2(unsigned operand) */ +unsigned log2(unsigned operand) +{ + unsigned temp; + unsigned log_val; + + temp = operand-1; + //temp = operand; + log_val = 0; + + while (temp > 0) + { + temp = temp/2; + log_val = log_val + 1; + } + + return log_val; +} + +void print_binary_value(FILE *outfile, int i) +{ + // Print integer value + switch (nlp) + { + case 1: + fprintf(outfile,"%d",dectobin( i, nlp )); + break; + case 2: + fprintf(outfile,"%02d",dectobin( i, nlp )); + break; + case 3: + fprintf(outfile,"%03d",dectobin( i, nlp )); + break; + case 4: + fprintf(outfile,"%04d",dectobin( i, nlp )); + break; + case 5: + fprintf(outfile,"%05d",dectobin( i, nlp )); + break; + case 6: + fprintf(outfile,"%06d",dectobin( i, nlp )); + break; + case 7: + fprintf(outfile,"%07d",dectobin( i, nlp )); + break; + case 8: + fprintf(outfile,"%08d",dectobin( i, nlp )); + break; + case 9: + fprintf(outfile,"%09d",dectobin( i, nlp )); + break; + case 10: + fprintf(outfile,"%10d",dectobin( i, nlp )); + break; + case 11: + fprintf(outfile,"%11d",dectobin( i, nlp )); + break; + case 12: + fprintf(outfile,"%12d",dectobin( i, nlp )); + break; + case 13: + fprintf(outfile,"%13d",dectobin( i, nlp )); + break; + case 14: + fprintf(outfile,"%14d",dectobin( i, nlp )); + break; + case 15: + fprintf(outfile,"%15d",dectobin( i, nlp )); + break; + case 16: + fprintf(outfile,"%16d",dectobin( i, nlp )); + break; + default: + break; + } +} + +// Print binary value -- First bit is "one". +void print_binary_value_fbone(FILE *outfile, int i) +{ + // Print integer value + switch ( log2(i) ) + { + // i = 1 + case 0: + fprintf(outfile,"%d",dectobin( i, i )); + break; + // i = 2:3 + case 1: + fprintf(outfile,"%d",dectobin( i, log2(i) )); + break; + // i = 4:7 + case 2: + fprintf(outfile,"%02d",dectobin( i, log2(i) )); + break; + // i = 8:15 + case 3: + fprintf(outfile,"%03d",dectobin( i, log2(i) )); + break; + // i = 16:31 + case 4: + fprintf(outfile,"%04d",dectobin( i, log2(i) )); + break; + // i = 32:63 + case 5: + fprintf(outfile,"%05d",dectobin( i, log2(i) )); + break; + default: + break; + } +} + + + \ No newline at end of file Index: hwlu/trunk =================================================================== --- hwlu/trunk (nonexistent) +++ hwlu/trunk (revision 5)

hwlu/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: hwlu/web_uploads =================================================================== --- hwlu/web_uploads (nonexistent) +++ hwlu/web_uploads (revision 5)

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hwlu/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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