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Rev 4 → Rev 5

/trunk/fsm/in_key.fsm
0,0 → 1,123
-- File Name : in_key.fsm --
-- Description : The control of in key blok --
-- Purpose : To be used by SYF --
-- Date : Aug 30, 2001 --
-- Version : 1.1 --
-- Author : Sigit Dewantor --
-- Address : VLSI RG, Dept. of Electrical Engineering ITB, --
-- Bandung, Indonesia --
-- E-mail : sigit@ic.vlsi.itb.ac.id --
 
ENTITY in_key IS
PORT ( clk,rst,key_sended : IN BIT;
en_bufin,req_key,ikey_ready : OUT BIT;
n_block : OUT BIT;
vdd, vss : IN BIT
);
END in_key;
 
ARCHITECTURE fsm OF in_key IS
 
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4,S5, S6, S7);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
BEGIN
PROCESS ( CURRENT_STATE, rst)
BEGIN
IF ( rst = '1' ) THEN
NEXT_STATE <= S0;
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '0';
ELSE
CASE CURRENT_STATE IS
WHEN S0 =>
if(key_sended = '1') then
req_key <= '0';
en_bufin <= '1';
ikey_ready <= '0';
n_block <= '0';
NEXT_STATE <= S1;
else
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '0';
NEXT_STATE <= S0;
end if;
WHEN S1 =>
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S2;
WHEN S2 =>
if(key_sended = '1') then
req_key <= '0';
en_bufin <= '1';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S3;
else
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S2;
end if;
WHEN S3 =>
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S4;
WHEN S4 =>
if(key_sended = '1') then
req_key <= '0';
en_bufin <= '1';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S5;
else
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S4;
end if;
WHEN S5 =>
req_key <= '1';
en_bufin <= '0';
ikey_ready <= '0';
n_block <= '1';
NEXT_STATE <= S6;
 
WHEN S6 =>
req_key <= '0';
en_bufin <= '0';
ikey_ready <= '1';
n_block <= '0';
NEXT_STATE <= S0;
WHEN OTHERS =>
ASSERT ( '1' )
REPORT "Illegal State";
 
END CASE;
END IF;
END PROCESS;
 
PROCESS (clk)
BEGIN
IF ((clk AND NOT clk'STABLE) ='1') THEN
CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;
 
END fsm;
/trunk/fsm/control_datain.fsm
0,0 → 1,109
-- File Name : control_datain.fsm --
-- Description : The control of data-in blok --
-- Purpose : To be used by SYF --
-- Date : Aug 30, 2001 --
-- Version : 1.1 --
-- Author : Martadinata A. --
-- Address : VLSI RG, Dept. of Electrical Engineering ITB, --
-- Bandung, Indonesia --
-- E-mail : marta@ic.vlsi.itb.ac.id --
 
ENTITY control_datain IS
PORT ( clk,rst,dt_sended,emp_buf : IN BIT;
en_bufin,req_dt,dt_ready : OUT BIT;
n_block : OUT BIT;
vdd, vss : IN BIT
);
END control_datain;
 
ARCHITECTURE fsm OF control_datain IS
 
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
BEGIN
PROCESS ( CURRENT_STATE, rst, emp_buf)
BEGIN
IF ( rst = '1' ) THEN
NEXT_STATE <= S0;
req_dt <= '1';
en_bufin <= '0';
dt_ready <= '0';
n_block <= '0';
ELSE
CASE CURRENT_STATE IS
WHEN S0 =>
if(dt_sended = '1') then
req_dt <= '0';
en_bufin <= '1';
dt_ready <= '0';
n_block <= '0';
NEXT_STATE <= S1;
else
req_dt <= '1';
en_bufin <= '0';
dt_ready <= '0';
n_block <= '0';
NEXT_STATE <= S0;
end if;
WHEN S1 =>
req_dt <= '1';
en_bufin <= '0';
dt_ready <= '0';
n_block <= '1';
NEXT_STATE <= S2;
WHEN S2 =>
if(dt_sended = '1') then
req_dt <= '0';
en_bufin <= '1';
dt_ready <= '0';
n_block <= '1';
NEXT_STATE <= S3;
else
req_dt <= '1';
en_bufin <= '0';
dt_ready <= '0';
n_block <= '1';
NEXT_STATE <= S2;
end if;
WHEN S3 =>
req_dt <= '0';
en_bufin <= '0';
dt_ready <= '1';
n_block <= '0';
NEXT_STATE <= S4;
WHEN S4 =>
if(emp_buf = '1') then
req_dt <= '1';
en_bufin <= '0';
dt_ready <= '0';
n_block <= '0';
NEXT_STATE <= S0;
else
req_dt <= '0';
en_bufin <= '0';
dt_ready <= '1';
n_block <= '0';
NEXT_STATE <= S4;
end if;
WHEN OTHERS =>
ASSERT ( '1' )
REPORT "Illegal State";
 
END CASE;
END IF;
END PROCESS;
 
PROCESS (clk)
BEGIN
IF ((clk AND NOT clk'STABLE) ='1') THEN
CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;
 
END fsm;
/trunk/fsm/control_dataout.fsm
0,0 → 1,109
-- File Name : control_dataout.fsm --
-- Description : The control of data-out blok --
-- Purpose : To be used by SYF --
-- Date : Aug 30, 2001 --
-- Version : 1.1 --
-- Author : Martadinata A. --
-- Address : VLSI RG, Dept. of Electrical Engineering ITB, --
-- Bandung, Indonesia --
-- E-mail : marta@ic.vlsi.itb.ac.id --
 
ENTITY control_dataout IS
PORT ( clk,rst,cp_ready,emp_bufout : IN BIT;
en_bufout,req_cp,cp_sended : OUT BIT;
n_block : OUT BIT;
vdd, vss : IN BIT
);
END control_dataout;
 
ARCHITECTURE fsm OF control_dataout IS
 
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4);
 
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
 
SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
 
BEGIN
PROCESS ( CURRENT_STATE, rst)
BEGIN
IF ( rst = '1' ) THEN
NEXT_STATE <= S0;
req_cp <= '1';
en_bufout <= '0';
cp_sended <= '0';
n_block <= '0';
ELSE
CASE CURRENT_STATE IS
WHEN S0 =>
if(cp_ready = '1') then
req_cp <= '0';
en_bufout <= '1';
cp_sended <= '0';
n_block <= '0';
NEXT_STATE <= S1;
else
req_cp <= '1';
en_bufout <= '0';
cp_sended <= '0';
n_block <= '0';
NEXT_STATE <= S0;
end if;
WHEN S1 =>
req_cp <= '0';
en_bufout <= '0';
cp_sended <= '1';
n_block <= '1';
NEXT_STATE <= S2;
WHEN S2 =>
if(emp_bufout = '1') then
req_cp <= '0';
en_bufout <= '1';
cp_sended <= '0';
n_block <= '1';
NEXT_STATE <= S3;
else
req_cp <= '0';
en_bufout <= '0';
cp_sended <= '1';
n_block <= '1';
NEXT_STATE <= S2;
end if;
WHEN S3 =>
req_cp <= '0';
en_bufout <= '0';
cp_sended <= '1';
n_block <= '0';
NEXT_STATE <= S4;
WHEN S4 =>
if(emp_bufout = '1') then
req_cp <= '1';
en_bufout <= '0';
cp_sended <= '0';
n_block <= '0';
NEXT_STATE <= S0;
else
req_cp <= '0';
en_bufout <= '0';
cp_sended <= '1';
n_block <= '0';
NEXT_STATE <= S4;
end if;
WHEN OTHERS =>
ASSERT ( '1' )
REPORT "Illegal State";
 
END CASE;
END IF;
END PROCESS;
 
PROCESS (clk)
BEGIN
IF ((clk AND NOT clk'STABLE) ='1') THEN
CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;
 
END fsm;

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