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Rev 4 → Rev 5

/trunk/rtl/vhdl/ami_dec.vhd
0,0 → 1,20
 
-- implementation of the AMI decoder.
 
entity ami_dec is
port (
clr_bar,
e0, e1 : in bit; -- inputs.
s : out bit -- output.
);
end ami_dec;
 
architecture behaviour of ami_dec is
begin
process (e0, e1, clr_bar) begin
if (clr_bar = '0')then
s <= '0';
end if;
s <= e0 or e1;
end process;
end behaviour;
/trunk/rtl/vhdl/hdb1_enc.vhd
0,0 → 1,43
 
-- implementation of the HDB1 encoder.
 
entity hdb1_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end hdb1_enc;
 
architecture behaviour of hdb1_enc is
signal q0, q1, q2 : bit; -- 3 flipflops for 6 states.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
q2 <= '0';
s0 <= '0';
s1 <= '0';
elsif clk'event and clk = '1' then
 
q0 <= (e and (not q1))
or ((not e) and (not q0) and q1 and q2 )
or ((not e) and q0 and q1 and (not q2) );
q1 <= (e and (not q1))
or ((not q1) and q2)
or ((not e) and q1 and (not q2));
 
q2 <= (not e) and (not q2);
 
s0 <= ((not q1) and (not q2))
or ((not e)and q1 and q2);
 
s1 <= (q1 and (not q2))
or ((not e) and (not q1) and q2);
end if;
end process;
end behaviour;
/trunk/rtl/vhdl/hdb1_dec.vhd
0,0 → 1,26
 
-- implementation of the HDB1 decoder.
 
entity hdb1_dec is
port (
clr_bar,
clk, e0, e1 : in bit; -- inputs.
s : out bit -- output.
);
end hdb1_dec;
 
architecture behaviour of hdb1_dec is
signal q0, q1: bit; -- two flipflops.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
s <= '0';
elsif clk'event and clk = '1' then
s <= ( q0 and (not e0) ) or ( q1 and (not e1) );
q0 <= (not q0) and e0;
q1 <= (not q1) and e1;
end if;
end process;
end behaviour;
/trunk/rtl/vhdl/ami_enc.vhd
0,0 → 1,27
 
-- implementation of the AMI encoder.
 
entity ami_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end ami_enc;
 
architecture behaviour of ami_enc is
signal q : bit; -- 1 flipflops for 2 states.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q <= '0';
s1 <= '0';
s0 <= '0';
elsif clk'event and clk = '1' then
q <= q xor e;
s1 <= q and e;
s0 <= e and (not q);
end if;
end process;
end behaviour;

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