URL
https://opencores.org/ocsvn/nysa_sata/nysa_sata/trunk
Subversion Repositories nysa_sata
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- This comparison shows the changes necessary to convert path
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- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/nysa_sata/trunk/test/test_sata.py
32,7 → 32,7
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@cocotb.test(skip = True) |
@cocotb.test(skip = False) |
def short_write_test(dut): |
""" |
Description: |
/nysa_sata/trunk/rtl/generic/ppfifo.v
448,6 → 448,7
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r_next_fifo <= 0; |
r_read_data <= 0; |
read_ready <= 0; |
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end |
else begin |
/nysa_sata/trunk/README.md
3,15 → 3,18
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Sata stack written in Verilog |
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Staus: TLDR Version: Simulations are working |
Staus: TLDR Version: Demonstrated reading and writing to a hard drive on a Spartan 6 LX45T board |
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This code was written a long time ago and I've learned much more about verilog and project organization |
since then. It has been proven in a Virtex 6 FPGA reading and writing to/from four Sata 2 hard drives at |
For a reference implementation here is a wishbone slave core used to verify the functionality of the SATA Stack: |
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https://github.com/CospanDesign/nysa-verilog/tree/master/verilog/wishbone/slave/wb_sata |
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More documentation can be found on the [wiki](https://github.com/CospanDesign/nysa-sata/wiki) |
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Most of the license is MIT but some of the licenses are GPL |
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TODO: Fix Link layer... there is a small FIFO in there that is used to handle all starting and stopping |
of the read, it's a work around and needs to be fixed |
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TODO: Fix Link layer so that it only instantiates one instance of the scrambler, not two |
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Code Organization: |
57,3 → 60,4
I leave the ethics up to the user and have licensesed most of the code as MIT but I did use some GPL cores |
and if the user desires to use this in their closed source project be warned about the GPL'ed modules in |
this stack. |
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