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URL https://opencores.org/ocsvn/usb_ft232h_avalon-mm_interface/usb_ft232h_avalon-mm_interface/trunk

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/usb_ft232h_avalon-mm_interface/trunk/hw/usb_ft232h.sv
3,301 → 3,420
* не придет следующий пакет
*/
 
`define WRDATA_ADDR 0
`define RDDATA_ADDR 1
`define TXSTATUSL_ADDR 2
`define TXSTATUSH_ADDR 3
`define RXSTATUSL_ADDR 4
`define RXSTATUSH_ADDR 5
 
module usb_ft232h (
//Avalon-MM Slave
clk,
reset,
address,
read,
readdata,
write,
writedata,
clk_i,
reset_i,
address_i,
read_i,
readdata_o,
write_i,
writedata_i,
 
//FT232H
usb_clk,
usb_data,
usb_rxf_n,
usb_txe_n,
usb_rd_n,
usb_wr_n,
usb_oe_n
usb_clk_i,
usb_data_io,
usb_rxf_n_i,
usb_txe_n_i,
usb_rd_n_o,
usb_wr_n_o,
usb_oe_n_o
);
 
parameter FIFO_DEPTH = 512;
parameter FIFO_WIDTHU = 9;
parameter TX_FIFO_DEPTH = 512;
parameter TX_FIFO_WIDTHU = 9;
parameter RX_FIFO_DEPTH = 512;
parameter RX_FIFO_WIDTHU = 9;
 
localparam WRDATA_ADDR = 4'd0;
localparam RDDATA_ADDR = 4'd1;
localparam TXSTATUSL_ADDR = 4'd2;
localparam TXSTATUSH_ADDR = 4'd3;
localparam RXSTATUSL_ADDR = 4'd4;
localparam RXSTATUSH_ADDR = 4'd5;
 
input logic clk;
input logic reset;
input logic [3:0]address;
input logic read;
output logic [7:0]readdata;
input logic write;
input logic [7:0]writedata;
 
input logic usb_clk;
inout logic [7:0]usb_data;
input logic usb_rxf_n;
input logic usb_txe_n;
output logic usb_rd_n;
output logic usb_wr_n;
output logic usb_oe_n;
input logic clk_i;
input logic reset_i;
input logic [3:0] address_i;
input logic read_i;
output logic [7:0] readdata_o;
input logic write_i;
input logic [7:0] writedata_i;
 
input logic usb_clk_i;
inout logic [7:0] usb_data_io;
input logic usb_rxf_n_i;
input logic usb_txe_n_i;
output logic usb_rd_n_o;
output logic usb_wr_n_o;
output logic usb_oe_n_o;
 
logic [15:0]txstatus;
logic [15:0]rxstatus;
 
logic [3:0]addr;
reg reg_usb_rd_n;
reg reg_usb_oe_n;
reg reg_usb_wr_n;
reg reg_rxf_wrreq;
reg reg_txf_rdreq;
reg error;
 
reg error;
reg rxerror;
reg [7:0] rxerrdata;
logic [15:0] txstatus;
logic [15:0] rxstatus;
 
logic [7:0]txf_wrdata;
logic txf_wrclk;
logic txf_wrreq;
logic txf_wrfull;
logic [FIFO_WIDTHU-1:0]txf_wrusedw;
logic txf_rdclk;
logic txf_rdreq;
logic [7:0]txf_rddata;
logic txf_rdempty;
reg read_pipe;
reg read_pipe2;
 
logic [7:0]rxf_wrdata;
logic rxf_wrclk;
logic rxf_wrreq;
logic rxf_wrfull;
logic [FIFO_WIDTHU-1:0]rxf_rdusedw;
logic rxf_rdclk;
logic rxf_rdreq;
logic [7:0]rxf_rddata;
logic rxf_rdempty;
logic rxf_rdfull;
reg adr_data;
reg adr_txsl;
reg adr_txsh;
reg adr_rxsl;
reg adr_rxsh;
 
 
logic [7:0] txf_wrdata;
logic txf_wrclk;
logic txf_wrreq;
logic txf_wrfull;
logic [TX_FIFO_WIDTHU-1:0] txf_wrusedw;
logic txf_rdclk;
logic txf_rdreq;
logic [7:0] txf_rddata;
logic txf_rdempty;
 
assign usb_data = usb_oe_n ? txf_rddata : {8{1'bZ}};
assign rxf_wrdata = usb_oe_n ? 8'b0 : usb_data;
logic [7:0] rxf_wrdata;
logic rxf_wrclk;
logic rxf_wrreq;
logic rxf_wrfull;
logic [RX_FIFO_WIDTHU-1:0] rxf_rdusedw;
logic rxf_rdclk;
logic rxf_rdreq;
logic [7:0] rxf_rddata;
logic rxf_rdempty;
logic rxf_rdfull;
 
assign usb_oe_n = (~usb_rxf_n & ~rxf_wrfull) ? reg_usb_oe_n : 1'b1;
assign usb_rd_n = (~usb_rxf_n & ~rxf_wrfull) ? reg_usb_rd_n : 1'b1;
assign usb_wr_n = (usb_oe_n & ~usb_txe_n) ? reg_usb_wr_n : 1'b1;
assign rxf_wrreq = (~usb_rxf_n & ~rxf_wrfull) ? reg_rxf_wrreq : 1'b0;
assign txf_rdreq = (reg_txf_rdreq & (~error));
 
assign txstatus[15] = ~txf_wrfull; //can write
assign txstatus[14:FIFO_WIDTHU+1] = 0;
assign txstatus[FIFO_WIDTHU] = txf_wrfull;
assign txstatus[FIFO_WIDTHU-1:0] = txf_wrusedw;
assign usb_data_io = ( usb_oe_n_o ) ? ( txf_rddata ) : ( {8{1'bZ}} );
 
assign rxstatus[15] = ~rxf_rdempty; //can read
assign rxstatus[14:FIFO_WIDTHU+1] = 0;
assign rxstatus[FIFO_WIDTHU] = rxf_rdfull;
assign rxstatus[FIFO_WIDTHU-1:0] = rxf_rdusedw;
assign rxf_wrclk = ~usb_clk_i;
assign txf_rdclk = usb_clk_i;
assign rxf_rdclk = clk_i;
assign txf_wrclk = ~clk_i;
 
assign txf_wrclk = ~clk;
assign txf_wrreq = (~txf_wrfull & (address == `WRDATA_ADDR)) ? write : 0;
assign txf_wrdata = writedata;
assign txf_rdclk = usb_clk;
assign txstatus[15] = ~txf_wrfull; //can write
assign txstatus[14:TX_FIFO_WIDTHU+1] = 0;
assign txstatus[TX_FIFO_WIDTHU] = txf_wrfull;
assign txstatus[TX_FIFO_WIDTHU-1:0] = ( txf_wrfull ? {TX_FIFO_WIDTHU{1'b0}} : txf_wrusedw );
 
assign rxf_wrclk = usb_clk;
assign rxf_rdclk = ~clk;
assign rxf_rdreq = (address == `RDDATA_ADDR) ? read : 0;
assign rxstatus[15] = ~rxf_rdempty; //can read
assign rxstatus[14:RX_FIFO_WIDTHU+1] = 0;
assign rxstatus[RX_FIFO_WIDTHU] = rxf_rdfull;
assign rxstatus[RX_FIFO_WIDTHU-1:0] = ( rxf_rdempty ? {RX_FIFO_WIDTHU{1'b0}} : rxf_rdusedw );
 
 
dcfifo txfifo (
.aclr (reset),
.data (txf_wrdata),
.rdclk (txf_rdclk),
.rdreq (txf_rdreq),
.wrclk (txf_wrclk),
.wrreq (txf_wrreq),
.q (txf_rddata),
.rdempty (txf_rdempty),
.wrfull (txf_wrfull),
.wrusedw (txf_wrusedw),
.aclr ( reset_i ),
.data ( txf_wrdata ),
.rdclk ( txf_rdclk ),
.rdreq ( txf_rdreq ),
.wrclk ( txf_wrclk ),
.wrreq ( txf_wrreq ),
.q ( txf_rddata ),
.rdempty ( txf_rdempty ),
.wrfull ( txf_wrfull ),
.wrusedw ( txf_wrusedw ),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty ());
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
txfifo.intended_device_family = "Cyclone IV E",
txfifo.lpm_numwords = FIFO_DEPTH,
txfifo.lpm_numwords = TX_FIFO_DEPTH,
txfifo.lpm_showahead = "OFF",
txfifo.lpm_type = "dcfifo",
txfifo.lpm_width = 8,
txfifo.lpm_widthu = FIFO_WIDTHU,
txfifo.lpm_widthu = TX_FIFO_WIDTHU,
txfifo.overflow_checking = "ON",
txfifo.rdsync_delaypipe = 4,
txfifo.read_aclr_synch = "OFF",
txfifo.rdsync_delaypipe = 11,
txfifo.read_aclr_synch = "ON",
txfifo.underflow_checking = "ON",
txfifo.use_eab = "ON",
txfifo.write_aclr_synch = "OFF",
txfifo.wrsync_delaypipe = 4;
txfifo.write_aclr_synch = "ON",
txfifo.wrsync_delaypipe = 11;
 
dcfifo rxfifo (
.aclr (reset),
.data (rxf_wrdata),
.rdclk (rxf_rdclk),
.rdreq (rxf_rdreq),
.wrclk (rxf_wrclk),
.wrreq (rxf_wrreq),
.q (rxf_rddata),
.rdempty (rxf_rdempty),
.wrfull (rxf_wrfull),
.wrusedw (),
.aclr ( reset_i ),
.data ( rxf_wrdata ),
.rdclk ( rxf_rdclk ),
.rdreq ( rxf_rdreq ),
.wrclk ( rxf_wrclk ),
.wrreq ( rxf_wrreq ),
.q ( rxf_rddata ),
.rdempty ( rxf_rdempty ),
.wrfull ( rxf_wrfull ),
.wrusedw (),
.eccstatus (),
.rdfull (rxf_rdfull),
.rdusedw (rxf_rdusedw),
.wrempty ());
.rdfull ( rxf_rdfull ),
.rdusedw ( rxf_rdusedw ),
.wrempty ());
defparam
rxfifo.intended_device_family = "Cyclone IV E",
rxfifo.lpm_numwords = FIFO_DEPTH,
rxfifo.lpm_numwords = RX_FIFO_DEPTH,
rxfifo.lpm_showahead = "OFF",
rxfifo.lpm_type = "dcfifo",
rxfifo.lpm_width = 8,
rxfifo.lpm_widthu = FIFO_WIDTHU,
rxfifo.lpm_widthu = RX_FIFO_WIDTHU,
rxfifo.overflow_checking = "ON",
rxfifo.rdsync_delaypipe = 4,
rxfifo.read_aclr_synch = "OFF",
rxfifo.rdsync_delaypipe = 11,
rxfifo.read_aclr_synch = "ON",
rxfifo.underflow_checking = "ON",
rxfifo.use_eab = "ON",
rxfifo.write_aclr_synch = "OFF",
rxfifo.wrsync_delaypipe = 4;
 
rxfifo.write_aclr_synch = "ON",
rxfifo.wrsync_delaypipe = 11;
 
always_ff @(negedge clk)
 
/* read usb data to rx fifo */
always_ff @( negedge rxf_wrclk or posedge reset_i )
begin
if(read)
addr <= address;
if( reset_i )
begin
rxf_wrreq <= 1'b0;
rxf_wrdata <= 8'b0;
rxerror <= 1'b0;
rxerrdata <= 8'b0;
end
else
begin
if( ~usb_rd_n_o & rxf_wrfull )
begin
rxerror <= 1'b1;
rxerrdata <= usb_data_io;
end
if( ~rxf_wrfull & ((~usb_rd_n_o & ~usb_rxf_n_i) | rxerror) )
begin
rxf_wrreq <= 1'b1;
if( rxerror )
begin
rxerror <= 1'b0;
rxf_wrdata <= rxerrdata;
end
else
rxf_wrdata <= usb_data_io;
end
else
begin
rxf_wrreq <= 1'b0;
end
end
end
always_ff @(posedge clk)
always_ff @( posedge usb_clk_i or posedge reset_i )
begin
case(addr)
`RDDATA_ADDR: begin
readdata <= rxf_rddata;
end
`TXSTATUSL_ADDR: begin
readdata <= txstatus[7:0];
end
`TXSTATUSH_ADDR: begin
readdata <= txstatus[15:8];
end
`RXSTATUSL_ADDR: begin
readdata <= rxstatus[7:0];
end
`RXSTATUSH_ADDR: begin
readdata <= rxstatus[15:8];
end
default: begin
readdata <= 8'b0;
end
endcase
if( reset_i )
begin
usb_oe_n_o <= 1'b1;
usb_rd_n_o <= 1'b1;
end
else
begin
if( ~usb_rxf_n_i & ~rxf_wrfull & ( usb_txe_n_i | ( ~txf_rdreq & ~error )) & ~rxerror )
begin
usb_oe_n_o <= 1'b0;
if( ~usb_oe_n_o )
usb_rd_n_o <= 1'b0;
end
else
begin
usb_oe_n_o <= 1'b1;
usb_rd_n_o <= 1'b1;
end
end
end
 
always_ff @(negedge txf_rdclk or posedge reset)
/*---------------------------------*/
 
/* write tx fifo data to usb */
always_ff @( negedge txf_rdclk or posedge reset_i )
begin
if(reset)
begin
reg_txf_rdreq <= 1'b0;
error <= 1'b0;
end
else
begin
if(usb_oe_n & (~txf_rdempty | error) & ~usb_txe_n)
begin
reg_txf_rdreq <= 1'b1;
end
if( reset_i )
begin
txf_rdreq <= 1'b0;
end
else
begin
if( ~usb_txe_n_i & ~txf_rdempty & ~error & usb_oe_n_o )
begin
txf_rdreq <= 1'b1;
end
else
begin
reg_txf_rdreq <= 1'b0;
end
if(reg_txf_rdreq)
begin
if(usb_txe_n)
error <= 1'b1;
else
error <= 1'b0;
end
end
txf_rdreq <= 1'b0;
end
end
always_ff @( posedge usb_clk_i or posedge reset_i )
begin
if( reset_i )
begin
usb_wr_n_o <= 1'b1;
error <= 1'b0;
end
else
begin
if( usb_txe_n_i & ~usb_wr_n_o )
begin
error <= 1'b1;
end
if( ~usb_txe_n_i & ( txf_rdreq | error ) & usb_oe_n_o )
begin
usb_wr_n_o <= 1'b0;
if( error )
error <= 1'b0;
end
else
begin
usb_wr_n_o <= 1'b1;
end
end
end
/*-----------------------------*/
 
always_ff @(posedge usb_clk or posedge reset)
 
/* avalon data to tx fifo*/
always_ff @( negedge txf_wrclk or posedge reset_i )
begin
if(reset)
begin
reg_usb_wr_n <= 1'b1;
end
else
begin
if(reg_txf_rdreq)
begin
reg_usb_wr_n <= 1'b0;
end
if( reset_i )
begin
txf_wrreq <= 1'b0;
txf_wrdata <= 8'b0;
end
else
begin
if( write_i & ( address_i == WRDATA_ADDR ) & ~txf_wrfull )
begin
txf_wrreq <= 1'b1;
txf_wrdata <= writedata_i;
end
else
reg_usb_wr_n <= 1'b1;
end
begin
txf_wrreq <= 1'b0;
end
end
end
/*------------------------------------*/
 
always_ff @(posedge usb_clk or posedge reset)
/* rx fifo data to avalon */
always_ff @( posedge clk_i or posedge reset_i )
begin
if(reset)
begin
reg_usb_rd_n <= 1'b1;
reg_usb_oe_n <= 1'b1;
end
else
begin
if((txf_rdempty | usb_txe_n | ~usb_oe_n) & ~rxf_wrfull & ~usb_rxf_n)
begin
reg_usb_oe_n <= 1'b0;
if(~reg_usb_oe_n)
begin
reg_usb_rd_n <= 1'b0;
end
else
begin
reg_usb_rd_n <= 1'b1;
end
end
if( reset_i )
begin
adr_data <= 1'b0;
adr_txsl <= 1'b0;
adr_txsh <= 1'b0;
adr_rxsl <= 1'b0;
adr_rxsh <= 1'b0;
end
else
begin
if( read_i )
begin
if( address_i == RDDATA_ADDR )
adr_data <= 1'b1;
else
adr_data <= 1'b0;
if( address_i == TXSTATUSL_ADDR )
adr_txsl <= 1'b1;
else
adr_txsl <= 1'b0;
if( address_i == TXSTATUSH_ADDR )
adr_txsh <= 1'b1;
else
adr_txsh <= 1'b0;
if( address_i == RXSTATUSL_ADDR )
adr_rxsl <= 1'b1;
else
adr_rxsl <= 1'b0;
if( address_i == RXSTATUSH_ADDR )
adr_rxsh <= 1'b1;
else
adr_rxsh <= 1'b0;
end
end
end
 
always_ff @( posedge clk_i or posedge reset_i )
begin
if( reset_i )
begin
read_pipe <= 1'b0;
end
else
begin
if( read_i )
read_pipe <= 1'b1;
else
begin
reg_usb_oe_n <= 1'b1;
reg_usb_rd_n <= 1'b1;
end
end
read_pipe <= 1'b0;
end
end
 
always_ff @(negedge rxf_wrclk or posedge reset)
always_ff @( negedge rxf_rdclk or posedge reset_i )
begin
if(reset)
begin
reg_rxf_wrreq <= 1'b0;
end
else
begin
if(~usb_rd_n & ~usb_rxf_n)
reg_rxf_wrreq <= 1'b1;
if( reset_i )
begin
rxf_rdreq <= 1'b0;
end
else
begin
if( read_pipe & adr_data & ~rxf_rdempty )
rxf_rdreq <= 1'b1;
else
reg_rxf_wrreq <= 1'b0;
end
rxf_rdreq <= 1'b0;
end
end
 
always_ff @( posedge clk_i or posedge reset_i )
begin
if( reset_i )
begin
read_pipe2 <= 1'b0;
end
else
begin
if( read_pipe )
read_pipe2 <= 1'b1;
else
read_pipe2 <= 1'b0;
end
end
 
always_ff @( posedge clk_i or posedge reset_i )
begin
if( reset_i )
begin
readdata_o <= 8'b0;
end
else
begin
if( read_pipe2 )
begin
if( adr_data )
readdata_o <= rxf_rddata;
else if( adr_txsl )
readdata_o <= txstatus[7:0];
else if( adr_txsh )
readdata_o <= txstatus[15:8];
else if( adr_rxsl )
readdata_o <= rxstatus[7:0];
else if( adr_rxsh )
readdata_o <= rxstatus[15:8];
else
readdata_o <= 8'b0;
end
end
end
/*------------------------------------*/
 
 
endmodule
/usb_ft232h_avalon-mm_interface/trunk/hw/usb_ft232h_hw.tcl
1,26 → 1,26
# TCL File Generated by Component Editor 15.1
# Tue May 31 16:12:41 BRT 2016
# TCL File Generated by Component Editor 16.0
# Wed Dec 07 11:31:54 BRT 2016
# DO NOT MODIFY
 
 
#
# usb_ft232h "USB FT232H" v1.0
# Dmitry Elmanov 2016.05.31.16:12:41
# USB FT232H Avalon-MM core
# usb_ft232h "USB FT232H" v1.3
# Dmitry Elmanov 2016.12.07.11:31:54
#
#
 
#
# request TCL package from ACDS 15.1
# request TCL package from ACDS 16.0
#
package require -exact qsys 15.1
package require -exact qsys 16.0
 
 
#
# module usb_ft232h
#
set_module_property DESCRIPTION "USB FT232H Avalon-MM core"
set_module_property DESCRIPTION ""
set_module_property NAME usb_ft232h
set_module_property VERSION 1.0
set_module_property VERSION 1.3
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP USB
46,22 → 46,34
#
# parameters
#
add_parameter FIFO_DEPTH INTEGER 512 ""
set_parameter_property FIFO_DEPTH DEFAULT_VALUE 512
set_parameter_property FIFO_DEPTH DISPLAY_NAME FIFO_DEPTH
set_parameter_property FIFO_DEPTH TYPE INTEGER
set_parameter_property FIFO_DEPTH UNITS None
set_parameter_property FIFO_DEPTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property FIFO_DEPTH DESCRIPTION ""
set_parameter_property FIFO_DEPTH HDL_PARAMETER true
add_parameter FIFO_WIDTHU INTEGER 9 ""
set_parameter_property FIFO_WIDTHU DEFAULT_VALUE 9
set_parameter_property FIFO_WIDTHU DISPLAY_NAME FIFO_WIDTHU
set_parameter_property FIFO_WIDTHU TYPE INTEGER
set_parameter_property FIFO_WIDTHU UNITS None
set_parameter_property FIFO_WIDTHU ALLOWED_RANGES -2147483648:2147483647
set_parameter_property FIFO_WIDTHU DESCRIPTION ""
set_parameter_property FIFO_WIDTHU HDL_PARAMETER true
add_parameter TX_FIFO_DEPTH INTEGER 512
set_parameter_property TX_FIFO_DEPTH DEFAULT_VALUE 512
set_parameter_property TX_FIFO_DEPTH DISPLAY_NAME TX_FIFO_DEPTH
set_parameter_property TX_FIFO_DEPTH TYPE INTEGER
set_parameter_property TX_FIFO_DEPTH UNITS None
set_parameter_property TX_FIFO_DEPTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property TX_FIFO_DEPTH HDL_PARAMETER true
add_parameter TX_FIFO_WIDTHU INTEGER 9
set_parameter_property TX_FIFO_WIDTHU DEFAULT_VALUE 9
set_parameter_property TX_FIFO_WIDTHU DISPLAY_NAME TX_FIFO_WIDTHU
set_parameter_property TX_FIFO_WIDTHU TYPE INTEGER
set_parameter_property TX_FIFO_WIDTHU UNITS None
set_parameter_property TX_FIFO_WIDTHU ALLOWED_RANGES -2147483648:2147483647
set_parameter_property TX_FIFO_WIDTHU HDL_PARAMETER true
add_parameter RX_FIFO_DEPTH INTEGER 512
set_parameter_property RX_FIFO_DEPTH DEFAULT_VALUE 512
set_parameter_property RX_FIFO_DEPTH DISPLAY_NAME RX_FIFO_DEPTH
set_parameter_property RX_FIFO_DEPTH TYPE INTEGER
set_parameter_property RX_FIFO_DEPTH UNITS None
set_parameter_property RX_FIFO_DEPTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property RX_FIFO_DEPTH HDL_PARAMETER true
add_parameter RX_FIFO_WIDTHU INTEGER 9
set_parameter_property RX_FIFO_WIDTHU DEFAULT_VALUE 9
set_parameter_property RX_FIFO_WIDTHU DISPLAY_NAME RX_FIFO_WIDTHU
set_parameter_property RX_FIFO_WIDTHU TYPE INTEGER
set_parameter_property RX_FIFO_WIDTHU UNITS None
set_parameter_property RX_FIFO_WIDTHU ALLOWED_RANGES -2147483648:2147483647
set_parameter_property RX_FIFO_WIDTHU HDL_PARAMETER true
 
 
#
70,62 → 82,12
 
 
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
 
add_interface_port clock clk clk Input 1
 
 
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
 
add_interface_port reset reset reset Input 1
 
 
#
# connection point ft232h
#
add_interface ft232h conduit end
set_interface_property ft232h associatedClock clock
set_interface_property ft232h associatedReset reset
set_interface_property ft232h ENABLED true
set_interface_property ft232h EXPORT_OF ""
set_interface_property ft232h PORT_NAME_MAP ""
set_interface_property ft232h CMSIS_SVD_VARIABLES ""
set_interface_property ft232h SVD_ADDRESS_GROUP ""
 
add_interface_port ft232h usb_clk clock Input 1
add_interface_port ft232h usb_oe_n oe_n Output 1
add_interface_port ft232h usb_rd_n rd_n Output 1
add_interface_port ft232h usb_wr_n wr_n Output 1
add_interface_port ft232h usb_rxf_n rxf_n Input 1
add_interface_port ft232h usb_txe_n txe_n Input 1
add_interface_port ft232h usb_data data Bidir 8
 
 
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits SYMBOLS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave associatedReset reset
set_interface_property avalon_slave associatedClock clock_sink
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits SYMBOLS
134,7 → 96,7
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 1
set_interface_property avalon_slave readLatency 3
set_interface_property avalon_slave readWaitStates 0
set_interface_property avalon_slave readWaitTime 0
set_interface_property avalon_slave setupTime 0
146,13 → 108,63
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
 
add_interface_port avalon_slave address address Input 4
add_interface_port avalon_slave read read Input 1
add_interface_port avalon_slave readdata readdata Output 8
add_interface_port avalon_slave write write Input 1
add_interface_port avalon_slave writedata writedata Input 8
add_interface_port avalon_slave address_i address Input 4
add_interface_port avalon_slave read_i read Input 1
add_interface_port avalon_slave write_i write Input 1
add_interface_port avalon_slave writedata_i writedata Input 8
add_interface_port avalon_slave readdata_o readdata Output 8
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
 
 
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
 
add_interface_port clock_sink clk_i clk Input 1
 
 
#
# connection point ft232h
#
add_interface ft232h conduit end
set_interface_property ft232h associatedClock clock_sink
set_interface_property ft232h associatedReset reset_sink
set_interface_property ft232h ENABLED true
set_interface_property ft232h EXPORT_OF ""
set_interface_property ft232h PORT_NAME_MAP ""
set_interface_property ft232h CMSIS_SVD_VARIABLES ""
set_interface_property ft232h SVD_ADDRESS_GROUP ""
 
add_interface_port ft232h usb_clk_i usb_clk Input 1
add_interface_port ft232h usb_rxf_n_i usb_rxf_n Input 1
add_interface_port ft232h usb_oe_n_o usb_oe_n Output 1
add_interface_port ft232h usb_wr_n_o usb_wr_n Output 1
add_interface_port ft232h usb_rd_n_o usb_rd_n Output 1
add_interface_port ft232h usb_data_io usb_data Bidir 8
add_interface_port ft232h usb_txe_n_i usb_txe_n Input 1
 
 
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 
add_interface_port reset_sink reset_i reset Input 1
 
/usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h.h File deleted
usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h.h Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_c_style.h =================================================================== --- usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_c_style.h (nonexistent) +++ usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_c_style.h (revision 5) @@ -0,0 +1,33 @@ +/* + * usb_ft232h.h + * + * Created on: 06 may 2016. + * Author: Dmitry Elmanov + */ + +#include + +#ifndef USB_FT232H_H_ +#define USB_FT232H_H_ + + +#define USB_FT232H_WRDATA_ADDR 0x0 +#define USB_FT232H_RDDATA_ADDR 0x1 +#define USB_FT232H_TXSTATUSL_ADDR 0x2 +#define USB_FT232H_TXSTATUSH_ADDR 0x3 +#define USB_FT232H_RXSTATUSL_ADDR 0x4 +#define USB_FT232H_RXSTATUSH_ADDR 0x5 + +#define USB_FT232H_STATUS_READY_MSK 0x8000 +#define USB_FT232H_STATUS_COUNT_MSK 0x7FFF + + +#define IOWR_USB_FT232H_DATA(base, data) IOWR_8DIRECT(base, USB_FT232H_WRDATA_ADDR, data) +#define IORD_USB_FT232H_DATA(base) IORD_8DIRECT(base, USB_FT232H_RDDATA_ADDR) +#define IORD_USB_FT232H_TXSTATUS(base) (IORD_8DIRECT(base, USB_FT232H_TXSTATUSL_ADDR) | (IORD_8DIRECT(base, USB_FT232H_TXSTATUSH_ADDR) << 8)) +#define IORD_USB_FT232H_RXSTATUS(base) (IORD_8DIRECT(base, USB_FT232H_RXSTATUSL_ADDR) | (IORD_8DIRECT(base, USB_FT232H_RXSTATUSH_ADDR) << 8)) +#define IORD_USB_FT232H_TXDATA_COUNT(base) (IORD_USB_FT232H_TXSTATUS(base) & USB_FT232H_STATUS_COUNT_MSK) +#define IORD_USB_FT232H_RXDATA_COUNT(base) (IORD_USB_FT232H_RXSTATUS(base) & USB_FT232H_STATUS_COUNT_MSK) + + +#endif /* USB_FT232H_H_ */
usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_c_style.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_cpp_style.h =================================================================== --- usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_cpp_style.h (nonexistent) +++ usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_cpp_style.h (revision 5) @@ -0,0 +1,87 @@ +/* + * usb_ft232h.h + * + * Created on: 06 february 2017. + * Author: Dmitry Elmanov + */ + +#ifndef USB_FT232H_H_ +#define USB_FT232H_H_ + +#include + + +const alt_u8 USB_FT232H_WRDATA_ADDR = 0x0; //!< Address for write data +const alt_u8 USB_FT232H_RDDATA_ADDR = 0x1; //!< Address for read data +const alt_u8 USB_FT232H_TXSTATUSL_ADDR = 0x2; //!< Address for low byte of TX FIFO status register +const alt_u8 USB_FT232H_TXSTATUSH_ADDR = 0x3; //!< Address for high byte of TX FIFO status register +const alt_u8 USB_FT232H_RXSTATUSL_ADDR = 0x4; //!< Address for low byte of RX FIFO status register +const alt_u8 USB_FT232H_RXSTATUSH_ADDR = 0x5; //!< Address for high byte of RX FIFO status register + +const alt_u16 USB_FT232H_STATUS_READY_MSK = 0x8000; //!< Ready bit mask of RX or TX FIFO status register +const alt_u16 USB_FT232H_STATUS_DATA_SIZE_MSK = 0x7FFF; //!< Data size mask of RX or TX FIFO status register + + + +/*! + * \brief Request data of rx FIFO status register + * \param[in] base Module address + * \return Rx FIFO status register data. + */ +inline alt_u16 usbFT232HGetRxFifoStatus(alt_u32 base) +{ + return (IORD_8DIRECT(base, USB_FT232H_RXSTATUSL_ADDR) | (IORD_8DIRECT(base, USB_FT232H_RXSTATUSH_ADDR) << 8)); +} + +/*! + * \brief Request data of tx FIFO status register + * \param[in] base Module address + * \return Tx FIFO status register data. + */ +inline alt_u16 usbFT232HGetTxFifoStatus(alt_u32 base) +{ + return (IORD_8DIRECT(base, USB_FT232H_TXSTATUSL_ADDR) | (IORD_8DIRECT(base, USB_FT232H_TXSTATUSH_ADDR) << 8)); +} + +/*! + * \brief Request number of bytes stored in rx FIFO + * \param[in] base Module address + * \return Number of bytes stored in rx FIFO + */ +inline alt_u16 usbFT232HGetNumberOfDataInRxFifo(alt_u32 base) +{ + return (usbFT232HGetRxFifoStatus(base) & USB_FT232H_STATUS_DATA_SIZE_MSK); +} + +/*! + * \brief Request number of bytes stored in tx FIFO + * \param[in] base Module address + * \return Number of bytes stored in tx FIFO + */ +inline alt_u16 usbFT232HGetNumberOfDataInTxFifo(alt_u32 base) +{ + return (usbFT232HGetTxFifoStatus(base) & USB_FT232H_STATUS_DATA_SIZE_MSK); +} + +/*! + * \brief Write byte to module + * \param[in] base Module address + * \param[in] byte Byte for write to the FIFO + */ +inline void usbFT232HWriteByte(alt_u32 base, alt_u8 byte) +{ + IOWR_8DIRECT(base, USB_FT232H_WRDATA_ADDR, byte); +} + +/*! + * \brief Read byte from the FIFO + * \param[in] base Module address + * \return Byte read from the FIFO + */ +inline alt_u8 usbFT232HReadByte(alt_u32 base) +{ + return IORD_8DIRECT(base, USB_FT232H_RDDATA_ADDR); +} + + +#endif /* USB_FT232H_H_ */
usb_ft232h_avalon-mm_interface/trunk/sw/usb_ft232h_cpp_style.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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