URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
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- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/w11/trunk/rtl/ibus/ibdr_rk11.vhd
1,4 → 1,4
-- $Id: ibdr_rk11.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- $Id: ibdr_rk11.vhd 317 2010-07-22 19:36:56Z mueller $ |
-- |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
75,7 → 75,7
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset |
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset |
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset |
constant ibaddr_rkda : slv3 := "101"; -- rkba address offset |
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset |
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset |
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset |
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/w11/trunk/rtl/vlib/Makefile.xflow
1,4 → 1,4
# $Id: Makefile.xflow 311 2010-06-30 17:52:37Z mueller $ |
# $Id: Makefile.xflow 317 2010-07-22 19:36:56Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
111,6 → 111,7
# %_map.log map log file (renamed %_map.mrp) |
# %_par.log par log file (renamed %.par) |
# %_pad.log pad file (renamed %_pad.txt) |
# %_twr.log trce log file (renamed %.twr) |
# |
%.ncd %.pcf: %.ngc |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
/w11/trunk/INSTALL.txt
0,0 → 1,7
# $Id: INSTALL.txt 317 2010-07-22 19:36:56Z mueller $ |
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For project installation notes see |
doc/INSTALL.txt |
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For further release and usage notes see |
doc/README.txt |
/w11/trunk/doc/INSTALL.txt
0,0 → 1,139
# $Id: INSTALL.txt 317 2010-07-22 19:36:56Z mueller $ |
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Guide to install and build w11a |
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Table of content: |
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1. Download |
2. Install and setup the build system |
3. Compile UNISIM/SIMPRIM libraries for ghdl |
4. The build system |
5. Building test benches |
6. Building systems |
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1. Download --------------------------------------------------------------- |
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All instructions below assume that the project files reside in a |
working directory with the name represented as <wdir> |
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To download latest tagged version (V0.5) of w11a |
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cd <wdir> |
svn co http://opencores.org/ocsvn/w11/w11/tags/w11a_V0.5 |
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To download latest snapshot of trunk |
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cd <wdir> |
svn co http://opencores.org/ocsvn/w11/w11/trunk |
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2. Install and setup the build system ------------------------------------- |
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The build system for test benches and systems requires |
- the definition of the environment variable RETROBASE |
- that the tools binary directory is in the path |
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For bash and alike use |
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export RETROBASE=<wdir> |
export PATH=$PATH:$RETROBASE/tools/bin |
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After that building functional model based test benches will work. If you |
want to also build post-xst or post-par test benches read next section. |
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3. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------ |
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The build system for test benches also supports test benches run against |
the gate level models derived after the xst, map or par step. In this |
case ghdl has to link against a compiled UNISIM or SIMPRIM library. |
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To make handling of the parallel installion of several WebPack versions |
easy the compiled libraries are stored in sub-directories under $XILINX: |
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$XILINX/ghdl/unisim |
$XILINX/ghdl/simprim |
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Two helper scripts will create these libraries: |
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<setup WebPack, e.g. source .../ISE_DS/settings32.sh> |
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cd $RETROBASE |
xilinx_ghdl_unisim |
xilinx_ghdl_simprim |
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If you have several WebPack versions installed, repeat for each version. |
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4. The build system ------------------------------------------------------- |
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Simulation and synthesis tools usually need a list of the VHDL source |
files, often in proper compilation order (libraries before components). |
The different tools have different formats of these 'project files'. |
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The build system employed in this project is based on |
"VHDL bill of material" or 'vbom' files |
which list for each vhdl source file the libraries and sources for |
the instantiated components, the later via their vbom, and last but |
not least the name of the vhdl source file. All file name are relative |
to the current directory. A recursive traversal through all vbom's gives |
for each vhld module all sources needed to compile it. The vbomconv script |
in tools/bin does this, and generates depending on options |
- make dependency files |
- ISE xst project files |
- ISE ISim project files |
- ghdl commands for analysis, inspection and make step |
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The master make files contain pattern rules like |
%.ngc : %.vbom -- synthesize with xst |
% : %.vbom -- build functional model test bench |
which encapsulate all the vbomconf magic |
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A full w11a is build from more than 80 source files, test benches from |
even more. Using the vbom's a large number of designs can be easily |
maintained. |
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5. Building test benches -------------------------------------------------- |
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To compile a test bench named <tbench> all is needed is |
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make <tbench> |
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The make file will use <tbench>.vbom, create all make dependency files, |
and generate the needed ghdl commands. |
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In many cases the test benches can also be compiled against the gate |
level models derived after the xst, map or par step. To compile them |
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make ghdl_tmp_clean |
make <tbench>_ssim # for post-xst |
make <tbench>_fsim # for post-map |
make <tbench>_tsim # for post-par |
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The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from |
the compilation remains of earlier functional model compiles. |
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6. Building systems ------------------------------------------------------- |
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To generate a bit file for a system named <sys> all is needed is |
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make <sys>.bit |
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The make file will use <sys>.vbom, create all make dependency files, build |
the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce). |
The log files will be named |
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<sys>_xst.log # xst log file |
<sys>_tra.log # translate (ngdbuild) log file (renamed %.bld) |
<sys>_map.log # map log file (renamed %_map.mrp) |
<sys>_par.log # par log file (renamed %.par) |
<sys>_pad.log # pad file (renamed %_pad.txt) |
<sys>_twr.log # trce log file (renamed %.twr) |
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To load the bitfile with WebPack impact into the target board use |
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make <sys>.impact |
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If only the xst or par output is wanted just use |
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make <sys>.ngc |
make <sys>.ncd |
/w11/trunk/doc/w11a_os_guide.txt
1,5 → 1,15
# $ $Id: w11a_os_guide.txt 316 2010-07-16 19:07:47Z mueller $ |
# $Id: w11a_os_guide.txt 317 2010-07-22 19:36:56Z mueller $ |
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Guide to run operating system images on w11a systems |
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Table of content: |
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1. I/O emulation setup |
2. FPGA Board setup |
3. Unix V5 system |
4. 2.11BSD system |
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1. I/O emulation setup ---------------------------------------------------- |
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All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11) |
/w11/trunk/doc/w11a_seq_flow.txt
1,4 → 1,4
$ $Id: w11a_seq_flow.txt 315 2010-07-11 22:18:39Z mueller $ |
# $Id: w11a_seq_flow.txt 317 2010-07-22 19:36:56Z mueller $ |
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The states are |
1. grouped by 'flows', related states are in a dashed box |
/w11/trunk/doc/w11a_tb_guide.txt
1,7 → 1,15
# $ $Id: w11a_tb_guide.txt 316 2010-07-16 19:07:47Z mueller $ |
# $Id: w11a_tb_guide.txt 317 2010-07-22 19:36:56Z mueller $ |
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== Guide to running w11a test benches == |
Guide to running w11a test benches |
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Table of content: |
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1. Unit tests benches |
2. Available unit tests benches |
3. System tests benches |
4. Available system tests benches |
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1. Unit tests benches ----------------------------------------------------- |
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All unit test benches have the same simple structure: |
/w11/trunk/doc/README.txt
0,0 → 1,57
# $Id: README.txt 317 2010-07-22 19:36:56Z mueller $ |
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Release notes for w11a |
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Table of content: |
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1. Documentation |
2. Files |
3. Change Log |
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1. Documentation ---------------------------------------------------------- |
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More detailed information on installation, build and test can be found |
in the doc directory, specifically |
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* README.txt: release notes |
* INSTALL.txt: installation and building test benches and systems |
* w11a_tb_guide.txt: running test benches |
* w11a_os_guide.txt: booting operating systems |
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2. Files ------------------------------------------------------------------ |
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doc Documentation |
rtl VHDL sources |
rtl/bplib - board and component support libs |
rtl/bplib/issi - for ISSI parts |
rtl/bplib/micron - for Micron parts |
rtl/bplib/nexys2 - for Digilent Nexsy2 board |
rtl/bplib/s3board - for Digilent S3BOARD |
rtl/ibus - ibus devices (UNIBUS peripherals) |
rtl/sys_gen - top level designs |
rtl/sys_gen/w11a - top level designs for w11a SoC |
rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2 |
rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD |
rtl/vlib - VHDL component libs |
rtl/vlib/comlib - communication |
rtl/vlib/genlib - general |
rtl/vlib/memlib - memory |
rtl/vlib/rri - remote-register-interface |
rtl/vlib/serport - serial port (UART) |
rtl/vlib/simlib - simulation helper lib |
rtl/vlib/xlib - Xilinx specific components |
rtl/w11a - w11a core |
tools helper programs |
tools/bin - scripts and binaries |
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3. Change Log ------------------------------------------------------------- |
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2010-07-24 - w11a version V0.5 ----------------------------- |
Initial release with |
- w11a CPU core |
- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05 |
- just for fun: iist (not fully implemented and tested yet) |
- two complete system configurations with |
- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3 |
- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2 |
/w11/trunk/doc/w11a_known_issues.txt
1,7 → 1,15
# $ $Id: w11a_known_issues.txt 316 2010-07-16 19:07:47Z mueller $ |
# $Id: w11a_known_issues.txt 317 2010-07-22 19:36:56Z mueller $ |
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1. Known differences between w11a and KB-11C (11/70) |
Summary of known issues for w11a CPU and systems |
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Table of content: |
1. Known differences between w11a and KB-11C (11/70) |
2. Known limitations |
3. Known bugs |
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1. Known differences between w11a and KB-11C (11/70) ---------------------- |
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- the SPL instruction in the 11/70 always fetched the next instruction |
regardless of pending device or even console interrupts. This is known |
as the 'spl bug', see |
30,7 → 38,7
depends on them, therefore they are considered acceptable implementation |
differences |
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2. Known limitations |
2. Known limitations ------------------------------------------------------ |
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- some programs use timing loops based on the execution speed of the |
original processors. This can lead to spurious timeouts, especially |
44,7 → 52,7
--> a 'watch dog' mechanism will be added in a future version which |
suspends the CPU when the server doesn't respond fast enough. |
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3. Known bugs |
3. Known bugs ------------------------------------------------------------- |
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- TCK-036 pri=L: RK11: hardware poll not working |
The RK11/RK05 hardware poll logic is probably no reflecting the |