URL
https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk
Subversion Repositories virtex7_pcie_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 41 to Rev 42
- ↔ Reverse comparison
Rev 41 → Rev 42
/virtex7_pcie_dma/trunk/firmware/sources/templates/pcie_package.vhd.template
216,7 → 216,7
-- Bitfields of Control Record |
{% endif %} |
{% if register.parent.is_sequence %} |
{% if register.index == 0 %} |
{% if register.index == 0 and ((not register.parent.parent.is_sequence) or register.parent.index == 0) %} |
type {{register.type_name|lower|prepend('bitfield_')|append('_t_type' if register.has_trigger_bitfields else '_w_type' if register.has_write_bitfields else '_r_type')}} is record |
{% for bf in register.bitfield if bf.is_write or bf.is_trigger %} |
{{"%-30s"|format(bf.name)}} : {{"%-32s"|format(bf|vhdl_logic_vector|semi)}} {{bf.desc|vhdl_comment(70)}} |
263,7 → 263,7
{% for register in registers if register is in_group('Bar2') %} |
{% for bf in register.bitfield %} |
{% if bf.is_write or bf.is_trigger %} |
constant {{"%-40s"|format(bf.full_name|prepend('REG_')|append('_C'))}}: {{"%-32s"|format(bf|vhdl_logic_vector)}} := {{ "%-22s"|format(bf.default|vhdl_constant(bf.bits)|semi) }} {{bf.desc|vhdl_comment(112)}} |
constant {{"%-40s"|format(bf.full_name|prepend('REG_')|append('_C'))}}: {{"%-32s"|format(bf|vhdl_logic_vector)}} := {{ "%-22s"|format(bf|vhdl_string_or_constant|semi) }} {{bf.desc|vhdl_comment(112)}} |
{% endif %} |
{% endfor %} |
{% endfor %} |
/virtex7_pcie_dma/trunk/software/wuppercodegen/wuppercodegen/filter.py
34,6 → 34,7
env.filters['version'] = version |
|
env.filters['vhdl_constant'] = vhdl_constant |
env.filters['vhdl_string_or_constant'] = vhdl_string_or_constant |
env.filters['vhdl_logic_vector'] = vhdl_logic_vector |
env.filters['vhdl_downto'] = vhdl_downto |
env.filters['vhdl_value'] = vhdl_value |
105,6 → 106,8
fmtstring = '"{0:0' + str(bits) + 'b}"' |
return fmtstring.format(value) |
|
def vhdl_string_or_constant(bitfield): |
return vhdl_constant(bitfield.default, bitfield.bits) if isinstance(bitfield.default, (int, long)) else bitfield.default[bitfield.parent.index] if isinstance(bitfield.default, list) else bitfield.default |
|
def vhdl_logic_vector(bitfield): |
r"""Format the bitfield value as std_logic_vector(\ *hi* downto *lo*).""" |