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URL https://opencores.org/ocsvn/zet86/zet86/trunk

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Rev 43 → Rev 44

/trunk/rtl-model/defines.v
23,4 → 23,4
`define ADD_IP `IR_SIZE'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8'h90
 
//`define DEBUG 1
`define DEBUG 1
/trunk/impl/virtex4-ml403ep/lcd/test_lcd_cntrl.v
1,16 → 1,20
module lcd_test (
// Pad signals
input sys_clk_in_,
input clk_,
output rs_,
output rw_,
output e_,
inout [7:4] db_,
input but_
inout [3:0] db_,
input but_,
output [5:0] led_
);
 
// Registers
reg [4:0] cnt;
 
// Module instantiations
lcd_display lcd0 (
.clk (sys_clk_in_),
lcd_display4 lcd0 (
.clk (cnt[4]),
.rst (but_),
.f1 (64'h123456f890abcde7),
.f2 (64'h7645321dcbaef987),
17,10 → 21,13
.m1 (16'b0101011101011111),
.m2 (16'b1110101110101111),
 
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_(db_)
.rs_ (rs_),
.rw_ (rw_),
.e_ (e_),
.db_ (db_),
.st (led_)
);
 
// Behaviour
always @(posedge clk_) cnt <= cnt + 5'b1;
endmodule
/trunk/impl/virtex4-ml403ep/lcd/ml403.ucf
1,16 → 1,27
NET sys_clk_in_ TNM_NET = "sys_clk_in_";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in_" 9.9 ns HIGH 50 %;
NET clk_ TNM_NET = "clk_";
TIMESPEC "TSSYSCLK" = PERIOD "clk_" 9.9 ns HIGH 50 %;
 
NET sys_clk_in_ LOC = AE14;
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
NET clk_ LOC = AE14;
NET clk_ IOSTANDARD = LVCMOS33;
 
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
 
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
NET db_[3] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[2] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[1] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[0] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
NET but_ LOC = B6; # C Button
NET but_ LOC = B6; # C Button
 
NET led_[0] LOC = G5; #GPLED0
NET led_[1] LOC = G6; #GPLED1
NET led_[2] LOC = A11; #GPLED2
NET led_[3] LOC = A12; #GPLED3
 
# North-East-South-West-Center LEDs
NET led_[4] LOC = C6; # C LED
NET led_[5] LOC = F9; # W LED
#NET led_[6] LOC = A5; # S LED
#NET led_[7] LOC = E10; # E LED
/trunk/impl/virtex4-ml403ep/sim/test_kotku.v
37,7 → 37,9
.sram_bw_ (s_bw),
.sram_cen_ (s_ce),
.sram_adv_ld_n_ (s_adv),
.flash_ce2_ (f_ce)
.flash_ce2_ (f_ce),
 
.but_ (1'b0)
);
 
flash_stub fs0 (
/trunk/impl/virtex4-ml403ep/sim/t.do
1,7 → 1,7
vdel -all -lib work
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
vlib work
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../kotku.v ../clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/vdu.v ../../../soc/vga/char_rom_b16.v ../../../soc/vga/ram2k_b16_attr.v ../../../soc/vga/ram2k_b16.v ../memory/flash_cntrl.v ../memory/zbt_cntrl.v CY7C1354BV25.v
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../dbg/hw_dbg.v
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl
add wave -label clk100 /testbench/clk
49,6 → 49,8
add wave -label we /testbench/kotku/we
add wave -label ack /testbench/kotku/ack
add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec
add wave -divider zbt
add wave -divider vdu
add wave -radix hexadecimal /testbench/kotku/vdu0/*
add wave -divider hw_dbg
add wave -radix hexadecimal /testbench/kotku/dbg0/*
run 50us
/trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj
14,9 → 14,11
verilog work "../../../../rtl-model/fetch.v"
verilog work "../../../../rtl-model/exec.v"
verilog work "../../../../soc/vga/rtl/vdu.v"
verilog work "../../../../soc/keyb/rtl/ps2_keyb.v"
verilog work "../../../../rtl-model/cpu.v"
verilog work "../../mem/zbt_cntrl.v"
verilog work "../../mem/flash_cntrl.v"
verilog work "../../dbg/hw_dbg.v"
verilog work "../clock.v"
verilog work "../kotku.v"
verilog work "../../lcd/lcd_display.v"
/trunk/impl/virtex4-ml403ep/syn/kotku.v
25,7 → 25,11
output rw_,
output e_,
output [7:4] db_,
input but_,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
`endif
 
output tft_lcd_clk_,
89,7 → 93,19
wire intr;
wire inta;
wire clk_100M;
wire rst;
wire [15:0] vdu_dat_i;
wire [11:1] vdu_adr_i;
wire vdu_we_i;
wire [ 1:0] vdu_sel_i;
wire vdu_stb_i;
wire vdu_tga_i;
 
wire [19:1] zbt_adr_i;
wire zbt_we_i;
wire [ 1:0] zbt_sel_i;
wire zbt_stb_i;
 
`ifdef DEBUG
wire [35:0] control0;
wire [ 5:0] funct;
104,9 → 120,18
wire [ 2:0] cnt;
wire op;
wire [15:0] r1, r2;
reg rst;
`else
wire rst;
 
wire [15:0] dbg_vdu_dat_o;
wire [11:1] dbg_vdu_adr_o;
wire dbg_vdu_we_o;
wire dbg_vdu_stb_o;
wire [ 1:0] dbg_vdu_sel_o;
wire dbg_vdu_tga_o;
 
wire [19:1] dbg_zbt_adr_o;
wire dbg_zbt_we_o;
wire [ 1:0] dbg_zbt_sel_o;
wire dbg_zbt_stb_o;
`endif
 
// Register declarations
126,13 → 151,13
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_rst_i (rst_lck),
.wb_dat_i (vdu_dat_i),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (adr[11:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_sel_i (sel),
.wb_adr_i (vdu_adr_i),
.wb_we_i (vdu_we_i),
.wb_tga_i (vdu_tga_i),
.wb_sel_i (vdu_sel_i),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_ack_o (vdu_ack_o),
151,7 → 176,7
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (flash_dat_o),
.wb_adr_i (adr[17:1]),
.wb_adr_i (adr[16:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_stb_i (flash_stb),
171,14 → 196,14
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_rst_i (rst_lck),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (zbt_stb),
.wb_cyc_i (zbt_stb),
.wb_adr_i (zbt_adr_i),
.wb_we_i (zbt_we_i),
.wb_sel_i (zbt_sel_i),
.wb_stb_i (zbt_stb_i),
.wb_cyc_i (zbt_stb_i),
.wb_ack_o (zbt_ack),
 
// Pad signals
282,6 → 307,32
.lcd_dat_ (db_)
);
 
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst_lck),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
.butw_ (butw_),
.butn_ (butn_),
.buts_ (buts_),
 
.vdu_dat_o (dbg_vdu_dat_o),
.vdu_adr_o (dbg_vdu_adr_o),
.vdu_we_o (dbg_vdu_we_o),
.vdu_stb_o (dbg_vdu_stb_o),
.vdu_sel_o (dbg_vdu_sel_o),
.vdu_tga_o (dbg_vdu_tga_o),
.vdu_ack_i (vdu_ack_sync[1]),
 
.zbt_dat_i (zbt_dat_o),
.zbt_adr_o (dbg_zbt_adr_o),
.zbt_we_o (dbg_zbt_we_o),
.zbt_sel_o (dbg_zbt_sel_o),
.zbt_stb_o (dbg_zbt_stb_o),
.zbt_ack_i (zbt_ack)
);
 
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
289,6 → 340,28
assign m2 = 16'b1111101110011111;
 
assign pc = (cs << 4) + ip;
 
assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o;
assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1];
assign vdu_we_i = rst ? dbg_vdu_we_o : we;
assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel;
assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena;
assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga;
assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr;
assign zbt_we_i = rst ? dbg_zbt_we_o : we;
assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel;
assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb;
`else
assign vdu_dat_i = dat_o;
assign vdu_adr_i = adr[11:1];
assign vdu_we_i = we;
assign vdu_sel_i = sel;
assign vdu_stb_i = stb & cyc & vdu_arena;
assign vdu_tga_i = tga;
assign zbt_adr_i = adr;
assign zbt_we_i = we;
assign zbt_sel_i = sel;
assign zbt_stb_i = zbt_stb;
`endif
 
assign io_dat_i = flash_io_arena ? flash_dat_o
330,7 → 403,7
// Behaviour
// vdu_stb_sync[0]
always @(posedge tft_lcd_clk_)
vdu_stb_sync[0] <= stb & cyc & vdu_arena;
vdu_stb_sync[0] <= vdu_stb_i;
 
// vdu_stb_sync[1]
always @(posedge clk)
348,11 → 421,7
: ((tga && stb && cyc && we && adr[15:8]==8'hf1) ?
dat_o : io_reg );
 
`ifdef DEBUG
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : (but_ ? 1'b0 : rst );
`else
`ifndef DEBUG
assign rst = rst_lck;
`endif
endmodule
/trunk/impl/virtex4-ml403ep/syn/ml403.ucf
100,17 → 100,20
NET tft_lcd_vsync_ SLEW = FAST;
NET tft_lcd_vsync_ DRIVE = 8;
 
#NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
#NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
#NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
NET e_ LOC = AE13 | IOSTANDARD = LVCMOS33 | TIG; # LCD_E
NET rs_ LOC = AC17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RS
NET rw_ LOC = AB17 | IOSTANDARD = LVCMOS33 | TIG; # LCD_RW
 
#NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
#NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
#NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
#NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
NET db_[7] LOC = AF12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB7
NET db_[6] LOC = AE12 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB6
NET db_[5] LOC = AC10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB5
NET db_[4] LOC = AB10 | IOSTANDARD = LVCMOS33 | TIG; # LCD_DB4
 
#NET but_ LOC = B6; # C Button
#NET but2_ LOC = A6; # S Button
NET butc_ LOC = B6; # C Button
NET butw_ LOC = E9; # W Button
NET bute_ LOC = F10; # E Button
NET butn_ LOC = E7; # N Button
NET buts_ LOC = A6; # S Button
 
#NET led_[0] LOC = G5; #GPLED0
#NET led_[1] LOC = G6; #GPLED1
/trunk/impl/virtex4-ml403ep/dbg/hw_dbg.v
0,0 → 1,411
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <zeus@opencores.org>
*
* Nobody can figure out what this file is for... hehe
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
 
`timescale 1ns/10ps
 
module hw_dbg (
input clk,
input rst_lck,
output reg rst,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
 
// Wishbone master interface for the VDU
output reg [15:0] vdu_dat_o,
output reg [11:1] vdu_adr_o,
output vdu_we_o,
output vdu_stb_o,
output [ 1:0] vdu_sel_o,
output reg vdu_tga_o,
input vdu_ack_i,
 
// Wishbone master interface for the ZBT SRAM
input [15:0] zbt_dat_i,
output [19:1] zbt_adr_o,
output zbt_we_o,
output [ 1:0] zbt_sel_o,
output reg zbt_stb_o,
input zbt_ack_i
);
 
// Registers and nets
reg [ 5:0] st;
reg op;
reg [ 6:0] cur;
reg mr, ml, md, mu, dm;
reg br, bl, bd, bu, bc;
reg [15:0] cnt;
reg [ 4:0] i;
reg [19:0] adr;
reg [ 2:0] sp;
reg [15:0] col;
reg [ 3:0] nibb;
reg [ 7:0] low_adr;
 
wire [7:0] o;
wire cur_dump;
wire action;
wire [2:0] off;
wire [3:0] nib, inc_nib, dec_nib;
wire up_down;
wire left_right;
wire spg;
 
// Module instantiations
init_msg msg0 (
.i (i),
.o (o)
);
 
inc i0 (
.i (nib),
.o (inc_nib)
);
 
dec d0 (
.i (nib),
.o (dec_nib)
);
 
// Continuous assignments
assign vdu_we_o = op;
assign vdu_stb_o = op;
assign vdu_sel_o = 2'b11;
assign zbt_we_o = 1'b0;
assign zbt_sel_o = 2'b11;
assign cur_dump = (cur < 7'd25 && cur > 7'd19);
assign off = cur - 7'd20;
assign nib = off==3'd0 ? adr[19:16]
: (off==3'd1 ? adr[15:12]
: (off==3'd2 ? adr[11:8]
: (off==3'd3 ? adr[7:4] : adr[3:0])));
 
assign left_right = mr | ml;
assign up_down = mu | md;
assign action = left_right | up_down | dm;
assign spg = sp>3'b0;
assign zbt_adr_o = { adr[19:5] + low_adr[7:4], low_adr[3:0] };
 
// Behaviour
always @(posedge clk)
if (rst_lck)
begin
vdu_dat_o <= 16'd12;
vdu_adr_o <= 11'h4;
vdu_tga_o <= 1'b1;
st <= 6'd0;
op <= 1'b1;
i <= 4'h0;
zbt_stb_o <= 1'b0;
end
else
case (st)
6'd0: if (vdu_ack_i) begin
vdu_dat_o <= { 8'h06, o };
vdu_adr_o <= i + 5'h4;
vdu_tga_o <= 1'b0;
st <= (i==5'd21) ? 6'h2 : 6'h1;
op <= 1'b0;
i <= i + 5'h1;
end
6'd1: if (!vdu_ack_i) begin
st <= 6'h0;
op <= 1'b1;
i <= i;
end
6'd2: // main wait state
if (!vdu_ack_i && action) begin
vdu_dat_o <= mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: ((ml && cur==7'd20) ? 7'd15 : cur - 7'b1);
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= left_right ? 6'h3 : (dm ? 6'h5 : 6'h4);
op <= left_right;
col <= 16'd80;
sp <= 2'h3;
nibb <= 4'h0;
end
6'd3: if (vdu_ack_i) begin
vdu_dat_o <= 16'h0;
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= 6'h2;
op <= 1'b0;
end
6'd4: // redraw the mem_dump counter
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h03, itoa(nib) };
vdu_adr_o <= cur;
vdu_tga_o <= 1'b0;
st <= 6'h3;
op <= 1'b1;
end
6'd5: // memory dump
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h05, spg ? 8'h20 : itoa(nibb) };
vdu_adr_o <= col;
vdu_tga_o <= 1'b0;
st <= 6'h6;
op <= 1'b1;
sp <= spg ? (sp - 3'b1) : 3'd4;
col <= col + 16'd1;
nibb <= spg ? nibb : (nibb + 4'h2);
end
6'd6: if (vdu_ack_i) begin
st <= (col==16'd160) ? 6'h7 : 6'h5;
op <= 1'b0;
end
6'd7: begin
low_adr <= 8'h0;
st <= 6'h8;
end
6'd8: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h5, itoa(zbt_adr_o[7:4]) };
vdu_adr_o <= col;
st <= 6'd9;
op <= 1'b1;
end
6'd9: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd10: if (!zbt_ack_i) begin
st <= 6'd11;
zbt_stb_o <= 1'b1;
end
6'd11: if (zbt_ack_i) begin
st <= 6'd12;
zbt_stb_o <= 1'b0;
end
6'd12: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[15:12]) };
vdu_adr_o <= col;
st <= 6'd13;
op <= 1'b1;
end
6'd13: if (vdu_ack_i) begin
st <= 6'd14;
op <= 1'b0;
col <= col + 16'd1;
end
6'd14: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[11:8]) };
vdu_adr_o <= col;
st <= 6'd15;
op <= 1'b1;
end
6'd15: if (vdu_ack_i) begin
st <= 6'd16;
op <= 1'b0;
col <= col + 16'd1;
end
6'd16: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[7:4]) };
vdu_adr_o <= col;
st <= 6'd17;
op <= 1'b1;
end
6'd17: if (vdu_ack_i) begin
st <= 6'd18;
op <= 1'b0;
col <= col + 16'd1;
end
6'd18: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[3:0]) };
vdu_adr_o <= col;
st <= 6'd19;
op <= 1'b1;
end
6'd19: if (vdu_ack_i) begin
st <= (zbt_adr_o[4:1]==4'hf) ? 6'd22 : 6'd20;
op <= 1'b0;
col <= col + 16'd1;
low_adr <= low_adr + 8'h1;
end
6'd20: if (!vdu_ack_i) begin
vdu_dat_o <= 16'h0720;
vdu_adr_o <= col;
st <= 6'd21;
op <= 1'b1;
end
6'd21: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd22: st <= (low_adr==8'h0) ? 6'd2 : 6'd8;
endcase
 
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : ((butc_ && cur==7'd12) ? 1'b0 : rst);
 
// cur
always @(posedge clk)
cur <= rst_lck ? 7'd12 : (mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: (ml ? (cur==7'd20 ? 7'd15 : cur - 7'b1) : cur));
 
// adr
always @(posedge clk)
adr <= rst_lck ? 16'h0
: (mu ? (off==3'd0 ? { inc_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], inc_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], inc_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], inc_nib, adr[3:0] }
: { adr[19:4], inc_nib }))))
: (md ? (off==3'd0 ? { dec_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], dec_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], dec_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], dec_nib, adr[3:0] }
: { adr[19:4], dec_nib })))) : adr));
 
// mr - move right
always @(posedge clk)
mr <= rst_lck ? 1'b0 : (bute_ && !br
&& cnt==16'h0 && cur != 7'd24);
 
// br - button right
always @(posedge clk) br <= (cnt==16'h0 ? bute_ : br);
 
// ml - move right
always @(posedge clk)
ml <= rst_lck ? 1'b0 : (butw_ && !bl
&& cnt==16'h0 && cur != 7'd12);
 
// bl - button right
always @(posedge clk) bl <= (cnt==16'h0 ? butw_ : bl);
 
// md - move down
always @(posedge clk)
md <= rst_lck ? 1'b0 : (buts_ && !bd && cnt==16'h0 && cur_dump);
 
// bd - button down
always @(posedge clk) bd <= (cnt==16'h0 ? buts_ : bd);
 
// mu - move up
always @(posedge clk)
mu <= rst_lck ? 1'b0 : (butn_ && !bu && cnt==16'h0 && cur_dump);
 
// bu - button up
always @(posedge clk) bu <= (cnt==16'h0 ? butn_ : bu);
 
// dm - dump
always @(posedge clk)
dm <= rst_lck ? 1'b0 : (butc_ && !bc && cur==7'd13);
 
// bc - center button
always @(posedge clk) bc <= (cnt==16'h0 ? butc_ : bc);
 
// cnt - button counter
always @(posedge clk) cnt <= cnt + 1'b1;
 
function [7:0] itoa;
input [3:0] i;
begin
if (i < 8'd10) itoa = i + 8'h30;
else itoa = i + 8'h57;
end
endfunction
endmodule
 
module init_msg (
input [4:0] i,
output reg [7:0] o
);
 
// Behaviour
always @(i)
case (i)
5'h00: o <= 8'h68; // h
5'h01: o <= 8'h77; // w
5'h02: o <= 8'h5f; // _
5'h03: o <= 8'h64; // d
5'h04: o <= 8'h62; // b
5'h05: o <= 8'h67; // g
5'h06: o <= 8'h20; //
5'h07: o <= 8'h5b; // [
5'h08: o <= 8'h43; // C
5'h09: o <= 8'h44; // D
5'h0a: o <= 8'h57; // W
5'h0b: o <= 8'h42; // B
5'h0c: o <= 8'h5d; // ]
5'h0d: o <= 8'h20; //
5'h0f: o <= 8'h78; // x
default: o <= 8'h30; // 0
endcase
endmodule
 
module inc (
input [3:0] i,
output reg [3:0] o
);
 
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'h1;
4'h1: o <= 4'h2;
4'h2: o <= 4'h3;
4'h3: o <= 4'h4;
4'h4: o <= 4'h5;
4'h5: o <= 4'h6;
4'h6: o <= 4'h7;
4'h7: o <= 4'h8;
4'h8: o <= 4'h9;
4'h9: o <= 4'ha;
4'ha: o <= 4'hb;
4'hb: o <= 4'hc;
4'hc: o <= 4'hd;
4'hd: o <= 4'he;
4'he: o <= 4'hf;
default: o <= 4'h0;
endcase
endmodule
 
module dec (
input [3:0] i,
output reg [3:0] o
);
 
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'hf;
4'h1: o <= 4'h0;
4'h2: o <= 4'h1;
4'h3: o <= 4'h2;
4'h4: o <= 4'h3;
4'h5: o <= 4'h4;
4'h6: o <= 4'h5;
4'h7: o <= 4'h6;
4'h8: o <= 4'h7;
4'h9: o <= 4'h8;
4'ha: o <= 4'h9;
4'hb: o <= 4'ha;
4'hc: o <= 4'hb;
4'hd: o <= 4'hc;
4'he: o <= 4'hd;
default: o <= 4'he;
endcase
endmodule
/trunk/impl/virtex4-ml403ep/mem/flash_cntrl.v
22,7 → 22,7
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [17:1] wb_adr_i,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
51,8 → 51,7
// flash_addr, 21 bits
always @(posedge wb_clk_i)
flash_addr_ <= wb_tga_i ? { 1'b1, base, wb_adr_i[8:1] }
: { 5'h0, wb_adr_i[17],
wb_adr_i[15:1] };
: { 5'h0, wb_adr_i[16:1] };
 
always @(posedge wb_clk_i) flash_ce2_ <= op;
always @(posedge wb_clk_i) wb_ack_o <= op;
/trunk/soc/bios/rombios.c
960,7 → 960,7
}
}
 
static char bios_svn_version_string[] = "$Revision: 1.9 $ $Date: 2009-02-06 03:48:27 $";
static char bios_svn_version_string[] = "$Revision: 1.10 $ $Date: 2009-02-19 19:06:56 $";
 
//--------------------------------------------------------------------------
// print_bios_banner
2101,7 → 2101,7
 
;; Keyboard
SET_INT_VECTOR(0x09, #0xF000, #int09_handler)
SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
;SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
 
xor ax, ax
mov ds, ax

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