URL
https://opencores.org/ocsvn/m1_core/m1_core/trunk
Subversion Repositories m1_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 46 to Rev 47
- ↔ Reverse comparison
Rev 46 → Rev 47
/trunk/doc/TODO.txt
3,9 → 3,7
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Implementation |
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Current implementation lacks separate L1 caches (there's a unified L2 into the DDR Controller). |
Also an INTC (Interrupt Controller) should be required to handle 32 IRQs and pass only one to the CPU. |
The CPU has no interrupt handling at all so it must be added. |
At the moment the CPU has no interrupt handling. |
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ISA Functional Verification |
24,5 → 22,5
- JUMP/BRANCH |
Jump are working (J JAL JR JALR) including the delay slot. |
Equality branches (BEQ BNE) execute 2 delay slots rather than just 1. |
Disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work. |
Disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet. |
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