URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 47 to Rev 48
- ↔ Reverse comparison
Rev 47 → Rev 48
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_user.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_user.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_user.v |
// Description : PIPE User Module for 7 Series Transceiver |
125,37 → 125,37
); |
|
//---------- Input Registers --------------------------- |
reg pclk_sel_reg1; |
reg resetovrd_start_reg1; |
reg txresetdone_reg1; |
reg rxresetdone_reg1; |
reg txelecidle_reg1; |
reg txcompliance_reg1; |
reg rxcdrlock_reg1; |
reg rxvalid_reg1; |
reg rxstatus_reg1; |
reg rate_done_reg1; |
reg rst_idle_reg1; |
reg rate_rxsync_reg1; |
reg rate_idle_reg1; |
reg rate_gen3_reg1; |
reg rxeq_adapt_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1; |
|
reg pclk_sel_reg2; |
reg resetovrd_start_reg2; |
reg txresetdone_reg2; |
reg rxresetdone_reg2; |
reg txelecidle_reg2; |
reg txcompliance_reg2; |
reg rxcdrlock_reg2; |
reg rxvalid_reg2; |
reg rxstatus_reg2; |
reg rate_done_reg2; |
reg rst_idle_reg2; |
reg rate_rxsync_reg2; |
reg rate_idle_reg2; |
reg rate_gen3_reg2; |
reg rxeq_adapt_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2; |
|
//---------- Internal Signal --------------------------- |
reg [ 1:0] oobclk_cnt = 2'd0; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express |
-- |
65,15 → 65,16
|
entity cl_a7pcie_x4 is |
generic ( |
CFG_VEND_ID : std_logic_vector := X"4953"; |
CFG_DEV_ID : std_logic_vector := X"5507"; |
CFG_VEND_ID : std_logic_vector := X"10EE"; |
CFG_DEV_ID : std_logic_vector := X"7024"; |
CFG_REV_ID : std_logic_vector := X"00"; |
CFG_SUBSYS_VEND_ID : std_logic_vector := X"10EE"; |
CFG_SUBSYS_ID : std_logic_vector := X"0701"; |
CFG_SUBSYS_ID : std_logic_vector := X"0007"; |
ALLOW_X8_GEN2 : string := "FALSE"; |
PIPE_PIPELINE_STAGES : integer := 1; |
AER_BASE_PTR : bit_vector := X"000"; |
AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE"; |
AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE"; |
AER_CAP_MULTIHEADER : string := "FALSE"; |
AER_CAP_NEXTPTR : bit_vector := X"000"; |
AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000"; |
89,7 → 90,7
|
C_DATA_WIDTH : integer := 64; |
CARDBUS_CIS_POINTER : bit_vector := X"00000000"; |
CLASS_CODE : bit_vector := X"FFFFFF"; |
CLASS_CODE : bit_vector := X"058000"; |
CMD_INTX_IMPLEMENTED : string := "TRUE"; |
CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE"; |
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2"; |
161,7 → 162,7
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0"; |
PCIE_CAP_NEXTPTR : bit_vector := X"00"; |
|
PM_CAP_DSI : string := "TRUE"; |
PM_CAP_DSI : string := "FALSE"; |
PM_CAP_D1SUPPORT : string := "FALSE"; |
PM_CAP_D2SUPPORT : string := "FALSE"; |
PM_CAP_NEXTPTR : bit_vector := X"60"; |
297,6 → 298,7
|
PL_AUTO_CONFIG : integer := 0; |
PL_FAST_TRAIN : string := "FALSE"; |
|
PCIE_EXT_CLK : string := "TRUE"; |
|
PM_BASE_PTR : bit_vector := X"40"; |
398,7 → 400,6
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE"; |
|
AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE"; |
AER_CAP_ID : bit_vector := X"0001"; |
AER_CAP_VERSION : bit_vector := X"1"; |
|
657,7 → 658,7
|
attribute CORE_GENERATION_INFO : string; |
attribute CORE_GENERATION_INFO of pcie_7x : ARCHITECTURE is |
"cl_a7pcie_x4,pcie_7x_v1_9,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}"; |
"cl_a7pcie_x4,pcie_7x_v1_10,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}"; |
component cl_a7pcie_x4_pcie_top is |
generic ( |
C_DATA_WIDTH : INTEGER range 32 to 128 := 64; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_bram_top_7x.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_bram_top_7x.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description : bram wrapper for Tx and Rx |
-- given the pcie block attributes calculate the number of brams |
-- and pipeline stages and instantiate the brams |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_pipeline.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_pipe_pipeline.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description: PIPE module for 7-Series PCIe Block |
-- |
-- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_brams_7x.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_brams_7x.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description : pcie bram wrapper |
-- arrange and connect brams |
-- implement address decoding, datapath muxing and pipeline stages |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_gt_rx_valid_filter_7x.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
---- Description: GTX module for 7-series Integrated PCIe Block |
---- |
---- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_drp.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_drp.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_drp.v |
// Description : PIPE DRP Module for 7 Series Transceiver |
104,21 → 104,21
); |
|
//---------- Input Registers --------------------------- |
reg gtxreset_reg1; |
reg [ 1:0] rate_reg1; |
reg x16x20_mode_reg1; |
reg x16_reg1; |
reg start_reg1; |
reg [15:0] do_reg1; |
reg rdy_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; |
|
reg gtxreset_reg2; |
reg [ 1:0] rate_reg2; |
reg x16x20_mode_reg2; |
reg x16_reg2; |
reg start_reg2; |
reg [15:0] do_reg2; |
reg rdy_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; |
|
//---------- Internal Signals -------------------------- |
reg [ 1:0] load_cnt = 2'd0; |
129,7 → 129,7
|
//---------- Output Registers -------------------------- |
reg done = 1'd0; |
reg [ 2:0] fsm = 1; |
reg [ 2:0] fsm = 0; |
|
//---------- DRP Address ------------------------------- |
// DRP access for *RXCDR_EIDLE includes |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_rx.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description: |
-- TRN to AXI RX module. Instantiates pipeline and null generator RX |
-- submodules. |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_lane.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_pipe_lane.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: PIPE per lane module for 7-Series PCIe Block |
-- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_top.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_gt_top.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
---- Description: GTX module for 7-series Integrated PCIe Block |
---- |
---- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_wrapper.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_qpll_wrapper.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : qpll_wrapper.v |
// Description : QPLL Wrapper Module for 7 Series Transceiver |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_tx.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
-- AXI to TRN TX module. Instantiates pipeline and throttle control TX |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_reset.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_qpll_reset.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : qpll_reset.v |
// Description : QPLL Reset Module for 7 Series Transceiver |
97,21 → 97,21
); |
|
//---------- Input Register ---------------------------- |
reg mmcm_lock_reg1; |
reg [PCIE_LANE-1:0] cplllock_reg1; |
reg [(PCIE_LANE-1)>>2:0]drp_done_reg1; |
reg [(PCIE_LANE-1)>>2:0]qplllock_reg1; |
reg [ 1:0] rate_reg1; |
reg [PCIE_LANE-1:0] qpllreset_in_reg1; |
reg [PCIE_LANE-1:0] qpllpd_in_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1; |
|
reg mmcm_lock_reg2; |
reg [PCIE_LANE-1:0] cplllock_reg2; |
reg [(PCIE_LANE-1)>>2:0]drp_done_reg2; |
reg [(PCIE_LANE-1)>>2:0]qplllock_reg2; |
reg [ 1:0] rate_reg2; |
reg [PCIE_LANE-1:0] qpllreset_in_reg2; |
reg [PCIE_LANE-1:0] qpllpd_in_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2; |
|
//---------- Output Register -------------------------- |
reg ovrd = 1'd0; |
120,18 → 120,18
reg [ 3:0] fsm = 2; |
|
//---------- FSM --------------------------------------- |
localparam FSM_IDLE = 0; |
localparam FSM_WAIT_LOCK = 1; |
localparam FSM_MMCM_LOCK = 2; |
localparam FSM_DRP_START_NOM = 3; |
localparam FSM_DRP_DONE_NOM = 4; |
localparam FSM_QPLLLOCK = 5; |
localparam FSM_DRP_START_OPT = 6; |
localparam FSM_DRP_DONE_OPT = 7; |
localparam FSM_QPLL_RESET = 8; |
localparam FSM_QPLLLOCK2 = 9; |
localparam FSM_QPLL_PDRESET = 10; |
localparam FSM_QPLL_PD = 11; |
localparam FSM_IDLE = 1; |
localparam FSM_WAIT_LOCK = 2; |
localparam FSM_MMCM_LOCK = 3; |
localparam FSM_DRP_START_NOM = 4; |
localparam FSM_DRP_DONE_NOM = 5; |
localparam FSM_QPLLLOCK = 6; |
localparam FSM_DRP_START_OPT = 7; |
localparam FSM_DRP_DONE_OPT = 8; |
localparam FSM_QPLL_RESET = 9; |
localparam FSM_QPLLLOCK2 = 10; |
localparam FSM_QPLL_PDRESET = 11; |
localparam FSM_QPLL_PD = 12; |
|
|
|
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_7x.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_7x.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express |
-- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_bram_7x.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_bram_7x.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description : single bram wrapper for the mb pcie block |
-- The bram A port is the write port |
-- the B port is the read port |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_drp.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_gtp_pipe_drp.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : gtp_pipe_drp.v |
// Description : GTP PIPE DRP Module for 7 Series Transceiver |
92,15 → 92,15
); |
|
//---------- Input Registers --------------------------- |
reg x16_reg1; |
reg start_reg1; |
reg [15:0] do_reg1; |
reg rdy_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; |
|
reg x16_reg2; |
reg start_reg2; |
reg [15:0] do_reg2; |
reg rdy_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; |
|
//---------- Internal Signals -------------------------- |
reg [ 1:0] load_cnt = 2'd0; |
110,7 → 110,7
|
//---------- Output Registers -------------------------- |
reg done = 1'd0; |
reg [ 2:0] fsm = 1; |
reg [ 2:0] fsm = 0; |
|
//---------- DRP Address ------------------------------- |
localparam ADDR_RX_DATAWIDTH = 9'h011; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_top.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_top.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express |
-- |
-- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_rxeq_scan.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_rxeq_scan.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : rxeq_scan.v |
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver |
98,21 → 98,21
); |
|
//---------- Input Register ---------------------------- |
reg [ 2:0] preset_reg1; |
reg preset_valid_reg1; |
reg [ 3:0] txpreset_reg1; |
reg [17:0] txcoeff_reg1; |
reg new_txcoeff_req_reg1; |
reg [ 5:0] fs_reg1; |
reg [ 5:0] lf_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1; |
|
reg [ 2:0] preset_reg2; |
reg preset_valid_reg2; |
reg [ 3:0] txpreset_reg2; |
reg [17:0] txcoeff_reg2; |
reg new_txcoeff_req_reg2; |
reg [ 5:0] fs_reg2; |
reg [ 5:0] lf_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2; |
|
//---------- Internal Signals -------------------------- |
reg adapt_done_cnt = 1'd0; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pcie_pipe_misc.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_pcie_pipe_misc.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- Description: Misc PIPE module for 7-SeriesPCIe Block |
-- |
-- |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_sync.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_sync.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_sync.v |
// Description : PIPE Sync Module for 7 Series Transceiver |
133,43 → 133,49
); |
|
//---------- Input Register ---------------------------- |
reg gen3_reg1; |
reg rate_idle_reg1; |
reg mmcm_lock_reg1; |
reg rxelecidle_reg1; |
reg rxcdrlock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1; |
|
reg gen3_reg2; |
reg rate_idle_reg2; |
reg mmcm_lock_reg2; |
reg rxelecidle_reg2; |
reg rxcdrlock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2; |
|
reg txsync_start_reg1; |
reg txphinitdone_reg1; |
reg txdlysresetdone_reg1; |
reg txphaligndone_reg1; |
reg txsyncdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1; |
|
reg txsync_start_reg2; |
reg txphinitdone_reg2; |
reg txdlysresetdone_reg2; |
reg txphaligndone_reg2; |
reg txsyncdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2; |
|
reg rxsync_start_reg1; |
reg rxdlysresetdone_reg1; |
reg rxphaligndone_m_reg1; |
reg rxphaligndone_s_reg1; |
reg rxsync_donem_reg1; |
reg rxsyncdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3; |
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1; |
|
reg rxsync_start_reg2; |
reg rxdlysresetdone_reg2; |
reg rxphaligndone_m_reg2; |
reg rxphaligndone_s_reg2; |
reg rxsync_donem_reg2; |
reg rxsyncdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2; |
|
//---------- Output Register --------------------------- |
reg txdlyen = 1'd0; |
242,6 → 248,13
rxphaligndone_s_reg2 <= 1'd0; |
rxsync_donem_reg2 <= 1'd0; |
rxsyncdone_reg2 <= 1'd0; |
//---------- 3rd Stage FF -------------------------- |
txsync_start_reg3 <= 1'd0; |
txphinitdone_reg3 <= 1'd0; |
txdlysresetdone_reg3 <= 1'd0; |
txphaligndone_reg3 <= 1'd0; |
txsyncdone_reg3 <= 1'd0; |
|
end |
else |
begin |
283,6 → 296,12
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1; |
rxsync_donem_reg2 <= rxsync_donem_reg1; |
rxsyncdone_reg2 <= rxsyncdone_reg1; |
//---------- 3rd Stage FF -------------------------- |
txsync_start_reg3 <= txsync_start_reg2; |
txphinitdone_reg3 <= txphinitdone_reg2; |
txdlysresetdone_reg3 <= txdlysresetdone_reg2; |
txphaligndone_reg3 <= txphaligndone_reg2; |
txsyncdone_reg3 <= txsyncdone_reg2; |
end |
|
end |
341,7 → 360,7
FSM_TXSYNC_START : |
|
begin |
fsm_tx <= (((!txdlysresetdone_reg2 && txdlysresetdone_reg1) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START); |
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START); |
txdlyen <= 1'd0; |
txsync_done <= 1'd0; |
end |
350,7 → 369,7
FSM_TXPHINITDONE : |
|
begin |
fsm_tx <= (((!txphinitdone_reg2 && txphinitdone_reg1) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE); |
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE); |
txdlyen <= 1'd0; |
txsync_done <= 1'd0; |
end |
360,9 → 379,9
|
begin |
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE) |
fsm_tx <= ((!txsyncdone_reg2 && txsyncdone_reg1) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); |
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); |
else |
fsm_tx <= ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); |
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); |
|
txdlyen <= 1'd0; |
txsync_done <= 1'd0; |
372,7 → 391,7
FSM_TXSYNC_DONE2 : |
|
begin |
if ((!txphaligndone_reg2 && txphaligndone_reg1) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1)) |
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1)) |
begin |
fsm_tx <= FSM_TXSYNC_IDLE; |
txdlyen <= !SYNC_SLAVE; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx_null_gen.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_rx_null_gen.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
-- TRN to AXI RX null generator. Generates null packets for use in discontinue situations. |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_rx_pipeline.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_rx_pipeline.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
-- TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_wrapper.v
49,11 → 49,11
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_wrapper.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_wrapper.v |
// Description : PIPE Wrapper for 7 Series Transceiver |
// Version : 20.1 |
// Version : 20.2 |
//------------------------------------------------------------------------------ |
|
//---------- PIPE Wrapper Hierarchy -------------------------------------------- |
338,8 → 338,8
); |
|
//---------- Input Registers --------------------------- |
reg reset_n_reg1; |
reg reset_n_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2; |
|
//---------- PIPE Clock Module Output ------------------ |
wire clk_pclk; |
744,7 → 744,7
.RST_USERRDY (rst_userrdy), |
.RST_TXSYNC_START (rst_txsync_start), |
.RST_IDLE (rst_idle), |
.RST_FSM (rst_fsm) |
.RST_FSM (rst_fsm[4:0]) |
|
); |
|
808,7 → 808,7
assign qrst_qpllreset = 1'd0; |
assign qrst_qpllpd = 1'd0; |
assign qrst_idle = 1'd0; |
assign qrst_fsm = 1; |
assign qrst_fsm = 4'd1; |
end |
|
endgenerate |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx_pipeline.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_tx_pipeline.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
--AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_reset.v
49,11 → 49,11
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_reset.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_reset.v |
// Description : PIPE Reset Module for 7 Series Transceiver |
// Version : 20.0 |
// Version : 20.2 |
//------------------------------------------------------------------------------ |
|
|
100,9 → 100,9
//---------- Output ------------------------------------ |
output RST_CPLLRESET, |
output RST_CPLLPD, |
output RST_DRP_START, |
output RST_DRP_X16X20_MODE, |
output RST_DRP_X16, |
output reg RST_DRP_START, |
output reg RST_DRP_X16X20_MODE, |
output reg RST_DRP_X16, |
output RST_RXUSRCLK_RESET, |
output RST_DCLK_RESET, |
output RST_GTRESET, |
109,32 → 109,32
output RST_USERRDY, |
output RST_TXSYNC_START, |
output RST_IDLE, |
output [ 4:0] RST_FSM |
output [4:0] RST_FSM |
|
); |
|
//---------- Input Register ---------------------------- |
reg [PCIE_LANE-1:0] drp_done_reg1; |
reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; |
reg [PCIE_LANE-1:0] cplllock_reg1; |
reg qpll_idle_reg1; |
reg [PCIE_LANE-1:0] rate_idle_reg1; |
reg [PCIE_LANE-1:0] rxcdrlock_reg1; |
reg mmcm_lock_reg1; |
reg [PCIE_LANE-1:0] resetdone_reg1; |
reg [PCIE_LANE-1:0] phystatus_reg1; |
reg [PCIE_LANE-1:0] txsync_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1; |
|
reg [PCIE_LANE-1:0] drp_done_reg2; |
reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; |
reg [PCIE_LANE-1:0] cplllock_reg2; |
reg qpll_idle_reg2; |
reg [PCIE_LANE-1:0] rate_idle_reg2; |
reg [PCIE_LANE-1:0] rxcdrlock_reg2; |
reg mmcm_lock_reg2; |
reg [PCIE_LANE-1:0] resetdone_reg2; |
reg [PCIE_LANE-1:0] phystatus_reg2; |
reg [PCIE_LANE-1:0] txsync_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2; |
|
//---------- Internal Signal --------------------------- |
reg [ 5:0] cfg_wait_cnt = 6'd0; |
142,32 → 142,32
//---------- Output Register --------------------------- |
reg cpllreset = 1'd0; |
reg cpllpd = 1'd0; |
reg rxusrclk_rst_reg1 = 1'd0; |
reg rxusrclk_rst_reg2 = 1'd0; |
reg dclk_rst_reg1 = 1'd0; |
reg dclk_rst_reg2 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0; |
reg gtreset = 1'd0; |
reg userrdy = 1'd0; |
reg [ 4:0] fsm = 2; |
reg [4:0] fsm = 5'h2; |
|
//---------- FSM --------------------------------------- |
localparam FSM_IDLE = 0; |
localparam FSM_CFG_WAIT = 1; |
localparam FSM_CPLLRESET = 2; |
localparam FSM_DRP_X16_START = 3; |
localparam FSM_DRP_X16_DONE = 4; |
localparam FSM_CPLLLOCK = 5; |
localparam FSM_DRP = 6; |
localparam FSM_GTRESET = 7; |
localparam FSM_RXPMARESETDONE_1 = 8; |
localparam FSM_RXPMARESETDONE_2 = 9; |
localparam FSM_DRP_X20_START = 10; |
localparam FSM_DRP_X20_DONE = 11; |
localparam FSM_MMCM_LOCK = 12; |
localparam FSM_RESETDONE = 13; |
localparam FSM_CPLL_PD = 14; |
localparam FSM_TXSYNC_START = 15; |
localparam FSM_TXSYNC_DONE = 16; |
localparam FSM_IDLE = 5'h0; |
localparam FSM_CFG_WAIT = 5'h1; |
localparam FSM_CPLLRESET = 5'h2; |
localparam FSM_DRP_X16_START = 5'h3; |
localparam FSM_DRP_X16_DONE = 5'h4; |
localparam FSM_CPLLLOCK = 5'h5; |
localparam FSM_DRP = 5'h6; |
localparam FSM_GTRESET = 5'h7; |
localparam FSM_RXPMARESETDONE_1 = 5'h8; |
localparam FSM_RXPMARESETDONE_2 = 5'h9; |
localparam FSM_DRP_X20_START = 5'hA; |
localparam FSM_DRP_X20_DONE = 5'hB; |
localparam FSM_MMCM_LOCK = 5'hC; |
localparam FSM_RESETDONE = 5'hD; |
localparam FSM_CPLL_PD = 5'hE; |
localparam FSM_TXSYNC_START = 5'hF; |
localparam FSM_TXSYNC_DONE = 5'h10; |
|
|
|
525,7 → 525,7
if (fsm == FSM_CFG_WAIT) |
begin |
dclk_rst_reg1 <= 1'd1; |
dclk_rst_reg2 <= 1'd1; |
dclk_rst_reg2 <= dclk_rst_reg1; |
end |
else |
begin |
543,9 → 543,6
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; |
assign RST_DCLK_RESET = dclk_rst_reg2; |
assign RST_GTRESET = gtreset; |
assign RST_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); |
assign RST_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE); |
assign RST_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); |
assign RST_USERRDY = userrdy; |
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); |
assign RST_IDLE = (fsm == FSM_IDLE); |
553,4 → 550,28
|
|
|
|
//-------------------------------------------------------------------------------------------------- |
// Register Output |
//-------------------------------------------------------------------------------------------------- |
always @ (posedge RST_CLK) |
begin |
|
if (!RST_RST_N) |
begin |
RST_DRP_START <= 1'd0; |
RST_DRP_X16X20_MODE <= 1'd0; |
RST_DRP_X16 <= 1'd0; |
end |
else |
begin |
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); |
RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE); |
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); |
end |
|
end |
|
|
|
endmodule |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_clock.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_clock.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_clock.v |
// Description : PIPE Clock Module for 7 Series Transceiver |
130,11 → 130,11
localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0; |
|
//---------- Input Registers --------------------------- |
reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}}; |
reg gen3_reg1 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}}; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0; |
|
reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}}; |
reg gen3_reg2 = 1'd0; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}}; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0; |
|
//---------- Internal Signals -------------------------- |
wire refclk; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_rate.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_rate.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_rate.v |
// Description : PIPE Rate Module for 7 Series Transceiver |
125,37 → 125,37
); |
|
//---------- Input FF or Buffer ------------------------ |
reg rst_idle_reg1; |
reg [ 1:0] rate_in_reg1; |
reg cplllock_reg1; |
reg qplllock_reg1; |
reg mmcm_lock_reg1; |
reg drp_done_reg1; |
reg rxpmaresetdone_reg1; |
reg txresetdone_reg1; |
reg rxresetdone_reg1; |
reg txratedone_reg1; |
reg rxratedone_reg1; |
reg phystatus_reg1; |
reg resetovrd_done_reg1; |
reg txsync_done_reg1; |
reg rxsync_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1; |
|
reg rst_idle_reg2; |
reg [ 1:0] rate_in_reg2; |
reg cplllock_reg2; |
reg qplllock_reg2; |
reg mmcm_lock_reg2; |
reg drp_done_reg2; |
reg rxpmaresetdone_reg2; |
reg txresetdone_reg2; |
reg rxresetdone_reg2; |
reg txratedone_reg2; |
reg rxratedone_reg2; |
reg phystatus_reg2; |
reg resetovrd_done_reg2; |
reg txsync_done_reg2; |
reg rxsync_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2; |
|
//---------- Internal Signals -------------------------- |
wire pll_lock; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_reset.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_gtp_pipe_reset.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : gtp_pipe_reset.v |
// Description : GTP PIPE Reset Module for 7 Series Transceiver |
95,8 → 95,8
//---------- Output ------------------------------------ |
output RST_CPLLRESET, |
output RST_CPLLPD, |
output RST_DRP_START, |
output RST_DRP_X16, |
output reg RST_DRP_START, |
output reg RST_DRP_X16, |
output RST_RXUSRCLK_RESET, |
output RST_DCLK_RESET, |
output RST_GTRESET, |
108,25 → 108,25
); |
|
//---------- Input Register ---------------------------- |
reg [PCIE_LANE-1:0] drp_done_reg1; |
reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; |
reg plllock_reg1; |
reg [PCIE_LANE-1:0] rate_idle_reg1; |
reg [PCIE_LANE-1:0] rxcdrlock_reg1; |
reg mmcm_lock_reg1; |
reg [PCIE_LANE-1:0] resetdone_reg1; |
reg [PCIE_LANE-1:0] phystatus_reg1; |
reg [PCIE_LANE-1:0] txsync_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1; |
|
reg [PCIE_LANE-1:0] drp_done_reg2; |
reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; |
reg plllock_reg2; |
reg [PCIE_LANE-1:0] rate_idle_reg2; |
reg [PCIE_LANE-1:0] rxcdrlock_reg2; |
reg mmcm_lock_reg2; |
reg [PCIE_LANE-1:0] resetdone_reg2; |
reg [PCIE_LANE-1:0] phystatus_reg2; |
reg [PCIE_LANE-1:0] txsync_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2; |
|
//---------- Internal Signal --------------------------- |
reg [ 5:0] cfg_wait_cnt = 6'd0; |
140,24 → 140,24
reg dclk_rst_reg2 = 1'd0; |
reg gtreset = 1'd0; |
reg userrdy = 1'd0; |
reg [ 3:0] fsm = 2; |
reg [ 4:0] fsm = 5'h1; |
|
//---------- FSM --------------------------------------- |
localparam FSM_IDLE = 0; |
localparam FSM_CFG_WAIT = 1; |
localparam FSM_PLLRESET = 2; |
localparam FSM_DRP_X16_START = 3; |
localparam FSM_DRP_X16_DONE = 4; |
localparam FSM_PLLLOCK = 5; |
localparam FSM_GTRESET = 6; |
localparam FSM_RXPMARESETDONE_1 = 7; |
localparam FSM_RXPMARESETDONE_2 = 8; |
localparam FSM_DRP_X20_START = 9; |
localparam FSM_DRP_X20_DONE = 10; |
localparam FSM_MMCM_LOCK = 11; |
localparam FSM_RESETDONE = 12; |
localparam FSM_TXSYNC_START = 13; |
localparam FSM_TXSYNC_DONE = 14; |
localparam FSM_IDLE = 5'h0; |
localparam FSM_CFG_WAIT = 5'h1; |
localparam FSM_PLLRESET = 5'h2; |
localparam FSM_DRP_X16_START = 5'h3; |
localparam FSM_DRP_X16_DONE = 5'h4; |
localparam FSM_PLLLOCK = 5'h5; |
localparam FSM_GTRESET = 5'h6; |
localparam FSM_RXPMARESETDONE_1 = 5'h7; |
localparam FSM_RXPMARESETDONE_2 = 5'h8; |
localparam FSM_DRP_X20_START = 5'h9; |
localparam FSM_DRP_X20_DONE = 5'hA; |
localparam FSM_MMCM_LOCK = 5'hB; |
localparam FSM_RESETDONE = 5'hC; |
localparam FSM_TXSYNC_START = 5'hD; |
localparam FSM_TXSYNC_DONE = 5'hE; |
|
|
|
487,7 → 487,7
if (fsm == FSM_CFG_WAIT) |
begin |
dclk_rst_reg1 <= 1'd1; |
dclk_rst_reg2 <= 1'd1; |
dclk_rst_reg2 <= dclk_rst_reg1; |
end |
else |
begin |
505,13 → 505,32
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2; |
assign RST_DCLK_RESET = dclk_rst_reg2; |
assign RST_GTRESET = gtreset; |
assign RST_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); |
assign RST_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); |
assign RST_USERRDY = userrdy; |
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START); |
assign RST_IDLE = (fsm == FSM_IDLE); |
assign RST_FSM = ({1'b0,fsm}); |
assign RST_FSM = fsm; |
|
|
|
//-------------------------------------------------------------------------------------------------- |
// Register Output |
//-------------------------------------------------------------------------------------------------- |
always @ (posedge RST_CLK) |
begin |
|
if (!RST_RST_N) |
begin |
RST_DRP_START <= 1'd0; |
RST_DRP_X16 <= 1'd0; |
end |
else |
begin |
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); |
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE); |
end |
|
end |
|
|
|
endmodule |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gt_wrapper.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_gt_wrapper.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : gt_wrapper.v |
// Description : GT Wrapper Module for 7 Series Transceiver |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_qpll_drp.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_qpll_drp.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : qpll_drp.v |
// Description : QPLL DRP Module for 7 Series Transceiver |
100,19 → 100,19
); |
|
//---------- Input Registers --------------------------- |
reg ovrd_reg1; |
reg gen3_reg1; |
reg qplllock_reg1; |
reg start_reg1; |
reg [15:0] do_reg1; |
reg rdy_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1; |
|
reg ovrd_reg2; |
reg gen3_reg2; |
reg qplllock_reg2; |
reg start_reg2; |
reg [15:0] do_reg2; |
reg rdy_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2; |
|
//---------- Internal Signals -------------------------- |
reg [ 1:0] load_cnt = 2'd0; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_top.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_top.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
-- TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_pipe_eq.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_pipe_eq.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : pipe_eq.v |
// Description : PIPE Equalization Module for 7 Series Transceiver |
109,32 → 109,32
); |
|
//---------- Input Registers --------------------------- |
reg gen3_reg1; |
reg gen3_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; |
|
reg [ 1:0] txeq_control_reg1; |
reg [ 3:0] txeq_preset_reg1; |
reg [ 5:0] txeq_deemph_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1; |
|
reg [ 1:0] txeq_control_reg2; |
reg [ 3:0] txeq_preset_reg2; |
reg [ 5:0] txeq_deemph_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2; |
|
reg [ 1:0] rxeq_control_reg1; |
reg [ 2:0] rxeq_preset_reg1; |
reg [ 5:0] rxeq_lffs_reg1; |
reg [ 3:0] rxeq_txpreset_reg1; |
reg rxeq_user_en_reg1; |
reg [17:0] rxeq_user_txcoeff_reg1; |
reg rxeq_user_mode_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1; |
|
reg [ 1:0] rxeq_control_reg2; |
reg [ 2:0] rxeq_preset_reg2; |
reg [ 5:0] rxeq_lffs_reg2; |
reg [ 3:0] rxeq_txpreset_reg2; |
reg rxeq_user_en_reg2; |
reg [17:0] rxeq_user_txcoeff_reg2; |
reg rxeq_user_mode_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2; |
|
//---------- Internal Signals -------------------------- |
reg [18:0] txeq_preset = 19'd0; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_gtp_pipe_rate.v
49,7 → 49,7
//----------------------------------------------------------------------------- |
// Project : Series-7 Integrated Block for PCI Express |
// File : cl_a7pcie_x4_gtp_pipe_rate.v |
// Version : 1.9 |
// Version : 1.10 |
//------------------------------------------------------------------------------ |
// Filename : gtp_pipe_rate.v |
// Description : PIPE Rate Module for 7 Series Transceiver |
97,21 → 97,21
); |
|
//---------- Input FF or Buffer ------------------------ |
reg [ 1:0] rate_in_reg1; |
reg drp_done_reg1; |
reg rxpmaresetdone_reg1; |
reg txratedone_reg1; |
reg rxratedone_reg1; |
reg phystatus_reg1; |
reg txsync_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1; |
|
reg [ 1:0] rate_in_reg2; |
reg drp_done_reg2; |
reg rxpmaresetdone_reg2; |
reg txratedone_reg2; |
reg rxratedone_reg2; |
reg phystatus_reg2; |
reg txsync_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2; |
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2; |
|
//---------- Internal Signals -------------------------- |
wire [ 2:0] rate; |
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1/source_artix7/cl_a7pcie_x4_axi_basic_tx_thrtl_ctl.vhd
49,7 → 49,7
------------------------------------------------------------------------------- |
-- Project : Series-7 Integrated Block for PCI Express |
-- File : cl_a7pcie_x4_axi_basic_tx_thrtl_ctl.vhd |
-- Version : 1.9 |
-- Version : 1.10 |
-- |
-- Description: |
-- TX throttle controller. Anticipates back-pressure from PCIe block and |
/pcie_ds_dma/trunk/projects/ac701_a200t_core/src/testbench/stend_ac701_core.vhd
162,9 → 162,9
|
--test_read_4kb( cmd, ret ); |
--test_adm_read_8kb( cmd, ret ); |
test_adm_read_16kb( cmd, ret ); |
--test_adm_read_16kb( cmd, ret ); |
--test_adm_write_16kb( cmd, ret ); |
--test_block_main( cmd, ret ); |
test_block_main( cmd, ret ); |
|
test_close; |
-- |
/pcie_ds_dma/trunk/projects/ac701_a200t_core/src/testbench/test_pkg.vhd
505,6 → 505,7
write( str, string'("TEST_BLOCK_MAIN" )); |
writeline( log, str ); |
|
-- block_write( cmd, ret, 4, 16#08#, x"0000AA55" ); |
block_read( cmd, ret, 4, 16#00#, data ); |
|
|