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URL https://opencores.org/ocsvn/camellia-vhdl/camellia-vhdl/trunk

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Rev 5 → Rev 6

/trunk/looping/control.vhd
56,8 → 56,7
 
architecture RTL of control is
 
type STATUS is (RST,
KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
type STATUS is (KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,
FL1,
SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,
149,547 → 148,557
reg_ka_s when KA,
reg_kb_s when KB,
(others=>'0') when others;
 
REGISTERS_UPDATE : process(clk)
REGISTERS_UPDATE : process(reset, clk)
variable coming_from_key : STD_LOGIC;
begin
if (clk'event and clk = '1') then
case PS is
when RST =>
reg_kl <= (others=>'0');
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
reg_kl_s <= (others=>'0');
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
reg_enc_dec <= '0';
reg_k_len <= (others=>'0');
key_acq <= '0';
data_acq <= '0';
output_rdy <= '0';
coming_from_key := '0';
when KEYa =>
coming_from_key := '1';
reg_kl <= key_in(0 to 127);
reg_kl_s <= key_in(0 to 127);
reg_k_len <= k_len;
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));
when KLEN_256 =>
reg_kr <= key_in(128 to 255);
reg_kr_s <= key_in(128 to 255);
when others =>
reg_kr <= (others=>'0');
reg_kr_s <= (others=>'0');
end case;
k1_sel <= SIG1;
when KEYb =>
key_acq <= '1';
k1_sel <= SIG2;
when KEYc =>
key_acq <= '0';
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
when KEYe =>
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= SIG5;
when KEYf =>
k1_sel <= SIG6;
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
if (reset = '1') then
reg_kl <= (others=>'0');
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
reg_kl_s <= (others=>'0');
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
reg_enc_dec <= '0';
reg_k_len <= (others=>'0');
output_rdy <= '0';
coming_from_key := '0';
else
if (clk'event and clk = '1') then
case PS is
when KEYa =>
coming_from_key := '1';
reg_kl <= key_in(0 to 127);
reg_kl_s <= key_in(0 to 127);
reg_k_len <= k_len;
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));
when KLEN_256 =>
reg_kr <= key_in(128 to 255);
reg_kr_s <= key_in(128 to 255);
when others =>
reg_kr <= (others=>'0');
reg_kr_s <= (others=>'0');
end case;
k1_sel <= SIG1;
when KEYb =>
k1_sel <= SIG2;
when KEYc =>
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
when KEYe =>
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= SIG5;
when KEYf =>
k1_sel <= SIG6;
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
else
reg_kb <= data_from;
reg_kb_s <= data_from;
end if;
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
reg_kl_s <= reg_kl;
reg_kr_s <= reg_kr;
end if;
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= KA_L;
else
reg_kb <= data_from;
reg_kb_s <= data_from;
k1_sel <= KB_L;
end if;
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
reg_kl_s <= reg_kl;
reg_kr_s <= reg_kr;
else -- DEC
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
else
reg_kb <= data_from;
reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
end if;
k1_sel <= KL_R;
end if;
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KB_L;
reg_enc_dec <= enc_dec;
when SIX1b =>
coming_from_key := '0';
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
k1_sel <= KL_L; -- for each value of reg_k_len
end if;
else -- DEC
if (coming_from_key = '1') then
when SIX1c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_kb <= data_from;
reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KA_R; -- for each value of reg_k_len
end if;
when SIX1d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
end if;
else -- DEC
k1_sel <= KA_L; -- for each value of reg_k_len
end if;
when SIX1e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
k1_sel <= KL_R;
else
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
k1_sel <= KR_R;
end if;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
end if;
k1_sel <= KL_R;
end if;
reg_enc_dec <= enc_dec;
when SIX1b =>
coming_from_key := '0';
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
when SIX1f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
else -- DEC
k1_sel <= KL_L; -- for each value of reg_k_len
end if;
data_acq <= '1';
when SIX1c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
when FL1 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
k2_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
k1_sel <= KA_R;
k2_sel <= KA_L;
end if;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KA_R; -- for each value of reg_k_len
end if;
data_acq <= '0';
when SIX1d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
when SIX2a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
else -- DEC
k1_sel <= KA_L; -- for each value of reg_k_len
end if;
when SIX1e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
when SIX2b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
when SIX2c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
k1_sel <= KR_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
end if;
when SIX1f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL1 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
when SIX2e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
k2_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
when SIX2f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
k2_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
when SIX2a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
when FL2 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
k2_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KL_R;
k2_sel <= KL_L;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
when SIX3a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
end if;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
end if;
when SIX2b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
when SIX3b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KA_L;
end if;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
when SIX3c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
end if;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
end if;
when SIX2c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
when SIX3d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
when SIX3f =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
end if;
when SIX2d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
when FL3 =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
k2_sel <= KR_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
when SIX2e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
when SIX4a =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_L;
end if;
end if;
when FL2 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_L;
k2_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KL_R;
k2_sel <= KL_L;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX3a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
end if;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX3b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
when SIX4b =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
else -- DEC
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KA_L;
end if;
end if;
when SIX3c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
when SIX4c =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
else -- DEC
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
end if;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX3d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
when SIX4d =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
when SIX4e =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3f =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
when SIX4f =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
when FL3 =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
k2_sel <= KR_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4a =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX4b =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_R;
else -- DEC
k1_sel <= KA_L;
end if;
when SIX4c =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4d =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4e =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when WT =>
-- do nothing
end case;
when WT =>
-- do nothing
end case;
 
if (PS = KEYa) then
data_to <= key_in(0 to 127); --kl
else
data_to <= data_in;
end if;
if (PS = KEYa) then
data_to <= key_in(0 to 127); --kl
else
data_to <= data_in;
end if;
 
case PS is
when KEYc =>
prexor_sel <= KL;
when KEYa | KEYe =>
prexor_sel <= KR;
when SIX1a =>
if (enc_dec = ENC) then
case PS is
when KEYc =>
prexor_sel <= KL;
else
when KEYa | KEYe =>
prexor_sel <= KR;
when SIX1a =>
if (enc_dec = ENC) then
prexor_sel <= KL;
else
if (reg_k_len = KLEN_128) then
prexor_sel <= KA;
else
prexor_sel <= KB;
end if;
end if;
when others =>
prexor_sel <= ZERO;
end case;
 
case PS is
when SIX3f =>
if (reg_k_len = KLEN_128) then
prexor_sel <= KA;
if (reg_enc_dec = ENC) then
postxor_sel <= KA;
else
postxor_sel <= KL;
end if;
else
prexor_sel <= KB;
postxor_sel <= ZERO;
end if;
end if;
when others =>
prexor_sel <= ZERO;
end case;
 
case PS is
when SIX3f =>
if (reg_k_len = KLEN_128) then
when SIX4f =>
if (reg_enc_dec = ENC) then
postxor_sel <= KA;
postxor_sel <= KB;
else
postxor_sel <= KL;
end if;
else
when others =>
postxor_sel <= ZERO;
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
postxor_sel <= KB;
else
postxor_sel <= KL;
end if;
when others =>
postxor_sel <= ZERO;
end case;
end case;
 
if (PS = SIX1a or PS = KEYa) then
newdata <= '1';
else
newdata <= '0';
end if;
if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
output_rdy <= '1';
else
output_rdy <= '0';
end if;
if (PS = SIX1a or PS = KEYa) then
newdata <= '1';
else
newdata <= '0';
end if;
if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
output_rdy <= '1';
else
output_rdy <= '0';
end if;
 
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
end if;
if (PS = KEYb) then
key_acq <= '1';
else
key_acq <= '0';
end if;
if (PS = SIX1b) then
data_acq <= '1';
else
data_acq <= '0';
end if;
end if;
end if;
end process;
 
STATE_UPDATE: process (clk)
STATE_UPDATE: process (reset, clk)
begin
 
if (clk'event and clk = '1') then
 
if (reset = '1') then
PS <= RST;
else
if (reset = '1') then
PS <= KEYa;
else
if (clk'event and clk = '1') then
PS <= NS;
end if;
end if;
698,8 → 707,6
NEXT_STATE: process (PS, data_rdy, key_rdy)
begin
case PS is
when RST =>
NS <= KEYa;
when KEYa =>
if(key_rdy = '1') then
NS <= KEYb;
808,8 → 815,6
NS <= WT;
end if;
end if;
-- when others =>
-- NS <= RST;
end case;
end process;
 
/trunk/looping/camellia_if.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 03/25/2008
-- Last Update: 03/28/2008
-- Last Update: 04/02/2008
-- Project Name: camellia-vhdl
-- Description: Interface to the Camellia core
--
78,15 → 78,17
signal s_data_out : STD_LOGIC_VECTOR (0 to 127);
signal s_output_rdy : STD_LOGIC;
signal key_count : STD_LOGIC_VECTOR (3 downto 0);
signal din_count : STD_LOGIC_VECTOR (2 downto 0);
signal dout_count : STD_LOGIC_VECTOR (2 downto 0);
signal key_count : STD_LOGIC_VECTOR (3 downto 0);
signal din_count : STD_LOGIC_VECTOR (2 downto 0);
signal dout_count : STD_LOGIC_VECTOR (2 downto 0);
signal reg_key : STD_LOGIC_VECTOR (0 to 255);
signal reg_din : STD_LOGIC_VECTOR (0 to 127);
signal reg_dout : STD_LOGIC_VECTOR (0 to 127);
signal reg_key : STD_LOGIC_VECTOR (0 to 255);
signal reg_din : STD_LOGIC_VECTOR (0 to 127);
signal reg_dout : STD_LOGIC_VECTOR (0 to 127);
signal reg_next_data : STD_LOGIC;
signal reg_next_key : STD_LOGIC;
signal int_out_rdy : STD_LOGIC;
signal int_out_rdy : STD_LOGIC;
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
105,20 → 107,14
begin
if (reset = '1') then
next_key <= '1';
reg_next_key <= '1';
key_count <= "0000";
reg_key <= (others=>'0');
s_key_rdy <= '0';
elsif (clk'event and clk = '1') then
if ((key_count = "0111" and k_len = KLEN_128) or
key_count = "1111") then
s_key_rdy <= '1';
elsif (s_key_acq = '1') then
s_key_rdy <= '0';
next_key <= '1';
end if;
if (en_key = '1') then
reg_next_key <= '0';
key_count <= key_count + "0001";
case k_len is
when KLEN_128 =>
130,7 → 126,22
end case;
else
key_count <= "0000";
end if;
if (s_key_acq = '1') then
reg_next_key <= '1';
else
reg_next_key <= reg_next_key;
end if;
end if;
if ((key_count = "0111" and k_len = KLEN_128) or
(key_count = "1100" and k_len = KLEN_192) or
key_count = "1111") then
s_key_rdy <= '1';
elsif (s_key_acq = '1') then
s_key_rdy <= '0';
else
s_key_rdy <= s_key_rdy;
end if;
end if;
140,24 → 151,32
begin
if (reset = '1') then
next_data <= '1';
reg_next_data <= '1';
din_count <= "000";
reg_din <= (others=>'0');
s_data_rdy <= '0';
elsif (clk'event and clk = '1') then
if (en_data = '1') then
reg_next_data <= '0';
din_count <= din_count + "001";
reg_din <= reg_din(16 to 127) & data_in;
else
din_count <= "000";
if (s_data_acq = '1') then
reg_next_data <= '1';
else
reg_next_data <= reg_next_data;
end if;
end if;
if (din_count = "111") then
s_data_rdy <= '1';
elsif (s_data_acq = '1') then
s_data_rdy <= '0';
next_data <= '1';
else
s_data_rdy <= s_data_rdy;
end if;
if (en_data = '1') then
din_count <= din_count + "001";
reg_din <= reg_din(16 to 127) & data_in;
else
din_count <= "000";
end if;
end if;
172,12 → 191,6
reg_dout <= (others=>'0');
elsif (clk'event and clk = '1') then
if (s_output_rdy = '1' and int_out_rdy = '0') then
dout_count <= "000";
reg_dout <= s_data_out;
int_out_rdy<= '1';
end if;
if (int_out_rdy = '1') then
if (dout_count /= "111") then
dout_count <= dout_count + "001";
185,6 → 198,12
else
int_out_rdy <= '0';
end if;
else
if (s_output_rdy = '1') then
dout_count <= "000";
reg_dout <= s_data_out;
int_out_rdy<= '1';
end if;
end if;
end if;
198,6 → 217,8
s_k_len <= k_len;
data_out <= reg_dout(0 to 15);
out_rdy <= int_out_rdy;
next_key <= reg_next_key;
next_data <= reg_next_data;
end RTL;
 
/trunk/looping/camellia.vhd
44,6 → 44,10
data_out : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
-- post-synthesis debug
);
end camellia;
 
/trunk/looping/camellia_tb.vhd
3,7 → 3,7
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 02/19/2008
-- Last Update: 03/28/2008
-- Last Update: 04/02/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module camellia
--
69,7 → 69,7
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant CLK_PERIOD : TIME := 20 ns;
constant CLK_PERIOD : TIME := 100 ns;
 
begin
 
80,8 → 80,9
tb : process
begin
reset <= '1';
wait for 15 ns;
wait for 80 ns;
reset <= '0';
wait until clk = '1';
data_in <= X"0123456789abcdeffedcba9876543210";
enc_dec <= ENC;
97,6 → 98,21
data_in <= X"67673138549669730857065648eabe43";
enc_dec <= DEC;
wait until data_acq = '1';
data_in <= X"0123456789abcdeffedcba9876543210";
enc_dec <= ENC;
data_rdy <= '1';
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_192;
key_rdy <= '1';
wait until key_acq = '1';
key_rdy <= '0';
wait until data_acq = '1';
data_rdy <= '0';
wait;
end process;
 
/trunk/looping/camellia_tb.do
29,4 → 29,4
add wave -HEX /uut/CTRL/reg_k_len
add wave -divider "datapath"
add wave -HEX -ports /uut/DP/*
run 1400 ns
run 6 us

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