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URL https://opencores.org/ocsvn/fifo_srl_uni/fifo_srl_uni/trunk

Subversion Repositories fifo_srl_uni

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Rev 5 → Rev 6

/fifo_srl_uni/trunk/tb_fifo_srl_uni_1.vhd
6,7 → 6,7
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
-- Company : SzuWar INC
-- Created : 09:45:13 16-03-2010
-- Last update: 23:36:11 20-03-2010
-- Last update: 14:49:11 21-03-2010
-- Platform : Xilinx ISE 10.1.03
-- Standard : VHDL'93
-------------------------------------------------------------------------------
38,7 → 38,7
generic (
iDataWidth : integer range 1 to 32 := 17;
ififoWidth : integer range 1 to 1023 := 33;
iInputReg : integer range 0 to 2 := 0;
iInputReg : integer range 0 to 3 := 0;
iOutputReg : integer range 0 to 3 := 2;
iFullFlagOfSet : integer range 0 to 1021 := 2;
iEmptyFlagOfSet : integer range 0 to 1021 := 5;
63,15 → 63,15
-- constants --
-------------------------------------------------------------------------------
constant iDataWidth : integer := 16;
constant ififoWidth : integer := 8;
constant iInputReg : integer := 0;
constant iOutputReg : integer := 1;
constant ififoWidth : integer := 33;
constant iInputReg : integer := 3;
constant iOutputReg : integer := 3;
constant iFullFlagOfSet : integer := 0;
constant iEmptyFlagOfSet : integer := 0;
constant iSizeDelayCounter : integer := 5;
constant iSizeDelayCounter : integer := 6;
constant iWriteDataCounter : integer := 10;
constant iReadDataCounter : integer := 13;
constant iWriteDataCounter : integer := 22;
constant iReadDataCounter : integer := 33;
-------------------------------------------------------------------------------
-- signals --
154,7 → 154,10
i_count_write <= i_count_write + 1;
else
 
DATA_I <= DATA_I;
WRITE_ENABLE_I <= '0';
READ_ENABLE_I <= '0';
v_count <= v_count + 1;
end if;
184,7 → 187,7
 
DATA_I <= x"0100";
WRITE_ENABLE_I <= '1';
READ_ENABLE_I <= '0';
READ_ENABLE_I <= '1';
v_count <= v_count + 1;
when x"0006" =>
/fifo_srl_uni/trunk/fifo_srl.do
0,0 → 1,47
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/v_count
add wave -noupdate -format Literal /tb_fifo_srl_uni_1/i_count_write
add wave -noupdate -format Literal /tb_fifo_srl_uni_1/i_count_read
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/clk_i
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/data_i
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/data_o
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/write_enable_i
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/read_enable_i
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/read_valid_o
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/fifo_count_o
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/full_flag_o
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/empty_flag_o
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/v_delay_counter
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/v_size_counter
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/v_zeros
add wave -noupdate -format Literal /tb_fifo_srl_uni_1/uut/v_write_enable
add wave -noupdate -format Literal /tb_fifo_srl_uni_1/uut/v_read_enable
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/i_size_counter
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/i_srl_select
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/i_temp
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/t_mux_in
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/t_srl_in
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/t_mux_out
add wave -noupdate -format Literal -radix decimal /tb_fifo_srl_uni_1/uut/t_reg_in
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/one_delay
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/ce_master
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/full_capacity
add wave -noupdate -format Logic -radix decimal /tb_fifo_srl_uni_1/uut/data_valid_off
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {164834 ps} 0}
configure wave -namecolwidth 259
configure wave -valuecolwidth 67
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {840 ns}
/fifo_srl_uni/trunk/fifo_srl_uni.vhd
6,7 → 6,7
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
-- Company : SzuWar INC
-- Created : 13:27:31 14-03-2010
-- Last update: 23:23:38 20-03-2010
-- Last update: 15:02:32 21-03-2010
-- Platform : Xilinx ISE 10.1.03
-- Standard : VHDL'93
-------------------------------------------------------------------------------
18,13 → 18,13
-- Date Version Author Description
-- 13:27:31 14-03-2010 1.0 szuwarek Created
-------------------------------------------------------------------------------
-- Version 1.1 unlimited size of Input and Output register.
-- Version 1.0
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--use ieee.numeric_std.all;
 
Library UNISIM;
use UNISIM.vcomponents.all;
34,7 → 34,7
generic (
iDataWidth : integer range 1 to 32 := 17;
ififoWidth : integer range 1 to 1023 := 32;
iInputReg : integer range 0 to 2 := 0;
iInputReg : integer range 0 to 3 := 0;
iOutputReg : integer range 0 to 3 := 2;
iFullFlagOfSet : integer range 0 to 1021 := 2;
iEmptyFlagOfSet : integer range 0 to 1021 := 5;
57,7 → 57,6
 
architecture fifo_srl_uni_rtl of fifo_srl_uni is
 
-------------------------------------------------------------------------------
-- functions --
-------------------------------------------------------------------------------
116,9 → 115,9
signal v_delay_counter : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
signal v_size_counter : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
signal v_zeros : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
signal v_ones : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
signal v_WRITE_ENABLE : std_logic_vector(iInputReg downto 0);
signal v_READ_ENABLE : std_logic_vector(iOutputReg downto 0);
signal v_valid_delay : std_logic_vector(iOutputReg downto 0);
signal i_size_counter : integer range 0 to 1023 := 0;
signal i_srl_select : integer range 0 to 64 := 0;
signal i_temp : integer range 0 to 64;
134,7 → 133,18
begin -- architecture fifo_srl_uni_r
 
v_zeros <= (others => '0');
v_ones <= (others => '1');
 
i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
i_size_counter <= conv_integer(v_size_counter);
 
ce_master <= v_WRITE_ENABLE(0) and (not full_capacity);
full_capacity <= '0' when i_size_counter < ififoWidth else '1';
 
t_mux_out(0) <= t_mux_in(i_srl_select);
READ_VALID_O <= v_READ_ENABLE(0) and (not v_valid_delay(0));
FIFO_COUNT_O <= v_size_counter;
-------------------------------------------------------------------------------
-- Input Register --
-------------------------------------------------------------------------------
141,7 → 151,7
GR0: if iInputReg = 0 generate
 
t_srl_in(0) <= DATA_I;
v_WRITE_ENABLE(0) <= WRITE_ENABLE_I;
v_WRITE_ENABLE(iInputReg) <= WRITE_ENABLE_I;
end generate GR0;
 
148,7 → 158,7
GR1: if iInputReg = 1 generate
 
t_srl_in(0) <= t_reg_in(0);
v_WRITE_ENABLE(1) <= WRITE_ENABLE_I;
v_WRITE_ENABLE(iInputReg) <= WRITE_ENABLE_I;
P1: process (CLK_I) is
begin -- process P1
156,7 → 166,7
if rising_edge(CLK_I) then
 
t_reg_in(0) <= DATA_I;
v_WRITE_ENABLE(0) <= v_WRITE_ENABLE(1);
v_WRITE_ENABLE(0) <= v_WRITE_ENABLE(iInputReg);
end if;
164,10 → 174,10
end generate GR1;
 
GR2: if iInputReg = 2 generate
GR2: if iInputReg > 1 generate
 
t_srl_in(0) <= t_reg_in(0);
v_WRITE_ENABLE(2) <= WRITE_ENABLE_I;
v_WRITE_ENABLE(iInputReg) <= WRITE_ENABLE_I;
 
P1: process (CLK_I) is
begin -- process P1
174,9 → 184,9
 
if rising_edge(CLK_I) then
 
t_reg_in(1) <= DATA_I;
t_reg_in(0) <= t_reg_in(1);
v_WRITE_ENABLE(1 downto 0) <= v_WRITE_ENABLE(2 downto 1);
t_reg_in(iInputReg - 1) <= DATA_I;
t_reg_in(0 to iInputReg - 2) <= t_reg_in(1 to iInputReg -1);
v_WRITE_ENABLE(iInputReg - 1 downto 0) <= v_WRITE_ENABLE(iInputReg downto 1);
end if;
215,10 → 225,6
-- FIFO Core, SRL16E based --
-------------------------------------------------------------------------------
i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
i_size_counter <= conv_integer(v_size_counter);
ce_master <= v_WRITE_ENABLE(0) and (not full_capacity);
P0: process (CLK_I) is
begin -- process P0
 
262,43 → 268,32
one_delay <= one_delay;
end if;
 
if i_size_counter = 0 then
 
data_valid_off <= '1';
 
else
 
data_valid_off <= '0';
end if;
end if;
end process P0;
 
full_capacity <= '0' when i_size_counter < ififoWidth else '1';
data_valid_off <= '1' when i_size_counter = 0 else '0';
-------------------------------------------------------------------------------
-- Output Register --
-------------------------------------------------------------------------------
t_mux_out(0) <= t_mux_in(i_srl_select);
READ_VALID_O <= v_READ_ENABLE(0) and (not data_valid_off);
FIFO_COUNT_O <= v_size_counter;
 
-- size of output register: 0 --
GM0: if iOutputReg = 0 generate
 
DATA_O <= t_mux_out(0);
v_READ_ENABLE(0) <= READ_ENABLE_I;
v_valid_delay(0) <= data_valid_off;
end generate GM0;
 
 
-- size of output register: 1 --
GM1: if iOutputReg = 1 generate
 
DATA_O <= t_mux_out(1);
v_READ_ENABLE(1) <= READ_ENABLE_I;
 
P2: process (CLK_I) is
begin -- process P2
 
306,6 → 301,7
 
v_READ_ENABLE(0) <= v_READ_ENABLE(1);
t_mux_out(1) <= t_mux_out(0);
v_valid_delay(0) <= data_valid_off;
end if;
312,7 → 308,8
end process P2;
end generate GM1;
 
-- size of output register: > 1 --
GM2: if iOutputReg > 1 generate
 
DATA_O <= t_mux_out(iOutputReg);
325,6 → 322,7
 
v_READ_ENABLE(iOutputReg - 1 downto 0) <= v_READ_ENABLE(iOutputReg downto 1);
t_mux_out(1 to iOutputReg) <= t_mux_out(0 to iOutputReg - 1);
v_valid_delay(iOutputReg - 1 downto 0) <= data_valid_off&v_valid_delay(iOutputReg - 1 downto 1);
end if;

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