Subversion Repositories fir_wishbone

/fir_wishbone/trunk/workspaces/simulation/questa/waves.do

/fir_wishbone/trunk/workspaces/simulation/questa/simulate.sh

fir_wishbone/trunk/workspaces/simulation/questa/simulate.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qpf =================================================================== --- fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qpf (nonexistent) +++ fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qpf (revision 6) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 12.1 Build 177 11/07/2012 SJ Full Version +# Date created = 22:57:28 March 05, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "12.1" +DATE = "22:57:28 March 05, 2014" + +# Revisions + +PROJECT_REVISION = "fir" Index: fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qsf =================================================================== --- fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qsf (nonexistent) +++ fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qsf (revision 6) @@ -0,0 +1,55 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 12.1 Build 177 11/07/2012 SJ Full Version +# Date created = 22:57:28 March 05, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# fir_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE AUTO +set_global_assignment -name TOP_LEVEL_ENTITY tb_fir +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28 MARCH 05, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl" +set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file