URL
https://opencores.org/ocsvn/quadratic_func/quadratic_func/trunk
Subversion Repositories quadratic_func
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/tags/arelease/docs/quadratic_func.pdf
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svn:mime-type = application/octet-stream
tags/arelease/docs/quadratic_func.pdf
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Index: tags/arelease/vhdl/quadratic_func_bench.vhd
===================================================================
--- tags/arelease/vhdl/quadratic_func_bench.vhd (revision 5)
+++ tags/arelease/vhdl/quadratic_func_bench.vhd (nonexistent)
@@ -1,182 +0,0 @@
-----------------------------------------------------------------------
--- --
--- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
--- --
-----------------------------------------------------------------------
--- --
--- Filename : quadratic_func_bench.vhd --
--- --
--- Author : Simon Doherty --
--- Senior Design Consultant --
--- www.zipcores.com --
--- --
--- Date last modified : 16.02.2009 --
--- --
--- Description : Quadratic function testbench --
--- --
-----------------------------------------------------------------------
-
-
-use std.textio.all;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_textio.all;
-use ieee.std_logic_arith.all;
-
-
-entity quadratic_func_bench is
-begin
-end quadratic_func_bench;
-
-
-architecture behav of quadratic_func_bench is
-
-
-component quadratic_func
-
-generic ( fw : integer ); -- width of fraction in range 0 to 8
-
-port (
-
- -- system clock
- clk : in std_logic;
-
- -- clock enable
- en : in std_logic;
-
- -- Coefficients as 8-bit signed fraction
- coeff_a : in std_logic_vector(7 downto 0);
- coeff_b : in std_logic_vector(7 downto 0);
- coeff_c : in std_logic_vector(7 downto 0);
-
- -- Input as a 8-bit signed fraction
- x_in : in std_logic_vector(7 downto 0);
-
- -- Output as a 24-bit signed fraction
- y_out : out std_logic_vector(23 downto 0));
-
-end component;
-
-
-signal clk : std_logic := '0';
-signal reset : std_logic := '0';
-signal capture : std_logic := '0';
-signal end_of_test : std_logic := '0';
-signal count : std_logic_vector(7 downto 0);
-
-signal coeff_a : std_logic_vector(7 downto 0);
-signal coeff_b : std_logic_vector(7 downto 0);
-signal coeff_c : std_logic_vector(7 downto 0);
-
-signal x_in : std_logic_vector(7 downto 0);
-signal y_out : std_logic_vector(23 downto 0);
-signal y_int : integer;
-
-
-begin
-
-
--- Generate a 100MHz clk
-clk <= not clk after 5 ns;
-
-
--- Test bench control
-test_bench_control: process
-begin
- -- start of test
- wait for 1 us;
- wait until clk'event and clk = '1';
- -- bring out of reset
- reset <= '1';
- -- module has 3-cycle latency
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- -- start capturing the output
- capture <= '1';
- wait until clk'event and clk = '1' and end_of_test = '1';
- -- module has 3-cycle latency
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- -- stop capturing the output
- capture <= '0';
- wait for 1 us;
- wait until clk'event and clk = '1';
- assert false report " SIMULATION FINISHED!" severity failure;
-end process test_bench_control;
-
-
--- generate input sequence from -128 to 127
-counter: process(clk, reset)
-begin
- if reset = '0' then
- count <= "10000000";
- elsif clk'event and clk = '1' then
- count <= unsigned(count) + '1';
- end if;
-end process counter;
-
-
--- check for end of test
-end_of_test <= '1' when (count = "01111111") else '0';
-
-
--- Fixed coefficients
-coeff_a <= std_logic_vector(conv_signed( 55 ,8));
-coeff_b <= std_logic_vector(conv_signed(-14, 8));
-coeff_c <= std_logic_vector(conv_signed( 19 ,8));
-
-
--- Input stimulus
-x_in <= count;
-
-
--- DUT
-quad_func: quadratic_func
-
-generic map ( fw => 6 )
-
-port map (
-
- -- system clock
- clk => clk,
-
- -- clock enable
- en => '1',
-
- -- 8-bit signed coefficients
- coeff_a => coeff_a,
- coeff_b => coeff_b,
- coeff_c => coeff_c,
-
- -- 8-bit signed input
- x_in => x_in,
-
- -- 24-bit signed output
- y_out => y_out );
-
-
--- Convert 24-bit output to integer
-y_int <= conv_integer(unsigned(y_out));
-
-
--- Capture output data
-grab_data: process (clk)
-
- file terminal : text open write_mode is "quadratic_func_out.txt";
- variable resoutline : line;
-
-begin
-
- if clk'event and clk = '1' then
- if capture = '1' then
- write(resoutline, y_int);
- writeline(terminal, resoutline);
- end if;
- end if;
-end process grab_data;
-
-
-end behav;
Index: tags/arelease/vhdl/quadratic_func.vhd
===================================================================
--- tags/arelease/vhdl/quadratic_func.vhd (revision 5)
+++ tags/arelease/vhdl/quadratic_func.vhd (nonexistent)
@@ -1,203 +0,0 @@
-----------------------------------------------------------------------
--- --
--- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
--- --
-----------------------------------------------------------------------
--- --
--- Filename : quadratic_func.vhd --
--- --
--- Author : Simon Doherty --
--- Senior Design Consultant --
--- www.zipcores.com --
--- --
--- Date last modified : 16.02.2009 --
--- --
--- Description : Quadratic function computes the --
--- relation y = ax^2 + bx + c --
--- --
-----------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_signed.all;
-
-
-entity quadratic_func is
-
-generic ( fw : integer := 6 ); -- width of fraction in range 0 to 8
-
-port (
-
- -- system clock
- clk : in std_logic;
-
- -- clock enable
- en : in std_logic;
-
- -- Coefficients as 8-bit signed fraction
- coeff_a : in std_logic_vector(7 downto 0);
- coeff_b : in std_logic_vector(7 downto 0);
- coeff_c : in std_logic_vector(7 downto 0);
-
- -- Input as a 8-bit signed fraction
- x_in : in std_logic_vector(7 downto 0);
-
- -- Output as a 24-bit signed fraction
- y_out : out std_logic_vector(23 downto 0));
-
-end entity;
-
-
-architecture rtl of quadratic_func is
-
-
-signal zeros : std_logic_vector(23 downto 0);
-
-signal coeff_a_reg : std_logic_vector(7 downto 0);
-signal coeff_b_reg : std_logic_vector(7 downto 0);
-signal coeff_c_reg : std_logic_vector(7 downto 0);
-signal coeff_c_del : std_logic_vector(7 downto 0);
-
-signal x2 : std_logic_vector(15 downto 0);
-signal x2_a : std_logic_vector(23 downto 0);
-signal x2_a_norm : std_logic_vector(23 downto 0);
-
-signal x1 : std_logic_vector(7 downto 0);
-signal x1_del : std_logic_vector(7 downto 0);
-signal x1_b : std_logic_vector(15 downto 0);
-signal x1_b_norm : std_logic_vector(15 + fw downto 0);
-
-signal x0_c_norm : std_logic_vector(7 + fw*2 downto 0);
-
-signal sum : std_logic_vector(23 downto 0);
-signal sum_reg : std_logic_vector(23 downto 0);
-
-
-begin
-
-
------------------
--- For padding --
------------------
-
-zeros <= (others => '0');
-
--------------------------------------------------------
--- Rename input x term to maintain naming convention --
--------------------------------------------------------
-
-x1 <= x_in;
-
--------------------------------
--- Pipeline the coefficients --
--------------------------------
-
-coeff_regs: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- coeff_a_reg <= coeff_a;
- coeff_b_reg <= coeff_b;
- coeff_c_reg <= coeff_c;
- end if;
- end if;
-end process coeff_regs;
-
------------------------------------------
--- Delays to compenstate for latencies --
------------------------------------------
-
-pipe_reg_del: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- -- x term requires 1 cycle of delay
- x1_del <= x1;
- -- coeff c requires 1 cycle of delay
- coeff_c_del <= coeff_c_reg;
- end if;
- end if;
-end process pipe_reg_del;
-
---------------
--- x^2 term --
---------------
-
-pipe_reg_x2: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x2 <= x1 * x1; -- 8*8 = 16-bits
- end if;
- end if;
-end process pipe_reg_x2;
-
--------------------
--- x^2 * coeff_a --
--------------------
-
-pipe_reg_x2_a: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x2_a <= x2 * coeff_a_reg; -- 16*8 = 24-bits
- end if;
- end if;
-end process pipe_reg_x2_a;
-
------------------
--- x * coeff_b --
------------------
-
-pipe_reg_x1_b: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x1_b <= x1_del * coeff_b_reg; -- 8*8 = 16-bits
- end if;
- end if;
-end process pipe_reg_x1_b;
-
-----------------------------------------------
--- 24-bits + 16-bits + 8-bits --
--- --
--- Need to normalize the x1 and c terms so --
--- that the binary points line up --
--- --
--- x1 term << fw, c term << fw*2 --
-----------------------------------------------
-
-x2_a_norm <= x2_a;
-x1_b_norm <= x1_b & zeros(fw - 1 downto 0);
-x0_c_norm <= coeff_c_del & zeros(fw*2 - 1 downto 0);
-
-------------------------------------------------------------
--- (x^2 * coeff_a) + (x * coeff_b) + coeff_c (24-bit add) --
-------------------------------------------------------------
-
-sum <= x2_a_norm + x1_b_norm + x0_c_norm;
-
------------------------------
--- Register the output sum --
------------------------------
-
-out_reg: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- sum_reg <= sum;
- end if;
- end if;
-end process out_reg;
-
----------------------------------------------
--- 24-bit output --
--- Integer part of result is y_out >> fw*3 --
----------------------------------------------
-
-y_out <= sum_reg;
-
-
-end rtl;
\ No newline at end of file
Index: trunk/docs/quadratic_plot.png
===================================================================
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Index: trunk/docs/quadratic_plot.png
===================================================================
--- trunk/docs/quadratic_plot.png (revision 5)
+++ trunk/docs/quadratic_plot.png (nonexistent)
trunk/docs/quadratic_plot.png
Property changes :
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## -1 +0,0 ##
-application/octet-stream
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Index: trunk/docs/quadratic_func.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/docs/quadratic_func.pdf
===================================================================
--- trunk/docs/quadratic_func.pdf (revision 5)
+++ trunk/docs/quadratic_func.pdf (nonexistent)
trunk/docs/quadratic_func.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/docs/quadratic_func_block_diag.png
===================================================================
Cannot display: file marked as a binary type.
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Index: trunk/docs/quadratic_func_block_diag.png
===================================================================
--- trunk/docs/quadratic_func_block_diag.png (revision 5)
+++ trunk/docs/quadratic_func_block_diag.png (nonexistent)
trunk/docs/quadratic_func_block_diag.png
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/vhdl/quadratic_func_bench.vhd
===================================================================
--- trunk/vhdl/quadratic_func_bench.vhd (revision 5)
+++ trunk/vhdl/quadratic_func_bench.vhd (nonexistent)
@@ -1,182 +0,0 @@
-----------------------------------------------------------------------
--- --
--- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
--- --
-----------------------------------------------------------------------
--- --
--- Filename : quadratic_func_bench.vhd --
--- --
--- Author : Simon Doherty --
--- Senior Design Consultant --
--- www.zipcores.com --
--- --
--- Date last modified : 16.02.2009 --
--- --
--- Description : Quadratic function testbench --
--- --
-----------------------------------------------------------------------
-
-
-use std.textio.all;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_textio.all;
-use ieee.std_logic_arith.all;
-
-
-entity quadratic_func_bench is
-begin
-end quadratic_func_bench;
-
-
-architecture behav of quadratic_func_bench is
-
-
-component quadratic_func
-
-generic ( fw : integer ); -- width of fraction in range 0 to 8
-
-port (
-
- -- system clock
- clk : in std_logic;
-
- -- clock enable
- en : in std_logic;
-
- -- Coefficients as 8-bit signed fraction
- coeff_a : in std_logic_vector(7 downto 0);
- coeff_b : in std_logic_vector(7 downto 0);
- coeff_c : in std_logic_vector(7 downto 0);
-
- -- Input as a 8-bit signed fraction
- x_in : in std_logic_vector(7 downto 0);
-
- -- Output as a 24-bit signed fraction
- y_out : out std_logic_vector(23 downto 0));
-
-end component;
-
-
-signal clk : std_logic := '0';
-signal reset : std_logic := '0';
-signal capture : std_logic := '0';
-signal end_of_test : std_logic := '0';
-signal count : std_logic_vector(7 downto 0);
-
-signal coeff_a : std_logic_vector(7 downto 0);
-signal coeff_b : std_logic_vector(7 downto 0);
-signal coeff_c : std_logic_vector(7 downto 0);
-
-signal x_in : std_logic_vector(7 downto 0);
-signal y_out : std_logic_vector(23 downto 0);
-signal y_int : integer;
-
-
-begin
-
-
--- Generate a 100MHz clk
-clk <= not clk after 5 ns;
-
-
--- Test bench control
-test_bench_control: process
-begin
- -- start of test
- wait for 1 us;
- wait until clk'event and clk = '1';
- -- bring out of reset
- reset <= '1';
- -- module has 3-cycle latency
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- -- start capturing the output
- capture <= '1';
- wait until clk'event and clk = '1' and end_of_test = '1';
- -- module has 3-cycle latency
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- wait until clk'event and clk = '1';
- -- stop capturing the output
- capture <= '0';
- wait for 1 us;
- wait until clk'event and clk = '1';
- assert false report " SIMULATION FINISHED!" severity failure;
-end process test_bench_control;
-
-
--- generate input sequence from -128 to 127
-counter: process(clk, reset)
-begin
- if reset = '0' then
- count <= "10000000";
- elsif clk'event and clk = '1' then
- count <= unsigned(count) + '1';
- end if;
-end process counter;
-
-
--- check for end of test
-end_of_test <= '1' when (count = "01111111") else '0';
-
-
--- Fixed coefficients
-coeff_a <= std_logic_vector(conv_signed( 55 ,8));
-coeff_b <= std_logic_vector(conv_signed(-14, 8));
-coeff_c <= std_logic_vector(conv_signed( 19 ,8));
-
-
--- Input stimulus
-x_in <= count;
-
-
--- DUT
-quad_func: quadratic_func
-
-generic map ( fw => 6 )
-
-port map (
-
- -- system clock
- clk => clk,
-
- -- clock enable
- en => '1',
-
- -- 8-bit signed coefficients
- coeff_a => coeff_a,
- coeff_b => coeff_b,
- coeff_c => coeff_c,
-
- -- 8-bit signed input
- x_in => x_in,
-
- -- 24-bit signed output
- y_out => y_out );
-
-
--- Convert 24-bit output to integer
-y_int <= conv_integer(unsigned(y_out));
-
-
--- Capture output data
-grab_data: process (clk)
-
- file terminal : text open write_mode is "quadratic_func_out.txt";
- variable resoutline : line;
-
-begin
-
- if clk'event and clk = '1' then
- if capture = '1' then
- write(resoutline, y_int);
- writeline(terminal, resoutline);
- end if;
- end if;
-end process grab_data;
-
-
-end behav;
Index: trunk/vhdl/quadratic_func.vhd
===================================================================
--- trunk/vhdl/quadratic_func.vhd (revision 5)
+++ trunk/vhdl/quadratic_func.vhd (nonexistent)
@@ -1,203 +0,0 @@
-----------------------------------------------------------------------
--- --
--- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
--- --
-----------------------------------------------------------------------
--- --
--- Filename : quadratic_func.vhd --
--- --
--- Author : Simon Doherty --
--- Senior Design Consultant --
--- www.zipcores.com --
--- --
--- Date last modified : 16.02.2009 --
--- --
--- Description : Quadratic function computes the --
--- relation y = ax^2 + bx + c --
--- --
-----------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_signed.all;
-
-
-entity quadratic_func is
-
-generic ( fw : integer := 6 ); -- width of fraction in range 0 to 8
-
-port (
-
- -- system clock
- clk : in std_logic;
-
- -- clock enable
- en : in std_logic;
-
- -- Coefficients as 8-bit signed fraction
- coeff_a : in std_logic_vector(7 downto 0);
- coeff_b : in std_logic_vector(7 downto 0);
- coeff_c : in std_logic_vector(7 downto 0);
-
- -- Input as a 8-bit signed fraction
- x_in : in std_logic_vector(7 downto 0);
-
- -- Output as a 24-bit signed fraction
- y_out : out std_logic_vector(23 downto 0));
-
-end entity;
-
-
-architecture rtl of quadratic_func is
-
-
-signal zeros : std_logic_vector(23 downto 0);
-
-signal coeff_a_reg : std_logic_vector(7 downto 0);
-signal coeff_b_reg : std_logic_vector(7 downto 0);
-signal coeff_c_reg : std_logic_vector(7 downto 0);
-signal coeff_c_del : std_logic_vector(7 downto 0);
-
-signal x2 : std_logic_vector(15 downto 0);
-signal x2_a : std_logic_vector(23 downto 0);
-signal x2_a_norm : std_logic_vector(23 downto 0);
-
-signal x1 : std_logic_vector(7 downto 0);
-signal x1_del : std_logic_vector(7 downto 0);
-signal x1_b : std_logic_vector(15 downto 0);
-signal x1_b_norm : std_logic_vector(15 + fw downto 0);
-
-signal x0_c_norm : std_logic_vector(7 + fw*2 downto 0);
-
-signal sum : std_logic_vector(23 downto 0);
-signal sum_reg : std_logic_vector(23 downto 0);
-
-
-begin
-
-
------------------
--- For padding --
------------------
-
-zeros <= (others => '0');
-
--------------------------------------------------------
--- Rename input x term to maintain naming convention --
--------------------------------------------------------
-
-x1 <= x_in;
-
--------------------------------
--- Pipeline the coefficients --
--------------------------------
-
-coeff_regs: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- coeff_a_reg <= coeff_a;
- coeff_b_reg <= coeff_b;
- coeff_c_reg <= coeff_c;
- end if;
- end if;
-end process coeff_regs;
-
------------------------------------------
--- Delays to compenstate for latencies --
------------------------------------------
-
-pipe_reg_del: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- -- x term requires 1 cycle of delay
- x1_del <= x1;
- -- coeff c requires 1 cycle of delay
- coeff_c_del <= coeff_c_reg;
- end if;
- end if;
-end process pipe_reg_del;
-
---------------
--- x^2 term --
---------------
-
-pipe_reg_x2: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x2 <= x1 * x1; -- 8*8 = 16-bits
- end if;
- end if;
-end process pipe_reg_x2;
-
--------------------
--- x^2 * coeff_a --
--------------------
-
-pipe_reg_x2_a: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x2_a <= x2 * coeff_a_reg; -- 16*8 = 24-bits
- end if;
- end if;
-end process pipe_reg_x2_a;
-
------------------
--- x * coeff_b --
------------------
-
-pipe_reg_x1_b: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- x1_b <= x1_del * coeff_b_reg; -- 8*8 = 16-bits
- end if;
- end if;
-end process pipe_reg_x1_b;
-
-----------------------------------------------
--- 24-bits + 16-bits + 8-bits --
--- --
--- Need to normalize the x1 and c terms so --
--- that the binary points line up --
--- --
--- x1 term << fw, c term << fw*2 --
-----------------------------------------------
-
-x2_a_norm <= x2_a;
-x1_b_norm <= x1_b & zeros(fw - 1 downto 0);
-x0_c_norm <= coeff_c_del & zeros(fw*2 - 1 downto 0);
-
-------------------------------------------------------------
--- (x^2 * coeff_a) + (x * coeff_b) + coeff_c (24-bit add) --
-------------------------------------------------------------
-
-sum <= x2_a_norm + x1_b_norm + x0_c_norm;
-
------------------------------
--- Register the output sum --
------------------------------
-
-out_reg: process (clk)
-begin
- if clk'event and clk = '1' then
- if en = '1' then
- sum_reg <= sum;
- end if;
- end if;
-end process out_reg;
-
----------------------------------------------
--- 24-bit output --
--- Integer part of result is y_out >> fw*3 --
----------------------------------------------
-
-y_out <= sum_reg;
-
-
-end rtl;
\ No newline at end of file
Index: quadratic_func/trunk/docs/quadratic_plot.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: quadratic_func/trunk/docs/quadratic_plot.png
===================================================================
--- quadratic_func/trunk/docs/quadratic_plot.png (nonexistent)
+++ quadratic_func/trunk/docs/quadratic_plot.png (revision 6)
quadratic_func/trunk/docs/quadratic_plot.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: quadratic_func/trunk/docs/quadratic_func_block_diag.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: quadratic_func/trunk/docs/quadratic_func_block_diag.png
===================================================================
--- quadratic_func/trunk/docs/quadratic_func_block_diag.png (nonexistent)
+++ quadratic_func/trunk/docs/quadratic_func_block_diag.png (revision 6)
quadratic_func/trunk/docs/quadratic_func_block_diag.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: quadratic_func/trunk/docs/quadratic_func.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: quadratic_func/trunk/docs/quadratic_func.pdf
===================================================================
--- quadratic_func/trunk/docs/quadratic_func.pdf (nonexistent)
+++ quadratic_func/trunk/docs/quadratic_func.pdf (revision 6)
quadratic_func/trunk/docs/quadratic_func.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: quadratic_func/trunk/vhdl/quadratic_func_bench.vhd
===================================================================
--- quadratic_func/trunk/vhdl/quadratic_func_bench.vhd (nonexistent)
+++ quadratic_func/trunk/vhdl/quadratic_func_bench.vhd (revision 6)
@@ -0,0 +1,182 @@
+----------------------------------------------------------------------
+-- --
+-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
+-- --
+----------------------------------------------------------------------
+-- --
+-- Filename : quadratic_func_bench.vhd --
+-- --
+-- Author : Simon Doherty --
+-- Senior Design Consultant --
+-- www.zipcores.com --
+-- --
+-- Date last modified : 16.02.2009 --
+-- --
+-- Description : Quadratic function testbench --
+-- --
+----------------------------------------------------------------------
+
+
+use std.textio.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_textio.all;
+use ieee.std_logic_arith.all;
+
+
+entity quadratic_func_bench is
+begin
+end quadratic_func_bench;
+
+
+architecture behav of quadratic_func_bench is
+
+
+component quadratic_func
+
+generic ( fw : integer ); -- width of fraction in range 0 to 8
+
+port (
+
+ -- system clock
+ clk : in std_logic;
+
+ -- clock enable
+ en : in std_logic;
+
+ -- Coefficients as 8-bit signed fraction
+ coeff_a : in std_logic_vector(7 downto 0);
+ coeff_b : in std_logic_vector(7 downto 0);
+ coeff_c : in std_logic_vector(7 downto 0);
+
+ -- Input as a 8-bit signed fraction
+ x_in : in std_logic_vector(7 downto 0);
+
+ -- Output as a 24-bit signed fraction
+ y_out : out std_logic_vector(23 downto 0));
+
+end component;
+
+
+signal clk : std_logic := '0';
+signal reset : std_logic := '0';
+signal capture : std_logic := '0';
+signal end_of_test : std_logic := '0';
+signal count : std_logic_vector(7 downto 0);
+
+signal coeff_a : std_logic_vector(7 downto 0);
+signal coeff_b : std_logic_vector(7 downto 0);
+signal coeff_c : std_logic_vector(7 downto 0);
+
+signal x_in : std_logic_vector(7 downto 0);
+signal y_out : std_logic_vector(23 downto 0);
+signal y_int : integer;
+
+
+begin
+
+
+-- Generate a 100MHz clk
+clk <= not clk after 5 ns;
+
+
+-- Test bench control
+test_bench_control: process
+begin
+ -- start of test
+ wait for 1 us;
+ wait until clk'event and clk = '1';
+ -- bring out of reset
+ reset <= '1';
+ -- module has 3-cycle latency
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ -- start capturing the output
+ capture <= '1';
+ wait until clk'event and clk = '1' and end_of_test = '1';
+ -- module has 3-cycle latency
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ -- stop capturing the output
+ capture <= '0';
+ wait for 1 us;
+ wait until clk'event and clk = '1';
+ assert false report " SIMULATION FINISHED!" severity failure;
+end process test_bench_control;
+
+
+-- generate input sequence from -128 to 127
+counter: process(clk, reset)
+begin
+ if reset = '0' then
+ count <= "10000000";
+ elsif clk'event and clk = '1' then
+ count <= unsigned(count) + '1';
+ end if;
+end process counter;
+
+
+-- check for end of test
+end_of_test <= '1' when (count = "01111111") else '0';
+
+
+-- Fixed coefficients
+coeff_a <= std_logic_vector(conv_signed( 55 ,8));
+coeff_b <= std_logic_vector(conv_signed(-14, 8));
+coeff_c <= std_logic_vector(conv_signed( 19 ,8));
+
+
+-- Input stimulus
+x_in <= count;
+
+
+-- DUT
+quad_func: quadratic_func
+
+generic map ( fw => 6 )
+
+port map (
+
+ -- system clock
+ clk => clk,
+
+ -- clock enable
+ en => '1',
+
+ -- 8-bit signed coefficients
+ coeff_a => coeff_a,
+ coeff_b => coeff_b,
+ coeff_c => coeff_c,
+
+ -- 8-bit signed input
+ x_in => x_in,
+
+ -- 24-bit signed output
+ y_out => y_out );
+
+
+-- Convert 24-bit output to integer
+y_int <= conv_integer(unsigned(y_out));
+
+
+-- Capture output data
+grab_data: process (clk)
+
+ file terminal : text open write_mode is "quadratic_func_out.txt";
+ variable resoutline : line;
+
+begin
+
+ if clk'event and clk = '1' then
+ if capture = '1' then
+ write(resoutline, y_int);
+ writeline(terminal, resoutline);
+ end if;
+ end if;
+end process grab_data;
+
+
+end behav;
Index: quadratic_func/trunk/vhdl/quadratic_func.vhd
===================================================================
--- quadratic_func/trunk/vhdl/quadratic_func.vhd (nonexistent)
+++ quadratic_func/trunk/vhdl/quadratic_func.vhd (revision 6)
@@ -0,0 +1,203 @@
+----------------------------------------------------------------------
+-- --
+-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
+-- --
+----------------------------------------------------------------------
+-- --
+-- Filename : quadratic_func.vhd --
+-- --
+-- Author : Simon Doherty --
+-- Senior Design Consultant --
+-- www.zipcores.com --
+-- --
+-- Date last modified : 16.02.2009 --
+-- --
+-- Description : Quadratic function computes the --
+-- relation y = ax^2 + bx + c --
+-- --
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+
+entity quadratic_func is
+
+generic ( fw : integer := 6 ); -- width of fraction in range 0 to 8
+
+port (
+
+ -- system clock
+ clk : in std_logic;
+
+ -- clock enable
+ en : in std_logic;
+
+ -- Coefficients as 8-bit signed fraction
+ coeff_a : in std_logic_vector(7 downto 0);
+ coeff_b : in std_logic_vector(7 downto 0);
+ coeff_c : in std_logic_vector(7 downto 0);
+
+ -- Input as a 8-bit signed fraction
+ x_in : in std_logic_vector(7 downto 0);
+
+ -- Output as a 24-bit signed fraction
+ y_out : out std_logic_vector(23 downto 0));
+
+end entity;
+
+
+architecture rtl of quadratic_func is
+
+
+signal zeros : std_logic_vector(23 downto 0);
+
+signal coeff_a_reg : std_logic_vector(7 downto 0);
+signal coeff_b_reg : std_logic_vector(7 downto 0);
+signal coeff_c_reg : std_logic_vector(7 downto 0);
+signal coeff_c_del : std_logic_vector(7 downto 0);
+
+signal x2 : std_logic_vector(15 downto 0);
+signal x2_a : std_logic_vector(23 downto 0);
+signal x2_a_norm : std_logic_vector(23 downto 0);
+
+signal x1 : std_logic_vector(7 downto 0);
+signal x1_del : std_logic_vector(7 downto 0);
+signal x1_b : std_logic_vector(15 downto 0);
+signal x1_b_norm : std_logic_vector(15 + fw downto 0);
+
+signal x0_c_norm : std_logic_vector(7 + fw*2 downto 0);
+
+signal sum : std_logic_vector(23 downto 0);
+signal sum_reg : std_logic_vector(23 downto 0);
+
+
+begin
+
+
+-----------------
+-- For padding --
+-----------------
+
+zeros <= (others => '0');
+
+-------------------------------------------------------
+-- Rename input x term to maintain naming convention --
+-------------------------------------------------------
+
+x1 <= x_in;
+
+-------------------------------
+-- Pipeline the coefficients --
+-------------------------------
+
+coeff_regs: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ coeff_a_reg <= coeff_a;
+ coeff_b_reg <= coeff_b;
+ coeff_c_reg <= coeff_c;
+ end if;
+ end if;
+end process coeff_regs;
+
+-----------------------------------------
+-- Delays to compenstate for latencies --
+-----------------------------------------
+
+pipe_reg_del: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ -- x term requires 1 cycle of delay
+ x1_del <= x1;
+ -- coeff c requires 1 cycle of delay
+ coeff_c_del <= coeff_c_reg;
+ end if;
+ end if;
+end process pipe_reg_del;
+
+--------------
+-- x^2 term --
+--------------
+
+pipe_reg_x2: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x2 <= x1 * x1; -- 8*8 = 16-bits
+ end if;
+ end if;
+end process pipe_reg_x2;
+
+-------------------
+-- x^2 * coeff_a --
+-------------------
+
+pipe_reg_x2_a: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x2_a <= x2 * coeff_a_reg; -- 16*8 = 24-bits
+ end if;
+ end if;
+end process pipe_reg_x2_a;
+
+-----------------
+-- x * coeff_b --
+-----------------
+
+pipe_reg_x1_b: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x1_b <= x1_del * coeff_b_reg; -- 8*8 = 16-bits
+ end if;
+ end if;
+end process pipe_reg_x1_b;
+
+----------------------------------------------
+-- 24-bits + 16-bits + 8-bits --
+-- --
+-- Need to normalize the x1 and c terms so --
+-- that the binary points line up --
+-- --
+-- x1 term << fw, c term << fw*2 --
+----------------------------------------------
+
+x2_a_norm <= x2_a;
+x1_b_norm <= x1_b & zeros(fw - 1 downto 0);
+x0_c_norm <= coeff_c_del & zeros(fw*2 - 1 downto 0);
+
+------------------------------------------------------------
+-- (x^2 * coeff_a) + (x * coeff_b) + coeff_c (24-bit add) --
+------------------------------------------------------------
+
+sum <= x2_a_norm + x1_b_norm + x0_c_norm;
+
+-----------------------------
+-- Register the output sum --
+-----------------------------
+
+out_reg: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ sum_reg <= sum;
+ end if;
+ end if;
+end process out_reg;
+
+---------------------------------------------
+-- 24-bit output --
+-- Integer part of result is y_out >> fw*3 --
+---------------------------------------------
+
+y_out <= sum_reg;
+
+
+end rtl;
\ No newline at end of file
Index: quadratic_func/trunk
===================================================================
--- quadratic_func/trunk (nonexistent)
+++ quadratic_func/trunk (revision 6)
quadratic_func/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: quadratic_func/web_uploads
===================================================================
--- quadratic_func/web_uploads (nonexistent)
+++ quadratic_func/web_uploads (revision 6)
quadratic_func/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: quadratic_func/branches
===================================================================
--- quadratic_func/branches (nonexistent)
+++ quadratic_func/branches (revision 6)
quadratic_func/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: quadratic_func/tags/arelease/docs/quadratic_func.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: quadratic_func/tags/arelease/docs/quadratic_func.pdf
===================================================================
--- quadratic_func/tags/arelease/docs/quadratic_func.pdf (nonexistent)
+++ quadratic_func/tags/arelease/docs/quadratic_func.pdf (revision 6)
quadratic_func/tags/arelease/docs/quadratic_func.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: quadratic_func/tags/arelease/vhdl/quadratic_func_bench.vhd
===================================================================
--- quadratic_func/tags/arelease/vhdl/quadratic_func_bench.vhd (nonexistent)
+++ quadratic_func/tags/arelease/vhdl/quadratic_func_bench.vhd (revision 6)
@@ -0,0 +1,182 @@
+----------------------------------------------------------------------
+-- --
+-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
+-- --
+----------------------------------------------------------------------
+-- --
+-- Filename : quadratic_func_bench.vhd --
+-- --
+-- Author : Simon Doherty --
+-- Senior Design Consultant --
+-- www.zipcores.com --
+-- --
+-- Date last modified : 16.02.2009 --
+-- --
+-- Description : Quadratic function testbench --
+-- --
+----------------------------------------------------------------------
+
+
+use std.textio.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_textio.all;
+use ieee.std_logic_arith.all;
+
+
+entity quadratic_func_bench is
+begin
+end quadratic_func_bench;
+
+
+architecture behav of quadratic_func_bench is
+
+
+component quadratic_func
+
+generic ( fw : integer ); -- width of fraction in range 0 to 8
+
+port (
+
+ -- system clock
+ clk : in std_logic;
+
+ -- clock enable
+ en : in std_logic;
+
+ -- Coefficients as 8-bit signed fraction
+ coeff_a : in std_logic_vector(7 downto 0);
+ coeff_b : in std_logic_vector(7 downto 0);
+ coeff_c : in std_logic_vector(7 downto 0);
+
+ -- Input as a 8-bit signed fraction
+ x_in : in std_logic_vector(7 downto 0);
+
+ -- Output as a 24-bit signed fraction
+ y_out : out std_logic_vector(23 downto 0));
+
+end component;
+
+
+signal clk : std_logic := '0';
+signal reset : std_logic := '0';
+signal capture : std_logic := '0';
+signal end_of_test : std_logic := '0';
+signal count : std_logic_vector(7 downto 0);
+
+signal coeff_a : std_logic_vector(7 downto 0);
+signal coeff_b : std_logic_vector(7 downto 0);
+signal coeff_c : std_logic_vector(7 downto 0);
+
+signal x_in : std_logic_vector(7 downto 0);
+signal y_out : std_logic_vector(23 downto 0);
+signal y_int : integer;
+
+
+begin
+
+
+-- Generate a 100MHz clk
+clk <= not clk after 5 ns;
+
+
+-- Test bench control
+test_bench_control: process
+begin
+ -- start of test
+ wait for 1 us;
+ wait until clk'event and clk = '1';
+ -- bring out of reset
+ reset <= '1';
+ -- module has 3-cycle latency
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ -- start capturing the output
+ capture <= '1';
+ wait until clk'event and clk = '1' and end_of_test = '1';
+ -- module has 3-cycle latency
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ -- stop capturing the output
+ capture <= '0';
+ wait for 1 us;
+ wait until clk'event and clk = '1';
+ assert false report " SIMULATION FINISHED!" severity failure;
+end process test_bench_control;
+
+
+-- generate input sequence from -128 to 127
+counter: process(clk, reset)
+begin
+ if reset = '0' then
+ count <= "10000000";
+ elsif clk'event and clk = '1' then
+ count <= unsigned(count) + '1';
+ end if;
+end process counter;
+
+
+-- check for end of test
+end_of_test <= '1' when (count = "01111111") else '0';
+
+
+-- Fixed coefficients
+coeff_a <= std_logic_vector(conv_signed( 55 ,8));
+coeff_b <= std_logic_vector(conv_signed(-14, 8));
+coeff_c <= std_logic_vector(conv_signed( 19 ,8));
+
+
+-- Input stimulus
+x_in <= count;
+
+
+-- DUT
+quad_func: quadratic_func
+
+generic map ( fw => 6 )
+
+port map (
+
+ -- system clock
+ clk => clk,
+
+ -- clock enable
+ en => '1',
+
+ -- 8-bit signed coefficients
+ coeff_a => coeff_a,
+ coeff_b => coeff_b,
+ coeff_c => coeff_c,
+
+ -- 8-bit signed input
+ x_in => x_in,
+
+ -- 24-bit signed output
+ y_out => y_out );
+
+
+-- Convert 24-bit output to integer
+y_int <= conv_integer(unsigned(y_out));
+
+
+-- Capture output data
+grab_data: process (clk)
+
+ file terminal : text open write_mode is "quadratic_func_out.txt";
+ variable resoutline : line;
+
+begin
+
+ if clk'event and clk = '1' then
+ if capture = '1' then
+ write(resoutline, y_int);
+ writeline(terminal, resoutline);
+ end if;
+ end if;
+end process grab_data;
+
+
+end behav;
Index: quadratic_func/tags/arelease/vhdl/quadratic_func.vhd
===================================================================
--- quadratic_func/tags/arelease/vhdl/quadratic_func.vhd (nonexistent)
+++ quadratic_func/tags/arelease/vhdl/quadratic_func.vhd (revision 6)
@@ -0,0 +1,203 @@
+----------------------------------------------------------------------
+-- --
+-- THIS VHDL SOURCE CODE IS PROVIDED UNDER THE GNU PUBLIC LICENSE --
+-- --
+----------------------------------------------------------------------
+-- --
+-- Filename : quadratic_func.vhd --
+-- --
+-- Author : Simon Doherty --
+-- Senior Design Consultant --
+-- www.zipcores.com --
+-- --
+-- Date last modified : 16.02.2009 --
+-- --
+-- Description : Quadratic function computes the --
+-- relation y = ax^2 + bx + c --
+-- --
+----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+
+entity quadratic_func is
+
+generic ( fw : integer := 6 ); -- width of fraction in range 0 to 8
+
+port (
+
+ -- system clock
+ clk : in std_logic;
+
+ -- clock enable
+ en : in std_logic;
+
+ -- Coefficients as 8-bit signed fraction
+ coeff_a : in std_logic_vector(7 downto 0);
+ coeff_b : in std_logic_vector(7 downto 0);
+ coeff_c : in std_logic_vector(7 downto 0);
+
+ -- Input as a 8-bit signed fraction
+ x_in : in std_logic_vector(7 downto 0);
+
+ -- Output as a 24-bit signed fraction
+ y_out : out std_logic_vector(23 downto 0));
+
+end entity;
+
+
+architecture rtl of quadratic_func is
+
+
+signal zeros : std_logic_vector(23 downto 0);
+
+signal coeff_a_reg : std_logic_vector(7 downto 0);
+signal coeff_b_reg : std_logic_vector(7 downto 0);
+signal coeff_c_reg : std_logic_vector(7 downto 0);
+signal coeff_c_del : std_logic_vector(7 downto 0);
+
+signal x2 : std_logic_vector(15 downto 0);
+signal x2_a : std_logic_vector(23 downto 0);
+signal x2_a_norm : std_logic_vector(23 downto 0);
+
+signal x1 : std_logic_vector(7 downto 0);
+signal x1_del : std_logic_vector(7 downto 0);
+signal x1_b : std_logic_vector(15 downto 0);
+signal x1_b_norm : std_logic_vector(15 + fw downto 0);
+
+signal x0_c_norm : std_logic_vector(7 + fw*2 downto 0);
+
+signal sum : std_logic_vector(23 downto 0);
+signal sum_reg : std_logic_vector(23 downto 0);
+
+
+begin
+
+
+-----------------
+-- For padding --
+-----------------
+
+zeros <= (others => '0');
+
+-------------------------------------------------------
+-- Rename input x term to maintain naming convention --
+-------------------------------------------------------
+
+x1 <= x_in;
+
+-------------------------------
+-- Pipeline the coefficients --
+-------------------------------
+
+coeff_regs: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ coeff_a_reg <= coeff_a;
+ coeff_b_reg <= coeff_b;
+ coeff_c_reg <= coeff_c;
+ end if;
+ end if;
+end process coeff_regs;
+
+-----------------------------------------
+-- Delays to compenstate for latencies --
+-----------------------------------------
+
+pipe_reg_del: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ -- x term requires 1 cycle of delay
+ x1_del <= x1;
+ -- coeff c requires 1 cycle of delay
+ coeff_c_del <= coeff_c_reg;
+ end if;
+ end if;
+end process pipe_reg_del;
+
+--------------
+-- x^2 term --
+--------------
+
+pipe_reg_x2: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x2 <= x1 * x1; -- 8*8 = 16-bits
+ end if;
+ end if;
+end process pipe_reg_x2;
+
+-------------------
+-- x^2 * coeff_a --
+-------------------
+
+pipe_reg_x2_a: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x2_a <= x2 * coeff_a_reg; -- 16*8 = 24-bits
+ end if;
+ end if;
+end process pipe_reg_x2_a;
+
+-----------------
+-- x * coeff_b --
+-----------------
+
+pipe_reg_x1_b: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ x1_b <= x1_del * coeff_b_reg; -- 8*8 = 16-bits
+ end if;
+ end if;
+end process pipe_reg_x1_b;
+
+----------------------------------------------
+-- 24-bits + 16-bits + 8-bits --
+-- --
+-- Need to normalize the x1 and c terms so --
+-- that the binary points line up --
+-- --
+-- x1 term << fw, c term << fw*2 --
+----------------------------------------------
+
+x2_a_norm <= x2_a;
+x1_b_norm <= x1_b & zeros(fw - 1 downto 0);
+x0_c_norm <= coeff_c_del & zeros(fw*2 - 1 downto 0);
+
+------------------------------------------------------------
+-- (x^2 * coeff_a) + (x * coeff_b) + coeff_c (24-bit add) --
+------------------------------------------------------------
+
+sum <= x2_a_norm + x1_b_norm + x0_c_norm;
+
+-----------------------------
+-- Register the output sum --
+-----------------------------
+
+out_reg: process (clk)
+begin
+ if clk'event and clk = '1' then
+ if en = '1' then
+ sum_reg <= sum;
+ end if;
+ end if;
+end process out_reg;
+
+---------------------------------------------
+-- 24-bit output --
+-- Integer part of result is y_out >> fw*3 --
+---------------------------------------------
+
+y_out <= sum_reg;
+
+
+end rtl;
\ No newline at end of file
Index: quadratic_func/tags
===================================================================
--- quadratic_func/tags (nonexistent)
+++ quadratic_func/tags (revision 6)
quadratic_func/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##