URL
https://opencores.org/ocsvn/uart/uart/trunk
Subversion Repositories uart
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- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/miniUART.vhd
21,10 → 21,14
--===========================================================================-- |
------------------------------------------------------------------------------- |
-- Revision list |
-- Version Author Date Changes |
-- Version Author Date Changes |
-- |
-- 0.1 Ovidiu Lupas 15 January 2000 New model |
-- ovilup@mail.dnttm.ro |
-- 0.1 Ovidiu Lupas 15 January 2000 New model |
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations |
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl |
-- the RSBusCtrl did not process all possible situations |
-- |
-- olupas@opencores.org |
------------------------------------------------------------------------------- |
-- Description : The memory consists of a dual-port memory addressed by |
-- two counters (RdCnt & WrCnt). The third counter (StatCnt) |
127,7 → 131,7
-- Implements the controller for Rx&Tx units |
----------------------------------------------------------------------------- |
RSBusCtrl : process(SysClk,Reset,Read,Load) |
variable StatM : unsigned(4 downto 0); |
variable StatM : Std_Logic_Vector(4 downto 0); |
begin |
if Rising_Edge(SysClk) then |
if Reset = '0' then |
146,6 → 150,9
when "00001" => |
IntRx_N <= '0'; |
CSReg(2) <= '1'; |
when "10001" => |
IntRx_N <= '0'; |
CSReg(2) <= '1'; |
when "01000" => |
IntTx_N <= '0'; |
when "11000" => |
194,4 → 201,4
TxData <= DataIn; |
end if; |
end process; |
end uart; --===================== End of architecture =======================-- |
end uart; --===================== End of architecture =======================-- |