URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
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- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/verilog/UART_regs.v
179,7 → 179,7
if (dlab) |
begin |
dl[`DL2] <= #1 wb_dat_i; |
dlc <= #1 dl; // reset the counter to dl value |
// dlc <= #1 dl; // reset the counter to dl value |
end |
else |
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb |
202,7 → 202,7
if (dlab) |
begin |
dl[`DL3] <= #1 wb_dat_i; |
dlc <= #1 dl; |
// dlc <= #1 dl; |
end |
else |
mcr <= #1 wb_dat_i[4:0]; |
262,7 → 262,7
if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4) |
begin |
dl[`DL4] <= #1 wb_dat_i; |
dlc <= #1 dl; |
// dlc <= #1 dl; |
end |
|
// |
280,6 → 280,12
always @(posedge wb_rst_i) |
dl <= #1 32'b0; |
|
always @(posedge wb_rst_i) |
begin |
dlc <= #1 32'hffffffff; // no enable signal will be generated |
end |
|
|
// Line Status Register is after the transmitter |
|
// Enable signal generation logic |
290,6 → 296,8
dlc <= #1 dl; |
else |
dlc <= #1 dlc - 1; // decrease count |
else |
dlc <= #1 32'hffffffff; // so that no enable signal will be generated |
end |
|
always @(dlc) |
/trunk/verilog/ToDo.txt
1,8 → 1,11
TODO: |
(+ done, ! working) |
|
! * Interrupts |
! * Status registers |
+ * Interrupts |
+ * Status registers |
+ * Break detection |
+ * RX fifo overrun detection |
* Timeout detection |
+ * Timeout detection |
|
* Test bench |
* more checking |