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/z80control/trunk/DE1/CII_Starter_USB_API.sof
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z80control/trunk/DE1/CII_Starter_USB_API.sof
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Index: z80control/trunk/DE1/rtl/VHDL/led_driver.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/led_driver.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/led_driver.vhd (revision 6)
@@ -0,0 +1,23 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+USE IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity led_driver is
+ port
+ (
+ ENABLE : in std_logic;
+ BYTE : in std_logic_vector(7 downto 0);
+ LEDBYTE : out std_logic_vector(7 downto 0)
+ );
+end led_driver;
+
+architecture rtl of led_driver is
+begin
+process(ENABLE, BYTE)
+begin
+ if (ENABLE = '1')then
+ LEDBYTE <= BYTE;
+ end if;
+end process;
+end rtl;
+
Index: z80control/trunk/DE1/rtl/VHDL/top_de1.vhd.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/top_de1.vhd.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/top_de1.vhd.bak (revision 6)
@@ -0,0 +1,642 @@
+-------------------------------------------------------------------------------------------------
+-- Z80_Soc (Z80 System on Chip)
+--
+-- Version history:
+-------------------
+-- version 0.6 for for Altera DE1
+-- Release Date: 2008 / 05 / 21
+--
+-- Version 0.5 Beta for Altera DE1
+-- Developer: Ronivon Candido Costa
+-- Release Date: 2008 / 04 / 16
+--
+-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
+-- This version developed and tested on: Altera DE1 Development Board
+--
+-- Peripherals configured (Using Ports):
+--
+-- 40 KB Internal ROM Read (0x0000h - 0x9FFFh)
+-- 08 KB Shared Memory Read/Write (0xA000h - 0xBFFFh)
+-- Locked Supr1 (0xC000h - 0xC7FFh)
+-- Supr2 (0xC800h - 0xCFFFh)
+-- Supr3 (0xD000h - 0xD7FFh)
+-- Supr4 (0xD800h - 0xDFFFh) -- Stack starts at DFEA and goes down
+-- Supr5 (0xE000h - 0xE7FFh)
+-- Supr6 (0xE800h - 0xEFFFh)
+-- Pram Locked (0xF000h - 0xF7FFh) -- Switched between 5 banks
+-- Sram (0xF800h - 0xF8FFh) -- Switched between 5 banks
+-- Ram (0xF900h - 0xFFFFh) -- Switched between 5 banks
+
+-- 08 Green Leds Out (Port 0x01h)
+-- 08 Red Leds Out (Port 0x02h)
+-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
+-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
+------------- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
+
+-- 01 Uart0 In/Out (Port 0x24h)
+
+-- 01 Rom Switching Out (Port 0xDDh)
+-- 02 Rom Switching Out (Port 0xDDh)
+-- 03 Rom Switching Out (Port 0xDDh)
+
+-- 00 to 07 Ram Switching Out (Port 0xDCh)
+
+--PRF F0h
+--STATS,RTCIN F0h --Brown Out and Pwr Fail Stat 60Hz
+--PFKILL F1h
+--RTCRST F2h
+--SFTPRT F3h
+--MEXPON F4h
+--MEXPOFF F5h
+--IOXPON F6h
+--IOXPOFF F7h
+
+--EPPAGE1 FCh
+--EPPAGE2 FDh
+
+-- 08 Switches In (Port 0x20h)
+-- 04 Push buttons In (Port 0x30h)
+-- 01 PS/2 keyboard In (Port 0x80h)
+-- 01 Video write port In (Port 0x90h)
+
+--
+-- Revision history:
+--
+-- 2008/05/23 - Modified RAM layout to support new and future improvements
+-- - Added port 0x90 to write a character to video.
+-- - Cursor x,y automatically updated after writing to port 0x90
+-- - Added port 0x91 for video cursor X
+-- - Added port 0x92 for video cursor Y
+-- - Updated ROM to demonstrate how to use these new resources
+-- - Changed ROM to support 14 bit addresses (16 Kb)
+--
+-- 2008/05/12 - Added support for the Rotary Knob
+-- - ROT_CENTER push button (Knob) reserved for RESET
+-- - The four push buttons are now available for the user (Port 0x30)
+--
+-- 2008/05/11 - Fixed access to RAM and VRAM,
+-- Released same ROM version for DE1 and S3E
+--
+-- 2008/05/01 - Added LCD support for Spartan 3E
+--
+-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
+--
+-- 2008/04/17 - Added Video support for 40x30 mode
+--
+-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
+--
+-- TO-DO:
+-- - Implement hardware control for the A/D and IO pins
+-- - Monitor program to introduce Z80 Assmebly codes and run
+-- - Serial communication, to download assembly code from PC
+-- - Add hardware support for 80x40 Video out
+-- - SD/MMC card interface to read/store data and programs
+-------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity TOP_DE1 is
+ port(
+
+ -- Clocks
+ CLOCK_27, -- 27 MHz
+ CLOCK_50, -- 50 MHz
+ EXT_CLOCK : in std_logic; -- External Clock
+
+ -- Buttons and switches
+ KEY : in std_logic_vector(3 downto 0); -- Push buttons
+ SW : in std_logic_vector(9 downto 0); -- Switches
+
+ -- LED displays
+ HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
+ : out std_logic_vector(6 downto 0);
+ LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
+ LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
+
+ -- RS-232 interface
+ UART_TXD : out std_logic; -- UART transmitter
+ UART_RXD : in std_logic; -- UART receiver
+
+ -- IRDA interface
+
+ -- IRDA_TXD : out std_logic; -- IRDA Transmitter
+ IRDA_RXD : in std_logic; -- IRDA Receiver
+
+ -- SDRAM
+ DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
+ DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
+ DRAM_LDQM, -- Low-byte Data Mask
+ DRAM_UDQM, -- High-byte Data Mask
+ DRAM_WE_N, -- Write Enable
+ DRAM_CAS_N, -- Column Address Strobe
+ DRAM_RAS_N, -- Row Address Strobe
+ DRAM_CS_N, -- Chip Select
+ DRAM_BA_0, -- Bank Address 0
+ DRAM_BA_1, -- Bank Address 0
+ DRAM_CLK, -- Clock
+ DRAM_CKE : out std_logic; -- Clock Enable
+
+ -- FLASH
+ FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
+ FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
+ FL_WE_N : out std_logic; -- Write Enable
+ FL_RST_N : out std_logic; -- Reset
+ FL_OE_N : out std_logic; -- Output Enable
+ FL_CE_N : out std_logic; -- Chip Enable
+
+ -- SRAM
+ SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
+ SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
+ SRAM_UB_N : out std_logic; -- High-byte Data Mask
+ SRAM_LB_N : out std_logic; -- Low-byte Data Mask
+ SRAM_WE_N : out std_logic; -- Write Enable
+ SRAM_CE_N : out std_logic; -- Chip Enable
+ SRAM_OE_N : out std_logic; -- Output Enable
+
+ -- SD card interface
+ SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
+ SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
+ SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
+ SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
+
+ -- USB JTAG link
+ TDI, -- CPLD -> FPGA (data in)
+ TCK, -- CPLD -> FPGA (clk)
+ TCS : in std_logic; -- CPLD -> FPGA (CS)
+ TDO : out std_logic; -- FPGA -> CPLD (data out)
+
+ -- I2C bus
+ I2C_SDAT : inout std_logic; -- I2C Data
+ I2C_SCLK : out std_logic; -- I2C Clock
+
+ -- PS/2 port
+ PS2_DAT, -- Data
+ PS2_CLK : inout std_logic; -- Clock
+
+ -- VGA output
+ VGA_HS, -- H_SYNC
+ VGA_VS : out std_logic; -- SYNC
+ VGA_R, -- Red[3:0]
+ VGA_G, -- Green[3:0]
+ VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
+
+ -- Audio CODEC
+ AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
+ AUD_ADCDAT : in std_logic; -- ADC Data
+ AUD_DACLRCK : inout std_logic; -- DAC LR Clock
+ AUD_DACDAT : out std_logic; -- DAC Data
+ AUD_BCLK : inout std_logic; -- Bit-Stream Clock
+ AUD_XCK : out std_logic; -- Chip Clock
+
+ -- General-purpose I/O
+ GPIO_0, -- GPIO Connection 0
+ GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
+);
+end TOP_DE1;
+
+architecture rtl of TOP_DE1 is
+
+ component T80se
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CLKEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+
+
+ component Clock_357Mhz
+ PORT (
+ clock_50Mhz : IN STD_LOGIC;
+ clock_60hz : OUT STD_LOGIC;
+ clock_357Mhz : OUT STD_LOGIC);
+ end component;
+
+ component clk_div
+ PORT
+ (
+ clock_25Mhz : IN STD_LOGIC;
+ clock_1MHz : OUT STD_LOGIC;
+ clock_100KHz : OUT STD_LOGIC;
+ clock_10KHz : OUT STD_LOGIC;
+ clock_1KHz : OUT STD_LOGIC;
+ clock_100Hz : OUT STD_LOGIC;
+ clock_10Hz : OUT STD_LOGIC;
+ clock_1Hz : OUT STD_LOGIC;
+ clock_10sec : OUT STD_LOGIC;
+ clock_1min : OUT STD_LOGIC;
+ clock_1hr : OUT STD_LOGIC);
+ end component;
+
+ component decoder_7seg
+ port (
+ NUMBER : in std_logic_vector(3 downto 0);
+ HEX_DISP : out std_logic_vector(6 downto 0));
+ end component;
+
+
+
+ COMPONENT miniUART
+ PORT (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+ END COMPONENT;
+
+
+ --component led_driver
+ --port (
+ -- ENABLE : in std_logic;
+ -- BYTE : in std_logic_vector(7 downto 0);
+ -- LEDBYTE : out std_logic_vector(7 downto 0));
+ --end component;
+
+
+
+
+ signal INT_n : std_logic;
+ signal M1_n : std_logic;
+ signal MREQ_n : std_logic;
+ signal IORQ_n : std_logic;
+ signal RD_n : std_logic;
+ signal WR_n : std_logic;
+ signal Rst_n_s : std_logic;
+
+ signal Clk_Z80 : std_logic;
+ signal Clk_357Mhz : std_logic;
+
+ signal DI_CPU : std_logic_vector(7 downto 0);
+ signal DO_CPU : std_logic_vector(7 downto 0);
+ signal A : std_logic_vector(15 downto 0);
+ signal One : std_logic;
+
+
+ signal D_ROM : std_logic_vector(7 downto 0);
+
+ signal clk25mhz : std_logic;
+ signal clk1hz : std_logic;
+ signal clk10hz : std_logic;
+ signal clk100hz : std_logic;
+ signal clk10sec : std_logic;
+ signal Clk_60hz : std_logic;
+
+ signal HEX_DISP0 : std_logic_vector(6 downto 0);
+ signal HEX_DISP1 : std_logic_vector(6 downto 0);
+ signal HEX_DISP2 : std_logic_vector(6 downto 0);
+ signal HEX_DISP3 : std_logic_vector(6 downto 0);
+
+ signal NUMBER0 : std_logic_vector(3 downto 0);
+ signal NUMBER1 : std_logic_vector(3 downto 0);
+ signal NUMBER2 : std_logic_vector(3 downto 0);
+ signal NUMBER3 : std_logic_vector(3 downto 0);
+
+
+ signal uart0_CS : std_Logic;
+ signal uart0_RD : std_Logic;
+ signal uart0_WR : std_Logic;
+ signal uart0_RxInt : std_Logic;
+ signal uart0_TxInt : std_Logic;
+ signal uart0_Addr : std_Logic_Vector(1 downto 0);
+ signal uart0_DataIn : std_Logic_Vector(7 downto 0);
+ signal uart0_DataOut : std_logic_Vector(7 downto 0);
+
+ signal IntVector : std_logic_Vector(7 downto 0);
+
+ signal Z80_RAM_ADR : Std_Logic_Vector(15 downto 0);
+
+ signal Z80_RAM_A12 : Std_Logic;
+ signal Z80_RAM_A13 : Std_Logic;
+ signal Z80_RAM_A14 : Std_Logic;
+ signal Z80_RAM_CE : Std_Logic;
+ signal Z80_RAM_OE : Std_Logic;
+ signal Z80_RAM_WE : Std_Logic;
+
+ signal Z80_EE_A15 : Std_Logic;
+ signal Z80_EE_A16 : Std_Logic;
+ signal Z80_EE_0E : Std_Logic;
+ signal Z80_EE_WE : Std_Logic;
+ signal Z80_EE_CE : Std_Logic;
+
+ signal Z80_ROM_CE : Std_Logic;
+
+ signal TestBit : Std_Logic;
+
+ signal LEDRED : std_logic_Vector(7 downto 0);
+
+
+begin
+ Rst_n_s <= not SW(9); -- Switch 9 toggles Reset on z80
+
+ HEX0 <= HEX_DISP0; -- Move Signal to Output Pins
+ HEX1 <= HEX_DISP1; -- Move Signal to Output Pins
+ HEX2 <= HEX_DISP2; -- Move Signal to Output Pins
+ HEX3 <= HEX_DISP3; -- Move Signal to Output Pins
+
+
+ -- SRAM control signals
+ SRAM_ADDR(15 downto 0) <= A - x"C000" when (A >= x"C000" and MREQ_n = '0');
+ SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= x"C000") else (others => 'Z');
+ SRAM_WE_N <= Wr_n or MREQ_n when A >= x"C000";
+ SRAM_OE_N <= Rd_n or MREQ_n when A >= x"C000";
+
+
+
+
+ -- FLASH control signals
+ FL_ADDR(15 downto 0) <= A when (A < x"A000" and MREQ_n = '0');
+ --FL_DQ <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A < x"A000") else (others => 'Z'); --this deltate
+ --D_ROM(7 downto 0) <= FL_DQ;
+ FL_WE_N <= Wr_n; -- Write Enable -- this make '1'
+ FL_OE_N <= Rd_n; -- Output Enable
+
+ FL_CE_N <= MREQ_n when A < x"A000"; -- Chip Enable works
+
+
+
+
+
+ --1FFFH is used for unlocking stuff
+
+ -- UART control signals
+ uart0_CS <= IORQ_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_RD <= Rd_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_WR <= Wr_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_Addr <= b"00";
+
+
+
+ ----------------------------------------------
+ --Z80 Interrupt Vectors
+ -- IBMVECT
+ --0040 AA1C DW COMMBOUT ;CHAN-B TRANSMIT BUFFER EMPTY
+ --0042 101B DW COMBCLI ;BSTATUS
+ --0044 F21C DW COMMBIN ;BRECEIVE
+ --0046 FF1A DW COMBCLII ;BEXTINT
+ --0048 281C DW COMMAOUT ;ATRBMTY
+ --004A 691C DW COMACLI ;WAS CRTEXINT ;ASTATUS
+ --004C 2F1B DW COMMAIN ;WAS CRTINP ;ARECEIVE
+ --004E 971C DW COMACLII ;WAS CRTEXIN? ;AEXTINT
+ IntVector(7 downto 0) <= x"4C" when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1');
+ ----------------------------------------------------------
+
+
+ DI_CPU <=
+
+ SRAM_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"C000") else
+
+ --Input ROM Code
+ FL_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"A000") else
+
+ --Z80 IN command to input UART0
+ uart0_DataIn(7 downto 0) when (Rd_n = '0' and MREQ_n = '1' and IORQ_n = '0' and A(7 downto 0) = x"24") else
+
+ IntVector(7 downto 0) when (MREQ_n = '1' and IORQ_n = '0' and M1_n = '0' and uart0_RxInt = '1') else -- After pulling int_n low serial interrupt input
+
+ "ZZZZZZZZ";
+
+
+
+
+
+ -- Process to latch z80 OUT instruction
+ pinout_process: process(Clk_Z80)
+ variable NUMBER0_sig : std_logic_vector(3 downto 0);
+ variable NUMBER1_sig : std_logic_vector(3 downto 0);
+ variable NUMBER2_sig : std_logic_vector(3 downto 0);
+ variable NUMBER3_sig : std_logic_vector(3 downto 0);
+ variable LEDR_sig : std_logic_vector(9 downto 0);
+ variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
+ variable uart0_buf_DataOut: std_logic_vector(7 downto 0);
+ --variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
+ begin
+ if Clk_Z80'event and Clk_Z80 = '1' then
+ if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
+
+ -- LEDR
+ if A(7 downto 0) = x"02" then
+ --LEDR_sig(7 downto 0) := DO_CPU;
+
+ -- HEX1 and HEX0
+ elsif A(7 downto 0) = x"10" then
+ NUMBER0_sig := DO_CPU(3 downto 0);
+ NUMBER1_sig := DO_CPU(7 downto 4);
+
+ -- HEX3 and HEX2
+ elsif A(7 downto 0) = x"11" then
+ NUMBER2_sig := DO_CPU(3 downto 0);
+ NUMBER3_sig := DO_CPU(7 downto 4);
+
+ elsif A(7 downto 0) = x"24" then
+ uart0_buf_DataOut := DO_CPU; --load data to uart output buffer
+
+ end if;
+ end if;
+ end if;
+ -- Latches the signals
+ NUMBER0 <= NUMBER0_sig;
+ NUMBER1 <= NUMBER1_sig;
+ NUMBER2 <= NUMBER2_sig;
+ NUMBER3 <= NUMBER3_sig;
+ --LEDR(7 downto 0) <= LEDR_sig(7 downto 0);
+ LEDRED <= LEDR_sig(7 downto 0);
+ uart0_DataOut <= uart0_buf_DataOut;
+ end process;
+
+ One <= '1';
+ z80_inst: T80se
+ port map (
+ M1_n => M1_n,
+ MREQ_n => MREQ_n,
+ IORQ_n => IORQ_n,
+ RD_n => Rd_n,
+ WR_n => Wr_n,
+ RFSH_n => open,
+ HALT_n => open,
+ WAIT_n => One,
+ INT_n => INT_n,
+ NMI_n => clk1hz, --Clk_60hz,
+ RESET_n => Rst_n_s,
+ BUSRQ_n => One,
+ BUSAK_n => open,
+ CLK_n => Clk_Z80,
+ CLKEN => One,
+ A => A,
+ DI => DI_CPU,
+ DO => DO_CPU
+ );
+
+
+ clkdiv_inst: clk_div
+ port map (
+ clock_25Mhz => CLOCK_27,
+ clock_1MHz => open,
+ clock_100KHz => open,
+ clock_10KHz => open,
+ clock_1KHz => open,
+ clock_100Hz => clk100hz,
+ clock_10Hz => clk10hz,
+ clock_1Hz => clk1hz,
+ clock_10sec => clk10sec,
+ clock_1min => open,
+ clock_1hr => open
+ );
+
+
+
+ clock_z80_inst : Clock_357Mhz
+ port map (
+ clock_50Mhz => CLOCK_50,
+ clock_60hz => Clk_60hz,
+ clock_357Mhz => Clk_Z80
+ );
+
+
+
+ DISPHEX0 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER0,
+ HEX_DISP => HEX_DISP0
+ );
+ DISPHEX1 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER1,
+ HEX_DISP => HEX_DISP1
+ );
+ DISPHEX2 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER2,
+ HEX_DISP => HEX_DISP2
+ );
+ DISPHEX3 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER3,
+ HEX_DISP => HEX_DISP3
+ );
+
+
+
+ U1 : miniUART PORT MAP (
+ SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
+ Reset => Key(0), --: in Std_Logic; -- Reset input
+ CS_N => uart0_cs, --: in Std_Logic;
+ RD_N => uart0_Rd, --: in Std_Logic;
+ WR_N => uart0_Wr, --: in Std_Logic;
+ RxD => UART_RXD, --: in Std_Logic;
+ TxD => UART_TXD, --: out Std_Logic;
+ IntRx_N => uart0_RxInt, --: out Std_Logic; -- Received Byte
+ IntTx_N => uart0_TxInt, --: out Std_Logic; -- Transmit Buffer Empty
+ Addr => uart0_Addr, --: in Std_Logic_Vector(1 downto 0); --
+ DataIn => uart0_DataOut, --: in Std_Logic_Vector(7 downto 0); --
+ DataOut => uart0_DataIn --: out Std_Logic_Vector(7 downto 0)); --
+ );
+
+
+ --u2: led_driver
+ --port map (
+ -- ENABLE => (IORQ_n and Wr_n),
+ -- BYTE => LEDRED, --: in std_logic_vector(7 downto 0);
+ -- LEDBYTE => LEDR(7 downto 0) --: out std_logic_vector(7 downto 0)
+ --);
+
+ LEDR(0) <= '1' when LEDRED(0) = '1' else '0';
+ LEDR(1) <= '1' when LEDRED(1) = '1' else '0';
+ LEDR(2) <= '1' when LEDRED(2) = '1' else '0';
+ LEDR(3) <= '1' when LEDRED(3) = '1' else '0';
+ LEDR(4) <= '1' when LEDRED(4) = '1' else '0';
+ LEDR(5) <= '1' when LEDRED(5) = '1' else '0';
+ LEDR(6) <= '1' when LEDRED(6) = '1' else '0';
+ LEDR(7) <= '1' when LEDRED(7) = '1' else '0';
+
+
+ INT_n <= '0' when uart0_RxInt ='1' else '1';
+
+ --INT_n <= not uart0_RxInt;
+
+ --TestBit <= uart0_TxInt;
+
+
+ LEDG(0) <= uart0_RxInt; -- block and no run
+ LEDG(1) <= uart0_TxInt; -- block and no run
+ --uart0_TxInt <= 'Z'; no run instead of block
+ --LEDG(1) <= TestBit; --why does uart0_TxInt need to be connected to led???????
+
+ --LEDG(2) <= '1';
+ LEDG(5) <= INT_n;
+ --LEDG(6) <= clk10sec;
+ --LEDG(7) <= clk1hz;
+
+ --LEDR(9 downto 0) <= b"0101010101";
+
+ FL_RST_N <= '1'; -- Reset
+ FL_ADDR(21 downto 16) <= b"000000";
+
+ SRAM_DQ(15 downto 8) <= (others => 'Z');
+ SRAM_ADDR(17 downto 16) <= "00";
+ SRAM_UB_N <= '1';
+ SRAM_LB_N <= '0';
+ SRAM_CE_N <= '0';
+
+ --
+ UART_TXD <= 'Z';
+ DRAM_ADDR <= (others => '0');
+ DRAM_LDQM <= '0';
+ DRAM_UDQM <= '0';
+ DRAM_WE_N <= '1';
+ DRAM_CAS_N <= '1';
+ DRAM_RAS_N <= '1';
+ DRAM_CS_N <= '1';
+ DRAM_BA_0 <= '0';
+ DRAM_BA_1 <= '0';
+ DRAM_CLK <= '0';
+ DRAM_CKE <= '0';
+ TDO <= '0';
+ I2C_SCLK <= '0';
+ AUD_DACDAT <= '0';
+ AUD_XCK <= '0';
+ -- Set all bidirectional ports to tri-state
+ DRAM_DQ <= (others => 'Z');
+
+ I2C_SDAT <= 'Z';
+ AUD_ADCLRCK <= 'Z';
+ AUD_DACLRCK <= 'Z';
+ AUD_BCLK <= 'Z';
+ GPIO_0 <= (others => 'Z');
+ GPIO_1 <= (others => 'Z');
+
+
+ VGA_HS <= '0';
+ VGA_VS <= '0';
+ VGA_R(3 downto 0) <= b"0000";
+ VGA_G(3 downto 0) <= b"0000";
+ VGA_B(3 downto 0) <= b"0000";
+
+end;
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/clock_357mhz.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/clock_357mhz.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/clock_357mhz.vhd (revision 6)
@@ -0,0 +1,51 @@
+-- 3.57 Mhz clock from a 50 Mhz input
+-- Ronivon C. costa
+-- 03/2008
+------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+ENTITY Clock_357Mhz IS
+ PORT (
+ clock_50Mhz : IN STD_LOGIC;
+ clock_60hz : OUT STD_LOGIC;
+ clock_357Mhz : OUT STD_LOGIC);
+ END Clock_357Mhz;
+
+ARCHITECTURE rtl OF Clock_357Mhz IS
+
+ SIGNAL counter: STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL clock_357Mhz_int : STD_LOGIC;
+ SIGNAL counter_60: STD_LOGIC_VECTOR(19 DOWNTO 0);
+ SIGNAL clock_60hz_int : STD_LOGIC;
+
+
+BEGIN
+
+ PROCESS (clock_50Mhz)
+ BEGIN
+ IF clock_50Mhz'EVENT and clock_50Mhz = '1' THEN
+ IF counter < "1110" THEN
+ counter <= counter + 1;
+ ELSE
+ counter <= "0000";
+ clock_357Mhz_int <= not clock_357Mhz_int;
+ END IF;
+ END IF;
+
+ IF clock_50Mhz'EVENT and clock_50Mhz = '1' THEN
+ IF counter_60 < x"CB735" THEN
+ counter_60 <= counter_60 + 1;
+ ELSE
+ counter_60 <= x"00000";
+ clock_60hz_int <= not clock_60hz_int;
+ END IF;
+ END IF;
+
+ clock_60hz <= clock_60hz_int;
+ clock_357Mhz <= clock_357Mhz_int;
+
+ END PROCESS;
+END rtl;
Index: z80control/trunk/DE1/rtl/VHDL/clkUnit.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/clkUnit.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/clkUnit.vhd (revision 6)
@@ -0,0 +1,135 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : clkUnit.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 1.0 Ovidiu Lupas 15 January 2000 New model
+-- 1.1 Ovidiu Lupas 28 May 2000 EnableRx/EnableTx ratio corrected
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description : Generates the Baud clock and enable signals for RX & TX
+-- units.
+-------------------------------------------------------------------------------
+-- Entity for Baud rate generator Unit - 9600 baudrate --
+-------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.UART_Def.all;
+-------------------------------------------------------------------------------
+-- Baud rate generator
+-------------------------------------------------------------------------------
+entity ClkUnit is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ EnableRx : out Std_Logic; -- Control signal
+ EnableTx : out Std_Logic; -- Control signal
+ Reset : in Std_Logic); -- Reset input
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for Baud rate generator Unit
+-------------------------------------------------------------------------------
+architecture Behaviour of ClkUnit is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal ClkDiv26 : Std_Logic;
+ signal tmpEnRX : Std_Logic;
+ signal tmpEnTX : Std_Logic;
+begin
+ -----------------------------------------------------------------------------
+ -- Divides the system clock of 50 MHz by 32
+ -----------------------------------------------------------------------------
+ DivClk26 : process(SysClk,Reset)
+ constant CntOne : unsigned(4 downto 0) := "00001";
+ variable Cnt26 : unsigned(5 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt26 := "000000";
+ ClkDiv26 <= '0';
+ else
+ Cnt26 := Cnt26 + CntOne;
+ case Cnt26 is
+ when "100000" =>
+ ClkDiv26 <= '1';
+ Cnt26 := "000000";
+ when others =>
+ ClkDiv26 <= '0';
+ end case;
+ end if;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Provides the EnableRX signal, at ~ 155 KHz
+ -----------------------------------------------------------------------------
+ DivClk10 : process(SysClk,Reset,Clkdiv26)
+ constant CntOne : unsigned(3 downto 0) := "0001";
+ variable Cnt10 : unsigned(3 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt10 := "0000";
+ tmpEnRX <= '0';
+ elsif ClkDiv26 = '1' then
+ Cnt10 := Cnt10 + CntOne;
+ end if;
+ case Cnt10 is
+ when "1010" =>
+ tmpEnRX <= '1';
+ Cnt10 := "0000";
+ when others =>
+ tmpEnRX <= '0';
+ end case;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Provides the EnableTX signal, at 9.6 KHz
+ -----------------------------------------------------------------------------
+ DivClk16 : process(SysClk,Reset,tmpEnRX)
+ constant CntOne : unsigned(4 downto 0) := "00001";
+ variable Cnt16 : unsigned(4 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt16 := "00000";
+ tmpEnTX <= '0';
+ elsif tmpEnRX = '1' then
+ Cnt16 := Cnt16 + CntOne;
+ end if;
+ case Cnt16 is
+ when "01111" =>
+ tmpEnTX <= '1';
+ Cnt16 := Cnt16 + CntOne;
+ when "10001" =>
+ Cnt16 := "00000";
+ tmpEnTX <= '0';
+ when others =>
+ tmpEnTX <= '0';
+ end case;
+ end if;
+ end process;
+
+ EnableRX <= tmpEnRX;
+ EnableTX <= tmpEnTX;
+end Behaviour; --==================== End of architecture ===================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/decoder_7seg.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/decoder_7seg.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/decoder_7seg.vhd (revision 6)
@@ -0,0 +1,40 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+USE IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity decoder_7seg is
+ port
+ (
+ NUMBER : in std_logic_vector(3 downto 0);
+ HEX_DISP : out std_logic_vector(6 downto 0)
+ );
+end decoder_7seg;
+
+architecture rtl of decoder_7seg is
+begin
+process(NUMBER)
+begin
+ case NUMBER is
+ --0 to 9
+ when "0000" => HEX_DISP <= "1000000";
+ when "0001" => HEX_DISP <= "1111001";
+ when "0010" => HEX_DISP <= "0100100";
+ when "0011" => HEX_DISP <= "0110000";
+ when "0100" => HEX_DISP <= "0011001";
+ when "0101" => HEX_DISP <= "0010010";
+ when "0110" => HEX_DISP <= "0000011";
+ when "0111" => HEX_DISP <= "1111000";
+ when "1000" => HEX_DISP <= "0000000";
+ when "1001" => HEX_DISP <= "0011000";
+ -- A to F
+ when "1010" => HEX_DISP <= "0001000";
+ when "1011" => HEX_DISP <= "0000011";
+ when "1100" => HEX_DISP <= "1000110";
+ when "1101" => HEX_DISP <= "0100001";
+ when "1110" => HEX_DISP <= "0000110";
+ when "1111" => HEX_DISP <= "0001110";
+ when others => HEX_DISP <= "1111111";
+ end case;
+end process;
+end rtl;
+
Index: z80control/trunk/DE1/rtl/VHDL/clk_div.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/clk_div.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/clk_div.vhd (revision 6)
@@ -0,0 +1,174 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+ENTITY clk_div IS
+
+ PORT
+ (
+ clock_25Mhz : IN STD_LOGIC;
+ clock_1MHz : OUT STD_LOGIC;
+ clock_100KHz : OUT STD_LOGIC;
+ clock_10KHz : OUT STD_LOGIC;
+ clock_1KHz : OUT STD_LOGIC;
+ clock_100Hz : OUT STD_LOGIC;
+ clock_10Hz : OUT STD_LOGIC;
+ clock_1Hz : OUT STD_LOGIC;
+ clock_10sec : OUT STD_LOGIC;
+ clock_1min : OUT STD_LOGIC;
+ clock_1hr : OUT STD_LOGIC);
+
+END clk_div;
+
+ARCHITECTURE a OF clk_div IS
+
+ SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
+ SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL count_10sec, count_1min, count_1hr : STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+ SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
+ SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
+ SIGNAL clock_10sec_int, clock_1min_int, clock_1hr_int : STD_LOGIC;
+
+BEGIN
+ PROCESS
+ BEGIN
+-- Divide by 25
+ WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
+ IF count_1Mhz < 24 THEN
+ count_1Mhz <= count_1Mhz + 1;
+ ELSE
+ count_1Mhz <= "00000";
+ END IF;
+ IF count_1Mhz < 12 THEN
+ clock_1Mhz_int <= '0';
+ ELSE
+ clock_1Mhz_int <= '1';
+ END IF;
+
+-- Ripple clocks are used in this code to save prescalar hardware
+-- Sync all clock prescalar outputs back to master clock signal
+ clock_1Mhz <= clock_1Mhz_int;
+ clock_100Khz <= clock_100Khz_int;
+ clock_10Khz <= clock_10Khz_int;
+ clock_1Khz <= clock_1Khz_int;
+ clock_100hz <= clock_100hz_int;
+ clock_10hz <= clock_10hz_int;
+ clock_1hz <= clock_1hz_int;
+ clock_10sec <= clock_10sec_int;
+ clock_1min <= clock_1min_int;
+ clock_1hr <= clock_1hr_int;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
+ IF count_100Khz /= 4 THEN
+ count_100Khz <= count_100Khz + 1;
+ ELSE
+ count_100khz <= "000";
+ clock_100Khz_int <= NOT clock_100Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
+ IF count_10Khz /= 4 THEN
+ count_10Khz <= count_10Khz + 1;
+ ELSE
+ count_10khz <= "000";
+ clock_10Khz_int <= NOT clock_10Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
+ IF count_1Khz /= 4 THEN
+ count_1Khz <= count_1Khz + 1;
+ ELSE
+ count_1khz <= "000";
+ clock_1Khz_int <= NOT clock_1Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
+ IF count_100hz /= 4 THEN
+ count_100hz <= count_100hz + 1;
+ ELSE
+ count_100hz <= "000";
+ clock_100hz_int <= NOT clock_100hz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
+ IF count_10hz /= 4 THEN
+ count_10hz <= count_10hz + 1;
+ ELSE
+ count_10hz <= "000";
+ clock_10hz_int <= NOT clock_10hz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
+ IF count_1hz /= 4 THEN
+ count_1hz <= count_1hz + 1;
+ ELSE
+ count_1hz <= "000";
+ clock_1hz_int <= NOT clock_1hz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1hz_int'EVENT and clock_1hz_int = '1';
+ IF count_10sec /= 4 THEN
+ count_10sec <= count_10sec + 1;
+ ELSE
+ count_10sec <= "000";
+ clock_10sec_int <= NOT clock_10sec_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_10sec_int'EVENT and clock_10sec_int = '1';
+ IF count_1min /= 4 THEN
+ count_1min <= count_1min + 1;
+ ELSE
+ count_1min <= "000";
+ clock_1min_int <= NOT clock_1min_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1min_int'EVENT and clock_1min_int = '1';
+ IF count_1hr /= 4 THEN
+ count_1hr <= count_1hr + 1;
+ ELSE
+ count_1hr <= "000";
+ clock_1hr_int <= NOT clock_1hr_int;
+ END IF;
+ END PROCESS;
+
+END a;
+
Index: z80control/trunk/DE1/rtl/VHDL/led_driver.vhd.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/led_driver.vhd.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/led_driver.vhd.bak (revision 6)
@@ -0,0 +1,23 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+USE IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity led_driver is
+ port
+ (
+ ENABLE : in std_logic;
+ BYTE : in std_logic_vector(7 downto 0);
+ LEDBYTE : out std_logic_vector(7 downto 0)
+ );
+end led_driver;
+
+architecture rtl of led_driver is
+begin
+process(ENABLE, BYTE)
+begin
+ if (ENABLE = '1')then
+ LEDBYTE <= BYTE;
+ end if;
+end process;
+end rtl;
+
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80_RegX.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80_RegX.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80_RegX.vhd (revision 6)
@@ -0,0 +1,176 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers for Xilinx Select RAM
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0242 : Initial release
+--
+-- 0244 : Removed UNISIM library and added componet declaration
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+ component RAM16X1D
+ port(
+ DPO : out std_ulogic;
+ SPO : out std_ulogic;
+ A0 : in std_ulogic;
+ A1 : in std_ulogic;
+ A2 : in std_ulogic;
+ A3 : in std_ulogic;
+ D : in std_ulogic;
+ DPRA0 : in std_ulogic;
+ DPRA1 : in std_ulogic;
+ DPRA2 : in std_ulogic;
+ DPRA3 : in std_ulogic;
+ WCLK : in std_ulogic;
+ WE : in std_ulogic);
+ end component;
+
+ signal ENH : std_logic;
+ signal ENL : std_logic;
+
+begin
+
+ ENH <= CEN and WEH;
+ ENL <= CEN and WEL;
+
+ bG1: for I in 0 to 7 generate
+ begin
+ Reg1H : RAM16X1D
+ port map(
+ DPO => DOBH(i),
+ SPO => DOAH(i),
+ A0 => AddrA(0),
+ A1 => AddrA(1),
+ A2 => AddrA(2),
+ A3 => '0',
+ D => DIH(i),
+ DPRA0 => AddrB(0),
+ DPRA1 => AddrB(1),
+ DPRA2 => AddrB(2),
+ DPRA3 => '0',
+ WCLK => Clk,
+ WE => ENH);
+ Reg1L : RAM16X1D
+ port map(
+ DPO => DOBL(i),
+ SPO => DOAL(i),
+ A0 => AddrA(0),
+ A1 => AddrA(1),
+ A2 => AddrA(2),
+ A3 => '0',
+ D => DIL(i),
+ DPRA0 => AddrB(0),
+ DPRA1 => AddrB(1),
+ DPRA2 => AddrB(2),
+ DPRA3 => '0',
+ WCLK => Clk,
+ WE => ENL);
+ Reg2H : RAM16X1D
+ port map(
+ DPO => DOCH(i),
+ SPO => open,
+ A0 => AddrA(0),
+ A1 => AddrA(1),
+ A2 => AddrA(2),
+ A3 => '0',
+ D => DIH(i),
+ DPRA0 => AddrC(0),
+ DPRA1 => AddrC(1),
+ DPRA2 => AddrC(2),
+ DPRA3 => '0',
+ WCLK => Clk,
+ WE => ENH);
+ Reg2L : RAM16X1D
+ port map(
+ DPO => DOCL(i),
+ SPO => open,
+ A0 => AddrA(0),
+ A1 => AddrA(1),
+ A2 => AddrA(2),
+ A3 => '0',
+ D => DIL(i),
+ DPRA0 => AddrC(0),
+ DPRA1 => AddrC(1),
+ DPRA2 => AddrC(2),
+ DPRA3 => '0',
+ WCLK => Clk,
+ WE => ENL);
+ end generate;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80se.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80se.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80se.vhd (revision 6)
@@ -0,0 +1,192 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0240
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0235 : First release
+--
+-- 0236 : Added T2Write generic
+--
+-- 0237 : Fixed T2Write with wait state
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80se is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 0 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CLKEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+end T80se;
+
+architecture rtl of T80se is
+
+ signal IntCycle_n : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal IORQ : std_logic;
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => IOWait)
+ port map(
+ CEN => CLKEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => RESET_n,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n,
+ CLK_n => CLK_n,
+ A => A,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ DI_Reg <= "00000000";
+ elsif CLK_n'event and CLK_n = '1' then
+ if CLKEN = '1' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ if MCycle = "001" then
+ if TState = "001" or (TState = "010" and Wait_n = '0') then
+ RD_n <= not IntCycle_n;
+ MREQ_n <= not IntCycle_n;
+ IORQ_n <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ MREQ_n <= '0';
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+ RD_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ if T2Write = 0 then
+ if TState = "010" and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ end if;
+ end if;
+ if TState = "010" and Wait_n = '1' then
+ DI_Reg <= DI;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T16450.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T16450.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T16450.vhd (revision 6)
@@ -0,0 +1,459 @@
+--
+-- 16450 compatible UART with synchronous bus interface
+-- RClk/BaudOut is XIn enable instead of actual clock
+--
+-- Version : 0249b
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First release
+--
+-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
+-- Added modem status and break detection
+-- Added support for 1.5 and 2 stop bits
+--
+-- 0249b : Fixed loopback break generation bugs found by Andy Dyer
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T16450 is
+ port(
+ MR_n : in std_logic;
+ XIn : in std_logic;
+ RClk : in std_logic;
+ CS_n : in std_logic;
+ Rd_n : in std_logic;
+ Wr_n : in std_logic;
+ A : in std_logic_vector(2 downto 0);
+ D_In : in std_logic_vector(7 downto 0);
+ D_Out : out std_logic_vector(7 downto 0);
+ SIn : in std_logic;
+ CTS_n : in std_logic;
+ DSR_n : in std_logic;
+ RI_n : in std_logic;
+ DCD_n : in std_logic;
+ SOut : out std_logic;
+ RTS_n : out std_logic;
+ DTR_n : out std_logic;
+ OUT1_n : out std_logic;
+ OUT2_n : out std_logic;
+ BaudOut : out std_logic;
+ Intr : out std_logic
+ );
+end T16450;
+
+architecture rtl of T16450 is
+
+ signal RBR : std_logic_vector(7 downto 0); -- Reciever Buffer Register
+ signal THR : std_logic_vector(7 downto 0); -- Transmitter Holding Register
+ signal IER : std_logic_vector(7 downto 0); -- Interrupt Enable Register
+ signal IIR : std_logic_vector(7 downto 0); -- Interrupt Ident. Register
+ signal LCR : std_logic_vector(7 downto 0); -- Line Control Register
+ signal MCR : std_logic_vector(7 downto 0); -- MODEM Control Register
+ signal LSR : std_logic_vector(7 downto 0); -- Line Status Register
+ signal MSR : std_logic_vector(7 downto 0); -- MODEM Status Register
+ signal SCR : std_logic_vector(7 downto 0); -- Scratch Register
+ signal DLL : std_logic_vector(7 downto 0); -- Divisor Latch (LS)
+ signal DLM : std_logic_vector(7 downto 0); -- Divisor Latch (MS)
+
+ signal DM0 : std_logic_vector(7 downto 0);
+ signal DM1 : std_logic_vector(7 downto 0);
+
+ signal MSR_In : std_logic_vector(3 downto 0);
+
+ signal Bit_Phase : unsigned(3 downto 0);
+ signal Brk_Cnt : unsigned(3 downto 0);
+ signal RX_Filtered : std_logic;
+ signal RX_ShiftReg : std_logic_vector(7 downto 0);
+ signal RX_Bit_Cnt : integer range 0 to 11;
+ signal RX_Parity : std_logic;
+ signal RXD : std_logic;
+
+ signal TX_Tick : std_logic;
+ signal TX_ShiftReg : std_logic_vector(7 downto 0);
+ signal TX_Bit_Cnt : integer range 0 to 11;
+ signal TX_Parity : std_logic;
+ signal TX_Next_Is_Stop : std_logic;
+ signal TX_Stop_Bit : std_logic;
+ signal TXD : std_logic;
+
+begin
+
+ DTR_n <= MCR(4) or not MCR(0);
+ RTS_n <= MCR(4) or not MCR(1);
+ OUT1_n <= MCR(4) or not MCR(2);
+ OUT2_n <= MCR(4) or not MCR(3);
+ SOut <= MCR(4) or (TXD and not LCR(6));
+ RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
+
+ Intr <= not IIR(0);
+
+ -- Registers
+ DM0 <= DLL when LCR(7) = '1' else RBR;
+ DM1 <= DLM when LCR(7) = '1' else IER;
+ with A select
+ D_Out <=
+ DM0 when "000",
+ DM1 when "001",
+ IIR when "010",
+ LCR when "011",
+ MCR when "100",
+ LSR when "101",
+ MSR when "110",
+ SCR when others;
+ process (MR_n, XIn)
+ begin
+ if MR_n = '0' then
+ THR <= "00000000";
+ IER <= "00000000";
+ LCR <= "00000000";
+ MCR <= "00000000";
+ MSR(3 downto 0) <= "0000";
+ SCR <= "00000000"; -- ??
+ DLL <= "00000000"; -- ??
+ DLM <= "00000000"; -- ??
+ elsif XIn'event and XIn = '1' then
+ if Wr_n = '0' and CS_n = '0' then
+ case A is
+ when "000" =>
+ if LCR(7) = '1' then
+ DLL <= D_In;
+ else
+ THR <= D_In;
+ end if;
+ when "001" =>
+ if LCR(7) = '1' then
+ DLM <= D_In;
+ else
+ IER(3 downto 0) <= D_In(3 downto 0);
+ end if;
+ when "011" =>
+ LCR <= D_In;
+ when "100" =>
+ MCR <= D_In;
+ when "111" =>
+ SCR <= D_In;
+ when others =>
+ end case;
+ end if;
+ if Rd_n = '0' and CS_n = '0' and A = "110" then
+ MSR(3 downto 0) <= "0000";
+ end if;
+ if MSR(4) /= MSR_In(0) then
+ MSR(0) <= '1';
+ end if;
+ if MSR(5) /= MSR_In(1) then
+ MSR(1) <= '1';
+ end if;
+ if MSR(6) = '0' and MSR_In(2) = '1' then
+ MSR(2) <= '1';
+ end if;
+ if MSR(7) /= MSR_In(3) then
+ MSR(3) <= '1';
+ end if;
+ end if;
+ end process;
+ process (XIn)
+ begin
+ if XIn'event and XIn = '1' then
+ if MCR(4) = '0' then
+ MSR(4) <= MSR_In(0);
+ MSR(5) <= MSR_In(1);
+ MSR(6) <= MSR_In(2);
+ MSR(7) <= MSR_In(3);
+ else
+ MSR(4) <= MCR(1);
+ MSR(5) <= MCR(0);
+ MSR(6) <= MCR(2);
+ MSR(7) <= MCR(3);
+ end if;
+ MSR_In(0) <= CTS_n;
+ MSR_In(1) <= DSR_n;
+ MSR_In(2) <= RI_n;
+ MSR_In(3) <= DCD_n;
+ end if;
+ end process;
+
+ IIR(7 downto 3) <= "00000";
+ IIR(2 downto 0) <=
+ "110" when IER(2) = '1' and LSR(4 downto 1) /= "0000" else
+ "100" when (IER(0) and LSR(0)) = '1' else
+ "010" when (IER(1) and LSR(5)) = '1' else
+ "000" when IER(3) = '1' and ((MCR(4) = '0' and MSR(3 downto 0) /= "0000") or
+ (MCR(4) = '1' and MCR(3 downto 0) /= "0000")) else
+ "001";
+
+ -- Baud x 16 clock generator
+ process (MR_n, XIn)
+ variable Baud_Cnt : unsigned(15 downto 0);
+ begin
+ if MR_n = '0' then
+ Baud_Cnt := "0000000000000000";
+ BaudOut <= '0';
+ elsif XIn'event and XIn = '1' then
+ if Baud_Cnt(15 downto 1) = "000000000000000" or (Wr_n = '0' and CS_n = '0' and A(2 downto 1) = "00" and LCR(7) = '1') then
+ Baud_Cnt(15 downto 8) := unsigned(DLM);
+ Baud_Cnt(7 downto 0) := unsigned(DLL);
+ BaudOut <= '1';
+ else
+ Baud_Cnt := Baud_Cnt - 1;
+ BaudOut <= '0';
+ end if;
+ end if;
+ end process;
+
+ -- Input filter
+ process (MR_n, XIn)
+ variable Samples : std_logic_vector(1 downto 0);
+ begin
+ if MR_n = '0' then
+ Samples := "11";
+ RX_Filtered <= '1';
+ elsif XIn'event and XIn = '1' then
+ if RClk = '1' then
+ Samples(1) := Samples(0);
+ Samples(0) := RXD;
+ end if;
+ if Samples = "00" then
+ RX_Filtered <= '0';
+ end if;
+ if Samples = "11" then
+ RX_Filtered <= '1';
+ end if;
+ end if;
+ end process;
+
+ -- Receive state machine
+ process (MR_n, XIn)
+ begin
+ if MR_n = '0' then
+ RBR <= "00000000";
+ LSR(4 downto 0) <= "00000";
+ Bit_Phase <= "0000";
+ Brk_Cnt <= "0000";
+ RX_ShiftReg(7 downto 0) <= "00000000";
+ RX_Bit_Cnt <= 0;
+ RX_Parity <= '0';
+ elsif XIn'event and XIn = '1' then
+ if A = "000" and LCR(7) = '0' and Rd_n = '0' and CS_n = '0' then
+ LSR(0) <= '0'; -- DR
+ end if;
+ if A = "101" and Rd_n = '0' and CS_n = '0' then
+ LSR(4) <= '0'; -- BI
+ LSR(3) <= '0'; -- FE
+ LSR(2) <= '0'; -- PE
+ LSR(1) <= '0'; -- OE
+ end if;
+ if RClk = '1' then
+ if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
+ Bit_Phase <= "0000";
+ else
+ Bit_Phase <= Bit_Phase + 1;
+ end if;
+ if Bit_Phase = "1111" then
+ if RX_Filtered = '1' then
+ Brk_Cnt <= "0000";
+ else
+ Brk_Cnt <= Brk_Cnt + 1;
+ end if;
+ if Brk_Cnt = "1100" then
+ LSR(4) <= '1'; -- BI
+ end if;
+ end if;
+ if RX_Bit_Cnt = 0 then
+ if Bit_Phase = "0111" then
+ RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+ RX_Parity <= not LCR(4); -- EPS
+ end if;
+ elsif Bit_Phase = "1111" then
+ RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+ if RX_Bit_Cnt = 10 then -- Parity stop bit
+ RX_Bit_Cnt <= 0;
+ LSR(0) <= '1'; -- UART Receive complete
+ LSR(3) <= not RX_Filtered; -- Framing error
+ elsif (RX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
+ (RX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
+ (RX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
+ (RX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then -- Stop bit/Parity
+ RX_Bit_Cnt <= 0;
+ if LCR(3) = '1' then -- PEN
+ RX_Bit_Cnt <= 10;
+ if LCR(5) = '1' then -- Stick parity
+ if RX_Filtered = LCR(4) then
+ LSR(2) <= '1';
+ end if;
+ else
+ if RX_Filtered /= RX_Parity then
+ LSR(2) <= '1';
+ end if;
+ end if;
+ else
+ LSR(0) <= '1'; -- UART Receive complete
+ LSR(3) <= not RX_Filtered; -- Framing error
+ end if;
+ RBR <= RX_ShiftReg(7 downto 0);
+ LSR(1) <= LSR(0);
+ if A = "101" and Rd_n = '0' and CS_n = '0' then
+ LSR(1) <= '0';
+ end if;
+ else
+ RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
+ RX_ShiftReg(7) <= RX_Filtered;
+ if LCR(1 downto 0) = "10" then
+ RX_ShiftReg(7) <= '0';
+ RX_ShiftReg(6) <= RX_Filtered;
+ end if;
+ if LCR(1 downto 0) = "01" then
+ RX_ShiftReg(7) <= '0';
+ RX_ShiftReg(6) <= '0';
+ RX_ShiftReg(5) <= RX_Filtered;
+ end if;
+ if LCR(1 downto 0) = "00" then
+ RX_ShiftReg(7) <= '0';
+ RX_ShiftReg(6) <= '0';
+ RX_ShiftReg(5) <= '0';
+ RX_ShiftReg(4) <= RX_Filtered;
+ end if;
+ RX_Parity <= RX_Filtered xor RX_Parity;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Transmit bit tick
+ process (MR_n, XIn)
+ variable TX_Cnt : unsigned(4 downto 0);
+ begin
+ if MR_n = '0' then
+ TX_Cnt := "00000";
+ TX_Tick <= '0';
+ elsif XIn'event and XIn = '1' then
+ TX_Tick <= '0';
+ if RClk = '1' then
+ TX_Cnt := TX_Cnt + 1;
+ if LCR(2) = '1' and TX_Stop_Bit = '1' then
+ if LCR(1 downto 0) = "00" then
+ if TX_Cnt = "10111" then
+ TX_Tick <= '1';
+ TX_Cnt(3 downto 0) := "0000";
+ end if;
+ else
+ if TX_Cnt = "11111" then
+ TX_Tick <= '1';
+ TX_Cnt(3 downto 0) := "0000";
+ end if;
+ end if;
+ else
+ TX_Cnt(4) := '1';
+ if TX_Cnt(3 downto 0) = "1111" then
+ TX_Tick <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Transmit state machine
+ process (MR_n, XIn)
+ begin
+ if MR_n = '0' then
+ LSR(7 downto 5) <= "011";
+ TX_Bit_Cnt <= 0;
+ TX_ShiftReg <= (others => '0');
+ TXD <= '1';
+ TX_Parity <= '0';
+ TX_Next_Is_Stop <= '0';
+ TX_Stop_Bit <= '0';
+ elsif XIn'event and XIn = '1' then
+ if TX_Tick = '1' then
+ TX_Next_Is_Stop <= '0';
+ TX_Stop_Bit <= TX_Next_Is_Stop;
+ case TX_Bit_Cnt is
+ when 0 =>
+ if LSR(5) <= '0' then -- THRE
+ TX_Bit_Cnt <= 1;
+ end if;
+ TXD <= '1';
+ when 1 => -- Start bit
+ TX_ShiftReg(7 downto 0) <= THR;
+ LSR(5) <= '1'; -- THRE
+ TXD <= '0';
+ TX_Parity <= not LCR(4); -- EPS
+ TX_Bit_Cnt <= TX_Bit_Cnt + 1;
+ when 10 => -- Parity bit
+ TXD <= TX_Parity;
+ if LCR(5) = '1' then -- Stick parity
+ TXD <= not LCR(4);
+ end if;
+ TX_Bit_Cnt <= 0;
+ TX_Next_Is_Stop <= '1';
+ when others =>
+ TX_Bit_Cnt <= TX_Bit_Cnt + 1;
+ if (TX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
+ (TX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
+ (TX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
+ (TX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then
+ TX_Bit_Cnt <= 0;
+ if LCR(3) = '1' then -- PEN
+ TX_Bit_Cnt <= 10;
+ else
+ TX_Next_Is_Stop <= '1';
+ end if;
+ LSR(6) <= '1'; -- TEMT
+ end if;
+ TXD <= TX_ShiftReg(0);
+ TX_ShiftReg(6 downto 0) <= TX_ShiftReg(7 downto 1);
+ TX_Parity <= TX_ShiftReg(0) xor TX_Parity;
+ end case;
+ end if;
+ if Wr_n = '0' and CS_n = '0' and A = "000" and LCR(7) = '0' then
+ LSR(5) <= '0'; -- THRE
+ LSR(6) <= '0'; -- TEMT
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/DebugSystemXR.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/DebugSystemXR.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/DebugSystemXR.vhd (revision 6)
@@ -0,0 +1,185 @@
+-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs
+-- that can be synthesized and used with
+-- the NoICE debugger that can be found at
+-- http://www.noicedebugger.com/
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity DebugSystemXR is
+ port(
+ Reset_n : in std_logic;
+ Clk : in std_logic;
+ NMI_n : in std_logic;
+ OE_n : out std_logic;
+ WE_n : out std_logic;
+ RAMCS_n : out std_logic;
+ ROMCS_n : out std_logic;
+ PGM_n : out std_logic;
+ A : out std_logic_vector(16 downto 0);
+ D : inout std_logic_vector(7 downto 0);
+ RXD0 : in std_logic;
+ CTS0 : in std_logic;
+ DSR0 : in std_logic;
+ RI0 : in std_logic;
+ DCD0 : in std_logic;
+ RXD1 : in std_logic;
+ CTS1 : in std_logic;
+ DSR1 : in std_logic;
+ RI1 : in std_logic;
+ DCD1 : in std_logic;
+ TXD0 : out std_logic;
+ RTS0 : out std_logic;
+ DTR0 : out std_logic;
+ TXD1 : out std_logic;
+ RTS1 : out std_logic;
+ DTR1 : out std_logic
+ );
+end entity DebugSystemXR;
+
+architecture struct of DebugSystemXR is
+
+ signal M1_n : std_logic;
+ signal MREQ_n : std_logic;
+ signal IORQ_n : std_logic;
+ signal RD_n : std_logic;
+ signal WR_n : std_logic;
+ signal RFSH_n : std_logic;
+ signal HALT_n : std_logic;
+ signal WAIT_n : std_logic;
+ signal INT_n : std_logic;
+ signal RESET_s : std_logic;
+ signal BUSRQ_n : std_logic;
+ signal BUSAK_n : std_logic;
+ signal A_i : std_logic_vector(15 downto 0);
+ signal D_i : std_logic_vector(7 downto 0);
+ signal ROM_D : std_logic_vector(7 downto 0);
+ signal UART0_D : std_logic_vector(7 downto 0);
+ signal UART1_D : std_logic_vector(7 downto 0);
+ signal CPU_D : std_logic_vector(7 downto 0);
+
+ signal Mirror : std_logic;
+
+ signal IOWR_n : std_logic;
+ signal RAMCS_n_i : std_logic;
+ signal UART0CS_n : std_logic;
+ signal UART1CS_n : std_logic;
+
+ signal BaudOut0 : std_logic;
+ signal BaudOut1 : std_logic;
+
+begin
+
+ Wait_n <= '1';
+ BusRq_n <= '1';
+ INT_n <= '1';
+
+ OE_n <= RD_n;
+ WE_n <= WR_n;
+ RAMCS_n <= RAMCS_n_i;
+ ROMCS_n <= '1';
+ PGM_n <= '1';
+ A(14 downto 0) <= A_i(14 downto 0);
+ A(16 downto 15) <= "00";
+ D <= D_i when WR_n = '0' else "ZZZZZZZZ";
+
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ Reset_s <= '0';
+ Mirror <= '0';
+ elsif Clk'event and Clk = '1' then
+ Reset_s <= '1';
+ if IORQ_n = '0' and A_i(7 downto 4) = "1111" then
+ Mirror <= D_i(0);
+ end if;
+ end if;
+ end process;
+
+ IOWR_n <= WR_n or IORQ_n;
+ RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;
+ UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';
+ UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';
+
+ CPU_D <=
+ D when RAMCS_n_i = '0' else
+ UART0_D when UART0CS_n = '0' else
+ UART1_D when UART1CS_n = '0' else
+ ROM_D;
+
+ u0 : entity work.T80s
+ generic map(Mode => 1, T2Write => 1, IOWait => 0)
+ port map(
+ RESET_n => RESET_s,
+ CLK_n => Clk,
+ WAIT_n => WAIT_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ BUSRQ_n => BUSRQ_n,
+ M1_n => M1_n,
+ MREQ_n => MREQ_n,
+ IORQ_n => IORQ_n,
+ RD_n => RD_n,
+ WR_n => WR_n,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ BUSAK_n => BUSAK_n,
+ A => A_i,
+ DI => CPU_D,
+ DO => D_i);
+
+ u1 : entity work.MonZ80
+ port map(
+ Clk => Clk,
+ A => A_i(10 downto 0),
+ D => ROM_D);
+
+ u3 : entity work.T16450
+ port map(
+ MR_n => Reset_s,
+ XIn => Clk,
+ RClk => BaudOut0,
+ CS_n => UART0CS_n,
+ Rd_n => RD_n,
+ Wr_n => IOWR_n,
+ A => A_i(2 downto 0),
+ D_In => D_i,
+ D_Out => UART0_D,
+ SIn => RXD0,
+ CTS_n => CTS0,
+ DSR_n => DSR0,
+ RI_n => RI0,
+ DCD_n => DCD0,
+ SOut => TXD0,
+ RTS_n => RTS0,
+ DTR_n => DTR0,
+ OUT1_n => open,
+ OUT2_n => open,
+ BaudOut => BaudOut0,
+ Intr => open);
+
+ u4 : entity work.T16450
+ port map(
+ MR_n => Reset_s,
+ XIn => Clk,
+ RClk => BaudOut1,
+ CS_n => UART1CS_n,
+ Rd_n => RD_n,
+ Wr_n => IOWR_n,
+ A => A_i(2 downto 0),
+ D_In => D_i,
+ D_Out => UART1_D,
+ SIn => RXD1,
+ CTS_n => CTS1,
+ DSR_n => DSR1,
+ RI_n => RI1,
+ DCD_n => DCD1,
+ SOut => TXD1,
+ RTS_n => RTS1,
+ DTR_n => DTR1,
+ OUT1_n => open,
+ OUT2_n => open,
+ BaudOut => BaudOut1,
+ Intr => open);
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/SSRAM2.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/SSRAM2.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/SSRAM2.vhd (revision 6)
@@ -0,0 +1,92 @@
+--
+-- Inferrable Synchronous SRAM for Leonardo synthesis, no write through!
+--
+-- Version : 0236
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SSRAM is
+ generic(
+ AddrWidth : integer := 16;
+ DataWidth : integer := 8
+ );
+ port(
+ Clk : in std_logic;
+ CE_n : in std_logic;
+ WE_n : in std_logic;
+ A : in std_logic_vector(AddrWidth - 1 downto 0);
+ DIn : in std_logic_vector(DataWidth - 1 downto 0);
+ DOut : out std_logic_vector(DataWidth - 1 downto 0)
+ );
+end SSRAM;
+
+architecture behaviour of SSRAM is
+
+ type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
+ signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
+-- signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+-- pragma translate_off
+ if not is_x(A) then
+-- pragma translate_on
+ DOut <= RAM(to_integer(unsigned(A(AddrWidth - 1 downto 0))));
+-- pragma translate_off
+ end if;
+-- pragma translate_on
+ if CE_n = '0' and WE_n = '0' then
+ RAM(to_integer(unsigned(A))) <= DIn;
+ end if;
+-- A_r <= A;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80_Reg.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80_Reg.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80_Reg.vhd (revision 6)
@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0242 : Initial release
+--
+-- 0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+ type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+ signal RegsH : Register_Image(0 to 7);
+ signal RegsL : Register_Image(0 to 7);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if CEN = '1' then
+ if WEH = '1' then
+ RegsH(to_integer(unsigned(AddrA))) <= DIH;
+ end if;
+ if WEL = '1' then
+ RegsL(to_integer(unsigned(AddrA))) <= DIL;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ DOAH <= RegsH(to_integer(unsigned(AddrA)));
+ DOAL <= RegsL(to_integer(unsigned(AddrA)));
+ DOBH <= RegsH(to_integer(unsigned(AddrB)));
+ DOBL <= RegsL(to_integer(unsigned(AddrB)));
+ DOCH <= RegsH(to_integer(unsigned(AddrC)));
+ DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80_Pack.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80_Pack.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80_Pack.vhd (revision 6)
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+ component T80
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+ end component;
+
+ component T80_Reg
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component T80_MCode
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+ end component;
+
+ component T80_ALU
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T8080se.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T8080se.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T8080se.vhd (revision 6)
@@ -0,0 +1,185 @@
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+-- STACK status output not supported
+--
+-- File history :
+--
+-- 0237 : First version
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+ generic(
+ Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK : in std_logic;
+ CLKEN : in std_logic;
+ READY : in std_logic;
+ HOLD : in std_logic;
+ INT : in std_logic;
+ INTE : out std_logic;
+ DBIN : out std_logic;
+ SYNC : out std_logic;
+ VAIT : out std_logic;
+ HLDA : out std_logic;
+ WR_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+end T8080se;
+
+architecture rtl of T8080se is
+
+ signal IntCycle_n : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal IORQ : std_logic;
+ signal INT_n : std_logic;
+ signal HALT_n : std_logic;
+ signal BUSRQ_n : std_logic;
+ signal BUSAK_n : std_logic;
+ signal DO_i : std_logic_vector(7 downto 0);
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+ signal One : std_logic;
+
+begin
+
+ INT_n <= not INT;
+ BUSRQ_n <= HOLD;
+ HLDA <= not BUSAK_n;
+ SYNC <= '1' when TState = "001" else '0';
+ VAIT <= '1' when TState = "010" else '0';
+ One <= '1';
+
+ DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
+ DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
+ DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
+ DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
+ DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
+ DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
+ DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
+ DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => 0)
+ port map(
+ CEN => CLKEN,
+ M1_n => open,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => open,
+ HALT_n => HALT_n,
+ WAIT_n => READY,
+ INT_n => INT_n,
+ NMI_n => One,
+ RESET_n => RESET_n,
+ BUSRQ_n => One,
+ BUSAK_n => BUSAK_n,
+ CLK_n => CLK,
+ A => A,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO_i,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n,
+ IntE => INTE);
+
+ process (RESET_n, CLK)
+ begin
+ if RESET_n = '0' then
+ DBIN <= '0';
+ WR_n <= '1';
+ DI_Reg <= "00000000";
+ elsif CLK'event and CLK = '1' then
+ if CLKEN = '1' then
+ DBIN <= '0';
+ WR_n <= '1';
+ if MCycle = "001" then
+ if TState = "001" or (TState = "010" and READY = '0') then
+ DBIN <= IntCycle_n;
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+ DBIN <= '1';
+ end if;
+ if T2Write = 0 then
+ if TState = "010" and Write = '1' then
+ WR_n <= '0';
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+ WR_n <= '0';
+ end if;
+ end if;
+ end if;
+ if TState = "010" and READY = '1' then
+ DI_Reg <= DI;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80.vhd (revision 6)
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0210 : Fixed wait and halt
+--
+-- 0211 : Fixed Refresh addition and IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+-- 0237 : Changed 8080 I/O address output, added IntE output
+--
+-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+-- 0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+end T80;
+
+architecture rtl of T80 is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ -- Registers
+ signal ACC, F : std_logic_vector(7 downto 0);
+ signal Ap, Fp : std_logic_vector(7 downto 0);
+ signal I : std_logic_vector(7 downto 0);
+ signal R : unsigned(7 downto 0);
+ signal SP, PC : unsigned(15 downto 0);
+
+ signal RegDIH : std_logic_vector(7 downto 0);
+ signal RegDIL : std_logic_vector(7 downto 0);
+ signal RegBusA : std_logic_vector(15 downto 0);
+ signal RegBusB : std_logic_vector(15 downto 0);
+ signal RegBusC : std_logic_vector(15 downto 0);
+ signal RegAddrA_r : std_logic_vector(2 downto 0);
+ signal RegAddrA : std_logic_vector(2 downto 0);
+ signal RegAddrB_r : std_logic_vector(2 downto 0);
+ signal RegAddrB : std_logic_vector(2 downto 0);
+ signal RegAddrC : std_logic_vector(2 downto 0);
+ signal RegWEH : std_logic;
+ signal RegWEL : std_logic;
+ signal Alternate : std_logic;
+
+ -- Help Registers
+ signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
+ signal IR : std_logic_vector(7 downto 0); -- Instruction register
+ signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
+ signal RegBusA_r : std_logic_vector(15 downto 0);
+
+ signal ID16 : signed(15 downto 0);
+ signal Save_Mux : std_logic_vector(7 downto 0);
+
+ signal TState : unsigned(2 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal IntE_FF1 : std_logic;
+ signal IntE_FF2 : std_logic;
+ signal Halt_FF : std_logic;
+ signal BusReq_s : std_logic;
+ signal BusAck : std_logic;
+ signal ClkEn : std_logic;
+ signal NMI_s : std_logic;
+ signal INT_s : std_logic;
+ signal IStatus : std_logic_vector(1 downto 0);
+
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal T_Res : std_logic;
+ signal XY_State : std_logic_vector(1 downto 0);
+ signal Pre_XY_F_M : std_logic_vector(2 downto 0);
+ signal NextIs_XY_Fetch : std_logic;
+ signal XY_Ind : std_logic;
+ signal No_BTR : std_logic;
+ signal BTR_r : std_logic;
+ signal Auto_Wait : std_logic;
+ signal Auto_Wait_t1 : std_logic;
+ signal Auto_Wait_t2 : std_logic;
+ signal IncDecZ : std_logic;
+
+ -- ALU signals
+ signal BusB : std_logic_vector(7 downto 0);
+ signal BusA : std_logic_vector(7 downto 0);
+ signal ALU_Q : std_logic_vector(7 downto 0);
+ signal F_Out : std_logic_vector(7 downto 0);
+
+ -- Registered micro code outputs
+ signal Read_To_Reg_r : std_logic_vector(4 downto 0);
+ signal Arith16_r : std_logic;
+ signal Z16_r : std_logic;
+ signal ALU_Op_r : std_logic_vector(3 downto 0);
+ signal Save_ALU_r : std_logic;
+ signal PreserveC_r : std_logic;
+ signal MCycles : std_logic_vector(2 downto 0);
+
+ -- Micro code outputs
+ signal MCycles_d : std_logic_vector(2 downto 0);
+ signal TStates : std_logic_vector(2 downto 0);
+ signal IntCycle : std_logic;
+ signal NMICycle : std_logic;
+ signal Inc_PC : std_logic;
+ signal Inc_WZ : std_logic;
+ signal IncDec_16 : std_logic_vector(3 downto 0);
+ signal Prefix : std_logic_vector(1 downto 0);
+ signal Read_To_Acc : std_logic;
+ signal Read_To_Reg : std_logic;
+ signal Set_BusB_To : std_logic_vector(3 downto 0);
+ signal Set_BusA_To : std_logic_vector(3 downto 0);
+ signal ALU_Op : std_logic_vector(3 downto 0);
+ signal Save_ALU : std_logic;
+ signal PreserveC : std_logic;
+ signal Arith16 : std_logic;
+ signal Set_Addr_To : std_logic_vector(2 downto 0);
+ signal Jump : std_logic;
+ signal JumpE : std_logic;
+ signal JumpXY : std_logic;
+ signal Call : std_logic;
+ signal RstP : std_logic;
+ signal LDZ : std_logic;
+ signal LDW : std_logic;
+ signal LDSPHL : std_logic;
+ signal IORQ_i : std_logic;
+ signal Special_LD : std_logic_vector(2 downto 0);
+ signal ExchangeDH : std_logic;
+ signal ExchangeRp : std_logic;
+ signal ExchangeAF : std_logic;
+ signal ExchangeRS : std_logic;
+ signal I_DJNZ : std_logic;
+ signal I_CPL : std_logic;
+ signal I_CCF : std_logic;
+ signal I_SCF : std_logic;
+ signal I_RETN : std_logic;
+ signal I_BT : std_logic;
+ signal I_BC : std_logic;
+ signal I_BTR : std_logic;
+ signal I_RLD : std_logic;
+ signal I_RRD : std_logic;
+ signal I_INRC : std_logic;
+ signal SetDI : std_logic;
+ signal SetEI : std_logic;
+ signal IMode : std_logic_vector(1 downto 0);
+ signal Halt : std_logic;
+
+begin
+
+ mcode : T80_MCode
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ IR => IR,
+ ISet => ISet,
+ MCycle => MCycle,
+ F => F,
+ NMICycle => NMICycle,
+ IntCycle => IntCycle,
+ MCycles => MCycles_d,
+ TStates => TStates,
+ Prefix => Prefix,
+ Inc_PC => Inc_PC,
+ Inc_WZ => Inc_WZ,
+ IncDec_16 => IncDec_16,
+ Read_To_Acc => Read_To_Acc,
+ Read_To_Reg => Read_To_Reg,
+ Set_BusB_To => Set_BusB_To,
+ Set_BusA_To => Set_BusA_To,
+ ALU_Op => ALU_Op,
+ Save_ALU => Save_ALU,
+ PreserveC => PreserveC,
+ Arith16 => Arith16,
+ Set_Addr_To => Set_Addr_To,
+ IORQ => IORQ_i,
+ Jump => Jump,
+ JumpE => JumpE,
+ JumpXY => JumpXY,
+ Call => Call,
+ RstP => RstP,
+ LDZ => LDZ,
+ LDW => LDW,
+ LDSPHL => LDSPHL,
+ Special_LD => Special_LD,
+ ExchangeDH => ExchangeDH,
+ ExchangeRp => ExchangeRp,
+ ExchangeAF => ExchangeAF,
+ ExchangeRS => ExchangeRS,
+ I_DJNZ => I_DJNZ,
+ I_CPL => I_CPL,
+ I_CCF => I_CCF,
+ I_SCF => I_SCF,
+ I_RETN => I_RETN,
+ I_BT => I_BT,
+ I_BC => I_BC,
+ I_BTR => I_BTR,
+ I_RLD => I_RLD,
+ I_RRD => I_RRD,
+ I_INRC => I_INRC,
+ SetDI => SetDI,
+ SetEI => SetEI,
+ IMode => IMode,
+ Halt => Halt,
+ NoRead => NoRead,
+ Write => Write);
+
+ alu : T80_ALU
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ Arith16 => Arith16_r,
+ Z16 => Z16_r,
+ ALU_Op => ALU_Op_r,
+ IR => IR(5 downto 0),
+ ISet => ISet,
+ BusA => BusA,
+ BusB => BusB,
+ F_In => F,
+ Q => ALU_Q,
+ F_Out => F_Out);
+
+ ClkEn <= CEN and not BusAck;
+
+ T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+ NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+ ((Set_Addr_To = aXY) or
+ (MCycle = "001" and IR = "11001011") or
+ (MCycle = "001" and IR = "00110110")) else '0';
+
+ Save_Mux <= BusB when ExchangeRp = '1' else
+ DI_Reg when Save_ALU_r = '0' else
+ ALU_Q;
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ PC <= (others => '0'); -- Program Counter
+ A <= (others => '0');
+ TmpAddr <= (others => '0');
+ IR <= "00000000";
+ ISet <= "00";
+ XY_State <= "00";
+ IStatus <= "00";
+ MCycles <= "000";
+ DO <= "00000000";
+
+ ACC <= (others => '1');
+ F <= (others => '1');
+ Ap <= (others => '1');
+ Fp <= (others => '1');
+ I <= (others => '0');
+ R <= (others => '0');
+ SP <= (others => '1');
+ Alternate <= '0';
+
+ Read_To_Reg_r <= "00000";
+ F <= (others => '1');
+ Arith16_r <= '0';
+ BTR_r <= '0';
+ Z16_r <= '0';
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ PreserveC_r <= '0';
+ XY_Ind <= '0';
+
+ elsif CLK_n'event and CLK_n = '1' then
+
+ if ClkEn = '1' then
+
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ Read_To_Reg_r <= "00000";
+
+ MCycles <= MCycles_d;
+
+ if IMode /= "11" then
+ IStatus <= IMode;
+ end if;
+
+ Arith16_r <= Arith16;
+ PreserveC_r <= PreserveC;
+ if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+ Z16_r <= '1';
+ else
+ Z16_r <= '0';
+ end if;
+
+ if MCycle = "001" and TState(2) = '0' then
+ -- MCycle = 1 and TState = 1, 2, or 3
+
+ if TState = 2 and Wait_n = '1' then
+ if Mode < 2 then
+ A(7 downto 0) <= std_logic_vector(R);
+ A(15 downto 8) <= I;
+ R(6 downto 0) <= R(6 downto 0) + 1;
+ end if;
+
+ if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+ PC <= PC + 1;
+ end if;
+
+ if IntCycle = '1' and IStatus = "01" then
+ IR <= "11111111";
+ elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+ IR <= "00000000";
+ else
+ IR <= DInst;
+ end if;
+
+ ISet <= "00";
+ if Prefix /= "00" then
+ if Prefix = "11" then
+ if IR(5) = '1' then
+ XY_State <= "10";
+ else
+ XY_State <= "01";
+ end if;
+ else
+ if Prefix = "10" then
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ ISet <= Prefix;
+ end if;
+ else
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ end if;
+
+ else
+ -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+ if MCycle = "110" then
+ XY_Ind <= '1';
+ if Prefix = "01" then
+ ISet <= "01";
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+ if Jump = '1' then
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(DI_Reg);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ elsif JumpXY = '1' then
+ A <= RegBusC;
+ PC <= unsigned(RegBusC);
+ elsif Call = '1' or RstP = '1' then
+ A <= TmpAddr;
+ PC <= unsigned(TmpAddr);
+ elsif MCycle = MCycles and NMICycle = '1' then
+ A <= "0000000001100110";
+ PC <= "0000000001100110";
+ elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+ A(15 downto 8) <= I;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(I);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ else
+ case Set_Addr_To is
+ when aXY =>
+ if XY_State = "00" then
+ A <= RegBusC;
+ else
+ if NextIs_XY_Fetch = '1' then
+ A <= std_logic_vector(PC);
+ else
+ A <= TmpAddr;
+ end if;
+ end if;
+ when aIOA =>
+ if Mode = 3 then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ elsif Mode = 2 then
+ -- Duplicate I/O address on 8080
+ A(15 downto 8) <= DI_Reg;
+ else
+ A(15 downto 8) <= ACC;
+ end if;
+ A(7 downto 0) <= DI_Reg;
+ when aSP =>
+ A <= std_logic_vector(SP);
+ when aBC =>
+ if Mode = 3 and IORQ_i = '1' then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ A(7 downto 0) <= RegBusC(7 downto 0);
+ else
+ A <= RegBusC;
+ end if;
+ when aDE =>
+ A <= RegBusC;
+ when aZI =>
+ if Inc_WZ = '1' then
+ A <= std_logic_vector(unsigned(TmpAddr) + 1);
+ else
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ end if;
+ when others =>
+ A <= std_logic_vector(PC);
+ end case;
+ end if;
+
+ Save_ALU_r <= Save_ALU;
+ ALU_Op_r <= ALU_Op;
+
+ if I_CPL = '1' then
+ -- CPL
+ ACC <= not ACC;
+ F(Flag_Y) <= not ACC(5);
+ F(Flag_H) <= '1';
+ F(Flag_X) <= not ACC(3);
+ F(Flag_N) <= '1';
+ end if;
+ if I_CCF = '1' then
+ -- CCF
+ F(Flag_C) <= not F(Flag_C);
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= F(Flag_C);
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ if I_SCF = '1' then
+ -- SCF
+ F(Flag_C) <= '1';
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= '0';
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ end if;
+
+ if TState = 2 and Wait_n = '1' then
+ if ISet = "01" and MCycle = "111" then
+ IR <= DInst;
+ end if;
+ if JumpE = '1' then
+ PC <= unsigned(signed(PC) + signed(DI_Reg));
+ elsif Inc_PC = '1' then
+ PC <= PC + 1;
+ end if;
+ if BTR_r = '1' then
+ PC <= PC - 2;
+ end if;
+ if RstP = '1' then
+ TmpAddr <= (others =>'0');
+ TmpAddr(5 downto 3) <= IR(5 downto 3);
+ end if;
+ end if;
+ if TState = 3 and MCycle = "110" then
+ TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+ end if;
+
+ if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+ if IncDec_16(2 downto 0) = "111" then
+ if IncDec_16(3) = '1' then
+ SP <= SP - 1;
+ else
+ SP <= SP + 1;
+ end if;
+ end if;
+ end if;
+
+ if LDSPHL = '1' then
+ SP <= unsigned(RegBusC);
+ end if;
+ if ExchangeAF = '1' then
+ Ap <= ACC;
+ ACC <= Ap;
+ Fp <= F;
+ F <= Fp;
+ end if;
+ if ExchangeRS = '1' then
+ Alternate <= not Alternate;
+ end if;
+ end if;
+
+ if TState = 3 then
+ if LDZ = '1' then
+ TmpAddr(7 downto 0) <= DI_Reg;
+ end if;
+ if LDW = '1' then
+ TmpAddr(15 downto 8) <= DI_Reg;
+ end if;
+
+ if Special_LD(2) = '1' then
+ case Special_LD(1 downto 0) is
+ when "00" =>
+ ACC <= I;
+ F(Flag_P) <= IntE_FF2;
+ when "01" =>
+ ACC <= std_logic_vector(R);
+ F(Flag_P) <= IntE_FF2;
+ when "10" =>
+ I <= ACC;
+ when others =>
+ R <= unsigned(ACC);
+ end case;
+ end if;
+ end if;
+
+ if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+ if Mode = 3 then
+ F(6) <= F_Out(6);
+ F(5) <= F_Out(5);
+ F(7) <= F_Out(7);
+ if PreserveC_r = '0' then
+ F(4) <= F_Out(4);
+ end if;
+ else
+ F(7 downto 1) <= F_Out(7 downto 1);
+ if PreserveC_r = '0' then
+ F(Flag_C) <= F_Out(0);
+ end if;
+ end if;
+ end if;
+ if T_Res = '1' and I_INRC = '1' then
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ if DI_Reg(7 downto 0) = "00000000" then
+ F(Flag_Z) <= '1';
+ else
+ F(Flag_Z) <= '0';
+ end if;
+ F(Flag_S) <= DI_Reg(7);
+ F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+ DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+ end if;
+
+ if TState = 1 then
+ DO <= BusB;
+ if I_RLD = '1' then
+ DO(3 downto 0) <= BusA(3 downto 0);
+ DO(7 downto 4) <= BusB(3 downto 0);
+ end if;
+ if I_RRD = '1' then
+ DO(3 downto 0) <= BusB(7 downto 4);
+ DO(7 downto 4) <= BusA(3 downto 0);
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+ Read_To_Reg_r(4) <= Read_To_Reg;
+ if Read_To_Acc = '1' then
+ Read_To_Reg_r(3 downto 0) <= "0111";
+ Read_To_Reg_r(4) <= '1';
+ end if;
+ end if;
+
+ if TState = 1 and I_BT = '1' then
+ F(Flag_X) <= ALU_Q(3);
+ F(Flag_Y) <= ALU_Q(1);
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ end if;
+ if I_BC = '1' or I_BT = '1' then
+ F(Flag_P) <= IncDecZ;
+ end if;
+
+ if (TState = 1 and Save_ALU_r = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10111" =>
+ ACC <= Save_Mux;
+ when "10110" =>
+ DO <= Save_Mux;
+ when "11000" =>
+ SP(7 downto 0) <= unsigned(Save_Mux);
+ when "11001" =>
+ SP(15 downto 8) <= unsigned(Save_Mux);
+ when "11011" =>
+ F <= Save_Mux;
+ when others =>
+ end case;
+ end if;
+
+ end if;
+
+ end if;
+
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ -- Bus A / Write
+ RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+ RegAddrA_r <= XY_State(1) & "11";
+ end if;
+
+ -- Bus B
+ RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+ RegAddrB_r <= XY_State(1) & "11";
+ end if;
+
+ -- Address from register
+ RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+ -- Jump (HL), LD SP,HL
+ if (JumpXY = '1' or LDSPHL = '1') then
+ RegAddrC <= Alternate & "10";
+ end if;
+ if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+ RegAddrC <= XY_State(1) & "11";
+ end if;
+
+ if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+ IncDecZ <= F_Out(Flag_Z);
+ end if;
+ if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+ if ID16 = 0 then
+ IncDecZ <= '0';
+ else
+ IncDecZ <= '1';
+ end if;
+ end if;
+
+ RegBusA_r <= RegBusA;
+ end if;
+ end if;
+ end process;
+
+ RegAddrA <=
+ -- 16 bit increment/decrement
+ Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+ XY_State(1) & "11" when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+ -- EX HL,DL
+ Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+ Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+ -- Bus A / Write
+ RegAddrA_r;
+
+ RegAddrB <=
+ -- EX HL,DL
+ Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+ -- Bus B
+ RegAddrB_r;
+
+ ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+ signed(RegBusA) + 1;
+
+ process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegWEH <= '0';
+ RegWEL <= '0';
+ if (TState = 1 and Save_ALU_r = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+ RegWEH <= not Read_To_Reg_r(0);
+ RegWEL <= Read_To_Reg_r(0);
+ when others =>
+ end case;
+ end if;
+
+ if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+ RegWEH <= '1';
+ RegWEL <= '1';
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ case IncDec_16(1 downto 0) is
+ when "00" | "01" | "10" =>
+ RegWEH <= '1';
+ RegWEL <= '1';
+ when others =>
+ end case;
+ end if;
+ end process;
+
+ process (Save_Mux, RegBusB, RegBusA_r, ID16,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegDIH <= Save_Mux;
+ RegDIL <= Save_Mux;
+
+ if ExchangeDH = '1' and TState = 3 then
+ RegDIH <= RegBusB(15 downto 8);
+ RegDIL <= RegBusB(7 downto 0);
+ end if;
+ if ExchangeDH = '1' and TState = 4 then
+ RegDIH <= RegBusA_r(15 downto 8);
+ RegDIL <= RegBusA_r(7 downto 0);
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ RegDIH <= std_logic_vector(ID16(15 downto 8));
+ RegDIL <= std_logic_vector(ID16(7 downto 0));
+ end if;
+ end process;
+
+ Regs : T80_Reg
+ port map(
+ Clk => CLK_n,
+ CEN => ClkEn,
+ WEH => RegWEH,
+ WEL => RegWEL,
+ AddrA => RegAddrA,
+ AddrB => RegAddrB,
+ AddrC => RegAddrC,
+ DIH => RegDIH,
+ DIL => RegDIL,
+ DOAH => RegBusA(15 downto 8),
+ DOAL => RegBusA(7 downto 0),
+ DOBH => RegBusB(15 downto 8),
+ DOBL => RegBusB(7 downto 0),
+ DOCH => RegBusC(15 downto 8),
+ DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ case Set_BusB_To is
+ when "0111" =>
+ BusB <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusB_To(0) = '1' then
+ BusB <= RegBusB(7 downto 0);
+ else
+ BusB <= RegBusB(15 downto 8);
+ end if;
+ when "0110" =>
+ BusB <= DI_Reg;
+ when "1000" =>
+ BusB <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusB <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusB <= "00000001";
+ when "1011" =>
+ BusB <= F;
+ when "1100" =>
+ BusB <= std_logic_vector(PC(7 downto 0));
+ when "1101" =>
+ BusB <= std_logic_vector(PC(15 downto 8));
+ when "1110" =>
+ BusB <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+
+ case Set_BusA_To is
+ when "0111" =>
+ BusA <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusA_To(0) = '1' then
+ BusA <= RegBusA(7 downto 0);
+ else
+ BusA <= RegBusA(15 downto 8);
+ end if;
+ when "0110" =>
+ BusA <= DI_Reg;
+ when "1000" =>
+ BusA <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusA <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusA <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+ process (RESET_n,CLK_n)
+ begin
+ if RESET_n = '0' then
+ RFSH_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
+ RFSH_n <= '0';
+ else
+ RFSH_n <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ MC <= std_logic_vector(MCycle);
+ TS <= std_logic_vector(TState);
+ DI_Reg <= DI;
+ HALT_n <= not Halt_FF;
+ BUSAK_n <= not BusAck;
+ IntCycle_n <= not IntCycle;
+ IntE <= IntE_FF1;
+ IORQ <= IORQ_i;
+ Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ variable OldNMI_n : std_logic;
+ begin
+ if RESET_n = '0' then
+ BusReq_s <= '0';
+ INT_s <= '0';
+ NMI_s <= '0';
+ OldNMI_n := '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ BusReq_s <= not BUSRQ_n;
+ INT_s <= not INT_n;
+ if NMICycle = '1' then
+ NMI_s <= '0';
+ elsif NMI_n = '0' and OldNMI_n = '1' then
+ NMI_s <= '1';
+ end if;
+ OldNMI_n := NMI_n;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ MCycle <= "001";
+ TState <= "000";
+ Pre_XY_F_M <= "000";
+ Halt_FF <= '0';
+ BusAck <= '0';
+ NMICycle <= '0';
+ IntCycle <= '0';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ No_BTR <= '0';
+ Auto_Wait_t1 <= '0';
+ Auto_Wait_t2 <= '0';
+ M1_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ Auto_Wait_t1 <= Auto_Wait;
+ Auto_Wait_t2 <= Auto_Wait_t1;
+ No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+ (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+ (I_BTR and (not IR(4) or F(Flag_Z)));
+ if TState = 2 then
+ if SetEI = '1' then
+ IntE_FF1 <= '1';
+ IntE_FF2 <= '1';
+ end if;
+ if I_RETN = '1' then
+ IntE_FF1 <= IntE_FF2;
+ end if;
+ end if;
+ if TState = 3 then
+ if SetDI = '1' then
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ end if;
+ if IntCycle = '1' or NMICycle = '1' then
+ Halt_FF <= '0';
+ end if;
+ if MCycle = "001" and TState = 2 and Wait_n = '1' then
+ M1_n <= '1';
+ end if;
+ if BusReq_s = '1' and BusAck = '1' then
+ else
+ BusAck <= '0';
+ if TState = 2 and Wait_n = '0' then
+ elsif T_Res = '1' then
+ if Halt = '1' then
+ Halt_FF <= '1';
+ end if;
+ if BusReq_s = '1' then
+ BusAck <= '1';
+ else
+ TState <= "001";
+ if NextIs_XY_Fetch = '1' then
+ MCycle <= "110";
+ Pre_XY_F_M <= MCycle;
+ if IR = "00110110" and Mode = 0 then
+ Pre_XY_F_M <= "010";
+ end if;
+ elsif (MCycle = "111") or
+ (MCycle = "110" and Mode = 1 and ISet /= "01") then
+ MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+ elsif (MCycle = MCycles) or
+ No_BTR = '1' or
+ (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+ M1_n <= '0';
+ MCycle <= "001";
+ IntCycle <= '0';
+ NMICycle <= '0';
+ if NMI_s = '1' and Prefix = "00" then
+ NMICycle <= '1';
+ IntE_FF1 <= '0';
+ elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+ IntCycle <= '1';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ else
+ MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+ end if;
+ end if;
+ else
+ if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+ TState <= TState + 1;
+ end if;
+ end if;
+ end if;
+ if TState = 0 then
+ M1_n <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process (IntCycle, NMICycle, MCycle)
+ begin
+ Auto_Wait <= '0';
+ if IntCycle = '1' or NMICycle = '1' then
+ if MCycle = "001" then
+ Auto_Wait <= '1';
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80_ALU.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80_ALU.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80_ALU.vhd (revision 6)
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+-- 0240 : Added GB operations
+--
+-- 0242 : Cleanup
+--
+-- 0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+ procedure AddSub(A : std_logic_vector;
+ B : std_logic_vector;
+ Sub : std_logic;
+ Carry_In : std_logic;
+ signal Res : out std_logic_vector;
+ signal Carry : out std_logic) is
+
+ variable B_i : unsigned(A'length - 1 downto 0);
+ variable Res_i : unsigned(A'length + 1 downto 0);
+ begin
+ if Sub = '1' then
+ B_i := not unsigned(B);
+ else
+ B_i := unsigned(B);
+ end if;
+
+ Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+ Carry <= Res_i(A'length + 1);
+ Res <= std_logic_vector(Res_i(A'length downto 1));
+ end;
+
+ -- AddSub variables (temporary signals)
+ signal UseCarry : std_logic;
+ signal Carry7_v : std_logic;
+ signal Overflow_v : std_logic;
+ signal HalfCarry_v : std_logic;
+ signal Carry_v : std_logic;
+ signal Q_v : std_logic_vector(7 downto 0);
+
+ signal BitMask : std_logic_vector(7 downto 0);
+
+begin
+
+ with IR(5 downto 3) select BitMask <= "00000001" when "000",
+ "00000010" when "001",
+ "00000100" when "010",
+ "00001000" when "011",
+ "00010000" when "100",
+ "00100000" when "101",
+ "01000000" when "110",
+ "10000000" when others;
+
+ UseCarry <= not ALU_Op(2) and ALU_Op(0);
+ AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+ AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+ AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+ -- bug fix - parity flag is just parity for 8080, also overflow for Z80
+ process (Carry_v, Carry7_v, Q_v)
+ begin
+ if(Mode=2) then
+ OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+ Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
+ OverFlow_v <= Carry_v xor Carry7_v;
+ end if;
+ end process;
+
+ process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+ variable Q_t : std_logic_vector(7 downto 0);
+ variable DAA_Q : unsigned(8 downto 0);
+ begin
+ Q_t := "--------";
+ F_Out <= F_In;
+ DAA_Q := "---------";
+ case ALU_Op is
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_C) <= '0';
+ case ALU_OP(2 downto 0) is
+ when "000" | "001" => -- ADD, ADC
+ Q_t := Q_v;
+ F_Out(Flag_C) <= Carry_v;
+ F_Out(Flag_H) <= HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "010" | "011" | "111" => -- SUB, SBC, CP
+ Q_t := Q_v;
+ F_Out(Flag_N) <= '1';
+ F_Out(Flag_C) <= not Carry_v;
+ F_Out(Flag_H) <= not HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "100" => -- AND
+ Q_t(7 downto 0) := BusA and BusB;
+ F_Out(Flag_H) <= '1';
+ when "101" => -- XOR
+ Q_t(7 downto 0) := BusA xor BusB;
+ F_Out(Flag_H) <= '0';
+ when others => -- OR "110"
+ Q_t(7 downto 0) := BusA or BusB;
+ F_Out(Flag_H) <= '0';
+ end case;
+ if ALU_Op(2 downto 0) = "111" then -- CP
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ else
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ end if;
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ if Z16 = '1' then
+ F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
+ end if;
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ case ALU_Op(2 downto 0) is
+ when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+ when others =>
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ end case;
+ if Arith16 = '1' then
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ F_Out(Flag_P) <= F_In(Flag_P);
+ end if;
+ when "1100" =>
+ -- DAA
+ F_Out(Flag_H) <= F_In(Flag_H);
+ F_Out(Flag_C) <= F_In(Flag_C);
+ DAA_Q(7 downto 0) := unsigned(BusA);
+ DAA_Q(8) := '0';
+ if F_In(Flag_N) = '0' then
+ -- After addition
+ -- Alow > 9 or H = 1
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if (DAA_Q(3 downto 0) > 9) then
+ F_Out(Flag_H) <= '1';
+ else
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q := DAA_Q + 6;
+ end if;
+ -- new Ahigh > 9 or C = 1
+ if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q + 96; -- 0x60
+ end if;
+ else
+ -- After subtraction
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if DAA_Q(3 downto 0) > 5 then
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+ end if;
+ if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q - 352; -- 0x160
+ end if;
+ end if;
+ F_Out(Flag_X) <= DAA_Q(3);
+ F_Out(Flag_Y) <= DAA_Q(5);
+ F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+ Q_t := std_logic_vector(DAA_Q(7 downto 0));
+ if DAA_Q(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= DAA_Q(7);
+ F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+ DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+ when "1101" | "1110" =>
+ -- RLD, RRD
+ Q_t(7 downto 4) := BusA(7 downto 4);
+ if ALU_Op(0) = '1' then
+ Q_t(3 downto 0) := BusB(7 downto 4);
+ else
+ Q_t(3 downto 0) := BusB(3 downto 0);
+ end if;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ when "1001" =>
+ -- BIT
+ Q_t(7 downto 0) := BusB and BitMask;
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ F_Out(Flag_P) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ F_Out(Flag_P) <= '0';
+ end if;
+ F_Out(Flag_H) <= '1';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= '0';
+ F_Out(Flag_Y) <= '0';
+ if IR(2 downto 0) /= "110" then
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ end if;
+ when "1010" =>
+ -- SET
+ Q_t(7 downto 0) := BusB or BitMask;
+ when "1011" =>
+ -- RES
+ Q_t(7 downto 0) := BusB and not BitMask;
+ when "1000" =>
+ -- ROT
+ case IR(5 downto 3) is
+ when "000" => -- RLC
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := BusA(7);
+ F_Out(Flag_C) <= BusA(7);
+ when "010" => -- RL
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(7);
+ when "001" => -- RRC
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(0);
+ F_Out(Flag_C) <= BusA(0);
+ when "011" => -- RR
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(0);
+ when "100" => -- SLA
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '0';
+ F_Out(Flag_C) <= BusA(7);
+ when "110" => -- SLL (Undocumented) / SWAP
+ if Mode = 3 then
+ Q_t(7 downto 4) := BusA(3 downto 0);
+ Q_t(3 downto 0) := BusA(7 downto 4);
+ F_Out(Flag_C) <= '0';
+ else
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '1';
+ F_Out(Flag_C) <= BusA(7);
+ end if;
+ when "101" => -- SRA
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(7);
+ F_Out(Flag_C) <= BusA(0);
+ when others => -- SRL
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := '0';
+ F_Out(Flag_C) <= BusA(0);
+ end case;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ if ISet = "00" then
+ F_Out(Flag_P) <= F_In(Flag_P);
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ end if;
+ when others =>
+ null;
+ end case;
+ Q <= Q_t;
+ end process;
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80a.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80a.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80a.vhd (revision 6)
@@ -0,0 +1,253 @@
+--
+-- Z80 compatible microprocessor core, asynchronous top level
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0211 : Fixed interrupt cycle
+--
+-- 0235 : Updated for T80 interface change
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+-- 0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80a is
+ generic(
+ Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ D : inout std_logic_vector(7 downto 0)
+ );
+end T80a;
+
+architecture rtl of T80a is
+
+ signal CEN : std_logic;
+ signal Reset_s : std_logic;
+ signal IntCycle_n : std_logic;
+ signal IORQ : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal MREQ : std_logic;
+ signal MReq_Inhibit : std_logic;
+ signal Req_Inhibit : std_logic;
+ signal RD : std_logic;
+ signal MREQ_n_i : std_logic;
+ signal IORQ_n_i : std_logic;
+ signal RD_n_i : std_logic;
+ signal WR_n_i : std_logic;
+ signal RFSH_n_i : std_logic;
+ signal BUSAK_n_i : std_logic;
+ signal A_i : std_logic_vector(15 downto 0);
+ signal DO : std_logic_vector(7 downto 0);
+ signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
+ signal Wait_s : std_logic;
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ CEN <= '1';
+
+ BUSAK_n <= BUSAK_n_i;
+ MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
+ RD_n_i <= not RD or Req_Inhibit;
+
+ MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
+ IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
+ RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+ WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
+ RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+ A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+ D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ Reset_s <= '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ Reset_s <= '1';
+ end if;
+ end process;
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => 1)
+ port map(
+ CEN => CEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n_i,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_s,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => Reset_s,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n_i,
+ CLK_n => CLK_n,
+ A => A_i,
+ DInst => D,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '0' then
+ Wait_s <= WAIT_n;
+ if TState = "011" and BUSAK_n_i = '1' then
+ DI_Reg <= to_x01(D);
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ WR_n_i <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ WR_n_i <= '1';
+ if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
+ WR_n_i <= not Write;
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ Req_Inhibit <= '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ if MCycle = "001" and TState = "010" then
+ Req_Inhibit <= '1';
+ else
+ Req_Inhibit <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ MReq_Inhibit <= '0';
+ elsif CLK_n'event and CLK_n = '0' then
+ if MCycle = "001" and TState = "010" then
+ MReq_Inhibit <= '1';
+ else
+ MReq_Inhibit <= '0';
+ end if;
+ end if;
+ end process;
+
+ process(Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '0';
+ elsif CLK_n'event and CLK_n = '0' then
+
+ if MCycle = "001" then
+ if TState = "001" then
+ RD <= IntCycle_n;
+ MREQ <= IntCycle_n;
+ IORQ_n_i <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '1';
+ end if;
+ if TState = "100" then
+ MREQ <= '0';
+ end if;
+ else
+ if TState = "001" and NoRead = '0' then
+ RD <= not Write;
+ IORQ_n_i <= not IORQ;
+ MREQ <= not IORQ;
+ end if;
+ if TState = "011" then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/SSRAMX.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/SSRAMX.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/SSRAMX.vhd (revision 6)
@@ -0,0 +1,132 @@
+--
+-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
+--
+-- Version : 0247
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0240 : Initial release
+--
+-- 0242 : Changed RAMB4_S8 to map by name
+--
+-- 0247 : Added RAMB4_S8 component declaration
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SSRAM is
+ generic(
+ AddrWidth : integer := 11;
+ DataWidth : integer := 8
+ );
+ port(
+ Clk : in std_logic;
+ CE_n : in std_logic;
+ WE_n : in std_logic;
+ A : in std_logic_vector(AddrWidth - 1 downto 0);
+ DIn : in std_logic_vector(DataWidth - 1 downto 0);
+ DOut : out std_logic_vector(DataWidth - 1 downto 0)
+ );
+end SSRAM;
+
+architecture rtl of SSRAM is
+
+ component RAMB4_S8
+ port(
+ DO : out std_logic_vector(7 downto 0);
+ ADDR : in std_logic_vector(8 downto 0);
+ CLK : in std_ulogic;
+ DI : in std_logic_vector(7 downto 0);
+ EN : in std_ulogic;
+ RST : in std_ulogic;
+ WE : in std_ulogic);
+ end component;
+
+ constant RAMs : integer := (2 ** AddrWidth) / 512;
+
+ type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
+
+ signal bRAMOut : bRAMOut_a;
+ signal biA_r : integer;
+ signal A_r : unsigned(A'left downto 0);
+-- signal A_i : std_logic_vector(8 downto 0);
+ signal WEA : std_logic_vector(RAMs - 1 downto 0);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ A_r <= unsigned(A);
+ end if;
+ end process;
+
+ biA_r <= to_integer(A_r(A'left downto 9));
+-- A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
+
+ bG1: for I in 0 to RAMs - 1 generate
+ begin
+ WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
+ BSSRAM : RAMB4_S8
+ port map(
+ DI => DIn,
+ EN => '1',
+ WE => WEA(I),
+ RST => '0',
+ CLK => Clk,
+ ADDR => A,
+ DO => bRAMOut(I));
+ end generate;
+
+ process (biA_r, bRAMOut)
+ begin
+ DOut <= bRAMOut(0);
+ for I in 1 to RAMs - 1 loop
+ if biA_r = I then
+ DOut <= bRAMOut(I);
+ end if;
+ end loop;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80_MCode.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80_MCode.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80_MCode.vhd (revision 6)
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0211 : Fixed IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0235 : Added IM 2 fix by Mike Johnson
+--
+-- 0238 : Added NoRead signal
+--
+-- 0238b: Fixed instruction timing for POP and DJNZ
+--
+-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+-- 0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ function is_cc_true(
+ F : std_logic_vector(7 downto 0);
+ cc : bit_vector(2 downto 0)
+ ) return boolean is
+ begin
+ if Mode = 3 then
+ case cc is
+ when "000" => return F(7) = '0'; -- NZ
+ when "001" => return F(7) = '1'; -- Z
+ when "010" => return F(4) = '0'; -- NC
+ when "011" => return F(4) = '1'; -- C
+ when "100" => return false;
+ when "101" => return false;
+ when "110" => return false;
+ when "111" => return false;
+ end case;
+ else
+ case cc is
+ when "000" => return F(6) = '0'; -- NZ
+ when "001" => return F(6) = '1'; -- Z
+ when "010" => return F(0) = '0'; -- NC
+ when "011" => return F(0) = '1'; -- C
+ when "100" => return F(2) = '0'; -- PO
+ when "101" => return F(2) = '1'; -- PE
+ when "110" => return F(7) = '0'; -- P
+ when "111" => return F(7) = '1'; -- M
+ end case;
+ end if;
+ end;
+
+begin
+
+ process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+ variable DDD : std_logic_vector(2 downto 0);
+ variable SSS : std_logic_vector(2 downto 0);
+ variable DPair : std_logic_vector(1 downto 0);
+ variable IRB : bit_vector(7 downto 0);
+ begin
+ DDD := IR(5 downto 3);
+ SSS := IR(2 downto 0);
+ DPair := IR(5 downto 4);
+ IRB := to_bitvector(IR);
+
+ MCycles <= "001";
+ if MCycle = "001" then
+ TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ Prefix <= "00";
+ Inc_PC <= '0';
+ Inc_WZ <= '0';
+ IncDec_16 <= "0000";
+ Read_To_Acc <= '0';
+ Read_To_Reg <= '0';
+ Set_BusB_To <= "0000";
+ Set_BusA_To <= "0000";
+ ALU_Op <= "0" & IR(5 downto 3);
+ Save_ALU <= '0';
+ PreserveC <= '0';
+ Arith16 <= '0';
+ IORQ <= '0';
+ Set_Addr_To <= aNone;
+ Jump <= '0';
+ JumpE <= '0';
+ JumpXY <= '0';
+ Call <= '0';
+ RstP <= '0';
+ LDZ <= '0';
+ LDW <= '0';
+ LDSPHL <= '0';
+ Special_LD <= "000";
+ ExchangeDH <= '0';
+ ExchangeRp <= '0';
+ ExchangeAF <= '0';
+ ExchangeRS <= '0';
+ I_DJNZ <= '0';
+ I_CPL <= '0';
+ I_CCF <= '0';
+ I_SCF <= '0';
+ I_RETN <= '0';
+ I_BT <= '0';
+ I_BC <= '0';
+ I_BTR <= '0';
+ I_RLD <= '0';
+ I_RRD <= '0';
+ I_INRC <= '0';
+ SetDI <= '0';
+ SetEI <= '0';
+ IMode <= "11";
+ Halt <= '0';
+ NoRead <= '0';
+ Write <= '0';
+
+ case ISet is
+ when "00" =>
+
+------------------------------------------------------------------------------
+--
+-- Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+-- 8 BIT LOAD GROUP
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- LD r,r'
+ Set_BusB_To(2 downto 0) <= SSS;
+ ExchangeRp <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+ -- LD r,n
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+ -- LD r,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+ -- LD (HL),r
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110110" =>
+ -- LD (HL),n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00001010" =>
+ -- LD A,(BC)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00011010" =>
+ -- LD A,(DE)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00111010" =>
+ if Mode = 3 then
+ -- LDD A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00000010" =>
+ -- LD (BC),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00010010" =>
+ -- LD (DE),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110010" =>
+ if Mode = 3 then
+ -- LDD (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 16 BIT LOAD GROUP
+ when "00000001"|"00010001"|"00100001"|"00110001" =>
+ -- LD dd,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "00101010" =>
+ if Mode = 3 then
+ -- LDI A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD HL,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00100010" =>
+ if Mode = 3 then
+ -- LDI (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "0101"; -- L
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "0100"; -- H
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11111001" =>
+ -- LD SP,HL
+ TStates <= "110";
+ LDSPHL <= '1';
+ when "11000101"|"11010101"|"11100101"|"11110101" =>
+ -- PUSH qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "0111";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 2 =>
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "1011";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ Write <= '1';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "11000001"|"11010001"|"11100001"|"11110001" =>
+ -- POP qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1011";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "0111";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+ when "11101011" =>
+ if Mode /= 3 then
+ -- EX DE,HL
+ ExchangeDH <= '1';
+ end if;
+ when "00001000" =>
+ if Mode = 3 then
+ -- LD (nn),SP
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "1000";
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "1001";
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EX AF,AF'
+ ExchangeAF <= '1';
+ end if;
+ when "11011001" =>
+ if Mode = 3 then
+ -- RETI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ SetEI <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EXX
+ ExchangeRS <= '1';
+ end if;
+ when "11100011" =>
+ if Mode /= 3 then
+ -- EX (SP),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0101";
+ Set_BusB_To <= "0101";
+ Set_Addr_To <= aSP;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0100";
+ Set_BusB_To <= "0100";
+ Set_Addr_To <= aSP;
+ when 5 =>
+ IncDec_16 <= "1111";
+ TStates <= "101";
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- ADD A,r
+ -- ADC A,r
+ -- SUB A,r
+ -- SBC A,r
+ -- AND A,r
+ -- OR A,r
+ -- XOR A,r
+ -- CP A,r
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- ADD A,(HL)
+ -- ADC A,(HL)
+ -- SUB A,(HL)
+ -- SBC A,(HL)
+ -- AND A,(HL)
+ -- OR A,(HL)
+ -- XOR A,(HL)
+ -- CP A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ when others => null;
+ end case;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- ADD A,n
+ -- ADC A,n
+ -- SUB A,n
+ -- SBC A,n
+ -- AND A,n
+ -- OR A,n
+ -- XOR A,n
+ -- CP A,n
+ MCycles <= "010";
+ if MCycle = "010" then
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ end if;
+ when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+ -- INC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ when "00110100" =>
+ -- INC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+ -- DEC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0010";
+ when "00110101" =>
+ -- DEC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ ALU_Op <= "0010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+ when "00100111" =>
+ -- DAA
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ ALU_Op <= "1100";
+ Save_ALU <= '1';
+ when "00101111" =>
+ -- CPL
+ I_CPL <= '1';
+ when "00111111" =>
+ -- CCF
+ I_CCF <= '1';
+ when "00110111" =>
+ -- SCF
+ I_SCF <= '1';
+ when "00000000" =>
+ if NMICycle = '1' then
+ -- NMI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif IntCycle = '1' then
+ -- INT (IM 2)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ LDZ <= '1';
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 5 =>
+ Jump <= '1';
+ when others => null;
+ end case;
+ else
+ -- NOP
+ end if;
+ when "01110110" =>
+ -- HALT
+ Halt <= '1';
+ when "11110011" =>
+ -- DI
+ SetDI <= '1';
+ when "11111011" =>
+ -- EI
+ SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+ when "00001001"|"00011001"|"00101001"|"00111001" =>
+ -- ADD HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ Arith16 <= '1';
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ Arith16 <= '1';
+ when others =>
+ end case;
+ when "00000011"|"00010011"|"00100011"|"00110011" =>
+ -- INC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "01";
+ IncDec_16(1 downto 0) <= DPair;
+ when "00001011"|"00011011"|"00101011"|"00111011" =>
+ -- DEC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "11";
+ IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+ when "00000111"
+ -- RLCA
+ |"00010111"
+ -- RLA
+ |"00001111"
+ -- RRCA
+ |"00011111" =>
+ -- RRA
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+
+-- JUMP GROUP
+ when "11000011" =>
+ -- JP nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ Jump <= '1';
+ when others => null;
+ end case;
+ when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+C),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "01" =>
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10" =>
+ -- LD A,($FF00+C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "11" =>
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- JP cc,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Jump <= '1';
+ end if;
+ when others => null;
+ end case;
+ end if;
+ when "00011000" =>
+ if Mode /= 2 then
+ -- JR e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00111000" =>
+ if Mode /= 2 then
+ -- JR C,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00110000" =>
+ if Mode /= 2 then
+ -- JR NC,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00101000" =>
+ if Mode /= 2 then
+ -- JR Z,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00100000" =>
+ if Mode /= 2 then
+ -- JR NZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "11101001" =>
+ -- JP (HL)
+ JumpXY <= '1';
+ when "00010000" =>
+ if Mode = 3 then
+ I_DJNZ <= '1';
+ elsif Mode < 2 then
+ -- DJNZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ I_DJNZ <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= "000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ I_DJNZ <= '1';
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+
+-- CALL AND RETURN GROUP
+ when "11001101" =>
+ -- CALL nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ IncDec_16 <= "1111";
+ Inc_PC <= '1';
+ TStates <= "100";
+ Set_Addr_To <= aSP;
+ LDW <= '1';
+ Set_BusB_To <= "1101";
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+ if IR(5) = '0' or Mode /= 3 then
+ -- CALL cc,nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ LDW <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ TStates <= "100";
+ Set_BusB_To <= "1101";
+ else
+ MCycles <= "011";
+ end if;
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11001001" =>
+ -- RET
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+nn),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "01" =>
+ -- ADD SP,n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ ALU_Op <= "0000";
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To <= "1000";
+ Set_BusB_To <= "0110";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To <= "1001";
+ Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+ when others =>
+ end case;
+ when "10" =>
+ -- LD A,($FF00+nn)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "11" =>
+ -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- RET cc
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Set_Addr_TO <= aSP;
+ else
+ MCycles <= "001";
+ end if;
+ TStates <= "101";
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ end if;
+ when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+ -- RST p
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ Write <= '1';
+ RstP <= '1';
+ when others => null;
+ end case;
+
+-- INPUT AND OUTPUT GROUP
+ when "11011011" =>
+ if Mode /= 3 then
+ -- IN A,(n)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11010011" =>
+ if Mode /= 3 then
+ -- OUT (n),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+ when "11001011" =>
+ if Mode /= 2 then
+ Prefix <= "01";
+ end if;
+
+ when "11101101" =>
+ if Mode < 2 then
+ Prefix <= "10";
+ end if;
+
+ when "11011101"|"11111101" =>
+ if Mode < 2 then
+ Prefix <= "11";
+ end if;
+
+ end case;
+
+ when "01" =>
+
+------------------------------------------------------------------------------
+--
+-- CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+ -- RLC r
+ -- RL r
+ -- RRC r
+ -- RR r
+ -- SLA r
+ -- SRA r
+ -- SRL r
+ -- SLL r (Undocumented) / SWAP r
+ if MCycle = "001" then
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+ -- RLC (HL)
+ -- RL (HL)
+ -- RRC (HL)
+ -- RR (HL)
+ -- SRA (HL)
+ -- SRL (HL)
+ -- SLA (HL)
+ -- SLL (HL) (Undocumented) / SWAP (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- BIT b,r
+ if MCycle = "001" then
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+ ALU_Op <= "1001";
+ end if;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+ -- BIT b,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7=>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1001";
+ TStates <= "100";
+ when others => null;
+ end case;
+ when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+ -- SET b,r
+ if MCycle = "001" then
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- SET b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7=>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- RES b,r
+ if MCycle = "001" then
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- RES b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end case;
+
+ when others =>
+
+------------------------------------------------------------------------------
+--
+-- ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+ |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+ | "10100100"|"10100101"|"10100110"|"10100111"
+ | "10101100"|"10101101"|"10101110"|"10101111"
+ | "10110100"|"10110101"|"10110110"|"10110111"
+ | "10111100"|"10111101"|"10111110"|"10111111"
+ |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+ null; -- NOP, undocumented
+ when "01111110"|"01111111" =>
+ -- NOP, undocumented
+ null;
+-- 8 BIT LOAD GROUP
+ when "01010111" =>
+ -- LD A,I
+ Special_LD <= "100";
+ TStates <= "101";
+ when "01011111" =>
+ -- LD A,R
+ Special_LD <= "101";
+ TStates <= "101";
+ when "01000111" =>
+ -- LD I,A
+ Special_LD <= "110";
+ TStates <= "101";
+ when "01001111" =>
+ -- LD R,A
+ Special_LD <= "111";
+ TStates <= "101";
+-- 16 BIT LOAD GROUP
+ when "01001011"|"01011011"|"01101011"|"01111011" =>
+ -- LD dd,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '1';
+ end if;
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "01000011"|"01010011"|"01100011"|"01110011" =>
+ -- LD (nn),dd
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1000";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1001";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10100000" | "10101000" | "10110000" | "10111000" =>
+ -- LDI, LDD, LDIR, LDDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0000";
+ Set_Addr_To <= aDE;
+ if IR(3) = '0' then
+ IncDec_16 <= "0110"; -- IX
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ I_BT <= '1';
+ TStates <= "101";
+ Write <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0101"; -- DE
+ else
+ IncDec_16 <= "1101";
+ end if;
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100001" | "10101001" | "10110001" | "10111001" =>
+ -- CPI, CPD, CPIR, CPDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0111";
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0110";
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ I_BC <= '1';
+ TStates <= "101";
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+ -- NEG
+ Alu_OP <= "0010";
+ Set_BusB_To <= "0111";
+ Set_BusA_To <= "1010";
+ Read_To_Acc <= '1';
+ Save_ALU <= '1';
+ when "01000110"|"01001110"|"01100110"|"01101110" =>
+ -- IM 0
+ IMode <= "00";
+ when "01010110"|"01110110" =>
+ -- IM 1
+ IMode <= "01";
+ when "01011110"|"01110111" =>
+ -- IM 2
+ IMode <= "10";
+-- 16 bit arithmetic
+ when "01001010"|"01011010"|"01101010"|"01111010" =>
+ -- ADC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0001";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01000010"|"01010010"|"01100010"|"01110010" =>
+ -- SBC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01101111" =>
+ -- RLD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1101";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RLD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01100111" =>
+ -- RRD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1110";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RRD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+ -- RETI, RETN
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ when others => null;
+ end case;
+ when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+ -- IN r,(C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ IORQ <= '1';
+ if IR(5 downto 3) /= "110" then
+ Read_To_Reg <= '1';
+ Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+ end if;
+ I_INRC <= '1';
+ when others =>
+ end case;
+ when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+ -- OUT (C),r
+ -- OUT (C),0
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To(2 downto 0) <= IR(5 downto 3);
+ if IR(5 downto 3) = "110" then
+ Set_BusB_To(3) <= '1';
+ end if;
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "10100010" | "10101010" | "10110010" | "10111010" =>
+ -- INI, IND, INIR, INDR
+ -- note B is decremented AFTER being put on the bus
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ IORQ <= '1';
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aXY;
+ when 3 =>
+ if IR(3) = '0' then
+ --IncDec_16 <= "0010";
+ IncDec_16 <= "0110";
+ else
+ --IncDec_16 <= "1010";
+ IncDec_16 <= "1110";
+ end if;
+ TStates <= "100";
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100011" | "10101011" | "10110011" | "10111011" =>
+ -- OUTI, OUTD, OTIR, OTDR
+ -- note B is decremented BEFORE being put on the bus.
+ -- mikej fix for hl inc
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aBC;
+ when 3 =>
+ if IR(3) = '0' then
+ IncDec_16 <= "0110"; -- mikej
+ else
+ IncDec_16 <= "1110"; -- mikej
+ end if;
+ IORQ <= '1';
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end case;
+
+ end case;
+
+ if Mode = 1 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ end if;
+
+ if Mode = 3 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "100";
+ end if;
+ end if;
+
+ if Mode < 2 then
+ if MCycle = "110" then
+ Inc_PC <= '1';
+ if Mode = 1 then
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ end if;
+ if IRB = "00110110" or IRB = "11001011" then
+ Set_Addr_To <= aNone;
+ end if;
+ end if;
+ if MCycle = "111" then
+ if Mode = 0 then
+ TStates <= "101";
+ end if;
+ if ISet /= "01" then
+ Set_Addr_To <= aXY;
+ end if;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ if IRB = "00110110" or ISet = "01" then
+ -- LD (HL),n
+ Inc_PC <= '1';
+ else
+ NoRead <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/SSRAM.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/SSRAM.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/SSRAM.vhd (revision 6)
@@ -0,0 +1,92 @@
+--
+-- Inferrable Synchronous SRAM for XST synthesis
+--
+-- Version : 0220
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+-- 0208 : Initial release
+-- 0218 : Fixed data out at write
+-- 0220 : Added support for XST
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SSRAM is
+ generic(
+ AddrWidth : integer := 11;
+ DataWidth : integer := 8
+ );
+ port(
+ Clk : in std_logic;
+ CE_n : in std_logic;
+ WE_n : in std_logic;
+ A : in std_logic_vector(AddrWidth - 1 downto 0);
+ DIn : in std_logic_vector(DataWidth - 1 downto 0);
+ DOut : out std_logic_vector(DataWidth - 1 downto 0)
+ );
+end SSRAM;
+
+architecture behaviour of SSRAM is
+
+ type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
+ signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
+ signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if (CE_n nor WE_n) = '1' then
+ RAM(to_integer(unsigned(A))) <= DIn;
+ end if;
+ A_r <= A;
+ end if;
+ end process;
+
+ DOut <= RAM(to_integer(unsigned(A_r)))
+-- pragma translate_off
+ when not is_x(A_r) else (others => '-')
+-- pragma translate_on
+ ;
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80set.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80set.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80set.vhd (revision 6)
@@ -0,0 +1,179 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0238
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0235 : First release
+--
+-- 0236 : Added T2Write generic
+--
+-- 0237 : Fixed T2Write with wait state
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80sed is
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CLKEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+end T80sed;
+
+architecture rtl of T80sed is
+
+ signal IntCycle_n : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal IORQ : std_logic;
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ u0 : T80
+ generic map(
+ Mode => 0,
+ IOWait => 1)
+ port map(
+ CEN => CLKEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => RESET_n,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n,
+ CLK_n => CLK_n,
+ A => A,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ DI_Reg <= "00000000";
+ elsif CLK_n'event and CLK_n = '1' then
+ if CLKEN = '1' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ if MCycle = "001" then
+ if TState = "001" or (TState = "010" and Wait_n = '0') then
+ RD_n <= not IntCycle_n;
+ MREQ_n <= not IntCycle_n;
+ IORQ_n <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ MREQ_n <= '0';
+ end if;
+ else
+ if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+ RD_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ if ((TState = "001") or (TState = "010")) and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ end if;
+ if TState = "010" and Wait_n = '1' then
+ DI_Reg <= DI;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/DebugSystem.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/DebugSystem.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/DebugSystem.vhd (revision 6)
@@ -0,0 +1,181 @@
+-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
+-- that can be synthesized and used with
+-- the NoICE debugger that can be found at
+-- http://www.noicedebugger.com/
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity DebugSystem is
+ port(
+ Reset_n : in std_logic;
+ Clk : in std_logic;
+ NMI_n : in std_logic;
+ RXD0 : in std_logic;
+ CTS0 : in std_logic;
+ DSR0 : in std_logic;
+ RI0 : in std_logic;
+ DCD0 : in std_logic;
+ RXD1 : in std_logic;
+ CTS1 : in std_logic;
+ DSR1 : in std_logic;
+ RI1 : in std_logic;
+ DCD1 : in std_logic;
+ TXD0 : out std_logic;
+ RTS0 : out std_logic;
+ DTR0 : out std_logic;
+ TXD1 : out std_logic;
+ RTS1 : out std_logic;
+ DTR1 : out std_logic
+ );
+end DebugSystem;
+
+architecture struct of DebugSystem is
+
+ signal M1_n : std_logic;
+ signal MREQ_n : std_logic;
+ signal IORQ_n : std_logic;
+ signal RD_n : std_logic;
+ signal WR_n : std_logic;
+ signal RFSH_n : std_logic;
+ signal HALT_n : std_logic;
+ signal WAIT_n : std_logic;
+ signal INT_n : std_logic;
+ signal RESET_s : std_logic;
+ signal BUSRQ_n : std_logic;
+ signal BUSAK_n : std_logic;
+ signal A : std_logic_vector(15 downto 0);
+ signal D : std_logic_vector(7 downto 0);
+ signal ROM_D : std_logic_vector(7 downto 0);
+ signal SRAM_D : std_logic_vector(7 downto 0);
+ signal UART0_D : std_logic_vector(7 downto 0);
+ signal UART1_D : std_logic_vector(7 downto 0);
+ signal CPU_D : std_logic_vector(7 downto 0);
+
+ signal Mirror : std_logic;
+
+ signal IOWR_n : std_logic;
+ signal RAMCS_n : std_logic;
+ signal UART0CS_n : std_logic;
+ signal UART1CS_n : std_logic;
+
+ signal BaudOut0 : std_logic;
+ signal BaudOut1 : std_logic;
+
+begin
+
+ Wait_n <= '1';
+ BusRq_n <= '1';
+ INT_n <= '1';
+
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ Reset_s <= '0';
+ Mirror <= '0';
+ elsif Clk'event and Clk = '1' then
+ Reset_s <= '1';
+ if IORQ_n = '0' and A(7 downto 4) = "1111" then
+ Mirror <= D(0);
+ end if;
+ end if;
+ end process;
+
+ IOWR_n <= WR_n or IORQ_n;
+ RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
+ UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
+ UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
+
+ CPU_D <=
+ SRAM_D when RAMCS_n = '0' else
+ UART0_D when UART0CS_n = '0' else
+ UART1_D when UART1CS_n = '0' else
+ ROM_D;
+
+ u0 : entity work.T80s
+ generic map(Mode => 1, T2Write => 1, IOWait => 0)
+ port map(
+ RESET_n => RESET_s,
+ CLK_n => Clk,
+ WAIT_n => WAIT_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ BUSRQ_n => BUSRQ_n,
+ M1_n => M1_n,
+ MREQ_n => MREQ_n,
+ IORQ_n => IORQ_n,
+ RD_n => RD_n,
+ WR_n => WR_n,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ BUSAK_n => BUSAK_n,
+ A => A,
+ DI => CPU_D,
+ DO => D);
+
+ u1 : entity work.MonZ80
+ port map(
+ Clk => Clk,
+ A => A(10 downto 0),
+ D => ROM_D);
+
+ u2 : entity work.SSRAM
+ generic map(
+ AddrWidth => 12)
+ port map(
+ Clk => Clk,
+ CE_n => RAMCS_n,
+ WE_n => WR_n,
+ A => A(11 downto 0),
+ DIn => D,
+ DOut => SRAM_D);
+
+ u3 : entity work.T16450
+ port map(
+ MR_n => Reset_s,
+ XIn => Clk,
+ RClk => BaudOut0,
+ CS_n => UART0CS_n,
+ Rd_n => RD_n,
+ Wr_n => IOWR_n,
+ A => A(2 downto 0),
+ D_In => D,
+ D_Out => UART0_D,
+ SIn => RXD0,
+ CTS_n => CTS0,
+ DSR_n => DSR0,
+ RI_n => RI0,
+ DCD_n => DCD0,
+ SOut => TXD0,
+ RTS_n => RTS0,
+ DTR_n => DTR0,
+ OUT1_n => open,
+ OUT2_n => open,
+ BaudOut => BaudOut0,
+ Intr => open);
+
+ u4 : entity work.T16450
+ port map(
+ MR_n => Reset_s,
+ XIn => Clk,
+ RClk => BaudOut1,
+ CS_n => UART1CS_n,
+ Rd_n => RD_n,
+ Wr_n => IOWR_n,
+ A => A(2 downto 0),
+ D_In => D,
+ D_Out => UART1_D,
+ SIn => RXD1,
+ CTS_n => CTS1,
+ DSR_n => DSR1,
+ RI_n => RI1,
+ DCD_n => DCD1,
+ SOut => TXD1,
+ RTS_n => RTS1,
+ DTR_n => DTR1,
+ OUT1_n => open,
+ OUT2_n => open,
+ BaudOut => BaudOut1,
+ Intr => open);
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/t80/T80s.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/t80/T80s.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/t80/T80s.vhd (revision 6)
@@ -0,0 +1,190 @@
+--
+-- Z80 compatible microprocessor core, synchronous top level
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0210 : Fixed read with wait
+--
+-- 0211 : Fixed interrupt cycle
+--
+-- 0235 : Updated for T80 interface change
+--
+-- 0236 : Added T2Write generic
+--
+-- 0237 : Fixed T2Write with wait state
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80s is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+end T80s;
+
+architecture rtl of T80s is
+
+ signal CEN : std_logic;
+ signal IntCycle_n : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal IORQ : std_logic;
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ CEN <= '1';
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => IOWait)
+ port map(
+ CEN => CEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => RESET_n,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n,
+ CLK_n => CLK_n,
+ A => A,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ DI_Reg <= "00000000";
+ elsif CLK_n'event and CLK_n = '1' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ if MCycle = "001" then
+ if TState = "001" or (TState = "010" and Wait_n = '0') then
+ RD_n <= not IntCycle_n;
+ MREQ_n <= not IntCycle_n;
+ IORQ_n <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ MREQ_n <= '0';
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+ RD_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ if T2Write = 0 then
+ if TState = "010" and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ end if;
+ end if;
+ if TState = "010" and Wait_n = '1' then
+ DI_Reg <= DI;
+ end if;
+ end if;
+ end process;
+
+end;
Index: z80control/trunk/DE1/rtl/VHDL/top_de1.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/top_de1.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/top_de1.vhd (revision 6)
@@ -0,0 +1,642 @@
+-------------------------------------------------------------------------------------------------
+-- Z80_Soc (Z80 System on Chip)
+--
+-- Version history:
+-------------------
+-- version 0.6 for for Altera DE1
+-- Release Date: 2008 / 05 / 21
+--
+-- Version 0.5 Beta for Altera DE1
+-- Developer: Ronivon Candido Costa
+-- Release Date: 2008 / 04 / 16
+--
+-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
+-- This version developed and tested on: Altera DE1 Development Board
+--
+-- Peripherals configured (Using Ports):
+--
+-- 40 KB Internal ROM Read (0x0000h - 0x9FFFh)
+-- 08 KB Shared Memory Read/Write (0xA000h - 0xBFFFh)
+-- Locked Supr1 (0xC000h - 0xC7FFh)
+-- Supr2 (0xC800h - 0xCFFFh)
+-- Supr3 (0xD000h - 0xD7FFh)
+-- Supr4 (0xD800h - 0xDFFFh) -- Stack starts at DFEA and goes down
+-- Supr5 (0xE000h - 0xE7FFh)
+-- Supr6 (0xE800h - 0xEFFFh)
+-- Pram Locked (0xF000h - 0xF7FFh) -- Switched between 5 banks
+-- Sram (0xF800h - 0xF8FFh) -- Switched between 5 banks
+-- Ram (0xF900h - 0xFFFFh) -- Switched between 5 banks
+
+-- 08 Green Leds Out (Port 0x01h)
+-- 08 Red Leds Out (Port 0x02h)
+-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
+-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
+------------- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
+
+-- 01 Uart0 In/Out (Port 0x24h)
+
+-- 01 Rom Switching Out (Port 0xDDh)
+-- 02 Rom Switching Out (Port 0xDDh)
+-- 03 Rom Switching Out (Port 0xDDh)
+
+-- 00 to 07 Ram Switching Out (Port 0xDCh)
+
+--PRF F0h
+--STATS,RTCIN F0h --Brown Out and Pwr Fail Stat 60Hz
+--PFKILL F1h
+--RTCRST F2h
+--SFTPRT F3h
+--MEXPON F4h
+--MEXPOFF F5h
+--IOXPON F6h
+--IOXPOFF F7h
+
+--EPPAGE1 FCh
+--EPPAGE2 FDh
+
+-- 08 Switches In (Port 0x20h)
+-- 04 Push buttons In (Port 0x30h)
+-- 01 PS/2 keyboard In (Port 0x80h)
+-- 01 Video write port In (Port 0x90h)
+
+--
+-- Revision history:
+--
+-- 2008/05/23 - Modified RAM layout to support new and future improvements
+-- - Added port 0x90 to write a character to video.
+-- - Cursor x,y automatically updated after writing to port 0x90
+-- - Added port 0x91 for video cursor X
+-- - Added port 0x92 for video cursor Y
+-- - Updated ROM to demonstrate how to use these new resources
+-- - Changed ROM to support 14 bit addresses (16 Kb)
+--
+-- 2008/05/12 - Added support for the Rotary Knob
+-- - ROT_CENTER push button (Knob) reserved for RESET
+-- - The four push buttons are now available for the user (Port 0x30)
+--
+-- 2008/05/11 - Fixed access to RAM and VRAM,
+-- Released same ROM version for DE1 and S3E
+--
+-- 2008/05/01 - Added LCD support for Spartan 3E
+--
+-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
+--
+-- 2008/04/17 - Added Video support for 40x30 mode
+--
+-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
+--
+-- TO-DO:
+-- - Implement hardware control for the A/D and IO pins
+-- - Monitor program to introduce Z80 Assmebly codes and run
+-- - Serial communication, to download assembly code from PC
+-- - Add hardware support for 80x40 Video out
+-- - SD/MMC card interface to read/store data and programs
+-------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity TOP_DE1 is
+ port(
+
+ -- Clocks
+ CLOCK_27, -- 27 MHz
+ CLOCK_50, -- 50 MHz
+ EXT_CLOCK : in std_logic; -- External Clock
+
+ -- Buttons and switches
+ KEY : in std_logic_vector(3 downto 0); -- Push buttons
+ SW : in std_logic_vector(9 downto 0); -- Switches
+
+ -- LED displays
+ HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
+ : out std_logic_vector(6 downto 0);
+ LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
+ LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
+
+ -- RS-232 interface
+ UART_TXD : out std_logic; -- UART transmitter
+ UART_RXD : in std_logic; -- UART receiver
+
+ -- IRDA interface
+
+ -- IRDA_TXD : out std_logic; -- IRDA Transmitter
+ IRDA_RXD : in std_logic; -- IRDA Receiver
+
+ -- SDRAM
+ DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
+ DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
+ DRAM_LDQM, -- Low-byte Data Mask
+ DRAM_UDQM, -- High-byte Data Mask
+ DRAM_WE_N, -- Write Enable
+ DRAM_CAS_N, -- Column Address Strobe
+ DRAM_RAS_N, -- Row Address Strobe
+ DRAM_CS_N, -- Chip Select
+ DRAM_BA_0, -- Bank Address 0
+ DRAM_BA_1, -- Bank Address 0
+ DRAM_CLK, -- Clock
+ DRAM_CKE : out std_logic; -- Clock Enable
+
+ -- FLASH
+ FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
+ FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
+ FL_WE_N : out std_logic; -- Write Enable
+ FL_RST_N : out std_logic; -- Reset
+ FL_OE_N : out std_logic; -- Output Enable
+ FL_CE_N : out std_logic; -- Chip Enable
+
+ -- SRAM
+ SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
+ SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
+ SRAM_UB_N : out std_logic; -- High-byte Data Mask
+ SRAM_LB_N : out std_logic; -- Low-byte Data Mask
+ SRAM_WE_N : out std_logic; -- Write Enable
+ SRAM_CE_N : out std_logic; -- Chip Enable
+ SRAM_OE_N : out std_logic; -- Output Enable
+
+ -- SD card interface
+ SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
+ SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
+ SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
+ SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
+
+ -- USB JTAG link
+ TDI, -- CPLD -> FPGA (data in)
+ TCK, -- CPLD -> FPGA (clk)
+ TCS : in std_logic; -- CPLD -> FPGA (CS)
+ TDO : out std_logic; -- FPGA -> CPLD (data out)
+
+ -- I2C bus
+ I2C_SDAT : inout std_logic; -- I2C Data
+ I2C_SCLK : out std_logic; -- I2C Clock
+
+ -- PS/2 port
+ PS2_DAT, -- Data
+ PS2_CLK : inout std_logic; -- Clock
+
+ -- VGA output
+ VGA_HS, -- H_SYNC
+ VGA_VS : out std_logic; -- SYNC
+ VGA_R, -- Red[3:0]
+ VGA_G, -- Green[3:0]
+ VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
+
+ -- Audio CODEC
+ AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
+ AUD_ADCDAT : in std_logic; -- ADC Data
+ AUD_DACLRCK : inout std_logic; -- DAC LR Clock
+ AUD_DACDAT : out std_logic; -- DAC Data
+ AUD_BCLK : inout std_logic; -- Bit-Stream Clock
+ AUD_XCK : out std_logic; -- Chip Clock
+
+ -- General-purpose I/O
+ GPIO_0, -- GPIO Connection 0
+ GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
+);
+end TOP_DE1;
+
+architecture rtl of TOP_DE1 is
+
+ component T80se
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CLKEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+
+
+ component Clock_357Mhz
+ PORT (
+ clock_50Mhz : IN STD_LOGIC;
+ clock_60hz : OUT STD_LOGIC;
+ clock_357Mhz : OUT STD_LOGIC);
+ end component;
+
+ component clk_div
+ PORT
+ (
+ clock_25Mhz : IN STD_LOGIC;
+ clock_1MHz : OUT STD_LOGIC;
+ clock_100KHz : OUT STD_LOGIC;
+ clock_10KHz : OUT STD_LOGIC;
+ clock_1KHz : OUT STD_LOGIC;
+ clock_100Hz : OUT STD_LOGIC;
+ clock_10Hz : OUT STD_LOGIC;
+ clock_1Hz : OUT STD_LOGIC;
+ clock_10sec : OUT STD_LOGIC;
+ clock_1min : OUT STD_LOGIC;
+ clock_1hr : OUT STD_LOGIC);
+ end component;
+
+ component decoder_7seg
+ port (
+ NUMBER : in std_logic_vector(3 downto 0);
+ HEX_DISP : out std_logic_vector(6 downto 0));
+ end component;
+
+
+
+ COMPONENT miniUART
+ PORT (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+ END COMPONENT;
+
+
+ --component led_driver
+ --port (
+ -- ENABLE : in std_logic;
+ -- BYTE : in std_logic_vector(7 downto 0);
+ -- LEDBYTE : out std_logic_vector(7 downto 0));
+ --end component;
+
+
+
+
+ signal INT_n : std_logic;
+ signal M1_n : std_logic;
+ signal MREQ_n : std_logic;
+ signal IORQ_n : std_logic;
+ signal RD_n : std_logic;
+ signal WR_n : std_logic;
+ signal Rst_n_s : std_logic;
+
+ signal Clk_Z80 : std_logic;
+ signal Clk_357Mhz : std_logic;
+
+ signal DI_CPU : std_logic_vector(7 downto 0);
+ signal DO_CPU : std_logic_vector(7 downto 0);
+ signal A : std_logic_vector(15 downto 0);
+ signal One : std_logic;
+
+
+ signal D_ROM : std_logic_vector(7 downto 0);
+
+ signal clk25mhz : std_logic;
+ signal clk1hz : std_logic;
+ signal clk10hz : std_logic;
+ signal clk100hz : std_logic;
+ signal clk10sec : std_logic;
+ signal Clk_60hz : std_logic;
+
+ signal HEX_DISP0 : std_logic_vector(6 downto 0);
+ signal HEX_DISP1 : std_logic_vector(6 downto 0);
+ signal HEX_DISP2 : std_logic_vector(6 downto 0);
+ signal HEX_DISP3 : std_logic_vector(6 downto 0);
+
+ signal NUMBER0 : std_logic_vector(3 downto 0);
+ signal NUMBER1 : std_logic_vector(3 downto 0);
+ signal NUMBER2 : std_logic_vector(3 downto 0);
+ signal NUMBER3 : std_logic_vector(3 downto 0);
+
+
+ signal uart0_CS : std_Logic;
+ signal uart0_RD : std_Logic;
+ signal uart0_WR : std_Logic;
+ signal uart0_RxInt : std_Logic;
+ signal uart0_TxInt : std_Logic;
+ signal uart0_Addr : std_Logic_Vector(1 downto 0);
+ signal uart0_DataIn : std_Logic_Vector(7 downto 0);
+ signal uart0_DataOut : std_logic_Vector(7 downto 0);
+
+ signal IntVector : std_logic_Vector(7 downto 0);
+
+ signal Z80_RAM_ADR : Std_Logic_Vector(15 downto 0);
+
+ signal Z80_RAM_A12 : Std_Logic;
+ signal Z80_RAM_A13 : Std_Logic;
+ signal Z80_RAM_A14 : Std_Logic;
+ signal Z80_RAM_CE : Std_Logic;
+ signal Z80_RAM_OE : Std_Logic;
+ signal Z80_RAM_WE : Std_Logic;
+
+ signal Z80_EE_A15 : Std_Logic;
+ signal Z80_EE_A16 : Std_Logic;
+ signal Z80_EE_0E : Std_Logic;
+ signal Z80_EE_WE : Std_Logic;
+ signal Z80_EE_CE : Std_Logic;
+
+ signal Z80_ROM_CE : Std_Logic;
+
+ signal TestBit : Std_Logic;
+
+ signal LEDRED : std_logic_Vector(7 downto 0);
+
+
+begin
+ Rst_n_s <= not SW(9); -- Switch 9 toggles Reset on z80
+
+ HEX0 <= HEX_DISP0; -- Move Signal to Output Pins
+ HEX1 <= HEX_DISP1; -- Move Signal to Output Pins
+ HEX2 <= HEX_DISP2; -- Move Signal to Output Pins
+ HEX3 <= HEX_DISP3; -- Move Signal to Output Pins
+
+
+ -- SRAM control signals
+ SRAM_ADDR(15 downto 0) <= A - x"C000" when (A >= x"C000" and MREQ_n = '0');
+ SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= x"C000") else (others => 'Z');
+ SRAM_WE_N <= Wr_n or MREQ_n when A >= x"C000";
+ SRAM_OE_N <= Rd_n or MREQ_n when A >= x"C000";
+
+
+
+
+ -- FLASH control signals
+ FL_ADDR(15 downto 0) <= A when (A < x"A000" and MREQ_n = '0');
+ --FL_DQ <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A < x"A000") else (others => 'Z'); --this deltate
+ --D_ROM(7 downto 0) <= FL_DQ;
+ FL_WE_N <= Wr_n; -- Write Enable -- this make '1'
+ FL_OE_N <= Rd_n; -- Output Enable
+
+ FL_CE_N <= MREQ_n when A < x"A000"; -- Chip Enable works
+
+
+
+
+
+ --1FFFH is used for unlocking stuff
+
+ -- UART control signals
+ uart0_CS <= IORQ_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_RD <= Rd_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_WR <= Wr_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
+ uart0_Addr <= b"00";
+
+
+
+ ----------------------------------------------
+ --Z80 Interrupt Vectors
+ -- IBMVECT
+ --0040 AA1C DW COMMBOUT ;CHAN-B TRANSMIT BUFFER EMPTY
+ --0042 101B DW COMBCLI ;BSTATUS
+ --0044 F21C DW COMMBIN ;BRECEIVE
+ --0046 FF1A DW COMBCLII ;BEXTINT
+ --0048 281C DW COMMAOUT ;ATRBMTY
+ --004A 691C DW COMACLI ;WAS CRTEXINT ;ASTATUS
+ --004C 2F1B DW COMMAIN ;WAS CRTINP ;ARECEIVE
+ --004E 971C DW COMACLII ;WAS CRTEXIN? ;AEXTINT
+ IntVector(7 downto 0) <= x"4C" when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1');
+ ----------------------------------------------------------
+
+
+ DI_CPU <=
+
+ SRAM_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"C000") else
+
+ --Input ROM Code
+ FL_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"A000") else
+
+ --Z80 IN command to input UART0
+ uart0_DataIn(7 downto 0) when (Rd_n = '0' and MREQ_n = '1' and IORQ_n = '0' and A(7 downto 0) = x"24") else
+
+ IntVector(7 downto 0) when (MREQ_n = '1' and IORQ_n = '0' and M1_n = '0' and uart0_RxInt = '1') else -- After pulling int_n low serial interrupt input
+
+ "ZZZZZZZZ";
+
+
+
+
+
+ -- Process to latch z80 OUT instruction
+ pinout_process: process(Clk_Z80)
+ variable NUMBER0_sig : std_logic_vector(3 downto 0);
+ variable NUMBER1_sig : std_logic_vector(3 downto 0);
+ variable NUMBER2_sig : std_logic_vector(3 downto 0);
+ variable NUMBER3_sig : std_logic_vector(3 downto 0);
+ variable LEDR_sig : std_logic_vector(9 downto 0);
+ variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
+ variable uart0_buf_DataOut: std_logic_vector(7 downto 0);
+ --variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
+ begin
+ if Clk_Z80'event and Clk_Z80 = '1' then
+ if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
+
+ -- LEDR
+ if A(7 downto 0) = x"02" then
+ LEDR_sig(7 downto 0) := DO_CPU;
+
+ -- HEX1 and HEX0
+ elsif A(7 downto 0) = x"10" then
+ NUMBER0_sig := DO_CPU(3 downto 0);
+ NUMBER1_sig := DO_CPU(7 downto 4);
+
+ -- HEX3 and HEX2
+ elsif A(7 downto 0) = x"11" then
+ NUMBER2_sig := DO_CPU(3 downto 0);
+ NUMBER3_sig := DO_CPU(7 downto 4);
+
+ elsif A(7 downto 0) = x"24" then
+ uart0_buf_DataOut := DO_CPU; --load data to uart output buffer
+
+ end if;
+ end if;
+ end if;
+ -- Latches the signals
+ NUMBER0 <= NUMBER0_sig;
+ NUMBER1 <= NUMBER1_sig;
+ NUMBER2 <= NUMBER2_sig;
+ NUMBER3 <= NUMBER3_sig;
+ --LEDR(7 downto 0) <= LEDR_sig(7 downto 0);
+ LEDRED <= LEDR_sig(7 downto 0);
+ uart0_DataOut <= uart0_buf_DataOut;
+ end process;
+
+ One <= '1';
+ z80_inst: T80se
+ port map (
+ M1_n => M1_n,
+ MREQ_n => MREQ_n,
+ IORQ_n => IORQ_n,
+ RD_n => Rd_n,
+ WR_n => Wr_n,
+ RFSH_n => open,
+ HALT_n => open,
+ WAIT_n => One,
+ INT_n => INT_n,
+ NMI_n => clk1hz, --Clk_60hz,
+ RESET_n => Rst_n_s,
+ BUSRQ_n => One,
+ BUSAK_n => open,
+ CLK_n => Clk_Z80,
+ CLKEN => One,
+ A => A,
+ DI => DI_CPU,
+ DO => DO_CPU
+ );
+
+
+ clkdiv_inst: clk_div
+ port map (
+ clock_25Mhz => CLOCK_27,
+ clock_1MHz => open,
+ clock_100KHz => open,
+ clock_10KHz => open,
+ clock_1KHz => open,
+ clock_100Hz => clk100hz,
+ clock_10Hz => clk10hz,
+ clock_1Hz => clk1hz,
+ clock_10sec => clk10sec,
+ clock_1min => open,
+ clock_1hr => open
+ );
+
+
+
+ clock_z80_inst : Clock_357Mhz
+ port map (
+ clock_50Mhz => CLOCK_50,
+ clock_60hz => Clk_60hz,
+ clock_357Mhz => Clk_Z80
+ );
+
+
+
+ DISPHEX0 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER0,
+ HEX_DISP => HEX_DISP0
+ );
+ DISPHEX1 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER1,
+ HEX_DISP => HEX_DISP1
+ );
+ DISPHEX2 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER2,
+ HEX_DISP => HEX_DISP2
+ );
+ DISPHEX3 : decoder_7seg PORT MAP (
+ NUMBER => NUMBER3,
+ HEX_DISP => HEX_DISP3
+ );
+
+
+
+ U1 : miniUART PORT MAP (
+ SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
+ Reset => Key(0), --: in Std_Logic; -- Reset input
+ CS_N => uart0_cs, --: in Std_Logic;
+ RD_N => uart0_Rd, --: in Std_Logic;
+ WR_N => uart0_Wr, --: in Std_Logic;
+ RxD => UART_RXD, --: in Std_Logic;
+ TxD => UART_TXD, --: out Std_Logic;
+ IntRx_N => uart0_RxInt, --: out Std_Logic; -- Received Byte
+ IntTx_N => uart0_TxInt, --: out Std_Logic; -- Transmit Buffer Empty
+ Addr => uart0_Addr, --: in Std_Logic_Vector(1 downto 0); --
+ DataIn => uart0_DataOut, --: in Std_Logic_Vector(7 downto 0); --
+ DataOut => uart0_DataIn --: out Std_Logic_Vector(7 downto 0)); --
+ );
+
+
+ --u2: led_driver
+ --port map (
+ -- ENABLE => (IORQ_n and Wr_n),
+ -- BYTE => LEDRED, --: in std_logic_vector(7 downto 0);
+ -- LEDBYTE => LEDR(7 downto 0) --: out std_logic_vector(7 downto 0)
+ --);
+
+ --LEDR(0) <= '1' when LEDRED(0) = '1' else '0';
+ --LEDR(1) <= '1' when LEDRED(1) = '1' else '0';
+ --LEDR(2) <= '1' when LEDRED(2) = '1' else '0';
+ --LEDR(3) <= '1' when LEDRED(3) = '1' else '0';
+ --LEDR(4) <= '1' when LEDRED(4) = '1' else '0';
+ --LEDR(5) <= '1' when LEDRED(5) = '1' else '0';
+ --LEDR(6) <= '1' when LEDRED(6) = '1' else '0';
+ --LEDR(7) <= '1' when LEDRED(7) = '1' else '0';
+
+
+ INT_n <= '0' when uart0_RxInt ='1' else '1';
+
+ --INT_n <= not uart0_RxInt;
+
+ --TestBit <= uart0_TxInt;
+
+
+ LEDG(0) <= uart0_RxInt; -- block and no run
+ LEDG(1) <= uart0_TxInt; -- block and no run
+ --uart0_TxInt <= 'Z'; no run instead of block
+ --LEDG(1) <= TestBit; --why does uart0_TxInt need to be connected to led???????
+
+ --LEDG(2) <= '1';
+ LEDG(5) <= INT_n;
+ --LEDG(6) <= clk10sec;
+ --LEDG(7) <= clk1hz;
+
+ --LEDR(9 downto 0) <= b"0101010101";
+
+ FL_RST_N <= '1'; -- Reset
+ FL_ADDR(21 downto 16) <= b"000000";
+
+ SRAM_DQ(15 downto 8) <= (others => 'Z');
+ SRAM_ADDR(17 downto 16) <= "00";
+ SRAM_UB_N <= '1';
+ SRAM_LB_N <= '0';
+ SRAM_CE_N <= '0';
+
+ --
+ UART_TXD <= 'Z';
+ DRAM_ADDR <= (others => '0');
+ DRAM_LDQM <= '0';
+ DRAM_UDQM <= '0';
+ DRAM_WE_N <= '1';
+ DRAM_CAS_N <= '1';
+ DRAM_RAS_N <= '1';
+ DRAM_CS_N <= '1';
+ DRAM_BA_0 <= '0';
+ DRAM_BA_1 <= '0';
+ DRAM_CLK <= '0';
+ DRAM_CKE <= '0';
+ TDO <= '0';
+ I2C_SCLK <= '0';
+ AUD_DACDAT <= '0';
+ AUD_XCK <= '0';
+ -- Set all bidirectional ports to tri-state
+ DRAM_DQ <= (others => 'Z');
+
+ I2C_SDAT <= 'Z';
+ AUD_ADCLRCK <= 'Z';
+ AUD_DACLRCK <= 'Z';
+ AUD_BCLK <= 'Z';
+ GPIO_0 <= (others => 'Z');
+ GPIO_1 <= (others => 'Z');
+
+
+ VGA_HS <= '0';
+ VGA_VS <= '0';
+ VGA_R(3 downto 0) <= b"0000";
+ VGA_G(3 downto 0) <= b"0000";
+ VGA_B(3 downto 0) <= b"0000";
+
+end;
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd.bak (revision 6)
@@ -0,0 +1,28 @@
+entity SEG7_LUT ( oSEG,iDIG );
+input [3:0] iDIG;
+output [6:0] oSEG;
+reg [6:0] oSEG;
+
+always @(iDIG)
+begin
+ case(iDIG)
+ 4'h1: oSEG = 7'b1111001; // ---t----
+ 4'h2: oSEG = 7'b0100100; // | |
+ 4'h3: oSEG = 7'b0110000; // lt rt
+ 4'h4: oSEG = 7'b0011001; // | |
+ 4'h5: oSEG = 7'b0010010; // ---m----
+ 4'h6: oSEG = 7'b0000010; // | |
+ 4'h7: oSEG = 7'b1111000; // lb rb
+ 4'h8: oSEG = 7'b0000000; // | |
+ 4'h9: oSEG = 7'b0011000; // ---b----
+ 4'ha: oSEG = 7'b0001000;
+ 4'hb: oSEG = 7'b0000011;
+ 4'hc: oSEG = 7'b1000110;
+ 4'hd: oSEG = 7'b0100001;
+ 4'he: oSEG = 7'b0000110;
+ 4'hf: oSEG = 7'b0001110;
+ 4'h0: oSEG = 7'b1000000;
+ endcase
+end
+
+endmodule
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.dpf
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.dpf (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.dpf (revision 6)
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.logdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.logdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.logdb (revision 6)
@@ -0,0 +1 @@
+v1
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.cdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry.sci
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry.sci
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry.sci (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry.sci (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry.sci
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.cdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.qmsg (revision 6)
@@ -0,0 +1,98 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 16 19:25:40 2010 " "Info: Processing started: Sat Jan 16 19:25:40 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder_7seg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder_7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder_7seg-rtl " "Info: Found design unit 1: decoder_7seg-rtl" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 13 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 decoder_7seg " "Info: Found entity 1: decoder_7seg" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-Behaviour " "Info: Found design unit 1: UART-Behaviour" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 57 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 36 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClkUnit-Behaviour " "Info: Found design unit 1: ClkUnit-Behaviour" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 52 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 ClkUnit " "Info: Found entity 1: ClkUnit" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 42 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "miniUART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file miniUART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 miniUART-uart " "Info: Found design unit 1: miniUART-uart" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 63 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 miniUART " "Info: Found entity 1: miniUART" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 45 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RxUnit-Behaviour " "Info: Found design unit 1: RxUnit-Behaviour" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 58 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 RxUnit " "Info: Found entity 1: RxUnit" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 43 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top_uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TOP_UART-rtl " "Info: Found design unit 1: TOP_UART-rtl" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 109 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TOP_UART " "Info: Found entity 1: TOP_UART" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 10 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TxUnit-Behaviour " "Info: Found design unit 1: TxUnit-Behaviour" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 55 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TxUnit " "Info: Found entity 1: TxUnit" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 41 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_lib.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_Def " "Info: Found design unit 1: UART_Def" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 35 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_Def-body " "Info: Found design unit 2: UART_Def-body" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 45 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top_uart " "Info: Elaborating entity \"top_uart\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX0 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX0\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX1 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX2 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX2\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX3 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_WE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_WE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_OE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_OE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_DAT3 top_uart.vhd(70) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(70): used implicit default value for signal \"SD_DAT3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CMD top_uart.vhd(71) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(71): used implicit default value for signal \"SD_CMD\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CLK top_uart.vhd(72) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(72): used implicit default value for signal \"SD_CLK\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_HS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_HS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_VS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_VS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_R top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_R\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_G top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_G\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_B top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_B\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[7\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[7\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[6\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[6\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[5\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[5\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[4\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[4\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[3\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[3\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[2\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[2\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[9\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[9\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[8\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[8\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[15\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[15\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[14\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[14\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[13\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[13\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[12\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[12\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[11\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[11\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[10\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[10\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[9\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[9\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[8\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[8\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[7\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[7\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[6\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[6\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[5\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[5\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[4\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[4\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[3\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[3\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[2\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[2\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[1\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[1\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[0\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[0\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "miniUART miniUART:U1 " "Info: Elaborating entity \"miniUART\" for hierarchy \"miniUART:U1\"" { } { { "top_uart.vhd" "U1" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"WR_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(190) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(190): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 190 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RxData miniUART.vhd(193) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(193): signal \"RxData\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 193 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CSReg miniUART.vhd(195) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(195): signal \"CSReg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 195 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(198) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(198): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 198 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DataIn miniUART.vhd(201) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(201): signal \"DataIn\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 201 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataOut miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"DataOut\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TxData miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"TxData\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClkUnit miniUART:U1\|ClkUnit:ClkDiv " "Info: Elaborating entity \"ClkUnit\" for hierarchy \"miniUART:U1\|ClkUnit:ClkDiv\"" { } { { "miniUART.vhd" "ClkDiv" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 127 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TxUnit miniUART:U1\|TxUnit:TxDev " "Info: Elaborating entity \"TxUnit\" for hierarchy \"miniUART:U1\|TxUnit:TxDev\"" { } { { "miniUART.vhd" "TxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 128 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RxUnit miniUART:U1\|RxUnit:RxDev " "Info: Elaborating entity \"RxUnit\" for hierarchy \"miniUART:U1\|RxUnit:RxDev\"" { } { { "miniUART.vhd" "RxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[0\]~6 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[0\]~6\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[1\]~7 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[1\]~7\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[2\]~5 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[2\]~5\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[3\]~4 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[3\]~4\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[4\]~3 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[4\]~3\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[5\]~2 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[5\]~2\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[6\]~1 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[6\]~1\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[7\]~0 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[7\]~0\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} } { } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 0 " "Warning: Ignored assignment(s) for \"CLOCK_27\[0\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 1 " "Warning: Ignored assignment(s) for \"CLOCK_27\[1\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "UART_TXD " "Warning: Inserted always-enabled tri-state buffer between \"UART_TXD\" and its non-tri-state driver." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} } { } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[0\] " "Warning: Bidir \"SRAM_DQ\[0\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[1\] " "Warning: Bidir \"SRAM_DQ\[1\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[2\] " "Warning: Bidir \"SRAM_DQ\[2\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[3\] " "Warning: Bidir \"SRAM_DQ\[3\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[4\] " "Warning: Bidir \"SRAM_DQ\[4\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[5\] " "Warning: Bidir \"SRAM_DQ\[5\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[6\] " "Warning: Bidir \"SRAM_DQ\[6\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[7\] " "Warning: Bidir \"SRAM_DQ\[7\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_DAT " "Warning: Bidir \"PS2_DAT\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_CLK " "Warning: Bidir \"PS2_CLK\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} } { } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS_HDR" "" "Warning: Removed fan-outs from the following always-disabled I/O buffers" { { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "UART_TXD UART_TXD " "Warning: Removed fan-out from the always-disabled I/O buffer \"UART_TXD\" to the node \"UART_TXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Removed fan-outs from the following always-disabled I/O buffers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[0\] GND " "Warning (13410): Pin \"HEX0\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[1\] GND " "Warning (13410): Pin \"HEX0\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[2\] GND " "Warning (13410): Pin \"HEX0\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[3\] GND " "Warning (13410): Pin \"HEX0\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[4\] GND " "Warning (13410): Pin \"HEX0\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[5\] GND " "Warning (13410): Pin \"HEX0\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[6\] GND " "Warning (13410): Pin \"HEX0\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[0\] GND " "Warning (13410): Pin \"HEX1\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[1\] GND " "Warning (13410): Pin \"HEX1\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[2\] GND " "Warning (13410): Pin \"HEX1\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[3\] GND " "Warning (13410): Pin \"HEX1\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[4\] GND " "Warning (13410): Pin \"HEX1\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[5\] GND " "Warning (13410): Pin \"HEX1\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[6\] GND " "Warning (13410): Pin \"HEX1\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[0\] GND " "Warning (13410): Pin \"HEX2\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[1\] GND " "Warning (13410): Pin \"HEX2\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[2\] GND " "Warning (13410): Pin \"HEX2\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[3\] GND " "Warning (13410): Pin \"HEX2\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[4\] GND " "Warning (13410): Pin \"HEX2\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[5\] GND " "Warning (13410): Pin \"HEX2\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[6\] GND " "Warning (13410): Pin \"HEX2\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[0\] GND " "Warning (13410): Pin \"HEX3\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[1\] GND " "Warning (13410): Pin \"HEX3\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[2\] GND " "Warning (13410): Pin \"HEX3\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[3\] GND " "Warning (13410): Pin \"HEX3\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[4\] GND " "Warning (13410): Pin \"HEX3\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[5\] GND " "Warning (13410): Pin \"HEX3\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[6\] GND " "Warning (13410): Pin \"HEX3\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[2\] GND " "Warning (13410): Pin \"LEDG\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[3\] GND " "Warning (13410): Pin \"LEDG\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[4\] GND " "Warning (13410): Pin \"LEDG\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[5\] GND " "Warning (13410): Pin \"LEDG\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[6\] GND " "Warning (13410): Pin \"LEDG\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[7\] GND " "Warning (13410): Pin \"LEDG\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[8\] GND " "Warning (13410): Pin \"LEDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[9\] GND " "Warning (13410): Pin \"LEDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[0\] GND " "Warning (13410): Pin \"DRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[1\] GND " "Warning (13410): Pin \"DRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[2\] GND " "Warning (13410): Pin \"DRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[3\] GND " "Warning (13410): Pin \"DRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[4\] GND " "Warning (13410): Pin \"DRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[5\] GND " "Warning (13410): Pin \"DRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[6\] GND " "Warning (13410): Pin \"DRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[7\] GND " "Warning (13410): Pin \"DRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[8\] GND " "Warning (13410): Pin \"DRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[9\] GND " "Warning (13410): Pin \"DRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[10\] GND " "Warning (13410): Pin \"DRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[11\] GND " "Warning (13410): Pin \"DRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_LDQM GND " "Warning (13410): Pin \"DRAM_LDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_UDQM GND " "Warning (13410): Pin \"DRAM_UDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_WE_N VCC " "Warning (13410): Pin \"DRAM_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CAS_N VCC " "Warning (13410): Pin \"DRAM_CAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_RAS_N VCC " "Warning (13410): Pin \"DRAM_RAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CS_N VCC " "Warning (13410): Pin \"DRAM_CS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_0 GND " "Warning (13410): Pin \"DRAM_BA_0\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_1 GND " "Warning (13410): Pin \"DRAM_BA_1\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CLK GND " "Warning (13410): Pin \"DRAM_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CKE GND " "Warning (13410): Pin \"DRAM_CKE\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[0\] GND " "Warning (13410): Pin \"FL_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[1\] GND " "Warning (13410): Pin \"FL_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[2\] GND " "Warning (13410): Pin \"FL_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[3\] GND " "Warning (13410): Pin \"FL_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[4\] GND " "Warning (13410): Pin \"FL_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[5\] GND " "Warning (13410): Pin \"FL_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[6\] GND " "Warning (13410): Pin \"FL_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[7\] GND " "Warning (13410): Pin \"FL_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[8\] GND " "Warning (13410): Pin \"FL_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[9\] GND " "Warning (13410): Pin \"FL_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[10\] GND " "Warning (13410): Pin \"FL_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[11\] GND " "Warning (13410): Pin \"FL_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[12\] GND " "Warning (13410): Pin \"FL_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[13\] GND " "Warning (13410): Pin \"FL_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[14\] GND " "Warning (13410): Pin \"FL_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[15\] GND " "Warning (13410): Pin \"FL_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[16\] GND " "Warning (13410): Pin \"FL_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[17\] GND " "Warning (13410): Pin \"FL_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[18\] GND " "Warning (13410): Pin \"FL_ADDR\[18\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[19\] GND " "Warning (13410): Pin \"FL_ADDR\[19\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[20\] GND " "Warning (13410): Pin \"FL_ADDR\[20\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[21\] GND " "Warning (13410): Pin \"FL_ADDR\[21\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_WE_N VCC " "Warning (13410): Pin \"FL_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_RST_N GND " "Warning (13410): Pin \"FL_RST_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_OE_N VCC " "Warning (13410): Pin \"FL_OE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_CE_N VCC " "Warning (13410): Pin \"FL_CE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[0\] GND " "Warning (13410): Pin \"SRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[1\] GND " "Warning (13410): Pin \"SRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[2\] GND " "Warning (13410): Pin \"SRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[3\] GND " "Warning (13410): Pin \"SRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[4\] GND " "Warning (13410): Pin \"SRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[5\] GND " "Warning (13410): Pin \"SRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[6\] GND " "Warning (13410): Pin \"SRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[7\] GND " "Warning (13410): Pin \"SRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[8\] GND " "Warning (13410): Pin \"SRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[9\] GND " "Warning (13410): Pin \"SRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[10\] GND " "Warning (13410): Pin \"SRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[11\] GND " "Warning (13410): Pin \"SRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[12\] GND " "Warning (13410): Pin \"SRAM_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[13\] GND " "Warning (13410): Pin \"SRAM_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[14\] GND " "Warning (13410): Pin \"SRAM_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[15\] GND " "Warning (13410): Pin \"SRAM_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[16\] GND " "Warning (13410): Pin \"SRAM_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[17\] GND " "Warning (13410): Pin \"SRAM_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_UB_N VCC " "Warning (13410): Pin \"SRAM_UB_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_LB_N GND " "Warning (13410): Pin \"SRAM_LB_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_WE_N GND " "Warning (13410): Pin \"SRAM_WE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_CE_N GND " "Warning (13410): Pin \"SRAM_CE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_OE_N GND " "Warning (13410): Pin \"SRAM_OE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_DAT3 GND " "Warning (13410): Pin \"SD_DAT3\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CMD GND " "Warning (13410): Pin \"SD_CMD\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CLK GND " "Warning (13410): Pin \"SD_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TDO GND " "Warning (13410): Pin \"TDO\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_HS GND " "Warning (13410): Pin \"VGA_HS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_VS GND " "Warning (13410): Pin \"VGA_VS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Warning (13410): Pin \"VGA_R\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Warning (13410): Pin \"VGA_R\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[2\] GND " "Warning (13410): Pin \"VGA_R\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[3\] GND " "Warning (13410): Pin \"VGA_R\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Warning (13410): Pin \"VGA_G\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Warning (13410): Pin \"VGA_G\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Warning (13410): Pin \"VGA_G\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Warning (13410): Pin \"VGA_G\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Warning (13410): Pin \"VGA_B\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Warning (13410): Pin \"VGA_B\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Warning (13410): Pin \"VGA_B\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Warning (13410): Pin \"VGA_B\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_DACDAT GND " "Warning (13410): Pin \"AUD_DACDAT\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_XCK GND " "Warning (13410): Pin \"AUD_XCK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "UART " "Warning: Ignored assignments for entity \"UART\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "16 " "Warning: Design contains 16 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_27 " "Warning (15610): No output dependent on input pin \"CLOCK_27\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "EXT_CLOCK " "Warning (15610): No output dependent on input pin \"EXT_CLOCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 16 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning (15610): No output dependent on input pin \"SW\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "IRDA_RXD " "Warning (15610): No output dependent on input pin \"IRDA_RXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SD_DAT " "Warning (15610): No output dependent on input pin \"SD_DAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TDI " "Warning (15610): No output dependent on input pin \"TDI\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 75 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCK " "Warning (15610): No output dependent on input pin \"TCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 76 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCS " "Warning (15610): No output dependent on input pin \"TCS\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 77 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_ADCDAT " "Warning (15610): No output dependent on input pin \"AUD_ADCDAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 97 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "451 " "Info: Implemented 451 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Info: Implemented 24 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "139 " "Info: Implemented 139 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "118 " "Info: Implemented 118 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "170 " "Info: Implemented 170 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 230 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 230 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Peak virtual memory: 195 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 16 19:25:45 2010 " "Info: Processing ended: Sat Jan 16 19:25:45 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.hdb
===================================================================
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svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.hdb
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## -0,0 +1 ##
+application/octet-stream
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.cdb
===================================================================
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svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.cdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.hdb
===================================================================
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svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.hdb
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\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.txt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.txt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.txt (revision 6)
@@ -0,0 +1,10 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; U1|RxDev ; 5 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; U1|TxDev ; 12 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; U1|ClkDiv ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; U1 ; 16 ; 8 ; 0 ; 8 ; 11 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate_sm.rvd
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate_sm.rvd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate_sm.rvd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate_sm.rvd (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate_sm.rvd
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry_dsc.sci
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry_dsc.sci
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry_dsc.sci (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry_dsc.sci (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sld_design_entry_dsc.sci
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.kpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.kpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.kpt (revision 6)
@@ -0,0 +1,1330 @@
+
+
+
+ U1/RxDev/BitCnt[0]
+
+
+ U1/TxDev/TBuff[7]
+
+ SA0
+
+
+
+ U1/RxDev/tmpRxD
+
+
+ U1/TxDev/TReg[6]
+
+
+ U1/RxDev/ShtReg[0]
+
+
+ U1/TxDev/TBuff[3]
+
+
+ U1/CSReg[0]
+
+ SA0
+
+
+
+ U1/CSReg[4]
+
+ SA1
+
+
+
+ U1/RxDev/ShtReg[4]
+
+
+ U1/ClkDiv/DivClk10:Cnt10[3]
+
+
+ U1/TxDev/TxD
+
+
+ U1/RxDev/Start
+
+
+ U1/TxDev/TReg[1]
+
+
+ U1/RxDev/DOut[4]
+
+
+ U1/TxDev/BitCnt[2]
+
+
+ U1/RxDev/SampleCnt[1]
+
+
+ U1/TxDev/tmpTBufE
+
+
+ U1/ClkDiv/DivClk26:Cnt26[3]
+
+
+ U1/RxDev/outErr
+
+
+ U1/TxDev/tmpTRegE
+
+
+ U1/TxDev/TBuff[6]
+
+
+ U1/TxDev/TReg[5]
+
+
+ U1/RxDev/BitCnt[3]
+
+
+ U1/RxDev/ShtReg[7]
+
+
+ U1/IntTx_N
+
+
+ U1/CSReg[7]
+
+ SA1
+
+
+
+ U1/CSReg[3]
+
+
+ U1/TxDev/TBuff[2]
+
+ SA0
+
+
+
+ U1/ClkDiv/DivClk10:Cnt10[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[0]
+
+
+ U1/RxDev/ShtReg[3]
+
+
+ U1/ClkDiv/tmpEnRX
+
+
+ U1/RxDev/DOut[0]
+
+
+ U1/IntRx_N
+
+
+ U1/TxDev/TReg[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[3]
+
+
+ U1/TxDev/BitCnt[3]
+
+
+ U1/RxDev/SampleCnt[2]
+
+
+ U1/RxDev/DOut[3]
+
+
+ U1/ClkDiv/ClkDiv26
+
+
+ U1/ClkDiv/DivClk26:Cnt26[0]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[4]
+
+
+ U1/RxDev/tmpDRdy
+
+
+ U1/RxDev/DOut[7]
+
+
+ U1/RxDev/BitCnt[2]
+
+
+ U1/RxDev/ShtReg[6]
+
+
+ U1/TxDev/TReg[4]
+
+
+ U1/RxDev/frameErr
+
+
+ U1/CSReg[6]
+
+ SA1
+
+
+
+ U1/TxDev/TBuff[5]
+
+
+ U1/CSReg[2]
+
+
+ U1/TxDev/TReg[7]
+
+
+ U1/ClkDiv/DivClk10:Cnt10[1]
+
+
+ U1/RxDev/ShtReg[2]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[1]
+
+
+ U1/TxDev/TBuff[1]
+
+ SA0
+
+
+
+ U1/ClkDiv/DivClk26:Cnt26[5]
+
+
+ U1/RxDev/DOut[1]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[4]
+
+
+ U1/TxDev/BitCnt[0]
+
+
+ U1/RxDev/DOut[6]
+
+
+ U1/RxDev/DOut[2]
+
+
+ U1/RxDev/SampleCnt[3]
+
+
+ U1/RxDev/BitCnt[1]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[1]
+
+
+ U1/RxDev/ShtReg[5]
+
+
+ U1/TxDev/TReg[3]
+
+
+ U1/ClkDiv/tmpEnTX
+
+
+ U1/TxDev/TBuff[4]
+
+ SA0
+
+
+
+ U1/CSReg[5]
+
+ SA1
+
+
+
+ U1/ClkDiv/DivClk10:Cnt10[2]
+
+
+ U1/CSReg[1]
+
+ SA0
+
+
+
+ U1/RxDev/ShtReg[1]
+
+
+ U1/TxDev/TBuff[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[2]
+
+
+ U1/TxDev/TReg[2]
+
+
+ U1/TxDev/BitCnt[1]
+
+
+ U1/RxDev/DOut[5]
+
+
+ U1/RxDev/SampleCnt[0]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[2]
+
+
+
+
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[2]
+
+
+ miniUART:U1|RxUnit:RxDev|outErr
+
+
+ miniUART:U1|CSReg[2]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[5]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[5]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[2]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[0]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[3]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[3]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1]
+
+
+ miniUART:U1|TxUnit:TxDev|tmpTBufE
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[0]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[2]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[2]
+
+
+ miniUART:U1|IntRx_N
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[4]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[3]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[5]
+
+
+ miniUART:U1|TxUnit:TxDev|tmpTRegE
+
+
+ miniUART:U1|RxUnit:RxDev|frameErr
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[6]
+
+
+ miniUART:U1|IntTx_N
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[4]
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[0]
+
+
+ miniUART:U1|RxUnit:RxDev|tmpDRdy
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[1]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[0]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[3]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[7]
+
+
+ miniUART:U1|RxUnit:RxDev|tmpRxD
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|ClkDiv26
+
+
+ miniUART:U1|TxUnit:TxDev|TxD
+
+
+ miniUART:U1|ClkUnit:ClkDiv|tmpEnTX
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[1]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[6]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[7]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[5]
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[3]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[0]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[7]
+
+
+ miniUART:U1|CSReg[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[6]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[3]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[6]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[2]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[3]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|tmpEnRX
+
+
+ miniUART:U1|RxUnit:RxDev|Start
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[4]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[4]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[3]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[1]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[2]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[0]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[0]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[5]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[1]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[4]
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
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+
+
+
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+
+
+
+
+
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+
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+
+
+
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+
+
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+
+
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+
+
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+
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+
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+
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+
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+
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+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cbx.xml
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cbx.xml (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cbx.xml (revision 6)
@@ -0,0 +1,5 @@
+
+
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.kpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.kpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.kpt (revision 6)
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.tan.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.tan.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.tan.qmsg (revision 6)
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:21:40 2010 " "Info: Processing started: Sun Jan 10 17:21:40 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[0\] " "Warning: Node \"miniUART:U1\|TxData\[0\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[3\] " "Warning: Node \"miniUART:U1\|TxData\[3\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[5\] " "Warning: Node \"miniUART:U1\|TxData\[5\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[6\] " "Warning: Node \"miniUART:U1\|TxData\[6\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[0\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]_240 " "Warning: Node \"miniUART:U1\|DataOut\[0\]_240\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[1\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[1\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[2\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[2\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[3\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[3\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[4\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[4\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[5\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[5\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[6\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[6\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[7\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[7\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[8\] " "Info: Assuming node \"SW\[8\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] register miniUART:U1\|RxUnit:RxDev\|frameErr 226.81 MHz 4.409 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 226.81 MHz between source register \"miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]\" and destination register \"miniUART:U1\|RxUnit:RxDev\|frameErr\" (period= 4.409 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.166 ns + Longest register register " "Info: + Longest register to register delay is 4.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LCFF_X39_Y14_N25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.513 ns) 0.908 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LCCOMB_X39_Y14_N18 4 " "Info: 2: + IC(0.395 ns) + CELL(0.513 ns) = 0.908 ns; Loc. = LCCOMB_X39_Y14_N18; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.178 ns) 1.404 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LCCOMB_X39_Y14_N4 6 " "Info: 3: + IC(0.318 ns) + CELL(0.178 ns) = 1.404 ns; Loc. = LCCOMB_X39_Y14_N4; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.496 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.322 ns) 2.040 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LCCOMB_X39_Y14_N12 2 " "Info: 4: + IC(0.314 ns) + CELL(0.322 ns) = 2.040 ns; Loc. = LCCOMB_X39_Y14_N12; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.636 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.178 ns) 2.525 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LCCOMB_X39_Y14_N22 10 " "Info: 5: + IC(0.307 ns) + CELL(0.178 ns) = 2.525 ns; Loc. = LCCOMB_X39_Y14_N22; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.485 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.758 ns) 4.166 ns miniUART:U1\|RxUnit:RxDev\|frameErr 6 REG LCFF_X39_Y11_N25 2 " "Info: 6: + IC(0.883 ns) + CELL(0.758 ns) = 4.166 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.949 ns ( 46.78 % ) " "Info: Total cell delay = 1.949 ns ( 46.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.217 ns ( 53.22 % ) " "Info: Total interconnect delay = 2.217 ns ( 53.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.395ns 0.318ns 0.314ns 0.307ns 0.883ns } { 0.000ns 0.513ns 0.178ns 0.322ns 0.178ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.856 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.602 ns) 2.856 ns miniUART:U1\|RxUnit:RxDev\|frameErr 3 REG LCFF_X39_Y11_N25 2 " "Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 2.856 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.00 % ) " "Info: Total cell delay = 1.628 ns ( 57.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.228 ns ( 43.00 % ) " "Info: Total interconnect delay = 1.228 ns ( 43.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.860 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 3 REG LCFF_X39_Y14_N25 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.395ns 0.318ns 0.314ns 0.307ns 0.883ns } { 0.000ns 0.513ns 0.178ns 0.322ns 0.178ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "miniUART:U1\|TxUnit:TxDev\|TReg\[0\] KEY\[0\] CLOCK_50 6.868 ns register " "Info: tsu for register \"miniUART:U1\|TxUnit:TxDev\|TReg\[0\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 6.868 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.768 ns + Longest pin register " "Info: + Longest pin to register delay is 9.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 PIN PIN_R22 54 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 54; PIN Node = 'KEY\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.688 ns) + CELL(0.545 ns) 7.097 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~32 2 COMB LCCOMB_X39_Y11_N14 4 " "Info: 2: + IC(5.688 ns) + CELL(0.545 ns) = 7.097 ns; Loc. = LCCOMB_X39_Y11_N14; Fanout = 4; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~32'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.233 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.322 ns) 7.735 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35 3 COMB LCCOMB_X39_Y11_N30 2 " "Info: 3: + IC(0.316 ns) + CELL(0.322 ns) = 7.735 ns; Loc. = LCCOMB_X39_Y11_N30; Fanout = 2; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.638 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.490 ns) + CELL(0.521 ns) 8.746 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~37 4 COMB LCCOMB_X38_Y11_N30 7 " "Info: 4: + IC(0.490 ns) + CELL(0.521 ns) = 8.746 ns; Loc. = LCCOMB_X38_Y11_N30; Fanout = 7; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~37'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.011 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.758 ns) 9.768 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 5 REG LCFF_X38_Y11_N9 1 " "Info: 5: + IC(0.264 ns) + CELL(0.758 ns) = 9.768 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.010 ns ( 30.81 % ) " "Info: Total cell delay = 3.010 ns ( 30.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.758 ns ( 69.19 % ) " "Info: Total interconnect delay = 6.758 ns ( 69.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.768 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.768 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~32 {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~37 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.688ns 0.316ns 0.490ns 0.264ns } { 0.000ns 0.864ns 0.545ns 0.322ns 0.521ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.862 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 2.862 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 3 REG LCFF_X38_Y11_N9 1 " "Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.88 % ) " "Info: Total cell delay = 1.628 ns ( 56.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 43.12 % ) " "Info: Total interconnect delay = 1.234 ns ( 43.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.768 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.768 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~32 {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~37 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.688ns 0.316ns 0.490ns 0.264ns } { 0.000ns 0.864ns 0.545ns 0.322ns 0.521ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "SW\[8\] LEDR\[7\] miniUART:U1\|DataOut\[7\]\$latch 8.405 ns register " "Info: tco from clock \"SW\[8\]\" to destination pin \"LEDR\[7\]\" through register \"miniUART:U1\|DataOut\[7\]\$latch\" is 8.405 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[8\] source 2.999 ns + Longest register " "Info: + Longest clock path from clock \"SW\[8\]\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[8\] 1 CLK PIN_M1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 3; CLK Node = 'SW\[8\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns SW\[8\]~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'SW\[8\]~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { SW[8] SW[8]~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.413 ns) + CELL(0.322 ns) 2.999 ns miniUART:U1\|DataOut\[7\]\$latch 3 REG LCCOMB_X40_Y13_N6 1 " "Info: 3: + IC(1.413 ns) + CELL(0.322 ns) = 2.999 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1\|DataOut\[7\]\$latch'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.735 ns" { SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.348 ns ( 44.95 % ) " "Info: Total cell delay = 1.348 ns ( 44.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.651 ns ( 55.05 % ) " "Info: Total interconnect delay = 1.651 ns ( 55.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { SW[8] SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { SW[8] {} SW[8]~combout {} SW[8]~clkctrl {} miniUART:U1|DataOut[7]$latch {} } { 0.000ns 0.000ns 0.238ns 1.413ns } { 0.000ns 1.026ns 0.000ns 0.322ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.406 ns + Longest register pin " "Info: + Longest register to pin delay is 5.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|DataOut\[7\]\$latch 1 REG LCCOMB_X40_Y13_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1\|DataOut\[7\]\$latch'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.411 ns) + CELL(2.995 ns) 5.406 ns LEDR\[7\] 2 PIN PIN_U18 0 " "Info: 2: + IC(2.411 ns) + CELL(2.995 ns) = 5.406 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'LEDR\[7\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.995 ns ( 55.40 % ) " "Info: Total cell delay = 2.995 ns ( 55.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.411 ns ( 44.60 % ) " "Info: Total interconnect delay = 2.411 ns ( 44.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.406 ns" { miniUART:U1|DataOut[7]$latch {} LEDR[7] {} } { 0.000ns 2.411ns } { 0.000ns 2.995ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { SW[8] SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { SW[8] {} SW[8]~combout {} SW[8]~clkctrl {} miniUART:U1|DataOut[7]$latch {} } { 0.000ns 0.000ns 0.238ns 1.413ns } { 0.000ns 1.026ns 0.000ns 0.322ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.406 ns" { miniUART:U1|DataOut[7]$latch {} LEDR[7] {} } { 0.000ns 2.411ns } { 0.000ns 2.995ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "miniUART:U1\|RxUnit:RxDev\|tmpDRdy SW\[1\] CLOCK_50 0.138 ns register " "Info: th for register \"miniUART:U1\|RxUnit:RxDev\|tmpDRdy\" (data pin = \"SW\[1\]\", clock pin = \"CLOCK_50\") is 0.138 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.858 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X39_Y12_N17 3 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.006 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.006 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[1\] 1 PIN PIN_L21 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L21; Fanout = 2; PIN Node = 'SW\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.339 ns) + CELL(0.545 ns) 2.910 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11 2 COMB LCCOMB_X39_Y12_N16 1 " "Info: 2: + IC(1.339 ns) + CELL(0.545 ns) = 2.910 ns; Loc. = LCCOMB_X39_Y12_N16; Fanout = 1; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.884 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 3.006 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X39_Y12_N17 3 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 3.006 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.667 ns ( 55.46 % ) " "Info: Total cell delay = 1.667 ns ( 55.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.339 ns ( 44.54 % ) " "Info: Total interconnect delay = 1.339 ns ( 44.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.006 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.339ns 0.000ns } { 0.000ns 1.026ns 0.545ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.006 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.339ns 0.000ns } { 0.000ns 1.026ns 0.545ns 0.096ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 15 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Peak virtual memory: 136 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:21:41 2010 " "Info: Processing ended: Sun Jan 10 17:21:41 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.fit.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.fit.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.fit.qmsg (revision 6)
@@ -0,0 +1,45 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:21:25 2010 " "Info: Processing started: Sun Jan 10 17:21:25 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "uart EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"uart\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" { } { } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 281 " "Warning: No exact pin location assignment(s) for 7 pins of 281 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLOCK_27 " "Info: Pin CLOCK_27 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_27 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IRDA_RXD " "Info: Pin IRDA_RXD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { IRDA_RXD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { IRDA_RXD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FL_CE_N " "Info: Pin FL_CE_N not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Info: Pin SD_DAT not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Info: Pin SD_DAT3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Info: Pin SD_CMD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Info: Pin SD_CLK not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|Equal1~0 " "Info: Destination node miniUART:U1\|Equal1~0" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|Equal1~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|DataOut\[0\]_240 " "Info: Destination node miniUART:U1\|DataOut\[0\]_240" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|DataOut[0]_240 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SW[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.3V 3 4 0 " "Info: Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 3 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 40 1 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 32 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 26 17 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 17 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 36 4 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 4 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 36 3 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 3 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 31 5 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 35 5 " "Info: I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 41 2 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 2 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[0\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_27\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Node \"CLOCK_24\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Node \"CLOCK_24\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[0\] " "Warning: Node \"CLOCK_27\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Node \"CLOCK_27\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.384 ns register register " "Info: Estimated most critical path is register to register delay of 4.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LAB_X39_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X39_Y14; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.322 ns) 0.738 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LAB_X39_Y14 4 " "Info: 2: + IC(0.416 ns) + CELL(0.322 ns) = 0.738 ns; Loc. = LAB_X39_Y14; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.738 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 1.414 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LAB_X39_Y14 6 " "Info: 3: + IC(0.498 ns) + CELL(0.178 ns) = 1.414 ns; Loc. = LAB_X39_Y14; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.512 ns) 2.057 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LAB_X39_Y14 2 " "Info: 4: + IC(0.131 ns) + CELL(0.512 ns) = 2.057 ns; Loc. = LAB_X39_Y14; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.733 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LAB_X39_Y14 10 " "Info: 5: + IC(0.498 ns) + CELL(0.178 ns) = 2.733 ns; Loc. = LAB_X39_Y14; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.758 ns) 4.384 ns miniUART:U1\|RxUnit:RxDev\|frameErr 6 REG LAB_X39_Y11 2 " "Info: 6: + IC(0.893 ns) + CELL(0.758 ns) = 4.384 ns; Loc. = LAB_X39_Y11; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.651 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.948 ns ( 44.43 % ) " "Info: Total cell delay = 1.948 ns ( 44.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.436 ns ( 55.57 % ) " "Info: Total interconnect delay = 2.436 ns ( 55.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.384 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X38_Y0 X50_Y13 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y0 to location X50_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "257 " "Warning: Found 257 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_DAT 0 " "Info: Pin \"PS2_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_CLK 0 " "Info: Pin \"PS2_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "118 " "Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[0\] a permanently disabled " "Info: Pin SRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[1\] a permanently disabled " "Info: Pin SRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[2\] a permanently disabled " "Info: Pin SRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[3\] a permanently disabled " "Info: Pin SRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[4\] a permanently disabled " "Info: Pin SRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[5\] a permanently disabled " "Info: Pin SRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[6\] a permanently disabled " "Info: Pin SRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[7\] a permanently disabled " "Info: Pin SRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_DAT a permanently disabled " "Info: Pin PS2_DAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_CLK a permanently disabled " "Info: Pin PS2_CLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[0\] a permanently disabled " "Info: Pin DRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[1\] a permanently disabled " "Info: Pin DRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[2\] a permanently disabled " "Info: Pin DRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[3\] a permanently disabled " "Info: Pin DRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[4\] a permanently disabled " "Info: Pin DRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[5\] a permanently disabled " "Info: Pin DRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[6\] a permanently disabled " "Info: Pin DRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[7\] a permanently disabled " "Info: Pin DRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[8\] a permanently disabled " "Info: Pin DRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[9\] a permanently disabled " "Info: Pin DRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[10\] a permanently disabled " "Info: Pin DRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[11\] a permanently disabled " "Info: Pin DRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[12\] a permanently disabled " "Info: Pin DRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[13\] a permanently disabled " "Info: Pin DRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[14\] a permanently disabled " "Info: Pin DRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[15\] a permanently disabled " "Info: Pin DRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[0\] a permanently disabled " "Info: Pin FL_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[1\] a permanently disabled " "Info: Pin FL_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[2\] a permanently disabled " "Info: Pin FL_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[3\] a permanently disabled " "Info: Pin FL_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[4\] a permanently disabled " "Info: Pin FL_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[5\] a permanently disabled " "Info: Pin FL_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[6\] a permanently disabled " "Info: Pin FL_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[7\] a permanently disabled " "Info: Pin FL_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[8\] a permanently disabled " "Info: Pin SRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[9\] a permanently disabled " "Info: Pin SRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[10\] a permanently disabled " "Info: Pin SRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[11\] a permanently disabled " "Info: Pin SRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[12\] a permanently disabled " "Info: Pin SRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[13\] a permanently disabled " "Info: Pin SRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[14\] a permanently disabled " "Info: Pin SRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[15\] a permanently disabled " "Info: Pin SRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Info: Pin AUD_ADCLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Info: Pin AUD_DACLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "246 " "Warning: Following 246 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[0\] VCC " "Info: Pin SRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[1\] VCC " "Info: Pin SRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[2\] VCC " "Info: Pin SRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[3\] VCC " "Info: Pin SRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[4\] VCC " "Info: Pin SRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[5\] VCC " "Info: Pin SRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[6\] VCC " "Info: Pin SRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[7\] VCC " "Info: Pin SRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_DAT VCC " "Info: Pin PS2_DAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_CLK VCC " "Info: Pin PS2_CLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[0\] VCC " "Info: Pin DRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[1\] VCC " "Info: Pin DRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[2\] VCC " "Info: Pin DRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[3\] VCC " "Info: Pin DRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[4\] VCC " "Info: Pin DRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[5\] VCC " "Info: Pin DRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[6\] VCC " "Info: Pin DRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[7\] VCC " "Info: Pin DRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[8\] VCC " "Info: Pin DRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[9\] VCC " "Info: Pin DRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[10\] VCC " "Info: Pin DRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[11\] VCC " "Info: Pin DRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[12\] VCC " "Info: Pin DRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[13\] VCC " "Info: Pin DRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[14\] VCC " "Info: Pin DRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[15\] VCC " "Info: Pin DRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[0\] VCC " "Info: Pin FL_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[1\] VCC " "Info: Pin FL_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[2\] VCC " "Info: Pin FL_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[3\] VCC " "Info: Pin FL_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[4\] VCC " "Info: Pin FL_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[5\] VCC " "Info: Pin FL_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[6\] VCC " "Info: Pin FL_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[7\] VCC " "Info: Pin FL_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[8\] VCC " "Info: Pin SRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[9\] VCC " "Info: Pin SRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[10\] VCC " "Info: Pin SRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[11\] VCC " "Info: Pin SRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[12\] VCC " "Info: Pin SRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[13\] VCC " "Info: Pin SRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[14\] VCC " "Info: Pin SRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[15\] VCC " "Info: Pin SRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SDAT VCC " "Info: Pin I2C_SDAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_ADCLRCK VCC " "Info: Pin AUD_ADCLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACLRCK VCC " "Info: Pin AUD_DACLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[0\] GND " "Info: Pin HEX0\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[1\] GND " "Info: Pin HEX0\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[2\] GND " "Info: Pin HEX0\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[3\] GND " "Info: Pin HEX0\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[4\] GND " "Info: Pin HEX0\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[5\] GND " "Info: Pin HEX0\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[6\] GND " "Info: Pin HEX0\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[0\] GND " "Info: Pin HEX1\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[1\] GND " "Info: Pin HEX1\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[2\] GND " "Info: Pin HEX1\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[3\] GND " "Info: Pin HEX1\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[4\] GND " "Info: Pin HEX1\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[5\] GND " "Info: Pin HEX1\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[6\] GND " "Info: Pin HEX1\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[0\] GND " "Info: Pin HEX2\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[1\] GND " "Info: Pin HEX2\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[2\] GND " "Info: Pin HEX2\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[3\] GND " "Info: Pin HEX2\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[4\] GND " "Info: Pin HEX2\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[5\] GND " "Info: Pin HEX2\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[6\] GND " "Info: Pin HEX2\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[0\] GND " "Info: Pin HEX3\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[1\] GND " "Info: Pin HEX3\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[2\] GND " "Info: Pin HEX3\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[3\] GND " "Info: Pin HEX3\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[4\] GND " "Info: Pin HEX3\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[5\] GND " "Info: Pin HEX3\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[6\] GND " "Info: Pin HEX3\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[2\] GND " "Info: Pin LEDG\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[3\] GND " "Info: Pin LEDG\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[4\] GND " "Info: Pin LEDG\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[5\] GND " "Info: Pin LEDG\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[6\] GND " "Info: Pin LEDG\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[7\] GND " "Info: Pin LEDG\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[8\] GND " "Info: Pin LEDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[9\] GND " "Info: Pin LEDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[0\] GND " "Info: Pin DRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[1\] GND " "Info: Pin DRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[2\] GND " "Info: Pin DRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[3\] GND " "Info: Pin DRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[4\] GND " "Info: Pin DRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[5\] GND " "Info: Pin DRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[6\] GND " "Info: Pin DRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[7\] GND " "Info: Pin DRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[8\] GND " "Info: Pin DRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[9\] GND " "Info: Pin DRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[10\] GND " "Info: Pin DRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[11\] GND " "Info: Pin DRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_LDQM GND " "Info: Pin DRAM_LDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_LDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_LDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_UDQM GND " "Info: Pin DRAM_UDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_UDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_UDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_WE_N VCC " "Info: Pin DRAM_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CAS_N VCC " "Info: Pin DRAM_CAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_RAS_N VCC " "Info: Pin DRAM_RAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_RAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_RAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CS_N VCC " "Info: Pin DRAM_CS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_0 GND " "Info: Pin DRAM_BA_0 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_0 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_0 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_1 GND " "Info: Pin DRAM_BA_1 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_1 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_1 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CLK GND " "Info: Pin DRAM_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE GND " "Info: Pin DRAM_CKE has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CKE } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[0\] GND " "Info: Pin FL_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[1\] GND " "Info: Pin FL_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[2\] GND " "Info: Pin FL_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[3\] GND " "Info: Pin FL_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[4\] GND " "Info: Pin FL_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[5\] GND " "Info: Pin FL_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[6\] GND " "Info: Pin FL_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[7\] GND " "Info: Pin FL_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[8\] GND " "Info: Pin FL_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[9\] GND " "Info: Pin FL_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[10\] GND " "Info: Pin FL_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[11\] GND " "Info: Pin FL_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[12\] GND " "Info: Pin FL_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[13\] GND " "Info: Pin FL_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[14\] GND " "Info: Pin FL_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[15\] GND " "Info: Pin FL_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[16\] GND " "Info: Pin FL_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[17\] GND " "Info: Pin FL_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[18\] GND " "Info: Pin FL_ADDR\[18\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[19\] GND " "Info: Pin FL_ADDR\[19\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[20\] GND " "Info: Pin FL_ADDR\[20\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[21\] GND " "Info: Pin FL_ADDR\[21\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_WE_N VCC " "Info: Pin FL_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N GND " "Info: Pin FL_RST_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_RST_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_OE_N VCC " "Info: Pin FL_OE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_CE_N VCC " "Info: Pin FL_CE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[0\] GND " "Info: Pin SRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[1\] GND " "Info: Pin SRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[2\] GND " "Info: Pin SRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[3\] GND " "Info: Pin SRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[4\] GND " "Info: Pin SRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[5\] GND " "Info: Pin SRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[6\] GND " "Info: Pin SRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[7\] GND " "Info: Pin SRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[8\] GND " "Info: Pin SRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[9\] GND " "Info: Pin SRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[10\] GND " "Info: Pin SRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[11\] GND " "Info: Pin SRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[12\] GND " "Info: Pin SRAM_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[13\] GND " "Info: Pin SRAM_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[14\] GND " "Info: Pin SRAM_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[15\] GND " "Info: Pin SRAM_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[16\] GND " "Info: Pin SRAM_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[17\] GND " "Info: Pin SRAM_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_UB_N VCC " "Info: Pin SRAM_UB_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_UB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_LB_N GND " "Info: Pin SRAM_LB_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_LB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N GND " "Info: Pin SRAM_WE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N GND " "Info: Pin SRAM_CE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_CE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N GND " "Info: Pin SRAM_OE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 GND " "Info: Pin SD_DAT3 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD GND " "Info: Pin SD_CMD has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { TDO } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SCLK GND " "Info: Pin I2C_SCLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_HS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_VS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_XCK GND " "Info: Pin AUD_XCK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_XCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 15 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "205 " "Info: Peak virtual memory: 205 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:21:34 2010 " "Info: Processing ended: Sun Jan 10 17:21:34 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm.qmsg (revision 6)
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 16 19:25:58 2010 " "Info: Processing started: Sat Jan 16 19:25:58 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 16 19:26:02 2010 " "Info: Processing ended: Sat Jan 16 19:26:02 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp0.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp0.ddb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp0.ddb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp0.ddb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp0.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp2.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp2.ddb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp2.ddb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp2.ddb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp2.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp_merge.kpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp_merge.kpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp_merge.kpt (revision 6)
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.syn_hier_info
===================================================================
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.eco.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.eco.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.eco.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.eco.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.eco.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.db_info
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.db_info (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.db_info (revision 6)
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+Version_Index = 167832322
+Creation_Time = Sun Oct 11 23:43:59 2009
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg_swap.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg_swap.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg_swap.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg_swap.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg_swap.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hier_info
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hier_info (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hier_info (revision 6)
@@ -0,0 +1,545 @@
+|top_uart
+CLOCK_27 => ~NO_FANOUT~
+CLOCK_50 => miniUART:U1.SysClk
+EXT_CLOCK => ~NO_FANOUT~
+KEY[0] => miniUART:U1.Reset
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => ~NO_FANOUT~
+SW[0] => miniUART:U1.CS_N
+SW[1] => miniUART:U1.RD_N
+SW[2] => miniUART:U1.WR_N
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => miniUART:U1.Addr[0]
+SW[8] => miniUART:U1.Addr[1]
+SW[9] => ~NO_FANOUT~
+LEDG[0] <= miniUART:U1.IntRx_N
+LEDG[1] <= miniUART:U1.IntTx_N
+LEDG[2] <=
+LEDG[3] <=
+LEDG[4] <=
+LEDG[5] <=
+LEDG[6] <=
+LEDG[7] <=
+LEDR[0] <= miniUART:U1.DataOut[0]
+LEDR[1] <= miniUART:U1.DataOut[1]
+LEDR[2] <= miniUART:U1.DataOut[2]
+LEDR[3] <= miniUART:U1.DataOut[3]
+LEDR[4] <= miniUART:U1.DataOut[4]
+LEDR[5] <= miniUART:U1.DataOut[5]
+LEDR[6] <= miniUART:U1.DataOut[6]
+LEDR[7] <= miniUART:U1.DataOut[7]
+LEDR[8] <=
+LEDR[9] <=
+UART_TXD <= UART_TXD~2.DB_MAX_OUTPUT_PORT_TYPE
+UART_RXD => miniUART:U1.RxD
+IRDA_RXD => ~NO_FANOUT~
+DRAM_DQ[0] <= DRAM_DQ[0]~0
+DRAM_DQ[1] <= DRAM_DQ[1]~1
+DRAM_DQ[2] <= DRAM_DQ[2]~2
+DRAM_DQ[3] <= DRAM_DQ[3]~3
+DRAM_DQ[4] <= DRAM_DQ[4]~4
+DRAM_DQ[5] <= DRAM_DQ[5]~5
+DRAM_DQ[6] <= DRAM_DQ[6]~6
+DRAM_DQ[7] <= DRAM_DQ[7]~7
+DRAM_DQ[8] <= DRAM_DQ[8]~8
+DRAM_DQ[9] <= DRAM_DQ[9]~9
+DRAM_DQ[10] <= DRAM_DQ[10]~10
+DRAM_DQ[11] <= DRAM_DQ[11]~11
+DRAM_DQ[12] <= DRAM_DQ[12]~12
+DRAM_DQ[13] <= DRAM_DQ[13]~13
+DRAM_DQ[14] <= DRAM_DQ[14]~14
+DRAM_DQ[15] <= DRAM_DQ[15]~15
+DRAM_ADDR[0] <=
+DRAM_ADDR[1] <=
+DRAM_ADDR[2] <=
+DRAM_ADDR[3] <=
+DRAM_ADDR[4] <=
+DRAM_ADDR[5] <=
+DRAM_ADDR[6] <=
+DRAM_ADDR[7] <=
+DRAM_ADDR[8] <=
+DRAM_ADDR[9] <=
+DRAM_ADDR[10] <=
+DRAM_ADDR[11] <=
+DRAM_LDQM <=
+DRAM_UDQM <=
+DRAM_WE_N <=
+DRAM_CAS_N <=
+DRAM_RAS_N <=
+DRAM_CS_N <=
+DRAM_BA_0 <=
+DRAM_BA_1 <=
+DRAM_CLK <=
+DRAM_CKE <=
+FL_DQ[0] <= FL_DQ[0]~0
+FL_DQ[1] <= FL_DQ[1]~1
+FL_DQ[2] <= FL_DQ[2]~2
+FL_DQ[3] <= FL_DQ[3]~3
+FL_DQ[4] <= FL_DQ[4]~4
+FL_DQ[5] <= FL_DQ[5]~5
+FL_DQ[6] <= FL_DQ[6]~6
+FL_DQ[7] <= FL_DQ[7]~7
+FL_ADDR[0] <=
+FL_ADDR[1] <=
+FL_ADDR[2] <=
+FL_ADDR[3] <=
+FL_ADDR[4] <=
+FL_ADDR[5] <=
+FL_ADDR[6] <=
+FL_ADDR[7] <=
+FL_ADDR[8] <=
+FL_ADDR[9] <=
+FL_ADDR[10] <=
+FL_ADDR[11] <=
+FL_ADDR[12] <=
+FL_ADDR[13] <=
+FL_ADDR[14] <=
+FL_ADDR[15] <=
+FL_ADDR[16] <=
+FL_ADDR[17] <=
+FL_ADDR[18] <=
+FL_ADDR[19] <=
+FL_ADDR[20] <=
+FL_ADDR[21] <=
+FL_WE_N <=
+FL_RST_N <=
+FL_OE_N <=
+FL_CE_N <=
+SRAM_DQ[0] <=
+SRAM_DQ[1] <=
+SRAM_DQ[2] <=
+SRAM_DQ[3] <=
+SRAM_DQ[4] <=
+SRAM_DQ[5] <=
+SRAM_DQ[6] <=
+SRAM_DQ[7] <=
+SRAM_DQ[8] <= SRAM_DQ[8]~0
+SRAM_DQ[9] <= SRAM_DQ[9]~1
+SRAM_DQ[10] <= SRAM_DQ[10]~2
+SRAM_DQ[11] <= SRAM_DQ[11]~3
+SRAM_DQ[12] <= SRAM_DQ[12]~4
+SRAM_DQ[13] <= SRAM_DQ[13]~5
+SRAM_DQ[14] <= SRAM_DQ[14]~6
+SRAM_DQ[15] <= SRAM_DQ[15]~7
+SRAM_ADDR[0] <=
+SRAM_ADDR[1] <=
+SRAM_ADDR[2] <=
+SRAM_ADDR[3] <=
+SRAM_ADDR[4] <=
+SRAM_ADDR[5] <=
+SRAM_ADDR[6] <=
+SRAM_ADDR[7] <=
+SRAM_ADDR[8] <=
+SRAM_ADDR[9] <=
+SRAM_ADDR[10] <=
+SRAM_ADDR[11] <=
+SRAM_ADDR[12] <=
+SRAM_ADDR[13] <=
+SRAM_ADDR[14] <=
+SRAM_ADDR[15] <=
+SRAM_ADDR[16] <=
+SRAM_ADDR[17] <=
+SRAM_UB_N <=
+SRAM_LB_N <=
+SRAM_CE_N <=
+SD_DAT => ~NO_FANOUT~
+TDI => ~NO_FANOUT~
+TCK => ~NO_FANOUT~
+TCS => ~NO_FANOUT~
+TDO <=
+I2C_SDAT <= I2C_SDAT~0
+I2C_SCLK <=
+PS2_DAT <=
+PS2_CLK <=
+VGA_B[0] <= comb~0.DB_MAX_OUTPUT_PORT_TYPE
+AUD_ADCLRCK <= AUD_ADCLRCK~0
+AUD_ADCDAT => ~NO_FANOUT~
+AUD_DACLRCK <= AUD_DACLRCK~0
+AUD_DACDAT <=
+AUD_BCLK <= AUD_BCLK~0
+AUD_XCK <=
+GPIO_0[0] <= GPIO_0[0]~0
+GPIO_0[1] <= GPIO_0[1]~1
+GPIO_0[2] <= GPIO_0[2]~2
+GPIO_0[3] <= GPIO_0[3]~3
+GPIO_0[4] <= GPIO_0[4]~4
+GPIO_0[5] <= GPIO_0[5]~5
+GPIO_0[6] <= GPIO_0[6]~6
+GPIO_0[7] <= GPIO_0[7]~7
+GPIO_0[8] <= GPIO_0[8]~8
+GPIO_0[9] <= GPIO_0[9]~9
+GPIO_0[10] <= GPIO_0[10]~10
+GPIO_0[11] <= GPIO_0[11]~11
+GPIO_0[12] <= GPIO_0[12]~12
+GPIO_0[13] <= GPIO_0[13]~13
+GPIO_0[14] <= GPIO_0[14]~14
+GPIO_0[15] <= GPIO_0[15]~15
+GPIO_0[16] <= GPIO_0[16]~16
+GPIO_0[17] <= GPIO_0[17]~17
+GPIO_0[18] <= GPIO_0[18]~18
+GPIO_0[19] <= GPIO_0[19]~19
+GPIO_0[20] <= GPIO_0[20]~20
+GPIO_0[21] <= GPIO_0[21]~21
+GPIO_0[22] <= GPIO_0[22]~22
+GPIO_0[23] <= GPIO_0[23]~23
+GPIO_0[24] <= GPIO_0[24]~24
+GPIO_0[25] <= GPIO_0[25]~25
+GPIO_0[26] <= GPIO_0[26]~26
+GPIO_0[27] <= GPIO_0[27]~27
+GPIO_0[28] <= GPIO_0[28]~28
+GPIO_0[29] <= GPIO_0[29]~29
+GPIO_0[30] <= GPIO_0[30]~30
+GPIO_0[31] <= GPIO_0[31]~31
+GPIO_0[32] <= GPIO_0[32]~32
+GPIO_0[33] <= GPIO_0[33]~33
+GPIO_0[34] <= GPIO_0[34]~34
+GPIO_0[35] <= GPIO_0[35]~35
+GPIO_1[0] <= GPIO_1[0]~0
+GPIO_1[1] <= GPIO_1[1]~1
+GPIO_1[2] <= GPIO_1[2]~2
+GPIO_1[3] <= GPIO_1[3]~3
+GPIO_1[4] <= GPIO_1[4]~4
+GPIO_1[5] <= GPIO_1[5]~5
+GPIO_1[6] <= GPIO_1[6]~6
+GPIO_1[7] <= GPIO_1[7]~7
+GPIO_1[8] <= GPIO_1[8]~8
+GPIO_1[9] <= GPIO_1[9]~9
+GPIO_1[10] <= GPIO_1[10]~10
+GPIO_1[11] <= GPIO_1[11]~11
+GPIO_1[12] <= GPIO_1[12]~12
+GPIO_1[13] <= GPIO_1[13]~13
+GPIO_1[14] <= GPIO_1[14]~14
+GPIO_1[15] <= GPIO_1[15]~15
+GPIO_1[16] <= GPIO_1[16]~16
+GPIO_1[17] <= GPIO_1[17]~17
+GPIO_1[18] <= GPIO_1[18]~18
+GPIO_1[19] <= GPIO_1[19]~19
+GPIO_1[20] <= GPIO_1[20]~20
+GPIO_1[21] <= GPIO_1[21]~21
+GPIO_1[22] <= GPIO_1[22]~22
+GPIO_1[23] <= GPIO_1[23]~23
+GPIO_1[24] <= GPIO_1[24]~24
+GPIO_1[25] <= GPIO_1[25]~25
+GPIO_1[26] <= GPIO_1[26]~26
+GPIO_1[27] <= GPIO_1[27]~27
+GPIO_1[28] <= GPIO_1[28]~28
+GPIO_1[29] <= GPIO_1[29]~29
+GPIO_1[30] <= GPIO_1[30]~30
+GPIO_1[31] <= GPIO_1[31]~31
+GPIO_1[32] <= GPIO_1[32]~32
+GPIO_1[33] <= GPIO_1[33]~33
+GPIO_1[34] <= GPIO_1[34]~34
+GPIO_1[35] <= GPIO_1[35]~35
+
+
+|top_uart|miniUART:U1
+SysClk => RxUnit:RxDev.Clk
+SysClk => TxUnit:TxDev.Clk
+SysClk => IntTx_N~reg0.CLK
+SysClk => IntRx_N~reg0.CLK
+SysClk => CSReg[7].CLK
+SysClk => CSReg[6].CLK
+SysClk => CSReg[5].CLK
+SysClk => CSReg[4].CLK
+SysClk => CSReg[3].CLK
+SysClk => CSReg[2].CLK
+SysClk => CSReg[1].CLK
+SysClk => CSReg[0].CLK
+SysClk => ClkUnit:ClkDiv.SysClk
+Reset => RxUnit:RxDev.Reset
+Reset => TxUnit:TxDev.Reset
+Reset => ClkUnit:ClkDiv.Reset
+Reset => CSReg~1.OUTPUTSELECT
+Reset => CSReg~0.OUTPUTSELECT
+Reset => IntRx_N~0.OUTPUTSELECT
+Reset => IntTx_N~0.OUTPUTSELECT
+Reset => StatM~4.OUTPUTSELECT
+Reset => StatM~3.OUTPUTSELECT
+Reset => StatM~2.OUTPUTSELECT
+Reset => StatM~1.OUTPUTSELECT
+Reset => StatM~0.OUTPUTSELECT
+Reset => CSReg[0].ENA
+Reset => CSReg[1].ENA
+Reset => CSReg[4].ENA
+Reset => CSReg[5].ENA
+Reset => CSReg[6].ENA
+Reset => CSReg[7].ENA
+CS_N => Load.IN0
+CS_N => Read.IN0
+RD_N => Read.IN1
+WR_N => Load.IN1
+RxD => RxUnit:RxDev.RxD
+TxD <= TxUnit:TxDev.TxD
+IntRx_N <= IntRx_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+IntTx_N <= IntTx_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+Addr[0] => Equal0.IN1
+Addr[0] => Equal1.IN0
+Addr[1] => Equal0.IN0
+Addr[1] => Equal1.IN1
+DataIn[0] => TxData[0].DATAIN
+DataIn[1] => TxData[1].DATAIN
+DataIn[2] => TxData[2].DATAIN
+DataIn[3] => TxData[3].DATAIN
+DataIn[4] => TxData[4].DATAIN
+DataIn[5] => TxData[5].DATAIN
+DataIn[6] => TxData[6].DATAIN
+DataIn[7] => TxData[7].DATAIN
+DataOut[0] <= DataOut[0]~9.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[1] <= DataOut[1]~10.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[2] <= DataOut[2]~11.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[3] <= DataOut[3]~12.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[4] <= DataOut[4]~13.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[5] <= DataOut[5]~14.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[6] <= DataOut[6]~15.DB_MAX_OUTPUT_PORT_TYPE
+DataOut[7] <= DataOut[7]~16.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top_uart|miniUART:U1|ClkUnit:ClkDiv
+SysClk => \DivClk26:Cnt26[5].CLK
+SysClk => \DivClk26:Cnt26[4].CLK
+SysClk => \DivClk26:Cnt26[3].CLK
+SysClk => \DivClk26:Cnt26[2].CLK
+SysClk => \DivClk26:Cnt26[1].CLK
+SysClk => \DivClk26:Cnt26[0].CLK
+SysClk => ClkDiv26.CLK
+SysClk => \DivClk10:Cnt10[3].CLK
+SysClk => \DivClk10:Cnt10[2].CLK
+SysClk => \DivClk10:Cnt10[1].CLK
+SysClk => \DivClk10:Cnt10[0].CLK
+SysClk => tmpEnRX.CLK
+SysClk => \DivClk16:Cnt16[4].CLK
+SysClk => \DivClk16:Cnt16[3].CLK
+SysClk => \DivClk16:Cnt16[2].CLK
+SysClk => \DivClk16:Cnt16[1].CLK
+SysClk => \DivClk16:Cnt16[0].CLK
+SysClk => tmpEnTX.CLK
+EnableRx <= tmpEnRX.DB_MAX_OUTPUT_PORT_TYPE
+EnableTx <= tmpEnTX.DB_MAX_OUTPUT_PORT_TYPE
+Reset => Cnt26~0.OUTPUTSELECT
+Reset => Cnt26~1.OUTPUTSELECT
+Reset => Cnt26~2.OUTPUTSELECT
+Reset => Cnt26~3.OUTPUTSELECT
+Reset => Cnt26~4.OUTPUTSELECT
+Reset => Cnt26~5.OUTPUTSELECT
+Reset => ClkDiv26~0.OUTPUTSELECT
+Reset => Cnt16~5.OUTPUTSELECT
+Reset => Cnt16~6.OUTPUTSELECT
+Reset => Cnt16~7.OUTPUTSELECT
+Reset => Cnt16~8.OUTPUTSELECT
+Reset => Cnt16~9.OUTPUTSELECT
+Reset => Cnt10~7.OUTPUTSELECT
+Reset => Cnt10~6.OUTPUTSELECT
+Reset => Cnt10~5.OUTPUTSELECT
+Reset => Cnt10~4.OUTPUTSELECT
+
+
+|top_uart|miniUART:U1|TxUnit:TxDev
+Clk => tmpTRegE.CLK
+Clk => tmpTBufE.CLK
+Clk => TxD~reg0.CLK
+Clk => BitCnt[3].CLK
+Clk => BitCnt[2].CLK
+Clk => BitCnt[1].CLK
+Clk => BitCnt[0].CLK
+Clk => TBuff[7].CLK
+Clk => TBuff[6].CLK
+Clk => TBuff[5].CLK
+Clk => TBuff[4].CLK
+Clk => TBuff[3].CLK
+Clk => TBuff[2].CLK
+Clk => TBuff[1].CLK
+Clk => TBuff[0].CLK
+Clk => TReg[7].CLK
+Clk => TReg[6].CLK
+Clk => TReg[5].CLK
+Clk => TReg[4].CLK
+Clk => TReg[3].CLK
+Clk => TReg[2].CLK
+Clk => TReg[1].CLK
+Clk => TReg[0].CLK
+Reset => BitCnt~15.OUTPUTSELECT
+Reset => BitCnt~14.OUTPUTSELECT
+Reset => BitCnt~13.OUTPUTSELECT
+Reset => BitCnt~12.OUTPUTSELECT
+Reset => TxD~3.OUTPUTSELECT
+Reset => tmpTBufE~3.OUTPUTSELECT
+Reset => tmpTRegE~4.OUTPUTSELECT
+Reset => TReg[0].ENA
+Reset => TReg[1].ENA
+Reset => TReg[2].ENA
+Reset => TReg[3].ENA
+Reset => TReg[4].ENA
+Reset => TReg[5].ENA
+Reset => TReg[6].ENA
+Reset => TReg[7].ENA
+Reset => TBuff[0].ENA
+Reset => TBuff[1].ENA
+Reset => TBuff[2].ENA
+Reset => TBuff[3].ENA
+Reset => TBuff[4].ENA
+Reset => TBuff[5].ENA
+Reset => TBuff[6].ENA
+Reset => TBuff[7].ENA
+Enable => TReg~23.OUTPUTSELECT
+Enable => TReg~22.OUTPUTSELECT
+Enable => TReg~21.OUTPUTSELECT
+Enable => TReg~20.OUTPUTSELECT
+Enable => TReg~19.OUTPUTSELECT
+Enable => TReg~18.OUTPUTSELECT
+Enable => TReg~17.OUTPUTSELECT
+Enable => TReg~16.OUTPUTSELECT
+Enable => BitCnt~7.OUTPUTSELECT
+Enable => BitCnt~6.OUTPUTSELECT
+Enable => BitCnt~5.OUTPUTSELECT
+Enable => BitCnt~4.OUTPUTSELECT
+Enable => TxD~1.OUTPUTSELECT
+Enable => tmpTBufE~1.OUTPUTSELECT
+Enable => tmpTRegE~2.OUTPUTSELECT
+Load => TReg~31.OUTPUTSELECT
+Load => TReg~30.OUTPUTSELECT
+Load => TReg~29.OUTPUTSELECT
+Load => TReg~28.OUTPUTSELECT
+Load => TReg~27.OUTPUTSELECT
+Load => TReg~26.OUTPUTSELECT
+Load => TReg~25.OUTPUTSELECT
+Load => TReg~24.OUTPUTSELECT
+Load => TBuff~7.OUTPUTSELECT
+Load => TBuff~6.OUTPUTSELECT
+Load => TBuff~5.OUTPUTSELECT
+Load => TBuff~4.OUTPUTSELECT
+Load => TBuff~3.OUTPUTSELECT
+Load => TBuff~2.OUTPUTSELECT
+Load => TBuff~1.OUTPUTSELECT
+Load => TBuff~0.OUTPUTSELECT
+Load => BitCnt~11.OUTPUTSELECT
+Load => BitCnt~10.OUTPUTSELECT
+Load => BitCnt~9.OUTPUTSELECT
+Load => BitCnt~8.OUTPUTSELECT
+Load => TxD~2.OUTPUTSELECT
+Load => tmpTBufE~2.OUTPUTSELECT
+Load => tmpTRegE~3.OUTPUTSELECT
+TxD <= TxD~reg0.DB_MAX_OUTPUT_PORT_TYPE
+TRegE <= tmpTRegE.DB_MAX_OUTPUT_PORT_TYPE
+TBufE <= tmpTBufE.DB_MAX_OUTPUT_PORT_TYPE
+DataO[0] => TBuff~7.DATAB
+DataO[1] => TBuff~6.DATAB
+DataO[2] => TBuff~5.DATAB
+DataO[3] => TBuff~4.DATAB
+DataO[4] => TBuff~3.DATAB
+DataO[5] => TBuff~2.DATAB
+DataO[6] => TBuff~1.DATAB
+DataO[7] => TBuff~0.DATAB
+
+
+|top_uart|miniUART:U1|RxUnit:RxDev
+Clk => BitCnt[3].CLK
+Clk => BitCnt[2].CLK
+Clk => BitCnt[1].CLK
+Clk => BitCnt[0].CLK
+Clk => SampleCnt[3].CLK
+Clk => SampleCnt[2].CLK
+Clk => SampleCnt[1].CLK
+Clk => SampleCnt[0].CLK
+Clk => Start.CLK
+Clk => tmpDRdy.CLK
+Clk => frameErr.CLK
+Clk => outErr.CLK
+Clk => ShtReg[7].CLK
+Clk => ShtReg[6].CLK
+Clk => ShtReg[5].CLK
+Clk => ShtReg[4].CLK
+Clk => ShtReg[3].CLK
+Clk => ShtReg[2].CLK
+Clk => ShtReg[1].CLK
+Clk => ShtReg[0].CLK
+Clk => DOut[7].CLK
+Clk => DOut[6].CLK
+Clk => DOut[5].CLK
+Clk => DOut[4].CLK
+Clk => DOut[3].CLK
+Clk => DOut[2].CLK
+Clk => DOut[1].CLK
+Clk => DOut[0].CLK
+Clk => tmpRxD.CLK
+Reset => DOut~39.OUTPUTSELECT
+Reset => DOut~38.OUTPUTSELECT
+Reset => DOut~37.OUTPUTSELECT
+Reset => DOut~36.OUTPUTSELECT
+Reset => DOut~35.OUTPUTSELECT
+Reset => DOut~34.OUTPUTSELECT
+Reset => DOut~33.OUTPUTSELECT
+Reset => DOut~32.OUTPUTSELECT
+Reset => ShtReg~39.OUTPUTSELECT
+Reset => ShtReg~38.OUTPUTSELECT
+Reset => ShtReg~37.OUTPUTSELECT
+Reset => ShtReg~36.OUTPUTSELECT
+Reset => ShtReg~35.OUTPUTSELECT
+Reset => ShtReg~34.OUTPUTSELECT
+Reset => ShtReg~33.OUTPUTSELECT
+Reset => ShtReg~32.OUTPUTSELECT
+Reset => outErr~4.OUTPUTSELECT
+Reset => frameErr~4.OUTPUTSELECT
+Reset => tmpDRdy~5.OUTPUTSELECT
+Reset => Start~6.OUTPUTSELECT
+Reset => SampleCnt~23.OUTPUTSELECT
+Reset => SampleCnt~22.OUTPUTSELECT
+Reset => SampleCnt~21.OUTPUTSELECT
+Reset => SampleCnt~20.OUTPUTSELECT
+Reset => BitCnt~23.OUTPUTSELECT
+Reset => BitCnt~22.OUTPUTSELECT
+Reset => BitCnt~21.OUTPUTSELECT
+Reset => BitCnt~20.OUTPUTSELECT
+Reset => tmpRxD.ENA
+Enable => DOut~31.OUTPUTSELECT
+Enable => DOut~30.OUTPUTSELECT
+Enable => DOut~29.OUTPUTSELECT
+Enable => DOut~28.OUTPUTSELECT
+Enable => DOut~27.OUTPUTSELECT
+Enable => DOut~26.OUTPUTSELECT
+Enable => DOut~25.OUTPUTSELECT
+Enable => DOut~24.OUTPUTSELECT
+Enable => tmpDRdy~4.OUTPUTSELECT
+Enable => outErr~3.OUTPUTSELECT
+Enable => frameErr~3.OUTPUTSELECT
+Enable => ShtReg~31.OUTPUTSELECT
+Enable => ShtReg~30.OUTPUTSELECT
+Enable => ShtReg~29.OUTPUTSELECT
+Enable => ShtReg~28.OUTPUTSELECT
+Enable => ShtReg~27.OUTPUTSELECT
+Enable => ShtReg~26.OUTPUTSELECT
+Enable => ShtReg~25.OUTPUTSELECT
+Enable => ShtReg~24.OUTPUTSELECT
+Enable => BitCnt~19.OUTPUTSELECT
+Enable => BitCnt~18.OUTPUTSELECT
+Enable => BitCnt~17.OUTPUTSELECT
+Enable => BitCnt~16.OUTPUTSELECT
+Enable => tmpRxD~2.OUTPUTSELECT
+Enable => Start~5.OUTPUTSELECT
+Enable => SampleCnt~19.OUTPUTSELECT
+Enable => SampleCnt~18.OUTPUTSELECT
+Enable => SampleCnt~17.OUTPUTSELECT
+Enable => SampleCnt~16.OUTPUTSELECT
+RxD => tmpRxD~0.DATAB
+RxD => Start~0.OUTPUTSELECT
+RxD => SampleCnt~3.OUTPUTSELECT
+RxD => SampleCnt~2.OUTPUTSELECT
+RxD => SampleCnt~1.OUTPUTSELECT
+RxD => SampleCnt~0.OUTPUTSELECT
+RD => tmpDRdy~0.OUTPUTSELECT
+FErr <= frameErr.DB_MAX_OUTPUT_PORT_TYPE
+OErr <= outErr.DB_MAX_OUTPUT_PORT_TYPE
+DRdy <= tmpDRdy.DB_MAX_OUTPUT_PORT_TYPE
+DataIn[0] <= DOut[0].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[1] <= DOut[1].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[2] <= DOut[2].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[3] <= DOut[3].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[4] <= DOut[4].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[5] <= DOut[5].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[6] <= DOut[6].DB_MAX_OUTPUT_PORT_TYPE
+DataIn[7] <= DOut[7].DB_MAX_OUTPUT_PORT_TYPE
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.qmsg (revision 6)
@@ -0,0 +1,161 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:11:42 2010 " "Info: Processing started: Sun Jan 10 17:11:42 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder_7seg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder_7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder_7seg-rtl " "Info: Found design unit 1: decoder_7seg-rtl" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 13 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 decoder_7seg " "Info: Found entity 1: decoder_7seg" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-Behaviour " "Info: Found design unit 1: UART-Behaviour" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 57 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 36 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClkUnit-Behaviour " "Info: Found design unit 1: ClkUnit-Behaviour" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 52 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 ClkUnit " "Info: Found entity 1: ClkUnit" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 42 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "miniUART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file miniUART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 miniUART-uart " "Info: Found design unit 1: miniUART-uart" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 63 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 miniUART " "Info: Found entity 1: miniUART" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 45 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RxUnit-Behaviour " "Info: Found design unit 1: RxUnit-Behaviour" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 58 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 RxUnit " "Info: Found entity 1: RxUnit" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 43 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top_uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TOP_UART-rtl " "Info: Found design unit 1: TOP_UART-rtl" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 109 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TOP_UART " "Info: Found entity 1: TOP_UART" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 10 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TxUnit-Behaviour " "Info: Found design unit 1: TxUnit-Behaviour" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 55 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TxUnit " "Info: Found entity 1: TxUnit" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 41 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_lib.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_Def " "Info: Found design unit 1: UART_Def" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 35 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_Def-body " "Info: Found design unit 2: UART_Def-body" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 45 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top_uart " "Info: Elaborating entity \"top_uart\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX0 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX0\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX1 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX2 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX2\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX3 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_WE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_WE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_OE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_OE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_DAT3 top_uart.vhd(70) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(70): used implicit default value for signal \"SD_DAT3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CMD top_uart.vhd(71) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(71): used implicit default value for signal \"SD_CMD\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CLK top_uart.vhd(72) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(72): used implicit default value for signal \"SD_CLK\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_HS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_HS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_VS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_VS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_R top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_R\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_G top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_G\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_B top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_B\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[7\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[7\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[6\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[6\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[5\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[5\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[4\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[4\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[3\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[3\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[2\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[2\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[9\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[9\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[8\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[8\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[15\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[15\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[14\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[14\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[13\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[13\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[12\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[12\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[11\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[11\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[10\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[10\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[9\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[9\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[8\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[8\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[7\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[7\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[6\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[6\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[5\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[5\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[4\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[4\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[3\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[3\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[2\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[2\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[1\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[1\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[0\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[0\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "miniUART miniUART:U1 " "Info: Elaborating entity \"miniUART\" for hierarchy \"miniUART:U1\"" { } { { "top_uart.vhd" "U1" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"WR_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(190) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(190): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 190 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RxData miniUART.vhd(193) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(193): signal \"RxData\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 193 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CSReg miniUART.vhd(195) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(195): signal \"CSReg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 195 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(198) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(198): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 198 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DataIn miniUART.vhd(201) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(201): signal \"DataIn\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 201 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataOut miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"DataOut\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TxData miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"TxData\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClkUnit miniUART:U1\|ClkUnit:ClkDiv " "Info: Elaborating entity \"ClkUnit\" for hierarchy \"miniUART:U1\|ClkUnit:ClkDiv\"" { } { { "miniUART.vhd" "ClkDiv" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 127 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TxUnit miniUART:U1\|TxUnit:TxDev " "Info: Elaborating entity \"TxUnit\" for hierarchy \"miniUART:U1\|TxUnit:TxDev\"" { } { { "miniUART.vhd" "TxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 128 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RxUnit miniUART:U1\|RxUnit:RxDev " "Info: Elaborating entity \"RxUnit\" for hierarchy \"miniUART:U1\|RxUnit:RxDev\"" { } { { "miniUART.vhd" "RxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[0\]~6 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[0\]~6\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[1\]~7 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[1\]~7\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[2\]~5 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[2\]~5\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[3\]~4 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[3\]~4\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[4\]~3 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[4\]~3\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[5\]~2 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[5\]~2\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[6\]~1 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[6\]~1\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[7\]~0 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[7\]~0\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} } { } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 0 " "Warning: Ignored assignment(s) for \"CLOCK_27\[0\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 1 " "Warning: Ignored assignment(s) for \"CLOCK_27\[1\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "UART_TXD " "Warning: Inserted always-enabled tri-state buffer between \"UART_TXD\" and its non-tri-state driver." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} } { } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[0\] " "Warning: Bidir \"SRAM_DQ\[0\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[1\] " "Warning: Bidir \"SRAM_DQ\[1\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[2\] " "Warning: Bidir \"SRAM_DQ\[2\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[3\] " "Warning: Bidir \"SRAM_DQ\[3\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[4\] " "Warning: Bidir \"SRAM_DQ\[4\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[5\] " "Warning: Bidir \"SRAM_DQ\[5\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[6\] " "Warning: Bidir \"SRAM_DQ\[6\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[7\] " "Warning: Bidir \"SRAM_DQ\[7\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_DAT " "Warning: Bidir \"PS2_DAT\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_CLK " "Warning: Bidir \"PS2_CLK\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} } { } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS_HDR" "" "Warning: Removed fan-outs from the following always-disabled I/O buffers" { { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "UART_TXD UART_TXD " "Warning: Removed fan-out from the always-disabled I/O buffer \"UART_TXD\" to the node \"UART_TXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Removed fan-outs from the following always-disabled I/O buffers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[0\] GND " "Warning (13410): Pin \"HEX0\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[1\] GND " "Warning (13410): Pin \"HEX0\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[2\] GND " "Warning (13410): Pin \"HEX0\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[3\] GND " "Warning (13410): Pin \"HEX0\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[4\] GND " "Warning (13410): Pin \"HEX0\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[5\] GND " "Warning (13410): Pin \"HEX0\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[6\] GND " "Warning (13410): Pin \"HEX0\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[0\] GND " "Warning (13410): Pin \"HEX1\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[1\] GND " "Warning (13410): Pin \"HEX1\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[2\] GND " "Warning (13410): Pin \"HEX1\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[3\] GND " "Warning (13410): Pin \"HEX1\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[4\] GND " "Warning (13410): Pin \"HEX1\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[5\] GND " "Warning (13410): Pin \"HEX1\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[6\] GND " "Warning (13410): Pin \"HEX1\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[0\] GND " "Warning (13410): Pin \"HEX2\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[1\] GND " "Warning (13410): Pin \"HEX2\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[2\] GND " "Warning (13410): Pin \"HEX2\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[3\] GND " "Warning (13410): Pin \"HEX2\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[4\] GND " "Warning (13410): Pin \"HEX2\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[5\] GND " "Warning (13410): Pin \"HEX2\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[6\] GND " "Warning (13410): Pin \"HEX2\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[0\] GND " "Warning (13410): Pin \"HEX3\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[1\] GND " "Warning (13410): Pin \"HEX3\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[2\] GND " "Warning (13410): Pin \"HEX3\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[3\] GND " "Warning (13410): Pin \"HEX3\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[4\] GND " "Warning (13410): Pin \"HEX3\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[5\] GND " "Warning (13410): Pin \"HEX3\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[6\] GND " "Warning (13410): Pin \"HEX3\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[2\] GND " "Warning (13410): Pin \"LEDG\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[3\] GND " "Warning (13410): Pin \"LEDG\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[4\] GND " "Warning (13410): Pin \"LEDG\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[5\] GND " "Warning (13410): Pin \"LEDG\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[6\] GND " "Warning (13410): Pin \"LEDG\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[7\] GND " "Warning (13410): Pin \"LEDG\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[8\] GND " "Warning (13410): Pin \"LEDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[9\] GND " "Warning (13410): Pin \"LEDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[0\] GND " "Warning (13410): Pin \"DRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[1\] GND " "Warning (13410): Pin \"DRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[2\] GND " "Warning (13410): Pin \"DRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[3\] GND " "Warning (13410): Pin \"DRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[4\] GND " "Warning (13410): Pin \"DRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[5\] GND " "Warning (13410): Pin \"DRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[6\] GND " "Warning (13410): Pin \"DRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[7\] GND " "Warning (13410): Pin \"DRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[8\] GND " "Warning (13410): Pin \"DRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[9\] GND " "Warning (13410): Pin \"DRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[10\] GND " "Warning (13410): Pin \"DRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[11\] GND " "Warning (13410): Pin \"DRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_LDQM GND " "Warning (13410): Pin \"DRAM_LDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_UDQM GND " "Warning (13410): Pin \"DRAM_UDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_WE_N VCC " "Warning (13410): Pin \"DRAM_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CAS_N VCC " "Warning (13410): Pin \"DRAM_CAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_RAS_N VCC " "Warning (13410): Pin \"DRAM_RAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CS_N VCC " "Warning (13410): Pin \"DRAM_CS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_0 GND " "Warning (13410): Pin \"DRAM_BA_0\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_1 GND " "Warning (13410): Pin \"DRAM_BA_1\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CLK GND " "Warning (13410): Pin \"DRAM_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CKE GND " "Warning (13410): Pin \"DRAM_CKE\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[0\] GND " "Warning (13410): Pin \"FL_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[1\] GND " "Warning (13410): Pin \"FL_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[2\] GND " "Warning (13410): Pin \"FL_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[3\] GND " "Warning (13410): Pin \"FL_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[4\] GND " "Warning (13410): Pin \"FL_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[5\] GND " "Warning (13410): Pin \"FL_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[6\] GND " "Warning (13410): Pin \"FL_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[7\] GND " "Warning (13410): Pin \"FL_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[8\] GND " "Warning (13410): Pin \"FL_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[9\] GND " "Warning (13410): Pin \"FL_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[10\] GND " "Warning (13410): Pin \"FL_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[11\] GND " "Warning (13410): Pin \"FL_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[12\] GND " "Warning (13410): Pin \"FL_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[13\] GND " "Warning (13410): Pin \"FL_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[14\] GND " "Warning (13410): Pin \"FL_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[15\] GND " "Warning (13410): Pin \"FL_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[16\] GND " "Warning (13410): Pin \"FL_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[17\] GND " "Warning (13410): Pin \"FL_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[18\] GND " "Warning (13410): Pin \"FL_ADDR\[18\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[19\] GND " "Warning (13410): Pin \"FL_ADDR\[19\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[20\] GND " "Warning (13410): Pin \"FL_ADDR\[20\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[21\] GND " "Warning (13410): Pin \"FL_ADDR\[21\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_WE_N VCC " "Warning (13410): Pin \"FL_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_RST_N GND " "Warning (13410): Pin \"FL_RST_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_OE_N VCC " "Warning (13410): Pin \"FL_OE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_CE_N VCC " "Warning (13410): Pin \"FL_CE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[0\] GND " "Warning (13410): Pin \"SRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[1\] GND " "Warning (13410): Pin \"SRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[2\] GND " "Warning (13410): Pin \"SRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[3\] GND " "Warning (13410): Pin \"SRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[4\] GND " "Warning (13410): Pin \"SRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[5\] GND " "Warning (13410): Pin \"SRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[6\] GND " "Warning (13410): Pin \"SRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[7\] GND " "Warning (13410): Pin \"SRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[8\] GND " "Warning (13410): Pin \"SRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[9\] GND " "Warning (13410): Pin \"SRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[10\] GND " "Warning (13410): Pin \"SRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[11\] GND " "Warning (13410): Pin \"SRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[12\] GND " "Warning (13410): Pin \"SRAM_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[13\] GND " "Warning (13410): Pin \"SRAM_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[14\] GND " "Warning (13410): Pin \"SRAM_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[15\] GND " "Warning (13410): Pin \"SRAM_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[16\] GND " "Warning (13410): Pin \"SRAM_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[17\] GND " "Warning (13410): Pin \"SRAM_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_UB_N VCC " "Warning (13410): Pin \"SRAM_UB_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_LB_N GND " "Warning (13410): Pin \"SRAM_LB_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_WE_N GND " "Warning (13410): Pin \"SRAM_WE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_CE_N GND " "Warning (13410): Pin \"SRAM_CE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_OE_N GND " "Warning (13410): Pin \"SRAM_OE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_DAT3 GND " "Warning (13410): Pin \"SD_DAT3\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CMD GND " "Warning (13410): Pin \"SD_CMD\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CLK GND " "Warning (13410): Pin \"SD_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TDO GND " "Warning (13410): Pin \"TDO\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_HS GND " "Warning (13410): Pin \"VGA_HS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_VS GND " "Warning (13410): Pin \"VGA_VS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Warning (13410): Pin \"VGA_R\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Warning (13410): Pin \"VGA_R\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[2\] GND " "Warning (13410): Pin \"VGA_R\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[3\] GND " "Warning (13410): Pin \"VGA_R\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Warning (13410): Pin \"VGA_G\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Warning (13410): Pin \"VGA_G\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Warning (13410): Pin \"VGA_G\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Warning (13410): Pin \"VGA_G\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Warning (13410): Pin \"VGA_B\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Warning (13410): Pin \"VGA_B\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Warning (13410): Pin \"VGA_B\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Warning (13410): Pin \"VGA_B\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_DACDAT GND " "Warning (13410): Pin \"AUD_DACDAT\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_XCK GND " "Warning (13410): Pin \"AUD_XCK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "UART " "Warning: Ignored assignments for entity \"UART\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "16 " "Warning: Design contains 16 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_27 " "Warning (15610): No output dependent on input pin \"CLOCK_27\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "EXT_CLOCK " "Warning (15610): No output dependent on input pin \"EXT_CLOCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 16 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning (15610): No output dependent on input pin \"SW\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "IRDA_RXD " "Warning (15610): No output dependent on input pin \"IRDA_RXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SD_DAT " "Warning (15610): No output dependent on input pin \"SD_DAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TDI " "Warning (15610): No output dependent on input pin \"TDI\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 75 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCK " "Warning (15610): No output dependent on input pin \"TCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 76 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCS " "Warning (15610): No output dependent on input pin \"TCS\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 77 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_ADCDAT " "Warning (15610): No output dependent on input pin \"AUD_ADCDAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 97 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "448 " "Info: Implemented 448 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Info: Implemented 24 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "139 " "Info: Implemented 139 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "118 " "Info: Implemented 118 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "167 " "Info: Implemented 167 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 230 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 230 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:11:50 2010 " "Info: Processing ended: Sun Jan 10 17:11:50 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:11:52 2010 " "Info: Processing started: Sun Jan 10 17:11:52 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "uart EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"uart\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" { } { } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 281 " "Warning: No exact pin location assignment(s) for 7 pins of 281 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLOCK_27 " "Info: Pin CLOCK_27 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_27 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IRDA_RXD " "Info: Pin IRDA_RXD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { IRDA_RXD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { IRDA_RXD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FL_CE_N " "Info: Pin FL_CE_N not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Info: Pin SD_DAT not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Info: Pin SD_DAT3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Info: Pin SD_CMD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Info: Pin SD_CLK not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|Equal1~0 " "Info: Destination node miniUART:U1\|Equal1~0" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|Equal1~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|DataOut\[0\]_240 " "Info: Destination node miniUART:U1\|DataOut\[0\]_240" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|DataOut[0]_240 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SW[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.3V 3 4 0 " "Info: Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 3 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 40 1 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 32 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 26 17 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 17 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 36 4 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 4 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 36 3 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 3 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 31 5 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 35 5 " "Info: I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 41 2 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 2 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[0\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_27\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Node \"CLOCK_24\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Node \"CLOCK_24\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[0\] " "Warning: Node \"CLOCK_27\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Node \"CLOCK_27\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.370 ns register register " "Info: Estimated most critical path is register to register delay of 4.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LAB_X35_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y12; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.322 ns) 0.738 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LAB_X35_Y12 4 " "Info: 2: + IC(0.416 ns) + CELL(0.322 ns) = 0.738 ns; Loc. = LAB_X35_Y12; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.738 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 1.414 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LAB_X35_Y12 6 " "Info: 3: + IC(0.498 ns) + CELL(0.178 ns) = 1.414 ns; Loc. = LAB_X35_Y12; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.512 ns) 2.057 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LAB_X35_Y12 2 " "Info: 4: + IC(0.131 ns) + CELL(0.512 ns) = 2.057 ns; Loc. = LAB_X35_Y12; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.733 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LAB_X35_Y12 10 " "Info: 5: + IC(0.498 ns) + CELL(0.178 ns) = 2.733 ns; Loc. = LAB_X35_Y12; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.758 ns) 4.370 ns miniUART:U1\|RxUnit:RxDev\|frameErr 6 REG LAB_X35_Y10 2 " "Info: 6: + IC(0.879 ns) + CELL(0.758 ns) = 4.370 ns; Loc. = LAB_X35_Y10; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.637 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.948 ns ( 44.58 % ) " "Info: Total cell delay = 1.948 ns ( 44.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.422 ns ( 55.42 % ) " "Info: Total interconnect delay = 2.422 ns ( 55.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.370 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X25_Y0 X37_Y13 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X25_Y0 to location X37_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "257 " "Warning: Found 257 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_DAT 0 " "Info: Pin \"PS2_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_CLK 0 " "Info: Pin \"PS2_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "118 " "Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[0\] a permanently disabled " "Info: Pin SRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[1\] a permanently disabled " "Info: Pin SRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[2\] a permanently disabled " "Info: Pin SRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[3\] a permanently disabled " "Info: Pin SRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[4\] a permanently disabled " "Info: Pin SRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[5\] a permanently disabled " "Info: Pin SRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[6\] a permanently disabled " "Info: Pin SRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[7\] a permanently disabled " "Info: Pin SRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_DAT a permanently disabled " "Info: Pin PS2_DAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_CLK a permanently disabled " "Info: Pin PS2_CLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[0\] a permanently disabled " "Info: Pin DRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[1\] a permanently disabled " "Info: Pin DRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[2\] a permanently disabled " "Info: Pin DRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[3\] a permanently disabled " "Info: Pin DRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[4\] a permanently disabled " "Info: Pin DRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[5\] a permanently disabled " "Info: Pin DRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[6\] a permanently disabled " "Info: Pin DRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[7\] a permanently disabled " "Info: Pin DRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[8\] a permanently disabled " "Info: Pin DRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[9\] a permanently disabled " "Info: Pin DRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[10\] a permanently disabled " "Info: Pin DRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[11\] a permanently disabled " "Info: Pin DRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[12\] a permanently disabled " "Info: Pin DRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[13\] a permanently disabled " "Info: Pin DRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[14\] a permanently disabled " "Info: Pin DRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[15\] a permanently disabled " "Info: Pin DRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[0\] a permanently disabled " "Info: Pin FL_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[1\] a permanently disabled " "Info: Pin FL_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[2\] a permanently disabled " "Info: Pin FL_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[3\] a permanently disabled " "Info: Pin FL_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[4\] a permanently disabled " "Info: Pin FL_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[5\] a permanently disabled " "Info: Pin FL_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[6\] a permanently disabled " "Info: Pin FL_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[7\] a permanently disabled " "Info: Pin FL_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[8\] a permanently disabled " "Info: Pin SRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[9\] a permanently disabled " "Info: Pin SRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[10\] a permanently disabled " "Info: Pin SRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[11\] a permanently disabled " "Info: Pin SRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[12\] a permanently disabled " "Info: Pin SRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[13\] a permanently disabled " "Info: Pin SRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[14\] a permanently disabled " "Info: Pin SRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[15\] a permanently disabled " "Info: Pin SRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Info: Pin AUD_ADCLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Info: Pin AUD_DACLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "246 " "Warning: Following 246 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[0\] VCC " "Info: Pin SRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[1\] VCC " "Info: Pin SRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[2\] VCC " "Info: Pin SRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[3\] VCC " "Info: Pin SRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[4\] VCC " "Info: Pin SRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[5\] VCC " "Info: Pin SRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[6\] VCC " "Info: Pin SRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[7\] VCC " "Info: Pin SRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_DAT VCC " "Info: Pin PS2_DAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_CLK VCC " "Info: Pin PS2_CLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[0\] VCC " "Info: Pin DRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[1\] VCC " "Info: Pin DRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[2\] VCC " "Info: Pin DRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[3\] VCC " "Info: Pin DRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[4\] VCC " "Info: Pin DRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[5\] VCC " "Info: Pin DRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[6\] VCC " "Info: Pin DRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[7\] VCC " "Info: Pin DRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[8\] VCC " "Info: Pin DRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[9\] VCC " "Info: Pin DRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[10\] VCC " "Info: Pin DRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[11\] VCC " "Info: Pin DRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[12\] VCC " "Info: Pin DRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[13\] VCC " "Info: Pin DRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[14\] VCC " "Info: Pin DRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[15\] VCC " "Info: Pin DRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[0\] VCC " "Info: Pin FL_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[1\] VCC " "Info: Pin FL_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[2\] VCC " "Info: Pin FL_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[3\] VCC " "Info: Pin FL_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[4\] VCC " "Info: Pin FL_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[5\] VCC " "Info: Pin FL_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[6\] VCC " "Info: Pin FL_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[7\] VCC " "Info: Pin FL_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[8\] VCC " "Info: Pin SRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[9\] VCC " "Info: Pin SRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[10\] VCC " "Info: Pin SRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[11\] VCC " "Info: Pin SRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[12\] VCC " "Info: Pin SRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[13\] VCC " "Info: Pin SRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[14\] VCC " "Info: Pin SRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[15\] VCC " "Info: Pin SRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SDAT VCC " "Info: Pin I2C_SDAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_ADCLRCK VCC " "Info: Pin AUD_ADCLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACLRCK VCC " "Info: Pin AUD_DACLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[0\] GND " "Info: Pin HEX0\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[1\] GND " "Info: Pin HEX0\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[2\] GND " "Info: Pin HEX0\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[3\] GND " "Info: Pin HEX0\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[4\] GND " "Info: Pin HEX0\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[5\] GND " "Info: Pin HEX0\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[6\] GND " "Info: Pin HEX0\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[0\] GND " "Info: Pin HEX1\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[1\] GND " "Info: Pin HEX1\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[2\] GND " "Info: Pin HEX1\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[3\] GND " "Info: Pin HEX1\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[4\] GND " "Info: Pin HEX1\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[5\] GND " "Info: Pin HEX1\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[6\] GND " "Info: Pin HEX1\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[0\] GND " "Info: Pin HEX2\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[1\] GND " "Info: Pin HEX2\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[2\] GND " "Info: Pin HEX2\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[3\] GND " "Info: Pin HEX2\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[4\] GND " "Info: Pin HEX2\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[5\] GND " "Info: Pin HEX2\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[6\] GND " "Info: Pin HEX2\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[0\] GND " "Info: Pin HEX3\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[1\] GND " "Info: Pin HEX3\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[2\] GND " "Info: Pin HEX3\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[3\] GND " "Info: Pin HEX3\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[4\] GND " "Info: Pin HEX3\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[5\] GND " "Info: Pin HEX3\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[6\] GND " "Info: Pin HEX3\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[2\] GND " "Info: Pin LEDG\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[3\] GND " "Info: Pin LEDG\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[4\] GND " "Info: Pin LEDG\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[5\] GND " "Info: Pin LEDG\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[6\] GND " "Info: Pin LEDG\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[7\] GND " "Info: Pin LEDG\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[8\] GND " "Info: Pin LEDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[9\] GND " "Info: Pin LEDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[0\] GND " "Info: Pin DRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[1\] GND " "Info: Pin DRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[2\] GND " "Info: Pin DRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[3\] GND " "Info: Pin DRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[4\] GND " "Info: Pin DRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[5\] GND " "Info: Pin DRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[6\] GND " "Info: Pin DRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[7\] GND " "Info: Pin DRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[8\] GND " "Info: Pin DRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[9\] GND " "Info: Pin DRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[10\] GND " "Info: Pin DRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[11\] GND " "Info: Pin DRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_LDQM GND " "Info: Pin DRAM_LDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_LDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_LDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_UDQM GND " "Info: Pin DRAM_UDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_UDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_UDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_WE_N VCC " "Info: Pin DRAM_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CAS_N VCC " "Info: Pin DRAM_CAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_RAS_N VCC " "Info: Pin DRAM_RAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_RAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_RAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CS_N VCC " "Info: Pin DRAM_CS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_0 GND " "Info: Pin DRAM_BA_0 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_0 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_0 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_1 GND " "Info: Pin DRAM_BA_1 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_1 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_1 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CLK GND " "Info: Pin DRAM_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE GND " "Info: Pin DRAM_CKE has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CKE } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[0\] GND " "Info: Pin FL_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[1\] GND " "Info: Pin FL_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[2\] GND " "Info: Pin FL_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[3\] GND " "Info: Pin FL_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[4\] GND " "Info: Pin FL_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[5\] GND " "Info: Pin FL_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[6\] GND " "Info: Pin FL_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[7\] GND " "Info: Pin FL_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[8\] GND " "Info: Pin FL_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[9\] GND " "Info: Pin FL_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[10\] GND " "Info: Pin FL_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[11\] GND " "Info: Pin FL_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[12\] GND " "Info: Pin FL_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[13\] GND " "Info: Pin FL_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[14\] GND " "Info: Pin FL_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[15\] GND " "Info: Pin FL_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[16\] GND " "Info: Pin FL_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[17\] GND " "Info: Pin FL_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[18\] GND " "Info: Pin FL_ADDR\[18\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[19\] GND " "Info: Pin FL_ADDR\[19\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[20\] GND " "Info: Pin FL_ADDR\[20\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[21\] GND " "Info: Pin FL_ADDR\[21\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_WE_N VCC " "Info: Pin FL_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N GND " "Info: Pin FL_RST_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_RST_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_OE_N VCC " "Info: Pin FL_OE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_CE_N VCC " "Info: Pin FL_CE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[0\] GND " "Info: Pin SRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[1\] GND " "Info: Pin SRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[2\] GND " "Info: Pin SRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[3\] GND " "Info: Pin SRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[4\] GND " "Info: Pin SRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[5\] GND " "Info: Pin SRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[6\] GND " "Info: Pin SRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[7\] GND " "Info: Pin SRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[8\] GND " "Info: Pin SRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[9\] GND " "Info: Pin SRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[10\] GND " "Info: Pin SRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[11\] GND " "Info: Pin SRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[12\] GND " "Info: Pin SRAM_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[13\] GND " "Info: Pin SRAM_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[14\] GND " "Info: Pin SRAM_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[15\] GND " "Info: Pin SRAM_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[16\] GND " "Info: Pin SRAM_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[17\] GND " "Info: Pin SRAM_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_UB_N VCC " "Info: Pin SRAM_UB_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_UB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_LB_N GND " "Info: Pin SRAM_LB_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_LB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N GND " "Info: Pin SRAM_WE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N GND " "Info: Pin SRAM_CE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_CE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N GND " "Info: Pin SRAM_OE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 GND " "Info: Pin SD_DAT3 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD GND " "Info: Pin SD_CMD has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { TDO } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SCLK GND " "Info: Pin I2C_SCLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_HS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_VS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_XCK GND " "Info: Pin AUD_XCK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_XCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 15 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "205 " "Info: Peak virtual memory: 205 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:12:04 2010 " "Info: Processing ended: Sun Jan 10 17:12:04 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:12:07 2010 " "Info: Processing started: Sun Jan 10 17:12:07 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:12:11 2010 " "Info: Processing ended: Sun Jan 10 17:12:11 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:12:12 2010 " "Info: Processing started: Sun Jan 10 17:12:12 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[3\] " "Warning: Node \"miniUART:U1\|TxData\[3\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[7\] " "Warning: Node \"miniUART:U1\|TxData\[7\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[0\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]_240 " "Warning: Node \"miniUART:U1\|DataOut\[0\]_240\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[1\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[1\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[2\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[2\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[3\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[3\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[4\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[4\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[5\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[5\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[6\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[6\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[7\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[7\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[8\] " "Info: Assuming node \"SW\[8\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] register miniUART:U1\|RxUnit:RxDev\|outErr 217.53 MHz 4.597 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 217.53 MHz between source register \"miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]\" and destination register \"miniUART:U1\|RxUnit:RxDev\|outErr\" (period= 4.597 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.353 ns + Longest register register " "Info: + Longest register to register delay is 4.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LCFF_X35_Y12_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y12_N9; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.491 ns) 0.873 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LCCOMB_X35_Y12_N10 4 " "Info: 2: + IC(0.382 ns) + CELL(0.491 ns) = 0.873 ns; Loc. = LCCOMB_X35_Y12_N10; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.873 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.512 ns) 1.729 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LCCOMB_X35_Y12_N28 6 " "Info: 3: + IC(0.344 ns) + CELL(0.512 ns) = 1.729 ns; Loc. = LCCOMB_X35_Y12_N28; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.178 ns) 2.210 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LCCOMB_X35_Y12_N12 2 " "Info: 4: + IC(0.303 ns) + CELL(0.178 ns) = 2.210 ns; Loc. = LCCOMB_X35_Y12_N12; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.481 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.310 ns) + CELL(0.178 ns) 2.698 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LCCOMB_X35_Y12_N30 10 " "Info: 5: + IC(0.310 ns) + CELL(0.178 ns) = 2.698 ns; Loc. = LCCOMB_X35_Y12_N30; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.488 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.897 ns) + CELL(0.758 ns) 4.353 ns miniUART:U1\|RxUnit:RxDev\|outErr 6 REG LCFF_X35_Y10_N27 2 " "Info: 6: + IC(0.897 ns) + CELL(0.758 ns) = 4.353 ns; Loc. = LCFF_X35_Y10_N27; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|outErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.655 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.117 ns ( 48.63 % ) " "Info: Total cell delay = 2.117 ns ( 48.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.236 ns ( 51.37 % ) " "Info: Total interconnect delay = 2.236 ns ( 51.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.353 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.353 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|outErr {} } { 0.000ns 0.382ns 0.344ns 0.303ns 0.310ns 0.897ns } { 0.000ns 0.491ns 0.512ns 0.178ns 0.178ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.005 ns - Smallest " "Info: - Smallest clock skew is -0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.858 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 68 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 68; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns miniUART:U1\|RxUnit:RxDev\|outErr 3 REG LCFF_X35_Y10_N27 2 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X35_Y10_N27; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|outErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|outErr {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.863 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 68 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 68; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.602 ns) 2.863 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 3 REG LCFF_X35_Y12_N9 4 " "Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.863 ns; Loc. = LCFF_X35_Y12_N9; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.86 % ) " "Info: Total cell delay = 1.628 ns ( 56.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.235 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.235 ns ( 43.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.863 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.863 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|outErr {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.863 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.863 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.353 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.353 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|outErr {} } { 0.000ns 0.382ns 0.344ns 0.303ns 0.310ns 0.897ns } { 0.000ns 0.491ns 0.512ns 0.178ns 0.178ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|outErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|outErr {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.863 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.863 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "miniUART:U1\|TxUnit:TxDev\|TReg\[0\] KEY\[0\] CLOCK_50 6.412 ns register " "Info: tsu for register \"miniUART:U1\|TxUnit:TxDev\|TReg\[0\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 6.412 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.303 ns + Longest pin register " "Info: + Longest pin to register delay is 9.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 PIN PIN_R22 55 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 55; PIN Node = 'KEY\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.665 ns) + CELL(0.544 ns) 7.073 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35 2 COMB LCCOMB_X35_Y10_N16 3 " "Info: 2: + IC(5.665 ns) + CELL(0.544 ns) = 7.073 ns; Loc. = LCCOMB_X35_Y10_N16; Fanout = 3; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.209 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~35 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.319 ns) 7.696 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~36 3 COMB LCCOMB_X35_Y10_N2 6 " "Info: 3: + IC(0.304 ns) + CELL(0.319 ns) = 7.696 ns; Loc. = LCCOMB_X35_Y10_N2; Fanout = 6; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~36'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~36 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.758 ns) 9.303 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 4 REG LCFF_X34_Y9_N1 1 " "Info: 4: + IC(0.849 ns) + CELL(0.758 ns) = 9.303 ns; Loc. = LCFF_X34_Y9_N1; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.607 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~36 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.485 ns ( 26.71 % ) " "Info: Total cell delay = 2.485 ns ( 26.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.818 ns ( 73.29 % ) " "Info: Total interconnect delay = 6.818 ns ( 73.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.303 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~36 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.303 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~36 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.665ns 0.304ns 0.849ns } { 0.000ns 0.864ns 0.544ns 0.319ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.853 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 68 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 68; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 3 REG LCFF_X34_Y9_N1 1 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X34_Y9_N1; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.303 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~36 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.303 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~36 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.665ns 0.304ns 0.849ns } { 0.000ns 0.864ns 0.544ns 0.319ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 UART_TXD miniUART:U1\|TxUnit:TxDev\|TxD 8.380 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"UART_TXD\" through register \"miniUART:U1\|TxUnit:TxDev\|TxD\" is 8.380 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.856 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 68 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 68; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.602 ns) 2.856 ns miniUART:U1\|TxUnit:TxDev\|TxD 3 REG LCFF_X32_Y10_N17 2 " "Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 2.856 ns; Loc. = LCFF_X32_Y10_N17; Fanout = 2; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TxD'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TxD } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 47 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.00 % ) " "Info: Total cell delay = 1.628 ns ( 57.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.228 ns ( 43.00 % ) " "Info: Total interconnect delay = 1.228 ns ( 43.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TxD } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TxD {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 47 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.247 ns + Longest register pin " "Info: + Longest register to pin delay is 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|TxUnit:TxDev\|TxD 1 REG LCFF_X32_Y10_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N17; Fanout = 2; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TxD'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|TxUnit:TxDev|TxD } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 47 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.271 ns) + CELL(2.976 ns) 5.247 ns UART_TXD 2 PIN PIN_G12 0 " "Info: 2: + IC(2.271 ns) + CELL(2.976 ns) = 5.247 ns; Loc. = PIN_G12; Fanout = 0; PIN Node = 'UART_TXD'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { miniUART:U1|TxUnit:TxDev|TxD UART_TXD } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.976 ns ( 56.72 % ) " "Info: Total cell delay = 2.976 ns ( 56.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.271 ns ( 43.28 % ) " "Info: Total interconnect delay = 2.271 ns ( 43.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { miniUART:U1|TxUnit:TxDev|TxD UART_TXD } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.247 ns" { miniUART:U1|TxUnit:TxDev|TxD {} UART_TXD {} } { 0.000ns 2.271ns } { 0.000ns 2.976ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TxD } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TxD {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { miniUART:U1|TxUnit:TxDev|TxD UART_TXD } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.247 ns" { miniUART:U1|TxUnit:TxDev|TxD {} UART_TXD {} } { 0.000ns 2.271ns } { 0.000ns 2.976ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "miniUART:U1\|RxUnit:RxDev\|tmpDRdy SW\[1\] CLOCK_50 0.249 ns register " "Info: th for register \"miniUART:U1\|RxUnit:RxDev\|tmpDRdy\" (data pin = \"SW\[1\]\", clock pin = \"CLOCK_50\") is 0.249 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.858 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 68 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 68; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X35_Y10_N1 3 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X35_Y10_N1; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.895 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[1\] 1 PIN PIN_L21 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L21; Fanout = 2; PIN Node = 'SW\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.521 ns) 2.799 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11 2 COMB LCCOMB_X35_Y10_N0 1 " "Info: 2: + IC(1.252 ns) + CELL(0.521 ns) = 2.799 ns; Loc. = LCCOMB_X35_Y10_N0; Fanout = 1; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.773 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.895 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X35_Y10_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.895 ns; Loc. = LCFF_X35_Y10_N1; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 56.75 % ) " "Info: Total cell delay = 1.643 ns ( 56.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.252 ns ( 43.25 % ) " "Info: Total interconnect delay = 1.252 ns ( 43.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.252ns 0.000ns } { 0.000ns 1.026ns 0.521ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.252ns 0.000ns } { 0.000ns 1.026ns 0.521ns 0.096ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 13 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Peak virtual memory: 136 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:12:13 2010 " "Info: Processing ended: Sun Jan 10 17:12:13 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 258 s " "Info: Quartus II Full Compilation was successful. 0 errors, 258 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.ecobp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.ecobp
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.ecobp (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.ecobp (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.ecobp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.ecobp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.ecobp
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.ecobp (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.ecobp (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.ecobp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv_sg.cdb
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rpp.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rpp.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rpp.qmsg (revision 6)
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II " "Info: Running Quartus II Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 09 22:57:37 2010 " "Info: Processing started: Sat Jan 09 22:57:37 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp uart -c uart --netlist_type=sgate " "Info: Command: quartus_rpp uart -c uart --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II " "Info: Quartus II Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Peak virtual memory: 113 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 09 22:57:37 2010 " "Info: Processing ended: Sat Jan 09 22:57:37 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.hdb
Property changes :
Added: svn:mime-type
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+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(2).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.map.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.map.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.map.qmsg (revision 6)
@@ -0,0 +1,98 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:21:19 2010 " "Info: Processing started: Sun Jan 10 17:21:19 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder_7seg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder_7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder_7seg-rtl " "Info: Found design unit 1: decoder_7seg-rtl" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 13 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 decoder_7seg " "Info: Found entity 1: decoder_7seg" { } { { "decoder_7seg.vhd" "" { Text "C:/altera/cores/vhdl/uart/decoder_7seg.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-Behaviour " "Info: Found design unit 1: UART-Behaviour" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 57 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" { } { { "uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart.vhd" 36 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClkUnit-Behaviour " "Info: Found design unit 1: ClkUnit-Behaviour" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 52 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 ClkUnit " "Info: Found entity 1: ClkUnit" { } { { "clkUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/clkUnit.vhd" 42 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "miniUART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file miniUART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 miniUART-uart " "Info: Found design unit 1: miniUART-uart" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 63 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 miniUART " "Info: Found entity 1: miniUART" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 45 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RxUnit-Behaviour " "Info: Found design unit 1: RxUnit-Behaviour" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 58 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 RxUnit " "Info: Found entity 1: RxUnit" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 43 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_uart.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top_uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TOP_UART-rtl " "Info: Found design unit 1: TOP_UART-rtl" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 109 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TOP_UART " "Info: Found entity 1: TOP_UART" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 10 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TxUnit-Behaviour " "Info: Found design unit 1: TxUnit-Behaviour" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 55 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 TxUnit " "Info: Found entity 1: TxUnit" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 41 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_lib.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_Def " "Info: Found design unit 1: UART_Def" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 35 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_Def-body " "Info: Found design unit 2: UART_Def-body" { } { { "uart_lib.vhd" "" { Text "C:/altera/cores/vhdl/uart/uart_lib.vhd" 45 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top_uart " "Info: Elaborating entity \"top_uart\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX0 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX0\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX1 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX1\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX2 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX2\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "HEX3 top_uart.vhd(23) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal \"HEX3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_WE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_WE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SRAM_OE_N top_uart.vhd(62) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal \"SRAM_OE_N\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_DAT3 top_uart.vhd(70) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(70): used implicit default value for signal \"SD_DAT3\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CMD top_uart.vhd(71) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(71): used implicit default value for signal \"SD_CMD\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SD_CLK top_uart.vhd(72) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(72): used implicit default value for signal \"SD_CLK\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_HS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_HS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_VS top_uart.vhd(89) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal \"VGA_VS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_R top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_R\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_G top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_G\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "VGA_B top_uart.vhd(91) " "Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal \"VGA_B\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[7\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[7\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[6\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[6\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[5\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[5\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[4\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[4\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[3\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[3\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDG\[2\] top_uart.vhd(25) " "Warning (10873): Using initial value X (don't care) for net \"LEDG\[2\]\" at top_uart.vhd(25)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[9\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[9\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[8\] top_uart.vhd(26) " "Warning (10873): Using initial value X (don't care) for net \"LEDR\[8\]\" at top_uart.vhd(26)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[15\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[15\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[14\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[14\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[13\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[13\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[12\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[12\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[11\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[11\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[10\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[10\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[9\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[9\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[8\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[8\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[7\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[7\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[6\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[6\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[5\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[5\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[4\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[4\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[3\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[3\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[2\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[2\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[1\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[1\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SRAM_ADDR\[0\] top_uart.vhd(61) " "Warning (10873): Using initial value X (don't care) for net \"SRAM_ADDR\[0\]\" at top_uart.vhd(61)" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "miniUART miniUART:U1 " "Info: Elaborating entity \"miniUART\" for hierarchy \"miniUART:U1\"" { } { { "top_uart.vhd" "U1" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N miniUART.vhd(180) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 180 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"CS_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR_N miniUART.vhd(185) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal \"WR_N\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 185 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(190) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(190): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 190 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(192) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 192 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RxData miniUART.vhd(193) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(193): signal \"RxData\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 193 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Read miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Read\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(194) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 194 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CSReg miniUART.vhd(195) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(195): signal \"CSReg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 195 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(198) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(198): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 198 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Load miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Addr miniUART.vhd(200) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal \"Addr\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DataIn miniUART.vhd(201) " "Warning (10492): VHDL Process Statement warning at miniUART.vhd(201): signal \"DataIn\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 201 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataOut miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"DataOut\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TxData miniUART.vhd(178) " "Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable \"TxData\", which holds its previous value in one or more paths through the process" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TxData\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"TxData\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[0\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[0\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[1\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[1\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[2\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[2\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[3\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[3\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[4\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[4\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[5\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[5\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[6\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[6\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DataOut\[7\] miniUART.vhd(178) " "Info (10041): Inferred latch for \"DataOut\[7\]\" at miniUART.vhd(178)" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ClkUnit miniUART:U1\|ClkUnit:ClkDiv " "Info: Elaborating entity \"ClkUnit\" for hierarchy \"miniUART:U1\|ClkUnit:ClkDiv\"" { } { { "miniUART.vhd" "ClkDiv" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 127 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TxUnit miniUART:U1\|TxUnit:TxDev " "Info: Elaborating entity \"TxUnit\" for hierarchy \"miniUART:U1\|TxUnit:TxDev\"" { } { { "miniUART.vhd" "TxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 128 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RxUnit miniUART:U1\|RxUnit:RxDev " "Info: Elaborating entity \"RxUnit\" for hierarchy \"miniUART:U1\|RxUnit:RxDev\"" { } { { "miniUART.vhd" "RxDev" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 129 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[0\]~6 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[0\]~6\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[1\]~7 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[1\]~7\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[2\]~5 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[2\]~5\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[3\]~4 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[3\]~4\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[4\]~3 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[4\]~3\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[5\]~2 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[5\]~2\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[6\]~1 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[6\]~1\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "miniUART:U1\|TxData\[7\]~0 " "Warning: Converted tri-state buffer \"miniUART:U1\|TxData\[7\]~0\" feeding internal logic into a wire" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} } { } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 0 " "Warning: Ignored assignment(s) for \"CLOCK_27\[0\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WSGN_INVALID_MEMBER_ASSIGNMENT" "CLOCK_27 1 " "Warning: Ignored assignment(s) for \"CLOCK_27\[1\]\" because \"CLOCK_27\" is not a bus or array" { } { { "top_uart.vhd" "CLOCK_27" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 0 "Ignored assignment(s) for \"%1!s!\[%2!d!\]\" because \"%1!s!\" is not a bus or array" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "UART_TXD " "Warning: Inserted always-enabled tri-state buffer between \"UART_TXD\" and its non-tri-state driver." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} } { } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "Warning: The following bidir pins have no drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[0\] " "Warning: Bidir \"SRAM_DQ\[0\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[1\] " "Warning: Bidir \"SRAM_DQ\[1\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[2\] " "Warning: Bidir \"SRAM_DQ\[2\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[3\] " "Warning: Bidir \"SRAM_DQ\[3\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[4\] " "Warning: Bidir \"SRAM_DQ\[4\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[5\] " "Warning: Bidir \"SRAM_DQ\[5\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[6\] " "Warning: Bidir \"SRAM_DQ\[6\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SRAM_DQ\[7\] " "Warning: Bidir \"SRAM_DQ\[7\]\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_DAT " "Warning: Bidir \"PS2_DAT\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "PS2_CLK " "Warning: Bidir \"PS2_CLK\" has no driver" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } } 0 0 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1} } { } 0 0 "The following bidir pins have no drivers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS_HDR" "" "Warning: Removed fan-outs from the following always-disabled I/O buffers" { { "Warning" "WOPT_OPT_REMOVED_FANIN_FROM_ALWAYS_DISABLED_IO_BUF_TO_TRI_BUS" "UART_TXD UART_TXD " "Warning: Removed fan-out from the always-disabled I/O buffer \"UART_TXD\" to the node \"UART_TXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 29 -1 0 } } } 0 0 "Removed fan-out from the always-disabled I/O buffer \"%1!s!\" to the node \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Removed fan-outs from the following always-disabled I/O buffers" 0 0 "" 0 -1}
+{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[0\] GND " "Warning (13410): Pin \"HEX0\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[1\] GND " "Warning (13410): Pin \"HEX0\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[2\] GND " "Warning (13410): Pin \"HEX0\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[3\] GND " "Warning (13410): Pin \"HEX0\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[4\] GND " "Warning (13410): Pin \"HEX0\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[5\] GND " "Warning (13410): Pin \"HEX0\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX0\[6\] GND " "Warning (13410): Pin \"HEX0\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[0\] GND " "Warning (13410): Pin \"HEX1\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[1\] GND " "Warning (13410): Pin \"HEX1\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[2\] GND " "Warning (13410): Pin \"HEX1\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[3\] GND " "Warning (13410): Pin \"HEX1\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[4\] GND " "Warning (13410): Pin \"HEX1\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[5\] GND " "Warning (13410): Pin \"HEX1\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX1\[6\] GND " "Warning (13410): Pin \"HEX1\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[0\] GND " "Warning (13410): Pin \"HEX2\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[1\] GND " "Warning (13410): Pin \"HEX2\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[2\] GND " "Warning (13410): Pin \"HEX2\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[3\] GND " "Warning (13410): Pin \"HEX2\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[4\] GND " "Warning (13410): Pin \"HEX2\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[5\] GND " "Warning (13410): Pin \"HEX2\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX2\[6\] GND " "Warning (13410): Pin \"HEX2\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[0\] GND " "Warning (13410): Pin \"HEX3\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[1\] GND " "Warning (13410): Pin \"HEX3\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[2\] GND " "Warning (13410): Pin \"HEX3\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[3\] GND " "Warning (13410): Pin \"HEX3\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[4\] GND " "Warning (13410): Pin \"HEX3\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[5\] GND " "Warning (13410): Pin \"HEX3\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[6\] GND " "Warning (13410): Pin \"HEX3\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[2\] GND " "Warning (13410): Pin \"LEDG\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[3\] GND " "Warning (13410): Pin \"LEDG\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[4\] GND " "Warning (13410): Pin \"LEDG\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[5\] GND " "Warning (13410): Pin \"LEDG\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[6\] GND " "Warning (13410): Pin \"LEDG\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[7\] GND " "Warning (13410): Pin \"LEDG\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[8\] GND " "Warning (13410): Pin \"LEDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[9\] GND " "Warning (13410): Pin \"LEDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[0\] GND " "Warning (13410): Pin \"DRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[1\] GND " "Warning (13410): Pin \"DRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[2\] GND " "Warning (13410): Pin \"DRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[3\] GND " "Warning (13410): Pin \"DRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[4\] GND " "Warning (13410): Pin \"DRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[5\] GND " "Warning (13410): Pin \"DRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[6\] GND " "Warning (13410): Pin \"DRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[7\] GND " "Warning (13410): Pin \"DRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[8\] GND " "Warning (13410): Pin \"DRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[9\] GND " "Warning (13410): Pin \"DRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[10\] GND " "Warning (13410): Pin \"DRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_ADDR\[11\] GND " "Warning (13410): Pin \"DRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_LDQM GND " "Warning (13410): Pin \"DRAM_LDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_UDQM GND " "Warning (13410): Pin \"DRAM_UDQM\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_WE_N VCC " "Warning (13410): Pin \"DRAM_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CAS_N VCC " "Warning (13410): Pin \"DRAM_CAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_RAS_N VCC " "Warning (13410): Pin \"DRAM_RAS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CS_N VCC " "Warning (13410): Pin \"DRAM_CS_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_0 GND " "Warning (13410): Pin \"DRAM_BA_0\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_BA_1 GND " "Warning (13410): Pin \"DRAM_BA_1\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CLK GND " "Warning (13410): Pin \"DRAM_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DRAM_CKE GND " "Warning (13410): Pin \"DRAM_CKE\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[0\] GND " "Warning (13410): Pin \"FL_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[1\] GND " "Warning (13410): Pin \"FL_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[2\] GND " "Warning (13410): Pin \"FL_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[3\] GND " "Warning (13410): Pin \"FL_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[4\] GND " "Warning (13410): Pin \"FL_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[5\] GND " "Warning (13410): Pin \"FL_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[6\] GND " "Warning (13410): Pin \"FL_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[7\] GND " "Warning (13410): Pin \"FL_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[8\] GND " "Warning (13410): Pin \"FL_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[9\] GND " "Warning (13410): Pin \"FL_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[10\] GND " "Warning (13410): Pin \"FL_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[11\] GND " "Warning (13410): Pin \"FL_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[12\] GND " "Warning (13410): Pin \"FL_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[13\] GND " "Warning (13410): Pin \"FL_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[14\] GND " "Warning (13410): Pin \"FL_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[15\] GND " "Warning (13410): Pin \"FL_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[16\] GND " "Warning (13410): Pin \"FL_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[17\] GND " "Warning (13410): Pin \"FL_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[18\] GND " "Warning (13410): Pin \"FL_ADDR\[18\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[19\] GND " "Warning (13410): Pin \"FL_ADDR\[19\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[20\] GND " "Warning (13410): Pin \"FL_ADDR\[20\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_ADDR\[21\] GND " "Warning (13410): Pin \"FL_ADDR\[21\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_WE_N VCC " "Warning (13410): Pin \"FL_WE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_RST_N GND " "Warning (13410): Pin \"FL_RST_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_OE_N VCC " "Warning (13410): Pin \"FL_OE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FL_CE_N VCC " "Warning (13410): Pin \"FL_CE_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[0\] GND " "Warning (13410): Pin \"SRAM_ADDR\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[1\] GND " "Warning (13410): Pin \"SRAM_ADDR\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[2\] GND " "Warning (13410): Pin \"SRAM_ADDR\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[3\] GND " "Warning (13410): Pin \"SRAM_ADDR\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[4\] GND " "Warning (13410): Pin \"SRAM_ADDR\[4\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[5\] GND " "Warning (13410): Pin \"SRAM_ADDR\[5\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[6\] GND " "Warning (13410): Pin \"SRAM_ADDR\[6\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[7\] GND " "Warning (13410): Pin \"SRAM_ADDR\[7\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[8\] GND " "Warning (13410): Pin \"SRAM_ADDR\[8\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[9\] GND " "Warning (13410): Pin \"SRAM_ADDR\[9\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[10\] GND " "Warning (13410): Pin \"SRAM_ADDR\[10\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[11\] GND " "Warning (13410): Pin \"SRAM_ADDR\[11\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[12\] GND " "Warning (13410): Pin \"SRAM_ADDR\[12\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[13\] GND " "Warning (13410): Pin \"SRAM_ADDR\[13\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[14\] GND " "Warning (13410): Pin \"SRAM_ADDR\[14\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[15\] GND " "Warning (13410): Pin \"SRAM_ADDR\[15\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[16\] GND " "Warning (13410): Pin \"SRAM_ADDR\[16\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_ADDR\[17\] GND " "Warning (13410): Pin \"SRAM_ADDR\[17\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_UB_N VCC " "Warning (13410): Pin \"SRAM_UB_N\" is stuck at VCC" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_LB_N GND " "Warning (13410): Pin \"SRAM_LB_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_WE_N GND " "Warning (13410): Pin \"SRAM_WE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_CE_N GND " "Warning (13410): Pin \"SRAM_CE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_OE_N GND " "Warning (13410): Pin \"SRAM_OE_N\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_DAT3 GND " "Warning (13410): Pin \"SD_DAT3\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CMD GND " "Warning (13410): Pin \"SD_CMD\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SD_CLK GND " "Warning (13410): Pin \"SD_CLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TDO GND " "Warning (13410): Pin \"TDO\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "I2C_SCLK GND " "Warning (13410): Pin \"I2C_SCLK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_HS GND " "Warning (13410): Pin \"VGA_HS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_VS GND " "Warning (13410): Pin \"VGA_VS\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Warning (13410): Pin \"VGA_R\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Warning (13410): Pin \"VGA_R\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[2\] GND " "Warning (13410): Pin \"VGA_R\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_R\[3\] GND " "Warning (13410): Pin \"VGA_R\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Warning (13410): Pin \"VGA_G\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Warning (13410): Pin \"VGA_G\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Warning (13410): Pin \"VGA_G\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Warning (13410): Pin \"VGA_G\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Warning (13410): Pin \"VGA_B\[0\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Warning (13410): Pin \"VGA_B\[1\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Warning (13410): Pin \"VGA_B\[2\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Warning (13410): Pin \"VGA_B\[3\]\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_DACDAT GND " "Warning (13410): Pin \"AUD_DACDAT\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "AUD_XCK GND " "Warning (13410): Pin \"AUD_XCK\" is stuck at GND" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "UART " "Warning: Ignored assignments for entity \"UART\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id \"Root Region\" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "16 " "Warning: Design contains 16 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_27 " "Warning (15610): No output dependent on input pin \"CLOCK_27\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "EXT_CLOCK " "Warning (15610): No output dependent on input pin \"EXT_CLOCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 16 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning (15610): No output dependent on input pin \"SW\[3\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "IRDA_RXD " "Warning (15610): No output dependent on input pin \"IRDA_RXD\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SD_DAT " "Warning (15610): No output dependent on input pin \"SD_DAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TDI " "Warning (15610): No output dependent on input pin \"TDI\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 75 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCK " "Warning (15610): No output dependent on input pin \"TCK\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 76 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "TCS " "Warning (15610): No output dependent on input pin \"TCS\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 77 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "AUD_ADCDAT " "Warning (15610): No output dependent on input pin \"AUD_ADCDAT\"" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 97 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "451 " "Info: Implemented 451 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Info: Implemented 24 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "139 " "Info: Implemented 139 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "118 " "Info: Implemented 118 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "170 " "Info: Implemented 170 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 230 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 230 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:21:23 2010 " "Info: Processing ended: Sun Jan 10 17:21:23 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.hdb
===================================================================
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svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.pre_map.hdb
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(0).cnf.hdb
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## -0,0 +1 ##
+application/octet-stream
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.cdb
===================================================================
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(6).cnf.cdb
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.rdb
===================================================================
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.rdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.rdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.rdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.rdb
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## -0,0 +1 ##
+application/octet-stream
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(4).cnf.hdb
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.tdb
===================================================================
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.tdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.tdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.tdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.tdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tis_db_list.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tis_db_list.ddb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tis_db_list.ddb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tis_db_list.ddb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tis_db_list.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(8).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.bpm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.bpm
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.bpm (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.bpm (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.bpm
Property changes :
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+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.bpm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.bpm
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.bpm (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.bpm (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.cmp.bpm
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.logdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.logdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.logdb (revision 6)
@@ -0,0 +1 @@
+v1
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hif
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hif (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.hif (revision 6)
@@ -0,0 +1,415 @@
+Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+11
+980
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+clk_div
+# storage
+db|uart.(1).cnf
+db|uart.(1).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+clk_div.vhd
+8d4021dfa58093e628a0fcd0f12c5e6c
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+decoder_7seg
+# storage
+db|uart.(3).cnf
+db|uart.(3).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+decoder_7seg.vhd
+21bfa49b85795d3ea5ab4287c1b509a
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+ constraint(number)
+3 downto 0
+PARAMETER_STRING
+USR
+ constraint(hex_disp)
+6 downto 0
+PARAMETER_STRING
+USR
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+miniUART
+# storage
+db|uart.(4).cnf
+db|uart.(4).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+miniUART.vhd
+61d37d24db63b96146af42b61f5f47
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+ constraint(addr)
+1 downto 0
+PARAMETER_STRING
+USR
+ constraint(datain)
+7 downto 0
+PARAMETER_STRING
+USR
+ constraint(dataout)
+7 downto 0
+PARAMETER_STRING
+USR
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# hierarchies {
+miniUART:U1
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+TxUnit
+# storage
+db|uart.(6).cnf
+db|uart.(6).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+TxUnit.vhd
+8242cf419679a982787d42686fe7647
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+ constraint(datao)
+7 downto 0
+PARAMETER_STRING
+USR
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# hierarchies {
+miniUART:U1|TxUnit:TxDev
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+RxUnit
+# storage
+db|uart.(7).cnf
+db|uart.(7).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+RxUnit.vhd
+dc8e76a7347ab43ebbefea7aedd6f5
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+ constraint(datain)
+7 downto 0
+PARAMETER_STRING
+USR
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# hierarchies {
+miniUART:U1|RxUnit:RxDev
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+TxUnit
+# storage
+db|uart.(9).cnf
+db|uart.(9).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+TxUnit.vhd
+8242cf419679a982787d42686fe7647
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+RxUnit
+# storage
+db|uart.(10).cnf
+db|uart.(10).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+RxUnit.vhd
+dc8e76a7347ab43ebbefea7aedd6f5
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+UART
+# storage
+db|uart.(8).cnf
+db|uart.(8).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+uart.vhd
+7b4bd997dca5c87516a6fe50a95d8b
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+brdivisor
+1302
+PARAMETER_SIGNED_DEC
+USR
+ constraint(wb_adr_i)
+1 downto 0
+PARAMETER_STRING
+USR
+ constraint(wb_dat_i)
+7 downto 0
+PARAMETER_STRING
+USR
+ constraint(wb_dat_o)
+7 downto 0
+PARAMETER_STRING
+USR
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+ClkUnit
+# storage
+db|uart.(2).cnf
+db|uart.(2).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+clkUnit.vhd
+dd57d2fade732dba78887ed762c1a44
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# include_file {
+uart_lib.vhd
+8cf118e5fffb90b86bbf25c5e65dfacc
+}
+# hierarchies {
+miniUART:U1|ClkUnit:ClkDiv
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+top_uart
+# storage
+db|uart.(0).cnf
+db|uart.(0).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+top_uart.vhd
+f8c7f5d44e2383c0ee1e674e7f28cf8
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# hierarchies {
+|
+}
+# lmf
+..|..|..|90sp2|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# complete
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm_labs.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm_labs.ddb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm_labs.ddb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm_labs.ddb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.asm_labs.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map_bb.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(3).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.html
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.html (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.html (revision 6)
@@ -0,0 +1,82 @@
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.asm.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.asm.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/prev_cmp_uart.asm.qmsg (revision 6)
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 17:21:36 2010 " "Info: Processing started: Sun Jan 10 17:21:36 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 17:21:39 2010 " "Info: Processing ended: Sun Jan 10 17:21:39 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.hdb (revision 6)
| Hierarchy | +Input | +Constant Input | +Unused Input | +Floating Input | +Output | +Constant Output | +Unused Output | +Floating Output | +Bidir | +Constant Bidir | +Unused Bidir | +Input only Bidir | +Output only Bidir | +
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| U1|RxDev | +5 | +0 | +0 | +0 | +11 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +
| U1|TxDev | +12 | +0 | +0 | +0 | +3 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +
| U1|ClkDiv | +2 | +0 | +0 | +0 | +2 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +
| U1 | +16 | +8 | +0 | +8 | +11 | +8 | +8 | +8 | +0 | +0 | +0 | +0 | +0 | +
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(1).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tmw_info
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tmw_info (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tmw_info (revision 6)
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:23
+start_analysis_synthesis:s:00:00:06-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:11-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.rtlv.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(7).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.rdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.rdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.rdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.rdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.lpc.rdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.fit.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.fit.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.fit.qmsg (revision 6)
@@ -0,0 +1,45 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 16 19:25:47 2010 " "Info: Processing started: Sat Jan 16 19:25:47 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "uart EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"uart\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is not available with your current license" { } { } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 281 " "Warning: No exact pin location assignment(s) for 7 pins of 281 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLOCK_27 " "Info: Pin CLOCK_27 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_27 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 14 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IRDA_RXD " "Info: Pin IRDA_RXD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { IRDA_RXD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 35 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { IRDA_RXD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FL_CE_N " "Info: Pin FL_CE_N not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Info: Pin SD_DAT not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 69 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Info: Pin SD_DAT3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Info: Pin SD_CMD not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Info: Pin SD_CLK not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node SW\[8\] (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|Equal1~0 " "Info: Destination node miniUART:U1\|Equal1~0" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 200 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|Equal1~0 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "miniUART:U1\|DataOut\[0\]_240 " "Info: Destination node miniUART:U1\|DataOut\[0\]_240" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|DataOut[0]_240 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SW[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.3V 3 4 0 " "Info: Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 3 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 40 1 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 32 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 1 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 26 17 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 17 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 36 4 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 4 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 36 3 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 3 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 31 5 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 35 5 " "Info: I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used -- 5 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 41 2 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 2 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[0\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_27\[1\]\"" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Node \"CLOCK_24\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Node \"CLOCK_24\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[0\] " "Warning: Node \"CLOCK_27\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Node \"CLOCK_27\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.384 ns register register " "Info: Estimated most critical path is register to register delay of 4.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LAB_X39_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X39_Y14; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.322 ns) 0.738 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LAB_X39_Y14 4 " "Info: 2: + IC(0.416 ns) + CELL(0.322 ns) = 0.738 ns; Loc. = LAB_X39_Y14; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.738 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 1.414 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LAB_X39_Y14 6 " "Info: 3: + IC(0.498 ns) + CELL(0.178 ns) = 1.414 ns; Loc. = LAB_X39_Y14; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.512 ns) 2.057 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LAB_X39_Y14 2 " "Info: 4: + IC(0.131 ns) + CELL(0.512 ns) = 2.057 ns; Loc. = LAB_X39_Y14; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.733 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LAB_X39_Y14 10 " "Info: 5: + IC(0.498 ns) + CELL(0.178 ns) = 2.733 ns; Loc. = LAB_X39_Y14; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.758 ns) 4.384 ns miniUART:U1\|RxUnit:RxDev\|frameErr 6 REG LAB_X39_Y11 2 " "Info: 6: + IC(0.893 ns) + CELL(0.758 ns) = 4.384 ns; Loc. = LAB_X39_Y11; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.651 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.948 ns ( 44.43 % ) " "Info: Total cell delay = 1.948 ns ( 44.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.436 ns ( 55.57 % ) " "Info: Total interconnect delay = 2.436 ns ( 55.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.384 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X38_Y0 X50_Y13 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y0 to location X50_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "257 " "Warning: Found 257 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_DAT 0 " "Info: Pin \"PS2_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_CLK 0 " "Info: Pin \"PS2_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "118 " "Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[0\] a permanently disabled " "Info: Pin SRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[1\] a permanently disabled " "Info: Pin SRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[2\] a permanently disabled " "Info: Pin SRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[3\] a permanently disabled " "Info: Pin SRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[4\] a permanently disabled " "Info: Pin SRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[5\] a permanently disabled " "Info: Pin SRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[6\] a permanently disabled " "Info: Pin SRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[7\] a permanently disabled " "Info: Pin SRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_DAT a permanently disabled " "Info: Pin PS2_DAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_CLK a permanently disabled " "Info: Pin PS2_CLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[0\] a permanently disabled " "Info: Pin DRAM_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[1\] a permanently disabled " "Info: Pin DRAM_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[2\] a permanently disabled " "Info: Pin DRAM_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[3\] a permanently disabled " "Info: Pin DRAM_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[4\] a permanently disabled " "Info: Pin DRAM_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[5\] a permanently disabled " "Info: Pin DRAM_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[6\] a permanently disabled " "Info: Pin DRAM_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[7\] a permanently disabled " "Info: Pin DRAM_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[8\] a permanently disabled " "Info: Pin DRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[9\] a permanently disabled " "Info: Pin DRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[10\] a permanently disabled " "Info: Pin DRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[11\] a permanently disabled " "Info: Pin DRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[12\] a permanently disabled " "Info: Pin DRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[13\] a permanently disabled " "Info: Pin DRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[14\] a permanently disabled " "Info: Pin DRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[15\] a permanently disabled " "Info: Pin DRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[0\] a permanently disabled " "Info: Pin FL_DQ\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[1\] a permanently disabled " "Info: Pin FL_DQ\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[2\] a permanently disabled " "Info: Pin FL_DQ\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[3\] a permanently disabled " "Info: Pin FL_DQ\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[4\] a permanently disabled " "Info: Pin FL_DQ\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[5\] a permanently disabled " "Info: Pin FL_DQ\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[6\] a permanently disabled " "Info: Pin FL_DQ\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[7\] a permanently disabled " "Info: Pin FL_DQ\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[8\] a permanently disabled " "Info: Pin SRAM_DQ\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[9\] a permanently disabled " "Info: Pin SRAM_DQ\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[10\] a permanently disabled " "Info: Pin SRAM_DQ\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[11\] a permanently disabled " "Info: Pin SRAM_DQ\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[12\] a permanently disabled " "Info: Pin SRAM_DQ\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[13\] a permanently disabled " "Info: Pin SRAM_DQ\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[14\] a permanently disabled " "Info: Pin SRAM_DQ\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[15\] a permanently disabled " "Info: Pin SRAM_DQ\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Info: Pin I2C_SDAT has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Info: Pin AUD_ADCLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Info: Pin AUD_DACLRCK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "246 " "Warning: Following 246 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[0\] VCC " "Info: Pin SRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[1\] VCC " "Info: Pin SRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[2\] VCC " "Info: Pin SRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[3\] VCC " "Info: Pin SRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[4\] VCC " "Info: Pin SRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[5\] VCC " "Info: Pin SRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[6\] VCC " "Info: Pin SRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[7\] VCC " "Info: Pin SRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_DAT VCC " "Info: Pin PS2_DAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 85 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PS2_CLK VCC " "Info: Pin PS2_CLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 86 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[0\] VCC " "Info: Pin DRAM_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[1\] VCC " "Info: Pin DRAM_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[2\] VCC " "Info: Pin DRAM_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[3\] VCC " "Info: Pin DRAM_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[4\] VCC " "Info: Pin DRAM_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[5\] VCC " "Info: Pin DRAM_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[6\] VCC " "Info: Pin DRAM_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[7\] VCC " "Info: Pin DRAM_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[8\] VCC " "Info: Pin DRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[9\] VCC " "Info: Pin DRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[10\] VCC " "Info: Pin DRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[11\] VCC " "Info: Pin DRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[12\] VCC " "Info: Pin DRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[13\] VCC " "Info: Pin DRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[14\] VCC " "Info: Pin DRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_DQ\[15\] VCC " "Info: Pin DRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 38 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[0\] VCC " "Info: Pin FL_DQ\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[1\] VCC " "Info: Pin FL_DQ\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[2\] VCC " "Info: Pin FL_DQ\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[3\] VCC " "Info: Pin FL_DQ\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[4\] VCC " "Info: Pin FL_DQ\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[5\] VCC " "Info: Pin FL_DQ\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[6\] VCC " "Info: Pin FL_DQ\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_DQ\[7\] VCC " "Info: Pin FL_DQ\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 52 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[8\] VCC " "Info: Pin SRAM_DQ\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[9\] VCC " "Info: Pin SRAM_DQ\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[10\] VCC " "Info: Pin SRAM_DQ\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[11\] VCC " "Info: Pin SRAM_DQ\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[12\] VCC " "Info: Pin SRAM_DQ\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[13\] VCC " "Info: Pin SRAM_DQ\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[14\] VCC " "Info: Pin SRAM_DQ\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_DQ\[15\] VCC " "Info: Pin SRAM_DQ\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 60 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SDAT VCC " "Info: Pin I2C_SDAT has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 81 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_ADCLRCK VCC " "Info: Pin AUD_ADCLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 96 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACLRCK VCC " "Info: Pin AUD_DACLRCK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 98 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 100 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 104 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 105 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[0\] GND " "Info: Pin HEX0\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[1\] GND " "Info: Pin HEX0\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[2\] GND " "Info: Pin HEX0\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[3\] GND " "Info: Pin HEX0\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[4\] GND " "Info: Pin HEX0\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[5\] GND " "Info: Pin HEX0\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[6\] GND " "Info: Pin HEX0\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX0[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[0\] GND " "Info: Pin HEX1\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[1\] GND " "Info: Pin HEX1\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[2\] GND " "Info: Pin HEX1\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[3\] GND " "Info: Pin HEX1\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[4\] GND " "Info: Pin HEX1\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[5\] GND " "Info: Pin HEX1\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[6\] GND " "Info: Pin HEX1\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX1[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[0\] GND " "Info: Pin HEX2\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[1\] GND " "Info: Pin HEX2\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[2\] GND " "Info: Pin HEX2\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[3\] GND " "Info: Pin HEX2\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[4\] GND " "Info: Pin HEX2\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[5\] GND " "Info: Pin HEX2\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[6\] GND " "Info: Pin HEX2\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX2[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[0\] GND " "Info: Pin HEX3\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[1\] GND " "Info: Pin HEX3\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[2\] GND " "Info: Pin HEX3\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[3\] GND " "Info: Pin HEX3\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[4\] GND " "Info: Pin HEX3\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[5\] GND " "Info: Pin HEX3\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[6\] GND " "Info: Pin HEX3\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { HEX3[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 23 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[2\] GND " "Info: Pin LEDG\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[3\] GND " "Info: Pin LEDG\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[4\] GND " "Info: Pin LEDG\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[5\] GND " "Info: Pin LEDG\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[6\] GND " "Info: Pin LEDG\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[7\] GND " "Info: Pin LEDG\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDG[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 25 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[8\] GND " "Info: Pin LEDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[9\] GND " "Info: Pin LEDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LEDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[0\] GND " "Info: Pin DRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[1\] GND " "Info: Pin DRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[2\] GND " "Info: Pin DRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[3\] GND " "Info: Pin DRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[4\] GND " "Info: Pin DRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[5\] GND " "Info: Pin DRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[6\] GND " "Info: Pin DRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[7\] GND " "Info: Pin DRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[8\] GND " "Info: Pin DRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[9\] GND " "Info: Pin DRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[10\] GND " "Info: Pin DRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_ADDR\[11\] GND " "Info: Pin DRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 39 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_LDQM GND " "Info: Pin DRAM_LDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_LDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 40 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_LDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_UDQM GND " "Info: Pin DRAM_UDQM has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_UDQM } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 41 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_UDQM } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_WE_N VCC " "Info: Pin DRAM_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 42 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CAS_N VCC " "Info: Pin DRAM_CAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 43 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_RAS_N VCC " "Info: Pin DRAM_RAS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_RAS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 44 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_RAS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CS_N VCC " "Info: Pin DRAM_CS_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CS_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 45 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CS_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_0 GND " "Info: Pin DRAM_BA_0 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_0 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 46 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_0 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_BA_1 GND " "Info: Pin DRAM_BA_1 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_BA_1 } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 47 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_BA_1 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CLK GND " "Info: Pin DRAM_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 48 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE GND " "Info: Pin DRAM_CKE has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DRAM_CKE } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 49 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[0\] GND " "Info: Pin FL_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[1\] GND " "Info: Pin FL_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[2\] GND " "Info: Pin FL_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[3\] GND " "Info: Pin FL_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[4\] GND " "Info: Pin FL_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[5\] GND " "Info: Pin FL_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[6\] GND " "Info: Pin FL_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[7\] GND " "Info: Pin FL_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[8\] GND " "Info: Pin FL_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[9\] GND " "Info: Pin FL_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[10\] GND " "Info: Pin FL_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[11\] GND " "Info: Pin FL_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[12\] GND " "Info: Pin FL_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[13\] GND " "Info: Pin FL_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[14\] GND " "Info: Pin FL_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[15\] GND " "Info: Pin FL_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[16\] GND " "Info: Pin FL_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[17\] GND " "Info: Pin FL_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[18\] GND " "Info: Pin FL_ADDR\[18\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[18] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[19\] GND " "Info: Pin FL_ADDR\[19\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[19] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[20\] GND " "Info: Pin FL_ADDR\[20\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[20] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_ADDR\[21\] GND " "Info: Pin FL_ADDR\[21\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_ADDR[21] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 53 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_ADDR[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_WE_N VCC " "Info: Pin FL_WE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 54 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N GND " "Info: Pin FL_RST_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_RST_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 55 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_OE_N VCC " "Info: Pin FL_OE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 56 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_CE_N VCC " "Info: Pin FL_CE_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { FL_CE_N } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 57 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[0\] GND " "Info: Pin SRAM_ADDR\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[1\] GND " "Info: Pin SRAM_ADDR\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[2\] GND " "Info: Pin SRAM_ADDR\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[3\] GND " "Info: Pin SRAM_ADDR\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[4\] GND " "Info: Pin SRAM_ADDR\[4\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[4] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[5\] GND " "Info: Pin SRAM_ADDR\[5\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[5] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[6\] GND " "Info: Pin SRAM_ADDR\[6\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[6] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[7\] GND " "Info: Pin SRAM_ADDR\[7\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[7] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[8\] GND " "Info: Pin SRAM_ADDR\[8\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[8] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[9\] GND " "Info: Pin SRAM_ADDR\[9\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[9] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[10\] GND " "Info: Pin SRAM_ADDR\[10\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[10] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[11\] GND " "Info: Pin SRAM_ADDR\[11\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[11] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[12\] GND " "Info: Pin SRAM_ADDR\[12\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[12] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[13\] GND " "Info: Pin SRAM_ADDR\[13\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[13] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[14\] GND " "Info: Pin SRAM_ADDR\[14\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[14] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[15\] GND " "Info: Pin SRAM_ADDR\[15\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[15] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[16\] GND " "Info: Pin SRAM_ADDR\[16\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[16] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_ADDR\[17\] GND " "Info: Pin SRAM_ADDR\[17\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_ADDR[17] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 61 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_ADDR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_UB_N VCC " "Info: Pin SRAM_UB_N has VCC driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_UB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 62 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_LB_N GND " "Info: Pin SRAM_LB_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_LB_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 63 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N GND " "Info: Pin SRAM_WE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_WE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 64 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_WE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N GND " "Info: Pin SRAM_CE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_CE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 65 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N GND " "Info: Pin SRAM_OE_N has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SRAM_OE_N } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 66 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_OE_N } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 GND " "Info: Pin SD_DAT3 has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_DAT3 } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 70 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD GND " "Info: Pin SD_CMD has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CMD } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 71 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { SD_CLK } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 72 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { TDO } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 78 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "I2C_SCLK GND " "Info: Pin I2C_SCLK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2C_SCLK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 82 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_HS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 89 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_VS } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 90 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_R[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 91 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_G[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 92 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[0] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[1] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[2] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { VGA_B[3] } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 93 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_DACDAT } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 99 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_XCK GND " "Info: Pin AUD_XCK has GND driving its datain port" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AUD_XCK } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 101 -1 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 15 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "205 " "Info: Peak virtual memory: 205 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 16 19:25:57 2010 " "Info: Processing ended: Sat Jan 16 19:25:57 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tan.qmsg
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tan.qmsg (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.tan.qmsg (revision 6)
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 16 19:26:03 2010 " "Info: Processing started: Sat Jan 16 19:26:03 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[0\] " "Warning: Node \"miniUART:U1\|TxData\[0\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[3\] " "Warning: Node \"miniUART:U1\|TxData\[3\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[5\] " "Warning: Node \"miniUART:U1\|TxData\[5\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|TxData\[6\] " "Warning: Node \"miniUART:U1\|TxData\[6\]\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 68 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[0\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[0\]_240 " "Warning: Node \"miniUART:U1\|DataOut\[0\]_240\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[1\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[1\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[2\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[2\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[3\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[3\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[4\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[4\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[5\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[5\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[6\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[6\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} { "Warning" "WTDB_COMB_LATCH_NODE" "miniUART:U1\|DataOut\[7\]\$latch " "Warning: Node \"miniUART:U1\|DataOut\[7\]\$latch\" is a latch" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 -1} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[8\] " "Info: Assuming node \"SW\[8\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] register miniUART:U1\|RxUnit:RxDev\|frameErr 226.81 MHz 4.409 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 226.81 MHz between source register \"miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]\" and destination register \"miniUART:U1\|RxUnit:RxDev\|frameErr\" (period= 4.409 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.166 ns + Longest register register " "Info: + Longest register to register delay is 4.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 1 REG LCFF_X39_Y14_N25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.513 ns) 0.908 ns miniUART:U1\|RxUnit:RxDev\|Equal1~0 2 COMB LCCOMB_X39_Y14_N18 4 " "Info: 2: + IC(0.395 ns) + CELL(0.513 ns) = 0.908 ns; Loc. = LCCOMB_X39_Y14_N18; Fanout = 4; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|Equal1~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 108 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.178 ns) 1.404 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8 3 COMB LCCOMB_X39_Y14_N4 6 " "Info: 3: + IC(0.318 ns) + CELL(0.178 ns) = 1.404 ns; Loc. = LCCOMB_X39_Y14_N4; Fanout = 6; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.496 ns" { miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.322 ns) 2.040 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10 4 COMB LCCOMB_X39_Y14_N12 2 " "Info: 4: + IC(0.314 ns) + CELL(0.322 ns) = 2.040 ns; Loc. = LCCOMB_X39_Y14_N12; Fanout = 2; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.636 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.178 ns) 2.525 ns miniUART:U1\|RxUnit:RxDev\|outErr~5 5 COMB LCCOMB_X39_Y14_N22 10 " "Info: 5: + IC(0.307 ns) + CELL(0.178 ns) = 2.525 ns; Loc. = LCCOMB_X39_Y14_N22; Fanout = 10; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|outErr~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.485 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.758 ns) 4.166 ns miniUART:U1\|RxUnit:RxDev\|frameErr 6 REG LCFF_X39_Y11_N25 2 " "Info: 6: + IC(0.883 ns) + CELL(0.758 ns) = 4.166 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.949 ns ( 46.78 % ) " "Info: Total cell delay = 1.949 ns ( 46.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.217 ns ( 53.22 % ) " "Info: Total interconnect delay = 2.217 ns ( 53.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.395ns 0.318ns 0.314ns 0.307ns 0.883ns } { 0.000ns 0.513ns 0.178ns 0.322ns 0.178ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.856 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.602 ns) 2.856 ns miniUART:U1\|RxUnit:RxDev\|frameErr 3 REG LCFF_X39_Y11_N25 2 " "Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 2.856 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1\|RxUnit:RxDev\|frameErr'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.00 % ) " "Info: Total cell delay = 1.628 ns ( 57.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.228 ns ( 43.00 % ) " "Info: Total interconnect delay = 1.228 ns ( 43.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.860 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\] 3 REG LCFF_X39_Y14_N25 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1\|RxUnit:RxDev\|SampleCnt\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 68 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] miniUART:U1|RxUnit:RxDev|Equal1~0 miniUART:U1|RxUnit:RxDev|tmpDRdy~8 miniUART:U1|RxUnit:RxDev|tmpDRdy~10 miniUART:U1|RxUnit:RxDev|outErr~5 miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.166 ns" { miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} miniUART:U1|RxUnit:RxDev|Equal1~0 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~8 {} miniUART:U1|RxUnit:RxDev|tmpDRdy~10 {} miniUART:U1|RxUnit:RxDev|outErr~5 {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.395ns 0.318ns 0.314ns 0.307ns 0.883ns } { 0.000ns 0.513ns 0.178ns 0.322ns 0.178ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.856 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|frameErr } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.856 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|frameErr {} } { 0.000ns 0.000ns 0.238ns 0.990ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|SampleCnt[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|SampleCnt[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "miniUART:U1\|TxUnit:TxDev\|TReg\[0\] KEY\[0\] CLOCK_50 6.868 ns register " "Info: tsu for register \"miniUART:U1\|TxUnit:TxDev\|TReg\[0\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 6.868 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.768 ns + Longest pin register " "Info: + Longest pin to register delay is 9.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns KEY\[0\] 1 PIN PIN_R22 54 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 54; PIN Node = 'KEY\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.688 ns) + CELL(0.545 ns) 7.097 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~32 2 COMB LCCOMB_X39_Y11_N14 4 " "Info: 2: + IC(5.688 ns) + CELL(0.545 ns) = 7.097 ns; Loc. = LCCOMB_X39_Y11_N14; Fanout = 4; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~32'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.233 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.322 ns) 7.735 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35 3 COMB LCCOMB_X39_Y11_N30 2 " "Info: 3: + IC(0.316 ns) + CELL(0.322 ns) = 7.735 ns; Loc. = LCCOMB_X39_Y11_N30; Fanout = 2; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~35'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.638 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.490 ns) + CELL(0.521 ns) 8.746 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~37 4 COMB LCCOMB_X38_Y11_N30 7 " "Info: 4: + IC(0.490 ns) + CELL(0.521 ns) = 8.746 ns; Loc. = LCCOMB_X38_Y11_N30; Fanout = 7; COMB Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]~37'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.011 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.758 ns) 9.768 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 5 REG LCFF_X38_Y11_N9 1 " "Info: 5: + IC(0.264 ns) + CELL(0.758 ns) = 9.768 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.010 ns ( 30.81 % ) " "Info: Total cell delay = 3.010 ns ( 30.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.758 ns ( 69.19 % ) " "Info: Total interconnect delay = 6.758 ns ( 69.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.768 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.768 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~32 {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~37 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.688ns 0.316ns 0.490ns 0.264ns } { 0.000ns 0.864ns 0.545ns 0.322ns 0.521ns 0.758ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" { } { { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.862 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 2.862 ns miniUART:U1\|TxUnit:TxDev\|TReg\[0\] 3 REG LCFF_X38_Y11_N9 1 " "Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1\|TxUnit:TxDev\|TReg\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "TxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/TxUnit.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.88 % ) " "Info: Total cell delay = 1.628 ns ( 56.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 43.12 % ) " "Info: Total interconnect delay = 1.234 ns ( 43.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.768 ns" { KEY[0] miniUART:U1|TxUnit:TxDev|TReg[0]~32 miniUART:U1|TxUnit:TxDev|TReg[0]~35 miniUART:U1|TxUnit:TxDev|TReg[0]~37 miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.768 ns" { KEY[0] {} KEY[0]~combout {} miniUART:U1|TxUnit:TxDev|TReg[0]~32 {} miniUART:U1|TxUnit:TxDev|TReg[0]~35 {} miniUART:U1|TxUnit:TxDev|TReg[0]~37 {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 5.688ns 0.316ns 0.490ns 0.264ns } { 0.000ns 0.864ns 0.545ns 0.322ns 0.521ns 0.758ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|TxUnit:TxDev|TReg[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|TxUnit:TxDev|TReg[0] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "SW\[8\] LEDR\[7\] miniUART:U1\|DataOut\[7\]\$latch 8.405 ns register " "Info: tco from clock \"SW\[8\]\" to destination pin \"LEDR\[7\]\" through register \"miniUART:U1\|DataOut\[7\]\$latch\" is 8.405 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW\[8\] source 2.999 ns + Longest register " "Info: + Longest clock path from clock \"SW\[8\]\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[8\] 1 CLK PIN_M1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 3; CLK Node = 'SW\[8\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns SW\[8\]~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'SW\[8\]~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { SW[8] SW[8]~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.413 ns) + CELL(0.322 ns) 2.999 ns miniUART:U1\|DataOut\[7\]\$latch 3 REG LCCOMB_X40_Y13_N6 1 " "Info: 3: + IC(1.413 ns) + CELL(0.322 ns) = 2.999 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1\|DataOut\[7\]\$latch'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.735 ns" { SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.348 ns ( 44.95 % ) " "Info: Total cell delay = 1.348 ns ( 44.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.651 ns ( 55.05 % ) " "Info: Total interconnect delay = 1.651 ns ( 55.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { SW[8] SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { SW[8] {} SW[8]~combout {} SW[8]~clkctrl {} miniUART:U1|DataOut[7]$latch {} } { 0.000ns 0.000ns 0.238ns 1.413ns } { 0.000ns 1.026ns 0.000ns 0.322ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.406 ns + Longest register pin " "Info: + Longest register to pin delay is 5.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miniUART:U1\|DataOut\[7\]\$latch 1 REG LCCOMB_X40_Y13_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1\|DataOut\[7\]\$latch'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "miniUART.vhd" "" { Text "C:/altera/cores/vhdl/uart/miniUART.vhd" 178 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.411 ns) + CELL(2.995 ns) 5.406 ns LEDR\[7\] 2 PIN PIN_U18 0 " "Info: 2: + IC(2.411 ns) + CELL(2.995 ns) = 5.406 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'LEDR\[7\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.995 ns ( 55.40 % ) " "Info: Total cell delay = 2.995 ns ( 55.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.411 ns ( 44.60 % ) " "Info: Total interconnect delay = 2.411 ns ( 44.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.406 ns" { miniUART:U1|DataOut[7]$latch {} LEDR[7] {} } { 0.000ns 2.411ns } { 0.000ns 2.995ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { SW[8] SW[8]~clkctrl miniUART:U1|DataOut[7]$latch } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { SW[8] {} SW[8]~combout {} SW[8]~clkctrl {} miniUART:U1|DataOut[7]$latch {} } { 0.000ns 0.000ns 0.238ns 1.413ns } { 0.000ns 1.026ns 0.000ns 0.322ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.406 ns" { miniUART:U1|DataOut[7]$latch LEDR[7] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.406 ns" { miniUART:U1|DataOut[7]$latch {} LEDR[7] {} } { 0.000ns 2.411ns } { 0.000ns 2.995ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "miniUART:U1\|RxUnit:RxDev\|tmpDRdy SW\[1\] CLOCK_50 0.138 ns register " "Info: th for register \"miniUART:U1\|RxUnit:RxDev\|tmpDRdy\" (data pin = \"SW\[1\]\", clock pin = \"CLOCK_50\") is 0.138 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.858 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 70 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X39_Y12_N17 3 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" { } { { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.006 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.006 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[1\] 1 PIN PIN_L21 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L21; Fanout = 2; PIN Node = 'SW\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "top_uart.vhd" "" { Text "C:/altera/cores/vhdl/uart/top_uart.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.339 ns) + CELL(0.545 ns) 2.910 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11 2 COMB LCCOMB_X39_Y12_N16 1 " "Info: 2: + IC(1.339 ns) + CELL(0.545 ns) = 2.910 ns; Loc. = LCCOMB_X39_Y12_N16; Fanout = 1; COMB Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy~11'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.884 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 3.006 ns miniUART:U1\|RxUnit:RxDev\|tmpDRdy 3 REG LCFF_X39_Y12_N17 3 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 3.006 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1\|RxUnit:RxDev\|tmpDRdy'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/altera/cores/vhdl/uart/RxUnit.vhd" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.667 ns ( 55.46 % ) " "Info: Total cell delay = 1.667 ns ( 55.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.339 ns ( 44.54 % ) " "Info: Total interconnect delay = 1.339 ns ( 44.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.006 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.339ns 0.000ns } { 0.000ns 1.026ns 0.545ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { CLOCK_50 CLOCK_50~clkctrl miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { SW[1] miniUART:U1|RxUnit:RxDev|tmpDRdy~11 miniUART:U1|RxUnit:RxDev|tmpDRdy } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.006 ns" { SW[1] {} SW[1]~combout {} miniUART:U1|RxUnit:RxDev|tmpDRdy~11 {} miniUART:U1|RxUnit:RxDev|tmpDRdy {} } { 0.000ns 0.000ns 1.339ns 0.000ns } { 0.000ns 1.026ns 0.545ns 0.096ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 15 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Peak virtual memory: 136 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 16 19:26:04 2010 " "Info: Processing ended: Sat Jan 16 19:26:04 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.cdb
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--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgdiff.cdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.hdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.hdb
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--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(9).cnf.hdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate.rvd
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate.rvd
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--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate.rvd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate.rvd (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.sgate.rvd
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.hdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.hdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.hdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.hdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.(10).cnf.hdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.logdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.logdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.logdb (revision 6)
@@ -0,0 +1 @@
+v1
Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.cdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.cdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.cdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.cdb (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/db/uart.map.cdb
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Index: z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/HexDigit.vhd (revision 6)
@@ -0,0 +1,28 @@
+entity SEG7_LUT ( oSEG,iDIG );
+input [3:0] iDIG;
+output [6:0] oSEG;
+reg [6:0] oSEG;
+
+always (iDIG)
+begin
+ case(iDIG)
+ 4'h1: oSEG = 7'b1111001; // ---t----
+ 4'h2: oSEG = 7'b0100100; // | |
+ 4'h3: oSEG = 7'b0110000; // lt rt
+ 4'h4: oSEG = 7'b0011001; // | |
+ 4'h5: oSEG = 7'b0010010; // ---m----
+ 4'h6: oSEG = 7'b0000010; // | |
+ 4'h7: oSEG = 7'b1111000; // lb rb
+ 4'h8: oSEG = 7'b0000000; // | |
+ 4'h9: oSEG = 7'b0011000; // ---b----
+ 4'ha: oSEG = 7'b0001000;
+ 4'hb: oSEG = 7'b0000011;
+ 4'hc: oSEG = 7'b1000110;
+ 4'hd: oSEG = 7'b0100001;
+ 4'he: oSEG = 7'b0000110;
+ 4'hf: oSEG = 7'b0001110;
+ 4'h0: oSEG = 7'b1000000;
+ endcase
+end
+
+endmodule
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
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Index: z80control/trunk/DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/DOCS/MiniUART.doc (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/DOCS/MiniUART.doc (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
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Index: z80control/trunk/DE1/rtl/VHDL/uart/clkUnit.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/clkUnit.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/clkUnit.vhd (revision 6)
@@ -0,0 +1,135 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : clkUnit.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 1.0 Ovidiu Lupas 15 January 2000 New model
+-- 1.1 Ovidiu Lupas 28 May 2000 EnableRx/EnableTx ratio corrected
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description : Generates the Baud clock and enable signals for RX & TX
+-- units.
+-------------------------------------------------------------------------------
+-- Entity for Baud rate generator Unit - 9600 baudrate --
+-------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.UART_Def.all;
+-------------------------------------------------------------------------------
+-- Baud rate generator
+-------------------------------------------------------------------------------
+entity ClkUnit is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ EnableRx : out Std_Logic; -- Control signal
+ EnableTx : out Std_Logic; -- Control signal
+ Reset : in Std_Logic); -- Reset input
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for Baud rate generator Unit
+-------------------------------------------------------------------------------
+architecture Behaviour of ClkUnit is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal ClkDiv26 : Std_Logic;
+ signal tmpEnRX : Std_Logic;
+ signal tmpEnTX : Std_Logic;
+begin
+ -----------------------------------------------------------------------------
+ -- Divides the system clock of 40 MHz by 26
+ -----------------------------------------------------------------------------
+ DivClk26 : process(SysClk,Reset)
+ constant CntOne : unsigned(4 downto 0) := "00001";
+ variable Cnt26 : unsigned(5 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt26 := "000000";
+ ClkDiv26 <= '0';
+ else
+ Cnt26 := Cnt26 + CntOne;
+ case Cnt26 is
+ when "100000" =>
+ ClkDiv26 <= '1';
+ Cnt26 := "000000";
+ when others =>
+ ClkDiv26 <= '0';
+ end case;
+ end if;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Provides the EnableRX signal, at ~ 155 KHz
+ -----------------------------------------------------------------------------
+ DivClk10 : process(SysClk,Reset,Clkdiv26)
+ constant CntOne : unsigned(3 downto 0) := "0001";
+ variable Cnt10 : unsigned(3 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt10 := "0000";
+ tmpEnRX <= '0';
+ elsif ClkDiv26 = '1' then
+ Cnt10 := Cnt10 + CntOne;
+ end if;
+ case Cnt10 is
+ when "1010" =>
+ tmpEnRX <= '1';
+ Cnt10 := "0000";
+ when others =>
+ tmpEnRX <= '0';
+ end case;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Provides the EnableTX signal, at 9.6 KHz
+ -----------------------------------------------------------------------------
+ DivClk16 : process(SysClk,Reset,tmpEnRX)
+ constant CntOne : unsigned(4 downto 0) := "00001";
+ variable Cnt16 : unsigned(4 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ Cnt16 := "00000";
+ tmpEnTX <= '0';
+ elsif tmpEnRX = '1' then
+ Cnt16 := Cnt16 + CntOne;
+ end if;
+ case Cnt16 is
+ when "01111" =>
+ tmpEnTX <= '1';
+ Cnt16 := Cnt16 + CntOne;
+ when "10001" =>
+ Cnt16 := "00000";
+ tmpEnTX <= '0';
+ when others =>
+ tmpEnTX <= '0';
+ end case;
+ end if;
+ end process;
+
+ EnableRX <= tmpEnRX;
+ EnableTX <= tmpEnTX;
+end Behaviour; --==================== End of architecture ===================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.vhd (revision 6)
@@ -0,0 +1,148 @@
+-------------------------------------------------------------------------------
+-- Title : UART
+-- Project : UART
+-------------------------------------------------------------------------------
+-- File : MiniUart.vhd
+-- Author : Philippe CARTON
+-- (philippe.carton2@libertysurf.fr)
+-- Organization:
+-- Created : 15/12/2001
+-- Last update : 8/1/2003
+-- Platform : Foundation 3.1i
+-- Simulators : ModelSim 5.5b
+-- Synthesizers: Xilinx Synthesis
+-- Targets : Xilinx Spartan
+-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
+-------------------------------------------------------------------------------
+-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
+-- Wishbone compatable.
+-------------------------------------------------------------------------------
+-- Copyright (c) notice
+-- This core adheres to the GNU public license
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Revision Number :
+-- Version :
+-- Date :
+-- Modifier : name
+-- Description :
+--
+------------------------------------------------------------------------------
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity UART is
+ generic(BRDIVISOR: INTEGER range 0 to 65535 := 1302); -- Baud rate divisor 130
+ port (
+-- Wishbone signals
+ WB_CLK_I : in std_logic; -- clock
+ WB_RST_I : in std_logic; -- Reset input
+ WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
+ WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
+ WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
+ WB_WE_I : in std_logic; -- Write Enable
+ WB_STB_I : in std_logic; -- Strobe
+ WB_ACK_O : out std_logic; -- Acknowledge
+-- process signals
+ IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
+ IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
+ BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
+ TxD_PAD_O: out std_logic; -- Tx RS232 Line
+ RxD_PAD_I: in std_logic); -- Rx RS232 Line
+end UART;
+
+-- Architecture for UART for synthesis
+architecture Behaviour of UART is
+
+ component Counter
+ generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
+ port (
+ Clk : in std_logic; -- Clock
+ Reset : in std_logic; -- Reset input
+ CE : in std_logic; -- Chip Enable
+ O : out std_logic); -- Output
+ end component;
+
+ component RxUnit
+ port (
+ Clk : in std_logic; -- system clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ ReadA : in Std_logic; -- Async Read Received Byte
+ RxD : in std_logic; -- RS-232 data input
+ RxAv : out std_logic; -- Byte available
+ DataO : out std_logic_vector(7 downto 0)); -- Byte received
+ end component;
+
+ component TxUnit
+ port (
+ Clk : in std_logic; -- Clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ LoadA : in std_logic; -- Asynchronous Load
+ TxD : out std_logic; -- RS-232 data output
+ Busy : out std_logic; -- Tx Busy
+ DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
+ end component;
+
+ signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
+ signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
+ signal SReg : std_logic_vector(7 downto 0); -- Status register
+ signal EnabRx : std_logic; -- Enable RX unit
+ signal EnabTx : std_logic; -- Enable TX unit
+ signal RxAv : std_logic; -- Data Received
+ signal TxBusy : std_logic; -- Transmiter Busy
+ signal ReadA : std_logic; -- Async Read receive buffer
+ signal LoadA : std_logic; -- Async Load transmit buffer
+ signal Sig0 : std_logic; -- gnd signal
+ signal Sig1 : std_logic; -- vcc signal
+ --signal Counter : std_logic_vector(2 downto 0);
+
+
+ begin
+ sig0 <= '0';
+ sig1 <= '1';
+ Uart_Rxrate : Counter -- Baud Rate adjust
+ generic map (COUNT => BRDIVISOR)
+ port map (BR_CLK_I, sig0, sig1, EnabRx);
+ Uart_Txrate : Counter -- 4 Divider for Tx
+ generic map (COUNT => 4)
+ port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
+ Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
+ Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
+ IntTx_O <= not TxBusy;
+ IntRx_O <= RxAv;
+ SReg(0) <= not TxBusy;
+ SReg(1) <= RxAv;
+ SReg(7 downto 2) <= "000000";
+
+ -- Implements WishBone data exchange.
+ -- Clocked on rising edge. Synchronous Reset RST_I
+ WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
+ variable StatM : std_logic_vector(4 downto 0);
+ begin
+ if Rising_Edge(WB_CLK_I) then
+ if (WB_RST_I = '1') then
+ ReadA <= '0';
+ LoadA <= '0';
+ else
+ if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
+ TxData <= WB_DAT_I;
+ LoadA <= '1'; -- Load signal
+ else LoadA <= '0';
+ end if;
+ if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
+ ReadA <= '1'; -- Read signal
+ else ReadA <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+ WB_ACK_O <= WB_STB_I;
+ WB_DAT_O <=
+ RxData when WB_ADR_I = "00" else -- Read Byte from Rx
+ SReg when WB_ADR_I = "01" else -- Read Status Reg
+ "00000000";
+end Behaviour;
Index: z80control/trunk/DE1/rtl/VHDL/uart/clk_div.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/clk_div.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/clk_div.vhd (revision 6)
@@ -0,0 +1,128 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+ENTITY clk_div IS
+
+ PORT
+ (
+ clock_25Mhz : IN STD_LOGIC;
+ clock_1MHz : OUT STD_LOGIC;
+ clock_100KHz : OUT STD_LOGIC;
+ clock_10KHz : OUT STD_LOGIC;
+ clock_1KHz : OUT STD_LOGIC;
+ clock_100Hz : OUT STD_LOGIC;
+ clock_10Hz : OUT STD_LOGIC;
+ clock_1Hz : OUT STD_LOGIC);
+
+END clk_div;
+
+ARCHITECTURE a OF clk_div IS
+
+ SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
+ SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
+ SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
+BEGIN
+ PROCESS
+ BEGIN
+-- Divide by 25
+ WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
+ IF count_1Mhz < 24 THEN
+ count_1Mhz <= count_1Mhz + 1;
+ ELSE
+ count_1Mhz <= "00000";
+ END IF;
+ IF count_1Mhz < 12 THEN
+ clock_1Mhz_int <= '0';
+ ELSE
+ clock_1Mhz_int <= '1';
+ END IF;
+
+-- Ripple clocks are used in this code to save prescalar hardware
+-- Sync all clock prescalar outputs back to master clock signal
+ clock_1Mhz <= clock_1Mhz_int;
+ clock_100Khz <= clock_100Khz_int;
+ clock_10Khz <= clock_10Khz_int;
+ clock_1Khz <= clock_1Khz_int;
+ clock_100hz <= clock_100hz_int;
+ clock_10hz <= clock_10hz_int;
+ clock_1hz <= clock_1hz_int;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
+ IF count_100Khz /= 4 THEN
+ count_100Khz <= count_100Khz + 1;
+ ELSE
+ count_100khz <= "000";
+ clock_100Khz_int <= NOT clock_100Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
+ IF count_10Khz /= 4 THEN
+ count_10Khz <= count_10Khz + 1;
+ ELSE
+ count_10khz <= "000";
+ clock_10Khz_int <= NOT clock_10Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
+ IF count_1Khz /= 4 THEN
+ count_1Khz <= count_1Khz + 1;
+ ELSE
+ count_1khz <= "000";
+ clock_1Khz_int <= NOT clock_1Khz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
+ IF count_100hz /= 4 THEN
+ count_100hz <= count_100hz + 1;
+ ELSE
+ count_100hz <= "000";
+ clock_100hz_int <= NOT clock_100hz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
+ IF count_10hz /= 4 THEN
+ count_10hz <= count_10hz + 1;
+ ELSE
+ count_10hz <= "000";
+ clock_10hz_int <= NOT clock_10hz_int;
+ END IF;
+ END PROCESS;
+
+-- Divide by 10
+ PROCESS
+ BEGIN
+ WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
+ IF count_1hz /= 4 THEN
+ count_1hz <= count_1hz + 1;
+ ELSE
+ count_1hz <= "000";
+ clock_1hz_int <= NOT clock_1hz_int;
+ END IF;
+ END PROCESS;
+
+END a;
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.qpf
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.qpf (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.qpf (revision 6)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 23:14:30 September 14, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "23:14:30 September 14, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "uart"
Index: z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd.bak (revision 6)
@@ -0,0 +1,210 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+--
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : miniuart.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas 15 January 2000 New model
+-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
+-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
+-- the RSBusCtrl did not process all possible situations
+--
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description : The memory consists of a dual-port memory addressed by
+-- two counters (RdCnt & WrCnt). The third counter (StatCnt)
+-- sets the status signals and keeps a track of the data flow.
+-------------------------------------------------------------------------------
+-- Entity for miniUART Unit - 9600 baudrate --
+-------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.UART_Def.all;
+
+entity miniUART is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ --IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for miniUART Controller Unit
+-------------------------------------------------------------------------------
+architecture uart of miniUART is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal RxData : Std_Logic_Vector(7 downto 0); --
+ signal TxData : Std_Logic_Vector(7 downto 0); --
+ signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register
+ -- CSReg detailed
+ -----------+--------+--------+--------+--------+--------+--------+--------+
+ -- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)|
+ -- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr |
+ -----------+--------+--------+--------+--------+--------+--------+--------+
+ signal EnabRx : Std_Logic; -- Enable RX unit
+ signal EnabTx : Std_Logic; -- Enable TX unit
+ signal DRdy : Std_Logic; -- Receive Data ready
+ signal TRegE : Std_Logic; -- Transmit register empty
+ signal TBufE : Std_Logic; -- Transmit buffer empty
+ signal FErr : Std_Logic; -- Frame error
+ signal OErr : Std_Logic; -- Output error
+ signal Read : Std_Logic; -- Read receive buffer
+ signal Load : Std_Logic; -- Load transmit buffer
+ -----------------------------------------------------------------------------
+ -- Baud rate Generator
+ -----------------------------------------------------------------------------
+ component ClkUnit is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ EnableRX : out Std_Logic; -- Control signal
+ EnableTX : out Std_Logic; -- Control signal
+ Reset : in Std_Logic); -- Reset input
+ end component;
+ -----------------------------------------------------------------------------
+ -- Receive Unit
+ -----------------------------------------------------------------------------
+ component RxUnit is
+ port (
+ Clk : in Std_Logic; -- Clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ RxD : in Std_Logic; -- RS-232 data input
+ RD : in Std_Logic; -- Read data signal
+ FErr : out Std_Logic; -- Status signal
+ OErr : out Std_Logic; -- Status signal
+ DRdy : out Std_Logic; -- Status signal
+ DataIn : out Std_Logic_Vector(7 downto 0));
+ end component;
+ -----------------------------------------------------------------------------
+ -- Transmitter Unit
+ -----------------------------------------------------------------------------
+ component TxUnit is
+ port (
+ Clk : in Std_Logic; -- Clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ Load : in Std_Logic; -- Load transmit data
+ TxD : out Std_Logic; -- RS-232 data output
+ TRegE : out Std_Logic; -- Tx register empty
+ TBufE : out Std_Logic; -- Tx buffer empty
+ DataO : in Std_Logic_Vector(7 downto 0));
+ end component;
+begin
+ -----------------------------------------------------------------------------
+ -- Instantiation of internal components
+ -----------------------------------------------------------------------------
+ ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset);
+ TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData);
+ RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
+
+ --IntRx_N <= DRdy;
+ --IntTx_N <= TBufE;
+ -----------------------------------------------------------------------------
+ -- Implements the controller for Rx&Tx units
+ -----------------------------------------------------------------------------
+ RSBusCtrl : process(SysClk,Reset,Read,Load)
+ variable StatM : Std_Logic_Vector(4 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ StatM := "00000";
+ --IntTx_N <= '0';
+ --IntRx_N <= '0';
+ CSReg <= "11110000";
+ else
+ StatM(0) := DRdy;
+ StatM(1) := FErr;
+ StatM(2) := OErr;
+ StatM(3) := TBufE;
+ StatM(4) := TRegE;
+ end if;
+ --case StatM is
+ --when "00001" =>
+ -- IntRx_N <= '1';
+ -- CSReg(2) <= '1';
+ --when "10001" =>
+ -- IntRx_N <= '1';
+ -- CSReg(2) <= '1';
+ --when "01000" =>
+ -- IntTx_N <= '1';
+ --when "10000" =>
+ -- IntTx_N <= '1';
+ -- CSReg(3) <= '1';
+ --when others => null;
+ --end case;
+
+ IntRx_N <= DRdy;
+ --IntTx_N <= TRegE;
+
+ --if Read = '1' then
+ -- CSReg(2) <= '0';
+ -- IntRx_N <= '0';
+ --end if;
+
+ --if Load = '1' then
+ -- CSReg(3) <= '0';
+ -- IntTx_N <= '0';
+ --end if;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Combinational section
+ -----------------------------------------------------------------------------
+ process(SysClk)
+ begin
+ if (CS_N = '0' and RD_N = '0') then
+ Read <= '1';
+ else Read <= '0';
+ end if;
+
+ if (CS_N = '0' and WR_N = '0') then
+ Load <= '1';
+ else Load <= '0';
+ end if;
+
+ if Read = '0' then
+ DataOut <= "ZZZZZZZZ";
+ elsif (Read = '1' and Addr = "00") then
+ DataOut <= RxData;
+ elsif (Read = '1' and Addr = "01") then
+ DataOut <= CSReg;
+ end if;
+
+ if Load = '0' then
+ TxData <= "ZZZZZZZZ";
+ elsif (Load = '1' and Addr = "00") then
+ TxData <= DataIn;
+ end if;
+ end process;
+end uart; --===================== End of architecture =======================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/miniUART.vhd (revision 6)
@@ -0,0 +1,204 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+--
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : miniuart.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas 15 January 2000 New model
+-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
+-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
+-- the RSBusCtrl did not process all possible situations
+--
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description : The memory consists of a dual-port memory addressed by
+-- two counters (RdCnt & WrCnt). The third counter (StatCnt)
+-- sets the status signals and keeps a track of the data flow.
+-------------------------------------------------------------------------------
+-- Entity for miniUART Unit - 9600 baudrate --
+-------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.UART_Def.all;
+
+entity miniUART is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for miniUART Controller Unit
+-------------------------------------------------------------------------------
+architecture uart of miniUART is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal RxData : Std_Logic_Vector(7 downto 0); --
+ signal TxData : Std_Logic_Vector(7 downto 0); --
+ signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register
+ -- CSReg detailed
+ -----------+--------+--------+--------+--------+--------+--------+--------+
+ -- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)|
+ -- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr |
+ -----------+--------+--------+--------+--------+--------+--------+--------+
+ signal EnabRx : Std_Logic; -- Enable RX unit
+ signal EnabTx : Std_Logic; -- Enable TX unit
+ signal DRdy : Std_Logic; -- Receive Data ready
+ signal TRegE : Std_Logic; -- Transmit register empty
+ signal TBufE : Std_Logic; -- Transmit buffer empty
+ signal FErr : Std_Logic; -- Frame error
+ signal OErr : Std_Logic; -- Output error
+ signal Read : Std_Logic; -- Read receive buffer
+ signal Load : Std_Logic; -- Load transmit buffer
+ -----------------------------------------------------------------------------
+ -- Baud rate Generator
+ -----------------------------------------------------------------------------
+ component ClkUnit is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ EnableRX : out Std_Logic; -- Control signal
+ EnableTX : out Std_Logic; -- Control signal
+ Reset : in Std_Logic); -- Reset input
+ end component;
+ -----------------------------------------------------------------------------
+ -- Receive Unit
+ -----------------------------------------------------------------------------
+ component RxUnit is
+ port (
+ Clk : in Std_Logic; -- Clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ RxD : in Std_Logic; -- RS-232 data input
+ RD : in Std_Logic; -- Read data signal
+ FErr : out Std_Logic; -- Status signal
+ OErr : out Std_Logic; -- Status signal
+ DRdy : out Std_Logic; -- Status signal
+ DataIn : out Std_Logic_Vector(7 downto 0));
+ end component;
+ -----------------------------------------------------------------------------
+ -- Transmitter Unit
+ -----------------------------------------------------------------------------
+ component TxUnit is
+ port (
+ Clk : in Std_Logic; -- Clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ Load : in Std_Logic; -- Load transmit data
+ TxD : out Std_Logic; -- RS-232 data output
+ TRegE : out Std_Logic; -- Tx register empty
+ TBufE : out Std_Logic; -- Tx buffer empty
+ DataO : in Std_Logic_Vector(7 downto 0));
+ end component;
+begin
+ -----------------------------------------------------------------------------
+ -- Instantiation of internal components
+ -----------------------------------------------------------------------------
+ ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset);
+ TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData);
+ RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
+ -----------------------------------------------------------------------------
+ -- Implements the controller for Rx&Tx units
+ -----------------------------------------------------------------------------
+ RSBusCtrl : process(SysClk,Reset,Read,Load)
+ variable StatM : Std_Logic_Vector(4 downto 0);
+ begin
+ if Rising_Edge(SysClk) then
+ if Reset = '0' then
+ StatM := "00000";
+ IntTx_N <= '1';
+ IntRx_N <= '1';
+ CSReg <= "11110000";
+ else
+ StatM(0) := DRdy;
+ StatM(1) := FErr;
+ StatM(2) := OErr;
+ StatM(3) := TBufE;
+ StatM(4) := TRegE;
+ end if;
+ case StatM is
+ when "00001" =>
+ IntRx_N <= '0';
+ CSReg(2) <= '1';
+ when "10001" =>
+ IntRx_N <= '0';
+ CSReg(2) <= '1';
+ when "01000" =>
+ IntTx_N <= '0';
+ when "11000" =>
+ IntTx_N <= '0';
+ CSReg(3) <= '1';
+ when others => null;
+ end case;
+
+ if Read = '1' then
+ CSReg(2) <= '0';
+ IntRx_N <= '1';
+ end if;
+
+ if Load = '1' then
+ CSReg(3) <= '0';
+ IntTx_N <= '1';
+ end if;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- Combinational section
+ -----------------------------------------------------------------------------
+ process(SysClk)
+ begin
+ if (CS_N = '0' and RD_N = '0') then
+ Read <= '1';
+ else Read <= '0';
+ end if;
+
+ if (CS_N = '0' and WR_N = '0') then
+ Load <= '1';
+ else Load <= '0';
+ end if;
+
+ if Read = '0' then
+ DataOut <= "ZZZZZZZZ";
+ elsif (Read = '1' and Addr = "00") then
+ DataOut <= RxData;
+ elsif (Read = '1' and Addr = "01") then
+ DataOut <= CSReg;
+ end if;
+
+ if Load = '0' then
+ TxData <= "ZZZZZZZZ";
+ elsif (Load = '1' and Addr = "00") then
+ TxData <= DataIn;
+ end if;
+ end process;
+end uart; --===================== End of architecture =======================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/RxUnit.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/RxUnit.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/RxUnit.vhd (revision 6)
@@ -0,0 +1,155 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+--
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : RxUnit.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas 15 January 2000 New model
+-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description : Implements the receive unit of the miniUART core. Samples
+-- 16 times the RxD line and retain the value in the middle of
+-- the time interval.
+-------------------------------------------------------------------------------
+-- Entity for Receive Unit - 9600 baudrate --
+-------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library work;
+ use work.UART_Def.all;
+-------------------------------------------------------------------------------
+-- Receive unit
+-------------------------------------------------------------------------------
+entity RxUnit is
+ port (
+ Clk : in Std_Logic; -- system clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ RxD : in Std_Logic; -- RS-232 data input
+ RD : in Std_Logic; -- Read data signal
+ FErr : out Std_Logic; -- Status signal
+ OErr : out Std_Logic; -- Status signal
+ DRdy : out Std_Logic; -- Status signal
+ DataIn : out Std_Logic_Vector(7 downto 0));
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for receive Unit
+-------------------------------------------------------------------------------
+architecture Behaviour of RxUnit is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal Start : Std_Logic; -- Syncro signal
+ signal tmpRxD : Std_Logic; -- RxD buffer
+ signal tmpDRdy : Std_Logic; -- Data ready buffer
+ signal outErr : Std_Logic; --
+ signal frameErr : Std_Logic; --
+ signal BitCnt : Unsigned(3 downto 0); --
+ signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
+ signal ShtReg : Std_Logic_Vector(7 downto 0); --
+ signal DOut : Std_Logic_Vector(7 downto 0); --
+begin
+ ---------------------------------------------------------------------
+ -- Receiver process
+ ---------------------------------------------------------------------
+ RcvProc : process(Clk,Reset,Enable,RxD)
+ variable tmpBitCnt : Integer range 0 to 15;
+ variable tmpSampleCnt : Integer range 0 to 15;
+ constant CntOne : Unsigned(3 downto 0):="0001";
+ begin
+ if Rising_Edge(Clk) then
+ tmpBitCnt := ToInteger(BitCnt);
+ tmpSampleCnt := ToInteger(SampleCnt);
+ if Reset = '0' then
+ BitCnt <= "0000";
+ SampleCnt <= "0000";
+ Start <= '0';
+ tmpDRdy <= '0';
+ frameErr <= '0';
+ outErr <= '0';
+
+ ShtReg <= "00000000"; --
+ DOut <= "00000000"; --
+ else
+ if RD = '1' then
+ tmpDRdy <= '0'; -- Data was read
+ end if;
+
+ if Enable = '1' then
+ if Start = '0' then
+ if RxD = '0' then -- Start bit,
+ SampleCnt <= SampleCnt + CntOne;
+ Start <= '1';
+ end if;
+ else
+ if tmpSampleCnt = 8 then -- reads the RxD line
+ tmpRxD <= RxD;
+ SampleCnt <= SampleCnt + CntOne;
+ elsif tmpSampleCnt = 15 then
+ case tmpBitCnt is
+ when 0 =>
+ if tmpRxD = '1' then -- Start Bit
+ Start <= '0';
+ else
+ BitCnt <= BitCnt + CntOne;
+ end if;
+ SampleCnt <= SampleCnt + CntOne;
+ when 1|2|3|4|5|6|7|8 =>
+ BitCnt <= BitCnt + CntOne;
+ SampleCnt <= SampleCnt + CntOne;
+ ShtReg <= tmpRxD & ShtReg(7 downto 1);
+ when 9 =>
+ if tmpRxD = '0' then -- stop bit expected
+ frameErr <= '1';
+ else
+ frameErr <= '0';
+ end if;
+
+ if tmpDRdy = '1' then --
+ outErr <= '1';
+ else
+ outErr <= '0';
+ end if;
+
+ tmpDRdy <= '1';
+ DOut <= ShtReg;
+ BitCnt <= "0000";
+ Start <= '0';
+ when others =>
+ null;
+ end case;
+ else
+ SampleCnt <= SampleCnt + CntOne;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ DRdy <= tmpDRdy;
+ DataIn <= DOut;
+ FErr <= frameErr;
+ OErr <= outErr;
+
+end Behaviour; --==================== End of architecture ====================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/TxUnit.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/TxUnit.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/TxUnit.vhd (revision 6)
@@ -0,0 +1,116 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+--
+-- Design units : miniUART core for the OCRP-1
+--
+-- File name : TxUnit.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas 15 January 2000 New model
+-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+-- Description :
+-------------------------------------------------------------------------------
+-- Entity for the Tx Unit --
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.Uart_Def.all;
+-------------------------------------------------------------------------------
+-- Transmitter unit
+-------------------------------------------------------------------------------
+entity TxUnit is
+ port (
+ Clk : in Std_Logic; -- Clock signal
+ Reset : in Std_Logic; -- Reset input
+ Enable : in Std_Logic; -- Enable input
+ Load : in Std_Logic; -- Load transmit data
+ TxD : out Std_Logic; -- RS-232 data output
+ TRegE : out Std_Logic; -- Tx register empty
+ TBufE : out Std_Logic; -- Tx buffer empty
+ DataO : in Std_Logic_Vector(7 downto 0));
+end entity; --================== End of entity ==============================--
+-------------------------------------------------------------------------------
+-- Architecture for TxUnit
+-------------------------------------------------------------------------------
+architecture Behaviour of TxUnit is
+ -----------------------------------------------------------------------------
+ -- Signals
+ -----------------------------------------------------------------------------
+ signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
+ signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
+ signal BitCnt : Unsigned(3 downto 0); -- bit counter
+ signal tmpTRegE : Std_Logic; --
+ signal tmpTBufE : Std_Logic; --
+begin
+ -----------------------------------------------------------------------------
+ -- Implements the Tx unit
+ -----------------------------------------------------------------------------
+ process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
+ variable tmp_TRegE : Std_Logic;
+ constant CntOne : Unsigned(3 downto 0):="0001";
+ begin
+ if Rising_Edge(Clk) then
+ if Reset = '0' then
+ tmpTRegE <= '1';
+ tmpTBufE <= '1';
+ TxD <= '1';
+ BitCnt <= "0000";
+ elsif Load = '1' then
+ TBuff <= DataO;
+ tmpTBufE <= '0';
+ elsif Enable = '1' then
+ if ( tmpTBufE = '0') and (tmpTRegE = '1') then
+ TReg <= TBuff;
+ tmpTRegE <= '0';
+-- tmp_TRegE := '0';
+ tmpTBufE <= '1';
+-- else
+-- tmp_TRegE := tmpTRegE;
+ end if;
+
+ if tmpTRegE = '0' then
+ case BitCnt is
+ when "0000" =>
+ TxD <= '0';
+ BitCnt <= BitCnt + CntOne;
+ when "0001" | "0010" | "0011" |
+ "0100" | "0101" | "0110" |
+ "0111" | "1000" =>
+ TxD <= TReg(0);
+ TReg <= '1' & TReg(7 downto 1);
+ BitCnt <= BitCnt + CntOne;
+ when "1001" =>
+ TxD <= '1';
+ TReg <= '1' & TReg(7 downto 1);
+ BitCnt <= "0000";
+ tmpTRegE <= '1';
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ TRegE <= tmpTRegE;
+ TBufE <= tmpTBufE;
+end Behaviour; --=================== End of architecture ====================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart_lib.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart_lib.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart_lib.vhd (revision 6)
@@ -0,0 +1,62 @@
+--===========================================================================--
+--
+-- S Y N T H E Z I A B L E miniUART C O R E
+--
+-- www.OpenCores.Org - January 2000
+-- This core adheres to the GNU public license
+--
+-- Design units : UART_Def
+--
+-- File name : uart_lib.vhd
+--
+-- Purpose : Implements an miniUART device for communication purposes
+-- between the OR1K processor and the Host computer through
+-- an RS-232 communication protocol.
+--
+-- Library : uart_lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--===========================================================================--
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas 15 January 2000 New model
+-- olupas@opencores.org
+-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- package UART_Def
+--------------------------------------------------------------------------------
+library IEEE,STD;
+use IEEE.Std_Logic_1164.all;
+use IEEE.Numeric_Std.all;
+--**--
+package UART_Def is
+ -----------------------------------------------------------------------------
+ -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
+ -- Error message for unknowns (U, X, W, Z, -), converted to 0
+ -- Verifies whether vector is too long (> 16 bits)
+ -----------------------------------------------------------------------------
+ function ToInteger (
+ Invector : in Unsigned(3 downto 0))
+ return Integer;
+end UART_Def; --==================== End of package header ======================--
+package body UART_Def is
+ function ToInteger (
+ InVector : in Unsigned(3 downto 0))
+ return Integer is
+ constant HeaderMsg : String := "To_Integer:";
+ constant MsgSeverity : Severity_Level := Warning;
+ variable Value : Integer := 0;
+ begin
+ for i in 0 to 3 loop
+ if (InVector(i) = '1') then
+ Value := Value + (2**I);
+ end if;
+ end loop;
+ return Value;
+ end ToInteger;
+end UART_Def; --================ End of package body ================--
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.map.summary
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.map.summary (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.map.summary (revision 6)
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sat Jan 16 19:25:45 2010
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : uart
+Top-level Entity Name : TOP_UART
+Family : Cyclone II
+Total logic elements : 157
+ Total combinational functions : 150
+ Dedicated logic registers : 70
+Total registers : 70
+Total pins : 281
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.flow.rpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.flow.rpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.flow.rpt (revision 6)
@@ -0,0 +1,122 @@
+Flow report for uart
+Sat Jan 16 19:26:04 2010
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+----------------------------------------------+
+; Flow Status ; Successful - Sat Jan 16 19:26:04 2010 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; uart ;
+; Top-level Entity Name ; TOP_UART ;
+; Family ; Cyclone II ;
+; Device ; EP2C20F484C7 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 155 / 18,752 ( < 1 % ) ;
+; Total combinational functions ; 150 / 18,752 ( < 1 % ) ;
+; Dedicated logic registers ; 70 / 18,752 ( < 1 % ) ;
+; Total registers ; 70 ;
+; Total pins ; 281 / 315 ( 89 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 239,616 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
+; Total PLLs ; 0 / 4 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 01/16/2010 19:25:41 ;
+; Main task ; Compilation ;
+; Revision Name ; uart ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 86839582821.126369874002712 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; C:/altera/cores/uart/uart.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; top_uart ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; top_uart ; Top ;
+; TOP_LEVEL_ENTITY ; top_uart ; uart ; -- ; -- ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-------------------------------+---------------+-------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 195 MB ; 00:00:04 ;
+; Fitter ; 00:00:09 ; 1.0 ; 205 MB ; 00:00:08 ;
+; Assembler ; 00:00:04 ; 1.0 ; 185 MB ; 00:00:03 ;
+; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 124 MB ; 00:00:00 ;
+; Total ; 00:00:18 ; -- ; -- ; 00:00:15 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; TYLER-LAPTOP ; Windows XP ; 5.1 ; i686 ;
+; Fitter ; TYLER-LAPTOP ; Windows XP ; 5.1 ; i686 ;
+; Assembler ; TYLER-LAPTOP ; Windows XP ; 5.1 ; i686 ;
+; Classic Timing Analyzer ; TYLER-LAPTOP ; Windows XP ; 5.1 ; i686 ;
++-------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
+quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
+quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
+quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
+
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.summary
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.summary (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.summary (revision 6)
@@ -0,0 +1,56 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 6.868 ns
+From : KEY[0]
+To : miniUART:U1|TxUnit:TxDev|TReg[6]
+From Clock : --
+To Clock : CLOCK_50
+Failed Paths : 0
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 8.405 ns
+From : miniUART:U1|DataOut[7]$latch
+To : LEDR[7]
+From Clock : SW[8]
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : 0.138 ns
+From : SW[1]
+To : miniUART:U1|RxUnit:RxDev|tmpDRdy
+From Clock : --
+To Clock : CLOCK_50
+Failed Paths : 0
+
+Type : Clock Setup: 'CLOCK_50'
+Slack : N/A
+Required Time : None
+Actual Time : 226.81 MHz ( period = 4.409 ns )
+From : miniUART:U1|RxUnit:RxDev|SampleCnt[1]
+To : miniUART:U1|RxUnit:RxDev|outErr
+From Clock : CLOCK_50
+To Clock : CLOCK_50
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.summary
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.summary (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.summary (revision 6)
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Sat Jan 16 19:25:56 2010
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : uart
+Top-level Entity Name : TOP_UART
+Family : Cyclone II
+Device : EP2C20F484C7
+Timing Models : Final
+Total logic elements : 155 / 18,752 ( < 1 % )
+ Total combinational functions : 150 / 18,752 ( < 1 % )
+ Dedicated logic registers : 70 / 18,752 ( < 1 % )
+Total registers : 70
+Total pins : 281 / 315 ( 89 % )
+Total virtual pins : 0
+Total memory bits : 0 / 239,616 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.map.rpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.map.rpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.map.rpt (revision 6)
@@ -0,0 +1,570 @@
+Analysis & Synthesis report for uart
+Sat Jan 16 19:25:45 2010
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. User-Specified and Inferred Latches
+ 8. Registers Removed During Synthesis
+ 9. General Register Statistics
+ 10. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 11. Port Connectivity Checks: "miniUART:U1"
+ 12. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sat Jan 16 19:25:45 2010 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; uart ;
+; Top-level Entity Name ; TOP_UART ;
+; Family ; Cyclone II ;
+; Total logic elements ; 157 ;
+; Total combinational functions ; 150 ;
+; Dedicated logic registers ; 70 ;
+; Total registers ; 70 ;
+; Total pins ; 281 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C20F484C7 ; ;
+; Top-level entity name ; top_uart ; uart ;
+; Family name ; Cyclone II ; Stratix II ;
+; Use Generated Physical Constraints File ; Off ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++--------------------------------------------------------------+--------------------+--------------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+-----------------+----------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+-----------------+----------------------------------------+
+; clkUnit.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/clkUnit.vhd ;
+; miniUART.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/miniUART.vhd ;
+; RxUnit.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/RxUnit.vhd ;
+; top_uart.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/top_uart.vhd ;
+; TxUnit.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/TxUnit.vhd ;
+; uart_lib.vhd ; yes ; User VHDL File ; C:/altera/cores/vhdl/uart/uart_lib.vhd ;
++----------------------------------+-----------------+-----------------+----------------------------------------+
+
+
++--------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+----------+
+; Resource ; Usage ;
++---------------------------------------------+----------+
+; Estimated Total logic elements ; 157 ;
+; ; ;
+; Total combinational functions ; 150 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 81 ;
+; -- 3 input functions ; 38 ;
+; -- <=2 input functions ; 31 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 150 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers ; 70 ;
+; -- Dedicated logic registers ; 70 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 281 ;
+; Maximum fan-out node ; CLOCK_50 ;
+; Maximum fan-out ; 70 ;
+; Total fan-out ; 695 ;
+; Average fan-out ; 1.39 ;
++---------------------------------------------+----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
+; |TOP_UART ; 150 (0) ; 70 (0) ; 0 ; 0 ; 0 ; 0 ; 281 ; 0 ; |TOP_UART ; work ;
+; |miniUART:U1| ; 150 (31) ; 70 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_UART|miniUART:U1 ; work ;
+; |ClkUnit:ClkDiv| ; 41 (41) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_UART|miniUART:U1|ClkUnit:ClkDiv ; work ;
+; |RxUnit:RxDev| ; 44 (44) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_UART|miniUART:U1|RxUnit:RxDev ; work ;
+; |TxUnit:TxDev| ; 34 (34) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TOP_UART|miniUART:U1|TxUnit:TxDev ; work ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches ;
++-----------------------------------------------------+--------------------------+------------------------+
+; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
++-----------------------------------------------------+--------------------------+------------------------+
+; miniUART:U1|DataOut[0]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[0]_240 ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[1]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[2]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[3]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[4]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[5]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[6]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|DataOut[7]$latch ; miniUART:U1|DataOut[0]~8 ; yes ;
+; miniUART:U1|TxData[0] ; miniUART:U1|process_1~2 ; yes ;
+; miniUART:U1|TxData[3] ; miniUART:U1|process_1~2 ; yes ;
+; miniUART:U1|TxData[5] ; miniUART:U1|process_1~2 ; yes ;
+; miniUART:U1|TxData[6] ; miniUART:U1|process_1~2 ; yes ;
+; Number of user-specified and inferred latches = 13 ; ; ;
++-----------------------------------------------------+--------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++-----------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++------------------------------------------+----------------------------------------+
+; Register name ; Reason for Removal ;
++------------------------------------------+----------------------------------------+
+; miniUART:U1|CSReg[0..1] ; Stuck at GND due to stuck port data_in ;
+; miniUART:U1|CSReg[4..7] ; Stuck at VCC due to stuck port data_in ;
+; miniUART:U1|TxUnit:TxDev|TBuff[1..2,4,7] ; Stuck at GND due to stuck port data_in ;
+; Total Number of Removed Registers = 10 ; ;
++------------------------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 70 ;
+; Number of registers using Synchronous Clear ; 4 ;
+; Number of registers using Synchronous Load ; 3 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 29 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
+; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |TOP_UART|miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[5] ;
+; 32:1 ; 5 bits ; 105 LEs ; 105 LEs ; 0 LEs ; Yes ; |TOP_UART|miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1] ;
+; 11:1 ; 3 bits ; 21 LEs ; 3 LEs ; 18 LEs ; Yes ; |TOP_UART|miniUART:U1|TxUnit:TxDev|TReg[4] ;
+; 11:1 ; 4 bits ; 28 LEs ; 4 LEs ; 24 LEs ; Yes ; |TOP_UART|miniUART:U1|TxUnit:TxDev|TReg[6] ;
+; 7:1 ; 10 bits ; 40 LEs ; 10 LEs ; 30 LEs ; Yes ; |TOP_UART|miniUART:U1|RxUnit:RxDev|outErr ;
+; 20:1 ; 3 bits ; 39 LEs ; 12 LEs ; 27 LEs ; Yes ; |TOP_UART|miniUART:U1|TxUnit:TxDev|BitCnt[2] ;
+; 9:1 ; 8 bits ; 48 LEs ; 8 LEs ; 40 LEs ; Yes ; |TOP_UART|miniUART:U1|RxUnit:RxDev|ShtReg[0] ;
+; 22:1 ; 4 bits ; 56 LEs ; 4 LEs ; 52 LEs ; Yes ; |TOP_UART|miniUART:U1|RxUnit:RxDev|SampleCnt[3] ;
+; 22:1 ; 3 bits ; 42 LEs ; 12 LEs ; 30 LEs ; Yes ; |TOP_UART|miniUART:U1|RxUnit:RxDev|BitCnt[1] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "miniUART:U1" ;
++--------------+-------+----------+--------------+
+; Port ; Type ; Severity ; Details ;
++--------------+-------+----------+--------------+
+; datain[6..5] ; Input ; Info ; Stuck at VCC ;
+; datain[2..1] ; Input ; Info ; Stuck at GND ;
+; datain[7] ; Input ; Info ; Stuck at GND ;
+; datain[4] ; Input ; Info ; Stuck at GND ;
+; datain[3] ; Input ; Info ; Stuck at VCC ;
+; datain[0] ; Input ; Info ; Stuck at VCC ;
++--------------+-------+----------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Jan 16 19:25:40 2010
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
+Info: Found 2 design units, including 1 entities, in source file decoder_7seg.vhd
+ Info: Found design unit 1: decoder_7seg-rtl
+ Info: Found entity 1: decoder_7seg
+Info: Found 2 design units, including 1 entities, in source file uart.vhd
+ Info: Found design unit 1: UART-Behaviour
+ Info: Found entity 1: UART
+Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd
+ Info: Found design unit 1: ClkUnit-Behaviour
+ Info: Found entity 1: ClkUnit
+Info: Found 2 design units, including 1 entities, in source file miniUART.vhd
+ Info: Found design unit 1: miniUART-uart
+ Info: Found entity 1: miniUART
+Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd
+ Info: Found design unit 1: RxUnit-Behaviour
+ Info: Found entity 1: RxUnit
+Info: Found 2 design units, including 1 entities, in source file top_uart.vhd
+ Info: Found design unit 1: TOP_UART-rtl
+ Info: Found entity 1: TOP_UART
+Info: Found 2 design units, including 1 entities, in source file TxUnit.vhd
+ Info: Found design unit 1: TxUnit-Behaviour
+ Info: Found entity 1: TxUnit
+Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd
+ Info: Found design unit 1: UART_Def
+ Info: Found design unit 2: UART_Def-body
+Info: Elaborating entity "top_uart" for the top level hierarchy
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal "HEX0" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal "HEX1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal "HEX2" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(23): used implicit default value for signal "HEX3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal "SRAM_WE_N" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(62): used implicit default value for signal "SRAM_OE_N" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(70): used implicit default value for signal "SD_DAT3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(71): used implicit default value for signal "SD_CMD" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(72): used implicit default value for signal "SD_CLK" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal "VGA_HS" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(89): used implicit default value for signal "VGA_VS" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal "VGA_R" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal "VGA_G" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10541): VHDL Signal Declaration warning at top_uart.vhd(91): used implicit default value for signal "VGA_B" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10873): Using initial value X (don't care) for net "LEDG[7]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDG[6]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDG[5]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDG[4]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDG[3]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDG[2]" at top_uart.vhd(25)
+Warning (10873): Using initial value X (don't care) for net "LEDR[9]" at top_uart.vhd(26)
+Warning (10873): Using initial value X (don't care) for net "LEDR[8]" at top_uart.vhd(26)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[15]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[14]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[13]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[12]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[11]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[10]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[9]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[8]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[7]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[6]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[5]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[4]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[3]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[2]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[1]" at top_uart.vhd(61)
+Warning (10873): Using initial value X (don't care) for net "SRAM_ADDR[0]" at top_uart.vhd(61)
+Info: Elaborating entity "miniUART" for hierarchy "miniUART:U1"
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal "CS_N" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(180): signal "RD_N" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal "CS_N" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(185): signal "WR_N" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(190): signal "Read" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal "Read" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(192): signal "Addr" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(193): signal "RxData" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal "Read" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(194): signal "Addr" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(195): signal "CSReg" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(198): signal "Load" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal "Load" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(200): signal "Addr" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at miniUART.vhd(201): signal "DataIn" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable "DataOut", which holds its previous value in one or more paths through the process
+Warning (10631): VHDL Process Statement warning at miniUART.vhd(178): inferring latch(es) for signal or variable "TxData", which holds its previous value in one or more paths through the process
+Info (10041): Inferred latch for "TxData[0]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[1]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[2]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[3]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[4]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[5]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[6]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "TxData[7]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[0]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[1]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[2]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[3]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[4]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[5]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[6]" at miniUART.vhd(178)
+Info (10041): Inferred latch for "DataOut[7]" at miniUART.vhd(178)
+Info: Elaborating entity "ClkUnit" for hierarchy "miniUART:U1|ClkUnit:ClkDiv"
+Info: Elaborating entity "TxUnit" for hierarchy "miniUART:U1|TxUnit:TxDev"
+Info: Elaborating entity "RxUnit" for hierarchy "miniUART:U1|RxUnit:RxDev"
+Warning: Tri-state node(s) do not directly drive top-level pin(s)
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[0]~6" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[1]~7" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[2]~5" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[3]~4" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[4]~3" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[5]~2" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[6]~1" feeding internal logic into a wire
+ Warning: Converted tri-state buffer "miniUART:U1|TxData[7]~0" feeding internal logic into a wire
+Warning: Ignored assignment(s) for "CLOCK_27[0]" because "CLOCK_27" is not a bus or array
+Warning: Ignored assignment(s) for "CLOCK_27[1]" because "CLOCK_27" is not a bus or array
+Warning: The following nodes have both tri-state and non-tri-state drivers
+ Warning: Inserted always-enabled tri-state buffer between "UART_TXD" and its non-tri-state driver.
+Warning: The following bidir pins have no drivers
+ Warning: Bidir "SRAM_DQ[0]" has no driver
+ Warning: Bidir "SRAM_DQ[1]" has no driver
+ Warning: Bidir "SRAM_DQ[2]" has no driver
+ Warning: Bidir "SRAM_DQ[3]" has no driver
+ Warning: Bidir "SRAM_DQ[4]" has no driver
+ Warning: Bidir "SRAM_DQ[5]" has no driver
+ Warning: Bidir "SRAM_DQ[6]" has no driver
+ Warning: Bidir "SRAM_DQ[7]" has no driver
+ Warning: Bidir "PS2_DAT" has no driver
+ Warning: Bidir "PS2_CLK" has no driver
+Warning: Removed fan-outs from the following always-disabled I/O buffers
+ Warning: Removed fan-out from the always-disabled I/O buffer "UART_TXD" to the node "UART_TXD"
+Warning: Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX0[0]" is stuck at GND
+ Warning (13410): Pin "HEX0[1]" is stuck at GND
+ Warning (13410): Pin "HEX0[2]" is stuck at GND
+ Warning (13410): Pin "HEX0[3]" is stuck at GND
+ Warning (13410): Pin "HEX0[4]" is stuck at GND
+ Warning (13410): Pin "HEX0[5]" is stuck at GND
+ Warning (13410): Pin "HEX0[6]" is stuck at GND
+ Warning (13410): Pin "HEX1[0]" is stuck at GND
+ Warning (13410): Pin "HEX1[1]" is stuck at GND
+ Warning (13410): Pin "HEX1[2]" is stuck at GND
+ Warning (13410): Pin "HEX1[3]" is stuck at GND
+ Warning (13410): Pin "HEX1[4]" is stuck at GND
+ Warning (13410): Pin "HEX1[5]" is stuck at GND
+ Warning (13410): Pin "HEX1[6]" is stuck at GND
+ Warning (13410): Pin "HEX2[0]" is stuck at GND
+ Warning (13410): Pin "HEX2[1]" is stuck at GND
+ Warning (13410): Pin "HEX2[2]" is stuck at GND
+ Warning (13410): Pin "HEX2[3]" is stuck at GND
+ Warning (13410): Pin "HEX2[4]" is stuck at GND
+ Warning (13410): Pin "HEX2[5]" is stuck at GND
+ Warning (13410): Pin "HEX2[6]" is stuck at GND
+ Warning (13410): Pin "HEX3[0]" is stuck at GND
+ Warning (13410): Pin "HEX3[1]" is stuck at GND
+ Warning (13410): Pin "HEX3[2]" is stuck at GND
+ Warning (13410): Pin "HEX3[3]" is stuck at GND
+ Warning (13410): Pin "HEX3[4]" is stuck at GND
+ Warning (13410): Pin "HEX3[5]" is stuck at GND
+ Warning (13410): Pin "HEX3[6]" is stuck at GND
+ Warning (13410): Pin "LEDG[2]" is stuck at GND
+ Warning (13410): Pin "LEDG[3]" is stuck at GND
+ Warning (13410): Pin "LEDG[4]" is stuck at GND
+ Warning (13410): Pin "LEDG[5]" is stuck at GND
+ Warning (13410): Pin "LEDG[6]" is stuck at GND
+ Warning (13410): Pin "LEDG[7]" is stuck at GND
+ Warning (13410): Pin "LEDR[8]" is stuck at GND
+ Warning (13410): Pin "LEDR[9]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[0]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[1]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[2]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[3]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[4]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[5]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[6]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[7]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[8]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[9]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[10]" is stuck at GND
+ Warning (13410): Pin "DRAM_ADDR[11]" is stuck at GND
+ Warning (13410): Pin "DRAM_LDQM" is stuck at GND
+ Warning (13410): Pin "DRAM_UDQM" is stuck at GND
+ Warning (13410): Pin "DRAM_WE_N" is stuck at VCC
+ Warning (13410): Pin "DRAM_CAS_N" is stuck at VCC
+ Warning (13410): Pin "DRAM_RAS_N" is stuck at VCC
+ Warning (13410): Pin "DRAM_CS_N" is stuck at VCC
+ Warning (13410): Pin "DRAM_BA_0" is stuck at GND
+ Warning (13410): Pin "DRAM_BA_1" is stuck at GND
+ Warning (13410): Pin "DRAM_CLK" is stuck at GND
+ Warning (13410): Pin "DRAM_CKE" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[0]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[1]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[2]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[3]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[4]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[5]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[6]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[7]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[8]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[9]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[10]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[11]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[12]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[13]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[14]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[15]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[16]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[17]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[18]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[19]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[20]" is stuck at GND
+ Warning (13410): Pin "FL_ADDR[21]" is stuck at GND
+ Warning (13410): Pin "FL_WE_N" is stuck at VCC
+ Warning (13410): Pin "FL_RST_N" is stuck at GND
+ Warning (13410): Pin "FL_OE_N" is stuck at VCC
+ Warning (13410): Pin "FL_CE_N" is stuck at VCC
+ Warning (13410): Pin "SRAM_ADDR[0]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[1]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[2]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[3]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[4]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[5]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[6]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[7]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[8]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[9]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[10]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[11]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[12]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[13]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[14]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[15]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[16]" is stuck at GND
+ Warning (13410): Pin "SRAM_ADDR[17]" is stuck at GND
+ Warning (13410): Pin "SRAM_UB_N" is stuck at VCC
+ Warning (13410): Pin "SRAM_LB_N" is stuck at GND
+ Warning (13410): Pin "SRAM_WE_N" is stuck at GND
+ Warning (13410): Pin "SRAM_CE_N" is stuck at GND
+ Warning (13410): Pin "SRAM_OE_N" is stuck at GND
+ Warning (13410): Pin "SD_DAT3" is stuck at GND
+ Warning (13410): Pin "SD_CMD" is stuck at GND
+ Warning (13410): Pin "SD_CLK" is stuck at GND
+ Warning (13410): Pin "TDO" is stuck at GND
+ Warning (13410): Pin "I2C_SCLK" is stuck at GND
+ Warning (13410): Pin "VGA_HS" is stuck at GND
+ Warning (13410): Pin "VGA_VS" is stuck at GND
+ Warning (13410): Pin "VGA_R[0]" is stuck at GND
+ Warning (13410): Pin "VGA_R[1]" is stuck at GND
+ Warning (13410): Pin "VGA_R[2]" is stuck at GND
+ Warning (13410): Pin "VGA_R[3]" is stuck at GND
+ Warning (13410): Pin "VGA_G[0]" is stuck at GND
+ Warning (13410): Pin "VGA_G[1]" is stuck at GND
+ Warning (13410): Pin "VGA_G[2]" is stuck at GND
+ Warning (13410): Pin "VGA_G[3]" is stuck at GND
+ Warning (13410): Pin "VGA_B[0]" is stuck at GND
+ Warning (13410): Pin "VGA_B[1]" is stuck at GND
+ Warning (13410): Pin "VGA_B[2]" is stuck at GND
+ Warning (13410): Pin "VGA_B[3]" is stuck at GND
+ Warning (13410): Pin "AUD_DACDAT" is stuck at GND
+ Warning (13410): Pin "AUD_XCK" is stuck at GND
+Warning: Ignored assignments for entity "UART" -- entity does not exist in design
+ Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity UART -section_id "Root Region" is ignored
+ Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity UART -section_id "Root Region" is ignored
+Warning: Design contains 16 input pin(s) that do not drive logic
+ Warning (15610): No output dependent on input pin "CLOCK_27"
+ Warning (15610): No output dependent on input pin "EXT_CLOCK"
+ Warning (15610): No output dependent on input pin "KEY[1]"
+ Warning (15610): No output dependent on input pin "KEY[2]"
+ Warning (15610): No output dependent on input pin "KEY[3]"
+ Warning (15610): No output dependent on input pin "SW[3]"
+ Warning (15610): No output dependent on input pin "SW[4]"
+ Warning (15610): No output dependent on input pin "SW[5]"
+ Warning (15610): No output dependent on input pin "SW[6]"
+ Warning (15610): No output dependent on input pin "SW[9]"
+ Warning (15610): No output dependent on input pin "IRDA_RXD"
+ Warning (15610): No output dependent on input pin "SD_DAT"
+ Warning (15610): No output dependent on input pin "TDI"
+ Warning (15610): No output dependent on input pin "TCK"
+ Warning (15610): No output dependent on input pin "TCS"
+ Warning (15610): No output dependent on input pin "AUD_ADCDAT"
+Info: Implemented 451 device resources after synthesis - the final resource count might be different
+ Info: Implemented 24 input pins
+ Info: Implemented 139 output pins
+ Info: Implemented 118 bidirectional pins
+ Info: Implemented 170 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 230 warnings
+ Info: Peak virtual memory: 195 megabytes
+ Info: Processing ended: Sat Jan 16 19:25:45 2010
+ Info: Elapsed time: 00:00:05
+ Info: Total CPU time (on all processors): 00:00:05
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/UARTtest.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/UARTtest.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/UARTtest.vhd (revision 6)
@@ -0,0 +1,213 @@
+--============================================================================--
+-- Design units : TestBench for miniUART device.
+--
+-- File name : UARTTest.vhd
+--
+-- Purpose : Implements the test bench for miniUART device.
+--
+-- Library : uart_Lib.vhd
+--
+-- Dependencies : IEEE.Std_Logic_1164
+--
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 0.1 Ovidiu Lupas December 1999 New model
+--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Clock generator
+-------------------------------------------------------------------------------
+library IEEE,work;
+use IEEE.Std_Logic_1164.all;
+--
+entity ClkGen is
+ port (
+ Clk : out Std_Logic); -- Oscillator clock
+end ClkGen;--==================== End of entity ==============================--
+--------------------------------------------------------------------------------
+-- Architecture for clock and reset signals generator
+--------------------------------------------------------------------------------
+architecture Behaviour of ClkGen is
+begin --========================== Architecture ==============================--
+ ------------------------------------------------------------------------------
+ -- Provide the system clock signal
+ ------------------------------------------------------------------------------
+ ClkDriver : process
+ variable clktmp : Std_Logic := '1';
+ variable tpw_CI_posedge : Time := 12 ns; -- ~40 MHz
+ begin
+ Clk <= clktmp;
+ clktmp := not clktmp;
+ wait for tpw_CI_posedge;
+ end process;
+end Behaviour; --=================== End of architecure =====================--
+-------------------------------------------------------------------------------
+-- LoopBack Device
+-------------------------------------------------------------------------------
+library IEEE,work;
+use IEEE.Std_Logic_1164.all;
+--
+entity LoopBack is
+ port (
+ Clk : in Std_Logic; -- Oscillator clock
+ RxWr : in Std_Logic; -- Rx line
+ TxWr : out Std_Logic); -- Tx line
+end LoopBack; --==================== End of entity ==========================--
+--------------------------------------------------------------------------------
+-- Architecture for clock and reset signals generator
+--------------------------------------------------------------------------------
+architecture Behaviour of LoopBack is
+begin --========================== Architecture ==============================--
+ ------------------------------------------------------------------------------
+ -- Provide the external clock signal
+ ------------------------------------------------------------------------------
+ ClkTrig : process(Clk)
+ begin
+ TxWr <= RxWr;
+ end process;
+end Behaviour; --=================== End of architecure =====================--
+
+--------------------------------------------------------------------------------
+-- Testbench for UART device
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.Uart_Def.all;
+
+entity UARTTEST is
+end UARTTEST;
+
+architecture stimulus of UARTTEST is
+ -------------------------------------------------------------------
+ -- Signals
+ -------------------------------------------------------------------
+ signal Reset : Std_Logic; -- Synchro signal
+ signal Clk : Std_Logic; -- Clock signal
+ signal DataIn : Std_Logic_Vector(7 downto 0);
+ signal DataOut : Std_Logic_Vector(7 downto 0);
+ signal RxD : Std_Logic; -- RS-232 data input
+ signal TxD : Std_Logic; -- RS-232 data output
+ signal CS_N : Std_Logic;
+ signal RD_N : Std_Logic;
+ signal WR_N : Std_Logic;
+ signal IntRx_N : Std_Logic; -- Receive interrupt
+ signal IntTx_N : Std_Logic; -- Transmit interrupt
+ signal Addr : Std_Logic_Vector(1 downto 0); --
+ -------------------------------------------------------------------
+ -- Clock Divider
+ -------------------------------------------------------------------
+ component ClkGen is
+ port (
+ Clk : out Std_Logic); -- Oscillator clock
+ end component;
+ -------------------------------------------------------------------
+ -- LoopBack Device
+ -------------------------------------------------------------------
+ component LoopBack is
+ port (
+ Clk : in Std_Logic; -- Oscillator clock
+ RxWr : in Std_Logic; -- Rx line
+ TxWr : out Std_Logic); -- Tx line
+ end component;
+ -------------------------------------------------------------------
+ -- UART Device
+ -------------------------------------------------------------------
+ component miniUART is
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+ end component;
+begin --======================== Architecture ========================--
+ ---------------------------------------------------------------------
+ -- Instantiation of components
+ ---------------------------------------------------------------------
+ Clock : ClkGen port map (Clk);
+ LoopDev : LoopBack port map (Clk,TxD,RxD);
+ miniUARTDev : miniUART port map (Clk,Reset,CS_N,RD_N,WR_N,RxD,TxD,
+ IntRx_N,IntTx_N,Addr,DataIn,DataOut);
+ ---------------------------------------------------------------------
+ -- Reset cycle
+ ---------------------------------------------------------------------
+ RstCyc : process
+ begin
+ Reset <= '1';
+ wait for 5 ns;
+ Reset <= '0';
+ wait for 250 ns;
+ Reset <= '1';
+ wait;
+ end process;
+ ---------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------
+ ProcCyc : process(Clk,IntRx_N,IntTx_N,Reset)
+ variable counter : unsigned(3 downto 0);
+ constant cone : unsigned(3 downto 0):= "0001";
+ variable temp : bit := '0';
+ begin
+ if Rising_Edge(Reset) then
+ counter := "0000";
+ WR_N <= '1';
+ RD_N <= '1';
+ CS_N <= '1';
+ elsif Rising_Edge(Clk) then
+ if IntTx_N = '0' then
+ if temp = '0' then
+ temp := '1';
+ case counter is
+ when "0000" =>
+ Addr <= "00";
+ DataIn <= x"AA";
+ WR_N <= '0';
+ CS_N <= '0';
+ counter := counter + cone;
+ when "0001" =>
+ Addr <= "00";
+ DataIn <= x"AF";
+ WR_N <= '0';
+ CS_N <= '0';
+ counter := counter + cone;
+ when "0010" =>
+ Addr <= "00";
+ DataIn <= x"55";
+ WR_N <= '0';
+ CS_N <= '0';
+ counter := counter + cone;
+ when "0011" =>
+ Addr <= "00";
+ DataIn <= x"E8";
+ WR_N <= '0';
+ CS_N <= '0';
+ counter := "0000";
+ when others => null;
+ end case;
+ elsif temp = '1' then
+ temp := '0';
+ end if;
+ elsif IntRx_N = '0' then
+ Addr <= "00";
+ RD_N <= '0';
+ CS_N <= '0';
+ else
+ RD_N <= '1';
+ CS_N <= '1';
+ WR_N <= '1';
+ DataIn <= "ZZZZZZZZ";
+ end if;
+ end if;
+ end process;
+end stimulus; --================== End of TestBench ==================--
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.pof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.pof
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.pof (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.pof (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/uart.pof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/DE2 pins.csv
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/DE2 pins.csv (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/DE2 pins.csv (revision 6)
@@ -0,0 +1,505 @@
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+# Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# File: C:\altera\cores\z80soc\DE1\z80soc.csv
+# Generated on: Mon Sep 14 22:50:01 2009
+
+# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.
+
+To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Group,Current Strength,PCB layer
+GPIO_0[0],Unknown,PIN_A13,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[1],Unknown,PIN_B13,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[2],Unknown,PIN_A14,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[3],Unknown,PIN_B14,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[4],Unknown,PIN_A15,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[5],Unknown,PIN_B15,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[6],Unknown,PIN_A16,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[7],Unknown,PIN_B16,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[8],Unknown,PIN_A17,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[9],Unknown,PIN_B17,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_0[10],Unknown,PIN_A18,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[11],Unknown,PIN_B18,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[12],Unknown,PIN_A19,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[13],Unknown,PIN_B19,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[14],Unknown,PIN_A20,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[15],Unknown,PIN_B20,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_0[16],Unknown,PIN_C21,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[17],Unknown,PIN_C22,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[18],Unknown,PIN_D21,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[19],Unknown,PIN_D22,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[20],Unknown,PIN_E21,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[21],Unknown,PIN_E22,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[22],Unknown,PIN_F21,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[23],Unknown,PIN_F22,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_0[24],Unknown,PIN_G21,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[25],Unknown,PIN_G22,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[26],Unknown,PIN_J21,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[27],Unknown,PIN_J22,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[28],Unknown,PIN_K21,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[29],Unknown,PIN_K22,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[30],Unknown,PIN_J19,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[31],Unknown,PIN_J20,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[32],Unknown,PIN_J18,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[33],Unknown,PIN_K20,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[34],Unknown,PIN_L19,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_0[35],Unknown,PIN_L18,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_1[0],Unknown,PIN_H12,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[1],Unknown,PIN_H13,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[2],Unknown,PIN_H14,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[3],Unknown,PIN_G15,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[4],Unknown,PIN_E14,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[5],Unknown,PIN_E15,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[6],Unknown,PIN_F15,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[7],Unknown,PIN_G16,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[8],Unknown,PIN_F12,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[9],Unknown,PIN_F13,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[10],Unknown,PIN_C14,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[11],Unknown,PIN_D14,4,B4_N1,3.3-V LVTTL,,,,
+GPIO_1[12],Unknown,PIN_D15,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[13],Unknown,PIN_D16,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[14],Unknown,PIN_C17,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[15],Unknown,PIN_C18,4,B4_N0,3.3-V LVTTL,,,,
+GPIO_1[16],Unknown,PIN_C19,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[17],Unknown,PIN_C20,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[18],Unknown,PIN_D19,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[19],Unknown,PIN_D20,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[20],Unknown,PIN_E20,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[21],Unknown,PIN_F20,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[22],Unknown,PIN_E19,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[23],Unknown,PIN_E18,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[24],Unknown,PIN_G20,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[25],Unknown,PIN_G18,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[26],Unknown,PIN_G17,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[27],Unknown,PIN_H17,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[28],Unknown,PIN_J15,5,B5_N1,3.3-V LVTTL,,,,
+GPIO_1[29],Unknown,PIN_H18,5,B5_N0,3.3-V LVTTL,,,,
+GPIO_1[30],Unknown,PIN_N22,6,B6_N0,3.3-V LVTTL,,,,
+GPIO_1[31],Unknown,PIN_N21,6,B6_N0,3.3-V LVTTL,,,,
+GPIO_1[32],Unknown,PIN_P15,6,B6_N0,3.3-V LVTTL,,,,
+GPIO_1[33],Unknown,PIN_N15,6,B6_N0,3.3-V LVTTL,,,,
+GPIO_1[34],Unknown,PIN_P17,6,B6_N0,3.3-V LVTTL,,,,
+GPIO_1[35],Unknown,PIN_P18,6,B6_N0,3.3-V LVTTL,,,,
+SW[0],Unknown,PIN_L22,5,B5_N1,3.3-V LVTTL,,,,
+SW[1],Unknown,PIN_L21,5,B5_N1,3.3-V LVTTL,,,,
+SW[2],Unknown,PIN_M22,6,B6_N0,3.3-V LVTTL,,,,
+SW[3],Unknown,PIN_V12,7,B7_N1,3.3-V LVTTL,,,,
+SW[4],Unknown,PIN_W12,7,B7_N1,3.3-V LVTTL,,,,
+SW[5],Unknown,PIN_U12,8,B8_N0,3.3-V LVTTL,,,,
+SW[6],Unknown,PIN_U11,8,B8_N0,3.3-V LVTTL,,,,
+SW[7],Unknown,PIN_M2,1,B1_N0,3.3-V LVTTL,,,,
+SW[8],Unknown,PIN_M1,1,B1_N0,3.3-V LVTTL,,,,
+SW[9],Unknown,PIN_L2,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[0],Unknown,PIN_J2,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[1],Unknown,PIN_J1,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[2],Unknown,PIN_H2,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[3],Unknown,PIN_H1,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[4],Unknown,PIN_F2,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[5],Unknown,PIN_F1,2,B2_N1,3.3-V LVTTL,,,,
+HEX0[6],Unknown,PIN_E2,2,B2_N1,3.3-V LVTTL,,,,
+HEX1[0],Unknown,PIN_E1,2,B2_N1,3.3-V LVTTL,,,,
+HEX1[1],Unknown,PIN_H6,2,B2_N0,3.3-V LVTTL,,,,
+HEX1[2],Unknown,PIN_H5,2,B2_N0,3.3-V LVTTL,,,,
+HEX1[3],Unknown,PIN_H4,2,B2_N0,3.3-V LVTTL,,,,
+HEX1[4],Unknown,PIN_G3,2,B2_N0,3.3-V LVTTL,,,,
+HEX1[5],Unknown,PIN_D2,2,B2_N0,3.3-V LVTTL,,,,
+HEX1[6],Unknown,PIN_D1,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[0],Unknown,PIN_G5,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[1],Unknown,PIN_G6,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[2],Unknown,PIN_C2,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[3],Unknown,PIN_C1,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[4],Unknown,PIN_E3,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[5],Unknown,PIN_E4,2,B2_N0,3.3-V LVTTL,,,,
+HEX2[6],Unknown,PIN_D3,2,B2_N0,3.3-V LVTTL,,,,
+HEX3[0],Unknown,PIN_F4,2,B2_N0,3.3-V LVTTL,,,,
+HEX3[1],Unknown,PIN_D5,2,B2_N0,3.3-V LVTTL,,,,
+HEX3[2],Unknown,PIN_D6,2,B2_N0,3.3-V LVTTL,,,,
+HEX3[3],Unknown,PIN_J4,2,B2_N1,3.3-V LVTTL,,,,
+HEX3[4],Unknown,PIN_L8,2,B2_N1,3.3-V LVTTL,,,,
+HEX3[5],Unknown,PIN_F3,2,B2_N0,3.3-V LVTTL,,,,
+HEX3[6],Unknown,PIN_D4,2,B2_N0,3.3-V LVTTL,,,,
+KEY[0],Unknown,PIN_R22,6,B6_N0,3.3-V LVTTL,,,,
+KEY[1],Unknown,PIN_R21,6,B6_N0,3.3-V LVTTL,,,,
+KEY[2],Unknown,PIN_T22,6,B6_N0,3.3-V LVTTL,,,,
+KEY[3],Unknown,PIN_T21,6,B6_N0,3.3-V LVTTL,,,,
+LEDR[0],Unknown,PIN_R20,6,B6_N0,3.3-V LVTTL,,,,
+LEDR[1],Unknown,PIN_R19,6,B6_N0,3.3-V LVTTL,,,,
+LEDR[2],Unknown,PIN_U19,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[3],Unknown,PIN_Y19,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[4],Unknown,PIN_T18,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[5],Unknown,PIN_V19,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[6],Unknown,PIN_Y18,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[7],Unknown,PIN_U18,6,B6_N1,3.3-V LVTTL,,,,
+LEDR[8],Unknown,PIN_R18,6,B6_N0,3.3-V LVTTL,,,,
+LEDR[9],Unknown,PIN_R17,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[0],Unknown,PIN_U22,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[1],Unknown,PIN_U21,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[2],Unknown,PIN_V22,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[3],Unknown,PIN_V21,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[4],Unknown,PIN_W22,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[5],Unknown,PIN_W21,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[6],Unknown,PIN_Y22,6,B6_N1,3.3-V LVTTL,,,,
+LEDG[7],Unknown,PIN_Y21,6,B6_N1,3.3-V LVTTL,,,,
+CLOCK_27[0],Unknown,PIN_D12,3,B3_N0,,,,,
+CLOCK_27[1],Unknown,PIN_E12,3,B3_N0,3.3-V LVTTL,,,,
+CLOCK_24[0],Unknown,PIN_B12,4,B4_N1,3.3-V LVTTL,,,,
+CLOCK_24[1],Unknown,PIN_A12,4,B4_N1,3.3-V LVTTL,,,,
+CLOCK_50,Unknown,PIN_L1,2,B2_N1,3.3-V LVTTL,,,,
+EXT_CLOCK,Unknown,PIN_M21,6,B6_N0,3.3-V LVTTL,,,,
+PS2_CLK,Unknown,PIN_H15,4,B4_N0,3.3-V LVTTL,,,,
+PS2_DAT,Unknown,PIN_J14,4,B4_N0,3.3-V LVTTL,,,,
+UART_RXD,Unknown,PIN_F14,4,B4_N1,3.3-V LVTTL,,,,
+UART_TXD,Unknown,PIN_G12,4,B4_N1,3.3-V LVTTL,,,,
+TDI,Unknown,PIN_E8,3,B3_N1,3.3-V LVTTL,,,,
+TCS,Unknown,PIN_D8,3,B3_N1,3.3-V LVTTL,,,,
+TCK,Unknown,PIN_C7,3,B3_N1,3.3-V LVTTL,,,,
+TDO,Unknown,PIN_D7,3,B3_N1,3.3-V LVTTL,,,,
+VGA_R[0],Unknown,PIN_D9,3,B3_N0,3.3-V LVTTL,,,,
+VGA_R[1],Unknown,PIN_C9,3,B3_N1,3.3-V LVTTL,,,,
+VGA_R[2],Unknown,PIN_A7,3,B3_N1,3.3-V LVTTL,,,,
+VGA_R[3],Unknown,PIN_B7,3,B3_N1,3.3-V LVTTL,,,,
+VGA_G[0],Unknown,PIN_B8,3,B3_N0,3.3-V LVTTL,,,,
+VGA_G[1],Unknown,PIN_C10,3,B3_N0,3.3-V LVTTL,,,,
+VGA_G[2],Unknown,PIN_B9,3,B3_N0,3.3-V LVTTL,,,,
+VGA_G[3],Unknown,PIN_A8,3,B3_N0,3.3-V LVTTL,,,,
+VGA_B[0],Unknown,PIN_A9,3,B3_N0,3.3-V LVTTL,,,,
+VGA_B[1],Unknown,PIN_D11,3,B3_N0,3.3-V LVTTL,,,,
+VGA_B[2],Unknown,PIN_A10,3,B3_N0,3.3-V LVTTL,,,,
+VGA_B[3],Unknown,PIN_B10,3,B3_N0,3.3-V LVTTL,,,,
+VGA_HS,Unknown,PIN_A11,3,B3_N0,3.3-V LVTTL,,,,
+VGA_VS,Unknown,PIN_B11,3,B3_N0,3.3-V LVTTL,,,,
+I2C_SCLK,Unknown,PIN_A3,3,B3_N1,3.3-V LVTTL,,,,
+I2C_SDAT,Unknown,PIN_B3,3,B3_N1,3.3-V LVTTL,,,,
+AUD_ADCLRCK,Unknown,PIN_A6,3,B3_N1,3.3-V LVTTL,,,,
+AUD_ADCDAT,Unknown,PIN_B6,3,B3_N1,3.3-V LVTTL,,,,
+AUD_DACLRCK,Unknown,PIN_A5,3,B3_N1,3.3-V LVTTL,,,,
+AUD_DACDAT,Unknown,PIN_B5,3,B3_N1,3.3-V LVTTL,,,,
+AUD_XCK,Unknown,PIN_B4,3,B3_N1,3.3-V LVTTL,,,,
+AUD_BCLK,Unknown,PIN_A4,3,B3_N1,3.3-V LVTTL,,,,
+DRAM_ADDR[0],Unknown,PIN_W4,1,B1_N1,,,,,
+DRAM_ADDR[1],Unknown,PIN_W5,1,B1_N1,,,,,
+DRAM_ADDR[2],Unknown,PIN_Y3,1,B1_N1,,,,,
+DRAM_ADDR[3],Unknown,PIN_Y4,1,B1_N1,,,,,
+DRAM_ADDR[4],Unknown,PIN_R6,1,B1_N1,,,,,
+DRAM_ADDR[5],Unknown,PIN_R5,1,B1_N1,,,,,
+DRAM_ADDR[6],Unknown,PIN_P6,1,B1_N0,,,,,
+DRAM_ADDR[7],Unknown,PIN_P5,1,B1_N0,,,,,
+DRAM_ADDR[8],Unknown,PIN_P3,1,B1_N0,,,,,
+DRAM_ADDR[9],Unknown,PIN_N4,1,B1_N0,,,,,
+DRAM_ADDR[10],Unknown,PIN_W3,1,B1_N1,,,,,
+DRAM_ADDR[11],Unknown,PIN_N6,1,B1_N0,,,,,
+DRAM_BA_0,Unknown,PIN_U3,1,B1_N1,,,,,
+DRAM_BA_1,Unknown,PIN_V4,1,B1_N1,,,,,
+DRAM_CAS_N,Unknown,PIN_T3,1,B1_N1,,,,,
+DRAM_CKE,Unknown,PIN_N3,1,B1_N0,,,,,
+DRAM_CLK,Unknown,PIN_U4,1,B1_N1,,,,,
+DRAM_CS_N,Unknown,PIN_T6,1,B1_N1,,,,,
+DRAM_DQ[0],Unknown,PIN_U1,1,B1_N1,,,,,
+DRAM_DQ[1],Unknown,PIN_U2,1,B1_N1,,,,,
+DRAM_DQ[2],Unknown,PIN_V1,1,B1_N1,,,,,
+DRAM_DQ[3],Unknown,PIN_V2,1,B1_N1,,,,,
+DRAM_DQ[4],Unknown,PIN_W1,1,B1_N1,,,,,
+DRAM_DQ[5],Unknown,PIN_W2,1,B1_N1,,,,,
+DRAM_DQ[6],Unknown,PIN_Y1,1,B1_N1,,,,,
+DRAM_DQ[7],Unknown,PIN_Y2,1,B1_N1,,,,,
+DRAM_DQ[8],Unknown,PIN_N1,1,B1_N0,,,,,
+DRAM_DQ[9],Unknown,PIN_N2,1,B1_N0,,,,,
+DRAM_DQ[10],Unknown,PIN_P1,1,B1_N0,,,,,
+DRAM_DQ[11],Unknown,PIN_P2,1,B1_N0,,,,,
+DRAM_DQ[12],Unknown,PIN_R1,1,B1_N0,,,,,
+DRAM_DQ[13],Unknown,PIN_R2,1,B1_N0,,,,,
+DRAM_DQ[14],Unknown,PIN_T1,1,B1_N0,,,,,
+DRAM_DQ[15],Unknown,PIN_T2,1,B1_N0,,,,,
+DRAM_LDQM,Unknown,PIN_R7,1,B1_N0,,,,,
+DRAM_RAS_N,Unknown,PIN_T5,1,B1_N1,,,,,
+DRAM_UDQM,Unknown,PIN_M5,1,B1_N0,,,,,
+DRAM_WE_N,Unknown,PIN_R8,1,B1_N0,,,,,
+FL_ADDR[0],Unknown,PIN_AB20,7,B7_N0,,,,,
+FL_ADDR[1],Unknown,PIN_AA14,7,B7_N1,,,,,
+FL_ADDR[2],Unknown,PIN_Y16,7,B7_N0,,,,,
+FL_ADDR[3],Unknown,PIN_R15,7,B7_N0,,,,,
+FL_ADDR[4],Unknown,PIN_T15,7,B7_N0,,,,,
+FL_ADDR[5],Unknown,PIN_U15,7,B7_N0,,,,,
+FL_ADDR[6],Unknown,PIN_V15,7,B7_N0,,,,,
+FL_ADDR[7],Unknown,PIN_W15,7,B7_N0,,,,,
+FL_ADDR[8],Unknown,PIN_R14,7,B7_N0,,,,,
+FL_ADDR[9],Unknown,PIN_Y13,7,B7_N1,,,,,
+FL_ADDR[10],Unknown,PIN_R12,7,B7_N1,,,,,
+FL_ADDR[11],Unknown,PIN_T12,7,B7_N1,,,,,
+FL_ADDR[12],Unknown,PIN_AB14,7,B7_N1,,,,,
+FL_ADDR[13],Unknown,PIN_AA13,7,B7_N1,,,,,
+FL_ADDR[14],Unknown,PIN_AB13,7,B7_N1,,,,,
+FL_ADDR[15],Unknown,PIN_AA12,7,B7_N1,,,,,
+FL_ADDR[16],Unknown,PIN_AB12,7,B7_N1,,,,,
+FL_ADDR[17],Unknown,PIN_AA20,7,B7_N0,,,,,
+FL_ADDR[18],Unknown,PIN_U14,7,B7_N0,,,,,
+FL_ADDR[19],Unknown,PIN_V14,7,B7_N1,,,,,
+FL_ADDR[20],Unknown,PIN_U13,7,B7_N1,,,,,
+FL_ADDR[21],Unknown,PIN_R13,7,B7_N0,,,,,
+FL_DQ[0],Unknown,PIN_AB16,7,B7_N1,,,,,
+FL_DQ[1],Unknown,PIN_AA16,7,B7_N1,,,,,
+FL_DQ[2],Unknown,PIN_AB17,7,B7_N1,,,,,
+FL_DQ[3],Unknown,PIN_AA17,7,B7_N1,,,,,
+FL_DQ[4],Unknown,PIN_AB18,7,B7_N0,,,,,
+FL_DQ[5],Unknown,PIN_AA18,7,B7_N0,,,,,
+FL_DQ[6],Unknown,PIN_AB19,7,B7_N0,,,,,
+FL_DQ[7],Unknown,PIN_AA19,7,B7_N0,,,,,
+FL_OE_N,Unknown,PIN_AA15,7,B7_N1,,,,,
+FL_RST_N,Unknown,PIN_W14,7,B7_N1,,,,,
+FL_WE_N,Unknown,PIN_Y14,7,B7_N0,,,,,
+SRAM_ADDR[0],Unknown,PIN_AA3,8,B8_N1,,,,,
+SRAM_ADDR[1],Unknown,PIN_AB3,8,B8_N1,,,,,
+SRAM_ADDR[2],Unknown,PIN_AA4,8,B8_N1,,,,,
+SRAM_ADDR[3],Unknown,PIN_AB4,8,B8_N1,,,,,
+SRAM_ADDR[4],Unknown,PIN_AA5,8,B8_N1,,,,,
+SRAM_ADDR[5],Unknown,PIN_AB10,8,B8_N0,,,,,
+SRAM_ADDR[6],Unknown,PIN_AA11,8,B8_N0,,,,,
+SRAM_ADDR[7],Unknown,PIN_AB11,8,B8_N0,,,,,
+SRAM_ADDR[8],Unknown,PIN_V11,8,B8_N0,,,,,
+SRAM_ADDR[9],Unknown,PIN_W11,8,B8_N0,,,,,
+SRAM_ADDR[10],Unknown,PIN_R11,8,B8_N0,,,,,
+SRAM_ADDR[11],Unknown,PIN_T11,8,B8_N0,,,,,
+SRAM_ADDR[12],Unknown,PIN_Y10,8,B8_N0,,,,,
+SRAM_ADDR[13],Unknown,PIN_U10,8,B8_N0,,,,,
+SRAM_ADDR[14],Unknown,PIN_R10,8,B8_N0,,,,,
+SRAM_ADDR[15],Unknown,PIN_T7,8,B8_N1,,,,,
+SRAM_ADDR[16],Unknown,PIN_Y6,8,B8_N1,,,,,
+SRAM_ADDR[17],Unknown,PIN_Y5,8,B8_N1,,,,,
+SRAM_CE_N,Unknown,PIN_AB5,8,B8_N1,,,,,
+SRAM_DQ[0],Unknown,PIN_AA6,8,B8_N1,,,,,
+SRAM_DQ[1],Unknown,PIN_AB6,8,B8_N1,,,,,
+SRAM_DQ[2],Unknown,PIN_AA7,8,B8_N1,,,,,
+SRAM_DQ[3],Unknown,PIN_AB7,8,B8_N1,,,,,
+SRAM_DQ[4],Unknown,PIN_AA8,8,B8_N0,,,,,
+SRAM_DQ[5],Unknown,PIN_AB8,8,B8_N0,,,,,
+SRAM_DQ[6],Unknown,PIN_AA9,8,B8_N0,,,,,
+SRAM_DQ[7],Unknown,PIN_AB9,8,B8_N0,,,,,
+SRAM_DQ[8],Unknown,PIN_Y9,8,B8_N0,,,,,
+SRAM_DQ[9],Unknown,PIN_W9,8,B8_N0,,,,,
+SRAM_DQ[10],Unknown,PIN_V9,8,B8_N1,,,,,
+SRAM_DQ[11],Unknown,PIN_U9,8,B8_N0,,,,,
+SRAM_DQ[12],Unknown,PIN_R9,8,B8_N0,,,,,
+SRAM_DQ[13],Unknown,PIN_W8,8,B8_N1,,,,,
+SRAM_DQ[14],Unknown,PIN_V8,8,B8_N1,,,,,
+SRAM_DQ[15],Unknown,PIN_U8,8,B8_N1,,,,,
+SRAM_LB_N,Unknown,PIN_Y7,8,B8_N1,,,,,
+SRAM_OE_N,Unknown,PIN_T8,8,B8_N1,,,,,
+SRAM_UB_N,Unknown,PIN_W7,8,B8_N1,,,,,
+SRAM_WE_N,Unknown,PIN_AA10,8,B8_N0,,,,,
+,Unknown,PIN_F5,,,,,,,
+,Unknown,PIN_E5,,,,,,,
+,Unknown,PIN_F6,,,,,,,
+,Unknown,PIN_C4,2,B2_N0,,,,,
+,Unknown,PIN_C3,2,B2_N0,,,,,
+,Unknown,PIN_H3,2,B2_N1,,,,,
+,Unknown,PIN_K5,2,B2_N1,,,,,
+,Unknown,PIN_K2,2,B2_N1,,,,,
+,Unknown,PIN_K6,2,B2_N1,,,,,
+,Unknown,PIN_L5,2,B2_N1,,,,,
+,Unknown,PIN_L6,2,B2_N1,,,,,
+,Unknown,PIN_K4,2,B2_N1,,,,,
+,Unknown,PIN_K1,2,B2_N1,,,,,
+,Unknown,PIN_L4,2,B2_N1,,,,,
+,Unknown,PIN_M6,1,B1_N0,,,,,
+,Unknown,PIN_U5,,,,,,,
+,Unknown,PIN_U6,,,,,,,
+,Unknown,PIN_V5,,,,,,,
+,Unknown,PIN_U7,,,,,,,
+,Unknown,PIN_V7,,,,,,,
+,Unknown,PIN_P9,8,B8_N1,,,,,
+,Unknown,PIN_P8,8,B8_N1,,,,,
+,Unknown,PIN_AB15,7,B7_N1,,,,,
+,Unknown,PIN_R16,7,B7_N0,,,,,
+,Unknown,PIN_T16,7,B7_N0,,,,,
+,Unknown,PIN_Y17,7,B7_N0,,,,,
+,Unknown,PIN_W16,7,B7_N0,,,,,
+,Unknown,PIN_V16,,,,,,,
+,Unknown,PIN_U16,,,,,,,
+,Unknown,PIN_V18,,,,,,,
+,Unknown,PIN_U17,,,,,,,
+,Unknown,PIN_T17,,,,,,,
+,Unknown,PIN_W20,6,B6_N1,,,,,
+,Unknown,PIN_Y20,6,B6_N1,,,,,
+,Unknown,PIN_V20,6,B6_N1,,,,,
+,Unknown,PIN_U20,6,B6_N1,,,,,
+,Unknown,PIN_N20,6,B6_N0,,,,,
+,Unknown,PIN_N18,6,B6_N0,,,,,
+,Unknown,PIN_N17,6,B6_N0,,,,,
+,Unknown,PIN_M17,6,B6_N0,,,,,
+,Unknown,PIN_M19,6,B6_N0,,,,,
+,Unknown,PIN_M18,6,B6_N0,,,,,
+,Unknown,PIN_H19,5,B5_N1,,,,,
+,Unknown,PIN_J17,5,B5_N1,,,,,
+,Unknown,PIN_H16,5,B5_N1,,,,,
+,Unknown,PIN_F18,,,,,,,
+,Unknown,PIN_F17,,,,,,,
+,Unknown,PIN_E17,,,,,,,
+,Unknown,PIN_F16,,,,,,,
+,Unknown,PIN_E16,,,,,,,
+,Unknown,PIN_C16,4,B4_N0,,,,,
+,Unknown,PIN_C13,4,B4_N1,,,,,
+,Unknown,PIN_E11,3,B3_N0,,,,,
+,Unknown,PIN_H11,3,B3_N0,,,,,
+,Unknown,PIN_G11,3,B3_N0,,,,,
+,Unknown,PIN_F11,3,B3_N0,,,,,
+,Unknown,PIN_F10,3,B3_N0,,,,,
+,Unknown,PIN_H10,3,B3_N0,,,,,
+,Unknown,PIN_H9,3,B3_N0,,,,,
+,Unknown,PIN_E9,3,B3_N0,,,,,
+,Unknown,PIN_F9,3,B3_N1,,,,,
+,Unknown,PIN_F8,3,B3_N1,,,,,
+,Unknown,PIN_G8,3,B3_N1,,,,,
+,Unknown,PIN_H8,3,B3_N1,,,,,
+,Unknown,PIN_E7,3,B3_N1,,,,,
+,Unknown,PIN_G7,3,B3_N1,,,,,
+,Unknown,PIN_H7,3,B3_N1,,,,,
+,Unknown,PIN_F7,,,,,,,
+,Unknown,PIN_E6,,,,,,,
+,Unknown,PIN_J10,,,,,,,
+,Unknown,PIN_J11,,,,,,,
+,Unknown,PIN_J12,,,,,,,
+,Unknown,PIN_J13,,,,,,,
+,Unknown,PIN_K9,,,,,,,
+,Unknown,PIN_K14,,,,,,,
+,Unknown,PIN_L9,,,,,,,
+,Unknown,PIN_L14,,,,,,,
+,Unknown,PIN_M9,,,,,,,
+,Unknown,PIN_M14,,,,,,,
+,Unknown,PIN_N9,,,,,,,
+,Unknown,PIN_N14,,,,,,,
+,Unknown,PIN_P10,,,,,,,
+,Unknown,PIN_P11,,,,,,,
+,Unknown,PIN_P12,,,,,,,
+,Unknown,PIN_P13,,,,,,,
+,Unknown,PIN_B1,2,,,,,,
+,Unknown,PIN_J7,2,,,,,,
+,Unknown,PIN_L3,2,,,,,,
+,Unknown,PIN_AA1,1,,,,,,
+,Unknown,PIN_M3,1,,,,,,
+,Unknown,PIN_P7,1,,,,,,
+,Unknown,PIN_T4,1,,,,,,
+,Unknown,PIN_AB2,8,,,,,,
+,Unknown,PIN_T9,8,,,,,,
+,Unknown,PIN_V10,8,,,,,,
+,Unknown,PIN_W6,8,,,,,,
+,Unknown,PIN_Y11,8,,,,,,
+,Unknown,PIN_AB21,7,,,,,,
+,Unknown,PIN_T14,7,,,,,,
+,Unknown,PIN_V13,7,,,,,,
+,Unknown,PIN_W17,7,,,,,,
+,Unknown,PIN_Y12,7,,,,,,
+,Unknown,PIN_AA22,6,,,,,,
+,Unknown,PIN_M20,6,,,,,,
+,Unknown,PIN_P16,6,,,,,,
+,Unknown,PIN_T19,6,,,,,,
+,Unknown,PIN_B22,5,,,,,,
+,Unknown,PIN_G19,5,,,,,,
+,Unknown,PIN_J16,5,,,,,,
+,Unknown,PIN_L20,5,,,,,,
+,Unknown,PIN_A21,4,,,,,,
+,Unknown,PIN_C12,4,,,,,,
+,Unknown,PIN_D17,4,,,,,,
+,Unknown,PIN_E13,4,,,,,,
+,Unknown,PIN_G14,4,,,,,,
+,Unknown,PIN_A2,3,,,,,,
+,Unknown,PIN_C6,3,,,,,,
+,Unknown,PIN_C11,3,,,,,,
+,Unknown,PIN_E10,3,,,,,,
+,Unknown,PIN_G9,3,,,,,,
+,Unknown,PIN_K10,,,,,,,
+,Unknown,PIN_K11,,,,,,,
+,Unknown,PIN_K12,,,,,,,
+,Unknown,PIN_K13,,,,,,,
+,Unknown,PIN_L10,,,,,,,
+,Unknown,PIN_L11,,,,,,,
+,Unknown,PIN_L12,,,,,,,
+,Unknown,PIN_L13,,,,,,,
+,Unknown,PIN_M10,,,,,,,
+,Unknown,PIN_M11,,,,,,,
+,Unknown,PIN_M12,,,,,,,
+,Unknown,PIN_M13,,,,,,,
+,Unknown,PIN_N10,,,,,,,
+,Unknown,PIN_N11,,,,,,,
+,Unknown,PIN_N12,,,,,,,
+,Unknown,PIN_N13,,,,,,,
+,Unknown,PIN_A1,,,,,,,
+,Unknown,PIN_A22,,,,,,,
+,Unknown,PIN_AA2,,,,,,,
+,Unknown,PIN_AA21,,,,,,,
+,Unknown,PIN_AB1,,,,,,,
+,Unknown,PIN_AB22,,,,,,,
+,Unknown,PIN_B2,,,,,,,
+,Unknown,PIN_B21,,,,,,,
+,Unknown,PIN_C5,,,,,,,
+,Unknown,PIN_C8,,,,,,,
+,Unknown,PIN_C15,,,,,,,
+,Unknown,PIN_D10,,,,,,,
+,Unknown,PIN_D13,,,,,,,
+,Unknown,PIN_D18,,,,,,,
+,Unknown,PIN_F19,,,,,,,
+,Unknown,PIN_G4,,,,,,,
+,Unknown,PIN_G10,,,,,,,
+,Unknown,PIN_G13,,,,,,,
+,Unknown,PIN_H20,,,,,,,
+,Unknown,PIN_K3,,,,,,,
+,Unknown,PIN_K7,,,,,,,
+,Unknown,PIN_K16,,,,,,,
+,Unknown,PIN_K19,,,,,,,
+,Unknown,PIN_M4,,,,,,,
+,Unknown,PIN_N7,,,,,,,
+,Unknown,PIN_N16,,,,,,,
+,Unknown,PIN_N19,,,,,,,
+,Unknown,PIN_R3,,,,,,,
+,Unknown,PIN_T10,,,,,,,
+,Unknown,PIN_T13,,,,,,,
+,Unknown,PIN_T20,,,,,,,
+,Unknown,PIN_V3,,,,,,,
+,Unknown,PIN_V6,,,,,,,
+,Unknown,PIN_V17,,,,,,,
+,Unknown,PIN_W10,,,,,,,
+,Unknown,PIN_W13,,,,,,,
+,Unknown,PIN_W19,,,,,,,
+,Unknown,PIN_Y8,,,,,,,
+,Unknown,PIN_Y15,,,,,,,
+,Unknown,PIN_G1,,,,,,,
+,Unknown,PIN_G2,,,,,,,
+,Unknown,PIN_H21,,,,,,,
+,Unknown,PIN_H22,,,,,,,
+,Unknown,PIN_J3,,,,,,,
+,Unknown,PIN_J5,,,,,,,
+,Unknown,PIN_J6,,,,,,,
+,Unknown,PIN_J8,,,,,,,
+,Unknown,PIN_J9,,,,,,,
+,Unknown,PIN_K8,,,,,,,
+,Unknown,PIN_K15,,,,,,,
+,Unknown,PIN_K17,,,,,,,
+,Unknown,PIN_K18,,,,,,,
+,Unknown,PIN_L7,,,,,,,
+,Unknown,PIN_L15,,,,,,,
+,Unknown,PIN_L16,,,,,,,
+,Unknown,PIN_L17,,,,,,,
+,Unknown,PIN_M7,,,,,,,
+,Unknown,PIN_M8,,,,,,,
+,Unknown,PIN_M15,,,,,,,
+,Unknown,PIN_M16,,,,,,,
+,Unknown,PIN_N5,,,,,,,
+,Unknown,PIN_N8,,,,,,,
+,Unknown,PIN_P4,,,,,,,
+,Unknown,PIN_P14,,,,,,,
+,Unknown,PIN_P19,,,,,,,
+,Unknown,PIN_P20,,,,,,,
+,Unknown,PIN_P21,,,,,,,
+,Unknown,PIN_P22,,,,,,,
+,Unknown,PIN_R4,,,,,,,
+,Unknown,PIN_W18,,,,,,,
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.asm.rpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.asm.rpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.asm.rpt (revision 6)
@@ -0,0 +1,129 @@
+Assembler report for uart
+Sat Jan 16 19:26:02 2010
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: C:/altera/cores/vhdl/uart/uart.sof
+ 6. Assembler Device Options: C:/altera/cores/vhdl/uart/uart.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sat Jan 16 19:26:02 2010 ;
+; Revision Name ; uart ;
+; Top-level Entity Name ; TOP_UART ;
+; Family ; Cyclone II ;
+; Device ; EP2C20F484C7 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Generate compressed bitstreams ; On ; On ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++------------------------------------+
+; Assembler Generated Files ;
++------------------------------------+
+; File Name ;
++------------------------------------+
+; C:/altera/cores/vhdl/uart/uart.sof ;
+; C:/altera/cores/vhdl/uart/uart.pof ;
++------------------------------------+
+
+
++--------------------------------------------------------------+
+; Assembler Device Options: C:/altera/cores/vhdl/uart/uart.sof ;
++----------------+---------------------------------------------+
+; Option ; Setting ;
++----------------+---------------------------------------------+
+; Device ; EP2C20F484C7 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x001D0ACF ;
++----------------+---------------------------------------------+
+
+
++--------------------------------------------------------------+
+; Assembler Device Options: C:/altera/cores/vhdl/uart/uart.pof ;
++--------------------+-----------------------------------------+
+; Option ; Setting ;
++--------------------+-----------------------------------------+
+; Device ; EPCS16 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x1DD5F952 ;
+; Compression Ratio ; 3 ;
++--------------------+-----------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Jan 16 19:25:58 2010
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off uart -c uart
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 185 megabytes
+ Info: Processing ended: Sat Jan 16 19:26:02 2010
+ Info: Elapsed time: 00:00:04
+ Info: Total CPU time (on all processors): 00:00:03
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf.bak (revision 6)
@@ -0,0 +1,55 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 23:14:30 September 14, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# uart_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY uart
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:14:30 SEPTEMBER 14, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name VHDL_FILE clkUnit.vhd
+set_global_assignment -name VHDL_FILE miniUART.vhd
+set_global_assignment -name VHDL_FILE RxUnit.vhd
+set_global_assignment -name VHDL_FILE top_uart.vhd
+set_global_assignment -name VHDL_FILE TxUnit.vhd
+set_global_assignment -name VHDL_FILE uart_lib.vhd
+set_global_assignment -name VHDL_FILE UARTtest.vhd
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.done
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.done (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.done (revision 6)
@@ -0,0 +1 @@
+Sat Jan 16 19:26:05 2010
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.rpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.rpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.tan.rpt (revision 6)
@@ -0,0 +1,702 @@
+Classic Timing Analyzer report for uart
+Sat Jan 16 19:26:04 2010
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Clock Setup: 'CLOCK_50'
+ 6. tsu
+ 7. tco
+ 8. th
+ 9. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+---------------------------------------+----------------------------------+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+---------------------------------------+----------------------------------+------------+----------+--------------+
+; Worst-case tsu ; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; -- ; CLOCK_50 ; 0 ;
+; Worst-case tco ; N/A ; None ; 8.405 ns ; miniUART:U1|DataOut[7]$latch ; LEDR[7] ; SW[8] ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; 0.138 ns ; SW[1] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; -- ; CLOCK_50 ; 0 ;
+; Clock Setup: 'CLOCK_50' ; N/A ; None ; 226.81 MHz ( period = 4.409 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+---------------------------------------+----------------------------------+------------+----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2C20F484C7 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; On ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; CLOCK_50 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+; SW[8] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'CLOCK_50' ;
++-----------------------------------------+-----------------------------------------------------+---------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+---------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 226.81 MHz ( period = 4.409 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.166 ns ;
+; N/A ; 226.81 MHz ( period = 4.409 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.166 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.00 MHz ( period = 4.386 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.147 ns ;
+; N/A ; 228.31 MHz ( period = 4.380 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 4.142 ns ;
+; N/A ; 237.98 MHz ( period = 4.202 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.959 ns ;
+; N/A ; 237.98 MHz ( period = 4.202 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.959 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.29 MHz ( period = 4.179 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.940 ns ;
+; N/A ; 239.64 MHz ( period = 4.173 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.935 ns ;
+; N/A ; 243.49 MHz ( period = 4.107 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.858 ns ;
+; N/A ; 243.49 MHz ( period = 4.107 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.858 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 244.86 MHz ( period = 4.084 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.839 ns ;
+; N/A ; 245.22 MHz ( period = 4.078 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.834 ns ;
+; N/A ; 246.31 MHz ( period = 4.060 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.817 ns ;
+; N/A ; 246.31 MHz ( period = 4.060 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.817 ns ;
+; N/A ; 247.65 MHz ( period = 4.038 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.795 ns ;
+; N/A ; 247.65 MHz ( period = 4.038 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.795 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 247.71 MHz ( period = 4.037 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.798 ns ;
+; N/A ; 248.08 MHz ( period = 4.031 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.793 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.07 MHz ( period = 4.015 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.776 ns ;
+; N/A ; 249.44 MHz ( period = 4.009 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.771 ns ;
+; N/A ; 253.68 MHz ( period = 3.942 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.698 ns ;
+; N/A ; 253.68 MHz ( period = 3.942 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.698 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 254.71 MHz ( period = 3.926 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.687 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.17 MHz ( period = 3.919 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.679 ns ;
+; N/A ; 255.56 MHz ( period = 3.913 ns ) ; miniUART:U1|RxUnit:RxDev|Start ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.674 ns ;
+; N/A ; 255.62 MHz ( period = 3.912 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.669 ns ;
+; N/A ; 255.62 MHz ( period = 3.912 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.669 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.14 MHz ( period = 3.889 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.650 ns ;
+; N/A ; 257.40 MHz ( period = 3.885 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.642 ns ;
+; N/A ; 257.40 MHz ( period = 3.885 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.642 ns ;
+; N/A ; 257.53 MHz ( period = 3.883 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.645 ns ;
+; N/A ; 257.60 MHz ( period = 3.882 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.643 ns ;
+; N/A ; 257.60 MHz ( period = 3.882 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.643 ns ;
+; N/A ; 257.60 MHz ( period = 3.882 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.643 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 258.93 MHz ( period = 3.862 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.623 ns ;
+; N/A ; 259.34 MHz ( period = 3.856 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.618 ns ;
+; N/A ; 260.21 MHz ( period = 3.843 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.604 ns ;
+; N/A ; 260.21 MHz ( period = 3.843 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.604 ns ;
+; N/A ; 261.71 MHz ( period = 3.821 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.582 ns ;
+; N/A ; 261.71 MHz ( period = 3.821 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.582 ns ;
+; N/A ; 261.71 MHz ( period = 3.821 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.582 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 265.39 MHz ( period = 3.768 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.529 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 266.24 MHz ( period = 3.756 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.517 ns ;
+; N/A ; 268.24 MHz ( period = 3.728 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.487 ns ;
+; N/A ; 274.42 MHz ( period = 3.644 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.405 ns ;
+; N/A ; 274.42 MHz ( period = 3.644 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.405 ns ;
+; N/A ; 275.03 MHz ( period = 3.636 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.397 ns ;
+; N/A ; 275.03 MHz ( period = 3.636 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.397 ns ;
+; N/A ; 276.70 MHz ( period = 3.614 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.375 ns ;
+; N/A ; 276.70 MHz ( period = 3.614 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.375 ns ;
+; N/A ; 276.70 MHz ( period = 3.614 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.375 ns ;
+; N/A ; 276.85 MHz ( period = 3.612 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.373 ns ;
+; N/A ; 276.85 MHz ( period = 3.612 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.373 ns ;
+; N/A ; 276.85 MHz ( period = 3.612 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.373 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 278.55 MHz ( period = 3.590 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.354 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 281.77 MHz ( period = 3.549 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.310 ns ;
+; N/A ; 282.41 MHz ( period = 3.541 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.296 ns ;
+; N/A ; 282.41 MHz ( period = 3.541 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.296 ns ;
+; N/A ; 284.82 MHz ( period = 3.511 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.270 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 285.47 MHz ( period = 3.503 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.260 ns ;
+; N/A ; 286.20 MHz ( period = 3.494 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.255 ns ;
+; N/A ; 286.20 MHz ( period = 3.494 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.255 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 287.36 MHz ( period = 3.480 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.241 ns ;
+; N/A ; 288.02 MHz ( period = 3.472 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.233 ns ;
+; N/A ; 288.02 MHz ( period = 3.472 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.233 ns ;
+; N/A ; 288.02 MHz ( period = 3.472 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.233 ns ;
+; N/A ; 288.35 MHz ( period = 3.468 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.229 ns ;
+; N/A ; 288.77 MHz ( period = 3.463 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.224 ns ;
+; N/A ; 288.77 MHz ( period = 3.463 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.224 ns ;
+; N/A ; 288.77 MHz ( period = 3.463 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.224 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.44 MHz ( period = 3.455 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.219 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 289.52 MHz ( period = 3.454 ns ) ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.209 ns ;
+; N/A ; 290.36 MHz ( period = 3.444 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.205 ns ;
+; N/A ; 290.36 MHz ( period = 3.444 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.205 ns ;
+; N/A ; 290.36 MHz ( period = 3.444 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.205 ns ;
+; N/A ; 291.38 MHz ( period = 3.432 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.193 ns ;
+; N/A ; 291.38 MHz ( period = 3.432 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.193 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 293.51 MHz ( period = 3.407 ns ) ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.168 ns ;
+; N/A ; 294.46 MHz ( period = 3.396 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.157 ns ;
+; N/A ; 294.64 MHz ( period = 3.394 ns ) ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.155 ns ;
+; N/A ; 294.72 MHz ( period = 3.393 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.158 ns ;
+; N/A ; 294.72 MHz ( period = 3.393 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.158 ns ;
+; N/A ; 294.72 MHz ( period = 3.393 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.158 ns ;
+; N/A ; 294.72 MHz ( period = 3.393 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.158 ns ;
+; N/A ; 294.72 MHz ( period = 3.393 ns ) ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.158 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+---------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+----------+-----------------------------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+----------+-----------------------------------------------+----------+
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; 6.868 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
+; N/A ; None ; 6.307 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[4] ; CLOCK_50 ;
+; N/A ; None ; 6.215 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; CLOCK_50 ;
+; N/A ; None ; 6.133 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ;
+; N/A ; None ; 6.133 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ;
+; N/A ; None ; 6.110 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ;
+; N/A ; None ; 6.104 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ;
+; N/A ; None ; 5.967 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[0] ; CLOCK_50 ;
+; N/A ; None ; 5.945 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; 5.897 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 5.896 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 5.716 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[3] ; CLOCK_50 ;
+; N/A ; None ; 5.714 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[1] ; CLOCK_50 ;
+; N/A ; None ; 5.627 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 5.627 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 5.627 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 5.599 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[5] ; CLOCK_50 ;
+; N/A ; None ; 5.508 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[3] ; CLOCK_50 ;
+; N/A ; None ; 5.473 ns ; KEY[0] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; 5.470 ns ; KEY[0] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; 5.445 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; 5.445 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; 5.445 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; 5.445 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; 5.322 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 5.322 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 5.201 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 5.156 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1] ; CLOCK_50 ;
+; N/A ; None ; 5.141 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 5.134 ns ; KEY[0] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; 5.127 ns ; KEY[0] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; 5.110 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 5.104 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[2] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ;
+; N/A ; None ; 5.055 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ;
+; N/A ; None ; 5.029 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; 4.990 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; CLOCK_50 ;
+; N/A ; None ; 4.977 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 4.811 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|tmpRxD ; CLOCK_50 ;
+; N/A ; None ; 4.758 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 4.640 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|ClkDiv26 ; CLOCK_50 ;
+; N/A ; None ; 4.621 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|tmpRxD ; CLOCK_50 ;
+; N/A ; None ; 4.615 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 4.590 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|Start ; CLOCK_50 ;
+; N/A ; None ; 4.548 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 4.349 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; 4.349 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; 4.291 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[0] ; CLOCK_50 ;
+; N/A ; None ; 4.288 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[2] ; CLOCK_50 ;
+; N/A ; None ; 4.287 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[4] ; CLOCK_50 ;
+; N/A ; None ; 4.272 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 4.270 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[0] ; CLOCK_50 ;
+; N/A ; None ; 4.268 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[3] ; CLOCK_50 ;
+; N/A ; None ; 4.268 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[1] ; CLOCK_50 ;
+; N/A ; None ; 4.267 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[2] ; CLOCK_50 ;
+; N/A ; None ; 4.229 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|Start ; CLOCK_50 ;
+; N/A ; None ; 4.212 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 4.212 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; 2.487 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
+; N/A ; None ; 2.427 ns ; SW[7] ; miniUART:U1|DataOut[5]$latch ; SW[8] ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; 2.320 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
+; N/A ; None ; 2.270 ns ; SW[7] ; miniUART:U1|DataOut[3]$latch ; SW[8] ;
+; N/A ; None ; 2.254 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; 2.245 ns ; SW[7] ; miniUART:U1|DataOut[2]$latch ; SW[8] ;
+; N/A ; None ; 2.216 ns ; SW[7] ; miniUART:U1|DataOut[1]$latch ; SW[8] ;
+; N/A ; None ; 2.069 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; 1.983 ns ; SW[7] ; miniUART:U1|DataOut[0]$latch ; SW[8] ;
+; N/A ; None ; 1.954 ns ; SW[7] ; miniUART:U1|DataOut[4]$latch ; SW[8] ;
+; N/A ; None ; 1.954 ns ; SW[7] ; miniUART:U1|DataOut[7]$latch ; SW[8] ;
+; N/A ; None ; 1.908 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; 1.888 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 1.877 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 1.778 ns ; SW[7] ; miniUART:U1|DataOut[6]$latch ; SW[8] ;
+; N/A ; None ; 1.723 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; 1.703 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; 1.692 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; 1.578 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 1.570 ns ; SW[0] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; 1.566 ns ; SW[0] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; 1.564 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; 1.397 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; 1.393 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; 1.214 ns ; SW[1] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; 1.210 ns ; SW[1] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; 1.070 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; 1.070 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; 1.070 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; 1.070 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; 0.900 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; 0.900 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; 0.900 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; 0.900 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; 0.866 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 0.753 ns ; SW[2] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; 0.746 ns ; SW[2] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; 0.681 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; 0.612 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; 0.586 ns ; SW[0] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; 0.579 ns ; SW[0] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; 0.490 ns ; SW[0] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
+; N/A ; None ; 0.347 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; 0.110 ns ; SW[1] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
++-------+--------------+------------+----------+-----------------------------------------------+----------+
+
+
++------------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+------------------------------+----------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+------------------------------+----------+------------+
+; N/A ; None ; 8.405 ns ; miniUART:U1|DataOut[7]$latch ; LEDR[7] ; SW[8] ;
+; N/A ; None ; 8.343 ns ; miniUART:U1|DataOut[4]$latch ; LEDR[4] ; SW[8] ;
+; N/A ; None ; 8.236 ns ; miniUART:U1|DataOut[6]$latch ; LEDR[6] ; SW[8] ;
+; N/A ; None ; 8.133 ns ; miniUART:U1|DataOut[3]$latch ; LEDR[3] ; SW[8] ;
+; N/A ; None ; 8.115 ns ; miniUART:U1|DataOut[5]$latch ; LEDR[5] ; SW[8] ;
+; N/A ; None ; 8.097 ns ; miniUART:U1|DataOut[2]$latch ; LEDR[2] ; SW[8] ;
+; N/A ; None ; 8.059 ns ; miniUART:U1|IntRx_N ; LEDG[0] ; CLOCK_50 ;
+; N/A ; None ; 7.761 ns ; miniUART:U1|IntTx_N ; LEDG[1] ; CLOCK_50 ;
+; N/A ; None ; 7.747 ns ; miniUART:U1|TxUnit:TxDev|TxD ; UART_TXD ; CLOCK_50 ;
+; N/A ; None ; 7.729 ns ; miniUART:U1|DataOut[1]$latch ; LEDR[1] ; SW[8] ;
+; N/A ; None ; 7.395 ns ; miniUART:U1|DataOut[0]$latch ; LEDR[0] ; SW[8] ;
++-------+--------------+------------+------------------------------+----------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+----------+-----------------------------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+----------+-----------------------------------------------+----------+
+; N/A ; None ; 0.138 ns ; SW[1] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
+; N/A ; None ; -0.099 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; -0.242 ns ; SW[0] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
+; N/A ; None ; -0.331 ns ; SW[0] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; -0.336 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; -0.338 ns ; SW[0] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; -0.364 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; -0.433 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -0.498 ns ; SW[2] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; -0.505 ns ; SW[2] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; -0.507 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; -0.618 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -0.652 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; -0.652 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; -0.652 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; -0.652 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; -0.822 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; -0.822 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; -0.822 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; -0.822 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; -0.856 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; -0.962 ns ; SW[1] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; -0.965 ns ; SW[7] ; miniUART:U1|DataOut[6]$latch ; SW[8] ;
+; N/A ; None ; -0.966 ns ; SW[1] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; -1.023 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; -1.131 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; -1.145 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -1.157 ns ; SW[7] ; miniUART:U1|DataOut[4]$latch ; SW[8] ;
+; N/A ; None ; -1.158 ns ; SW[7] ; miniUART:U1|DataOut[7]$latch ; SW[8] ;
+; N/A ; None ; -1.175 ns ; SW[7] ; miniUART:U1|DataOut[0]$latch ; SW[8] ;
+; N/A ; None ; -1.316 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; -1.318 ns ; SW[0] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; -1.322 ns ; SW[0] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; -1.330 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -1.401 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -1.412 ns ; SW[7] ; miniUART:U1|DataOut[1]$latch ; SW[8] ;
+; N/A ; None ; -1.437 ns ; SW[7] ; miniUART:U1|DataOut[2]$latch ; SW[8] ;
+; N/A ; None ; -1.455 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -1.466 ns ; SW[7] ; miniUART:U1|DataOut[3]$latch ; SW[8] ;
+; N/A ; None ; -1.586 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -1.619 ns ; SW[7] ; miniUART:U1|DataOut[5]$latch ; SW[8] ;
+; N/A ; None ; -1.640 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; -1.919 ns ; SW[0] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; -2.086 ns ; SW[2] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
+; N/A ; None ; -3.661 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|outErr ; CLOCK_50 ;
+; N/A ; None ; -3.665 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|frameErr ; CLOCK_50 ;
+; N/A ; None ; -3.681 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[7] ; CLOCK_50 ;
+; N/A ; None ; -3.876 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[7] ; CLOCK_50 ;
+; N/A ; None ; -3.877 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[1] ; CLOCK_50 ;
+; N/A ; None ; -3.878 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[4] ; CLOCK_50 ;
+; N/A ; None ; -3.880 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[6] ; CLOCK_50 ;
+; N/A ; None ; -3.882 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[1] ; CLOCK_50 ;
+; N/A ; None ; -3.883 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[0] ; CLOCK_50 ;
+; N/A ; None ; -3.964 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -3.964 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|tmpDRdy ; CLOCK_50 ;
+; N/A ; None ; -3.981 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|Start ; CLOCK_50 ;
+; N/A ; None ; -4.019 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[2] ; CLOCK_50 ;
+; N/A ; None ; -4.020 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[3] ; CLOCK_50 ;
+; N/A ; None ; -4.020 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[1] ; CLOCK_50 ;
+; N/A ; None ; -4.022 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[0] ; CLOCK_50 ;
+; N/A ; None ; -4.024 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -4.039 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[1] ; CLOCK_50 ;
+; N/A ; None ; -4.039 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[4] ; CLOCK_50 ;
+; N/A ; None ; -4.040 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[2] ; CLOCK_50 ;
+; N/A ; None ; -4.043 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[3] ; CLOCK_50 ;
+; N/A ; None ; -4.043 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[0] ; CLOCK_50 ;
+; N/A ; None ; -4.073 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[2] ; CLOCK_50 ;
+; N/A ; None ; -4.079 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[5] ; CLOCK_50 ;
+; N/A ; None ; -4.101 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|tmpTRegE ; CLOCK_50 ;
+; N/A ; None ; -4.101 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|tmpTBufE ; CLOCK_50 ;
+; N/A ; None ; -4.146 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[0] ; CLOCK_50 ;
+; N/A ; None ; -4.300 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -4.342 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|Start ; CLOCK_50 ;
+; N/A ; None ; -4.349 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[0] ; CLOCK_50 ;
+; N/A ; None ; -4.353 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[5] ; CLOCK_50 ;
+; N/A ; None ; -4.366 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -4.367 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -4.373 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|tmpRxD ; CLOCK_50 ;
+; N/A ; None ; -4.383 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[6] ; CLOCK_50 ;
+; N/A ; None ; -4.392 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|ClkDiv26 ; CLOCK_50 ;
+; N/A ; None ; -4.494 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[3] ; CLOCK_50 ;
+; N/A ; None ; -4.510 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -4.510 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -4.548 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|ShtReg[4] ; CLOCK_50 ;
+; N/A ; None ; -4.552 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -4.562 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -4.563 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|tmpRxD ; CLOCK_50 ;
+; N/A ; None ; -4.724 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[2] ; CLOCK_50 ;
+; N/A ; None ; -4.729 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -4.742 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; CLOCK_50 ;
+; N/A ; None ; -4.768 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -4.771 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -4.781 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TxD ; CLOCK_50 ;
+; N/A ; None ; -4.856 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[2] ; CLOCK_50 ;
+; N/A ; None ; -4.879 ns ; KEY[0] ; miniUART:U1|IntTx_N ; CLOCK_50 ;
+; N/A ; None ; -4.886 ns ; KEY[0] ; miniUART:U1|CSReg[3] ; CLOCK_50 ;
+; N/A ; None ; -4.893 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; CLOCK_50 ;
+; N/A ; None ; -4.908 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1] ; CLOCK_50 ;
+; N/A ; None ; -4.922 ns ; KEY[0] ; miniUART:U1|RxUnit:RxDev|DOut[3] ; CLOCK_50 ;
+; N/A ; None ; -4.996 ns ; KEY[0] ; miniUART:U1|CSReg[2] ; CLOCK_50 ;
+; N/A ; None ; -4.997 ns ; KEY[0] ; miniUART:U1|IntRx_N ; CLOCK_50 ;
+; N/A ; None ; -5.197 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[0] ; CLOCK_50 ;
+; N/A ; None ; -5.197 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[3] ; CLOCK_50 ;
+; N/A ; None ; -5.197 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[5] ; CLOCK_50 ;
+; N/A ; None ; -5.197 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TBuff[6] ; CLOCK_50 ;
+; N/A ; None ; -5.260 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[3] ; CLOCK_50 ;
+; N/A ; None ; -5.351 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[5] ; CLOCK_50 ;
+; N/A ; None ; -5.354 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[4] ; CLOCK_50 ;
+; N/A ; None ; -5.379 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; CLOCK_50 ;
+; N/A ; None ; -5.379 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; CLOCK_50 ;
+; N/A ; None ; -5.379 ns ; UART_RXD ; miniUART:U1|RxUnit:RxDev|SampleCnt[2] ; CLOCK_50 ;
+; N/A ; None ; -5.404 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[7] ; CLOCK_50 ;
+; N/A ; None ; -5.759 ns ; KEY[0] ; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[0] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[1] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[2] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[3] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[4] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[5] ; CLOCK_50 ;
+; N/A ; None ; -6.467 ns ; KEY[0] ; miniUART:U1|TxUnit:TxDev|TReg[6] ; CLOCK_50 ;
++---------------+-------------+-----------+----------+-----------------------------------------------+----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Jan 16 19:26:03 2010
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart -c uart --timing_analysis_only
+Warning: Timing Analysis is analyzing one or more combinational loops as latches
+ Warning: Node "miniUART:U1|TxData[0]" is a latch
+ Warning: Node "miniUART:U1|TxData[3]" is a latch
+ Warning: Node "miniUART:U1|TxData[5]" is a latch
+ Warning: Node "miniUART:U1|TxData[6]" is a latch
+ Warning: Node "miniUART:U1|DataOut[0]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[0]_240" is a latch
+ Warning: Node "miniUART:U1|DataOut[1]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[2]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[3]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[4]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[5]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[6]$latch" is a latch
+ Warning: Node "miniUART:U1|DataOut[7]$latch" is a latch
+Warning: Found pins functioning as undefined clocks and/or memory enables
+ Info: Assuming node "CLOCK_50" is an undefined clock
+ Info: Assuming node "SW[8]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
+Info: Clock "CLOCK_50" has Internal fmax of 226.81 MHz between source register "miniUART:U1|RxUnit:RxDev|SampleCnt[1]" and destination register "miniUART:U1|RxUnit:RxDev|frameErr" (period= 4.409 ns)
+ Info: + Longest register to register delay is 4.166 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1|RxUnit:RxDev|SampleCnt[1]'
+ Info: 2: + IC(0.395 ns) + CELL(0.513 ns) = 0.908 ns; Loc. = LCCOMB_X39_Y14_N18; Fanout = 4; COMB Node = 'miniUART:U1|RxUnit:RxDev|Equal1~0'
+ Info: 3: + IC(0.318 ns) + CELL(0.178 ns) = 1.404 ns; Loc. = LCCOMB_X39_Y14_N4; Fanout = 6; COMB Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy~8'
+ Info: 4: + IC(0.314 ns) + CELL(0.322 ns) = 2.040 ns; Loc. = LCCOMB_X39_Y14_N12; Fanout = 2; COMB Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy~10'
+ Info: 5: + IC(0.307 ns) + CELL(0.178 ns) = 2.525 ns; Loc. = LCCOMB_X39_Y14_N22; Fanout = 10; COMB Node = 'miniUART:U1|RxUnit:RxDev|outErr~5'
+ Info: 6: + IC(0.883 ns) + CELL(0.758 ns) = 4.166 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1|RxUnit:RxDev|frameErr'
+ Info: Total cell delay = 1.949 ns ( 46.78 % )
+ Info: Total interconnect delay = 2.217 ns ( 53.22 % )
+ Info: - Smallest clock skew is -0.004 ns
+ Info: + Shortest clock path from clock "CLOCK_50" to destination register is 2.856 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'
+ Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'
+ Info: 3: + IC(0.990 ns) + CELL(0.602 ns) = 2.856 ns; Loc. = LCFF_X39_Y11_N25; Fanout = 2; REG Node = 'miniUART:U1|RxUnit:RxDev|frameErr'
+ Info: Total cell delay = 1.628 ns ( 57.00 % )
+ Info: Total interconnect delay = 1.228 ns ( 43.00 % )
+ Info: - Longest clock path from clock "CLOCK_50" to source register is 2.860 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'
+ Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'
+ Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X39_Y14_N25; Fanout = 4; REG Node = 'miniUART:U1|RxUnit:RxDev|SampleCnt[1]'
+ Info: Total cell delay = 1.628 ns ( 56.92 % )
+ Info: Total interconnect delay = 1.232 ns ( 43.08 % )
+ Info: + Micro clock to output delay of source is 0.277 ns
+ Info: + Micro setup delay of destination is -0.038 ns
+Info: tsu for register "miniUART:U1|TxUnit:TxDev|TReg[0]" (data pin = "KEY[0]", clock pin = "CLOCK_50") is 6.868 ns
+ Info: + Longest pin to register delay is 9.768 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_R22; Fanout = 54; PIN Node = 'KEY[0]'
+ Info: 2: + IC(5.688 ns) + CELL(0.545 ns) = 7.097 ns; Loc. = LCCOMB_X39_Y11_N14; Fanout = 4; COMB Node = 'miniUART:U1|TxUnit:TxDev|TReg[0]~32'
+ Info: 3: + IC(0.316 ns) + CELL(0.322 ns) = 7.735 ns; Loc. = LCCOMB_X39_Y11_N30; Fanout = 2; COMB Node = 'miniUART:U1|TxUnit:TxDev|TReg[0]~35'
+ Info: 4: + IC(0.490 ns) + CELL(0.521 ns) = 8.746 ns; Loc. = LCCOMB_X38_Y11_N30; Fanout = 7; COMB Node = 'miniUART:U1|TxUnit:TxDev|TReg[0]~37'
+ Info: 5: + IC(0.264 ns) + CELL(0.758 ns) = 9.768 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1|TxUnit:TxDev|TReg[0]'
+ Info: Total cell delay = 3.010 ns ( 30.81 % )
+ Info: Total interconnect delay = 6.758 ns ( 69.19 % )
+ Info: + Micro setup delay of destination is -0.038 ns
+ Info: - Shortest clock path from clock "CLOCK_50" to destination register is 2.862 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'
+ Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'
+ Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X38_Y11_N9; Fanout = 1; REG Node = 'miniUART:U1|TxUnit:TxDev|TReg[0]'
+ Info: Total cell delay = 1.628 ns ( 56.88 % )
+ Info: Total interconnect delay = 1.234 ns ( 43.12 % )
+Info: tco from clock "SW[8]" to destination pin "LEDR[7]" through register "miniUART:U1|DataOut[7]$latch" is 8.405 ns
+ Info: + Longest clock path from clock "SW[8]" to source register is 2.999 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 3; CLK Node = 'SW[8]'
+ Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'SW[8]~clkctrl'
+ Info: 3: + IC(1.413 ns) + CELL(0.322 ns) = 2.999 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1|DataOut[7]$latch'
+ Info: Total cell delay = 1.348 ns ( 44.95 % )
+ Info: Total interconnect delay = 1.651 ns ( 55.05 % )
+ Info: + Micro clock to output delay of source is 0.000 ns
+ Info: + Longest register to pin delay is 5.406 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X40_Y13_N6; Fanout = 1; REG Node = 'miniUART:U1|DataOut[7]$latch'
+ Info: 2: + IC(2.411 ns) + CELL(2.995 ns) = 5.406 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'LEDR[7]'
+ Info: Total cell delay = 2.995 ns ( 55.40 % )
+ Info: Total interconnect delay = 2.411 ns ( 44.60 % )
+Info: th for register "miniUART:U1|RxUnit:RxDev|tmpDRdy" (data pin = "SW[1]", clock pin = "CLOCK_50") is 0.138 ns
+ Info: + Longest clock path from clock "CLOCK_50" to destination register is 2.858 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'CLOCK_50'
+ Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 70; COMB Node = 'CLOCK_50~clkctrl'
+ Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy'
+ Info: Total cell delay = 1.628 ns ( 56.96 % )
+ Info: Total interconnect delay = 1.230 ns ( 43.04 % )
+ Info: + Micro hold delay of destination is 0.286 ns
+ Info: - Shortest pin to register delay is 3.006 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L21; Fanout = 2; PIN Node = 'SW[1]'
+ Info: 2: + IC(1.339 ns) + CELL(0.545 ns) = 2.910 ns; Loc. = LCCOMB_X39_Y12_N16; Fanout = 1; COMB Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy~11'
+ Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 3.006 ns; Loc. = LCFF_X39_Y12_N17; Fanout = 3; REG Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy'
+ Info: Total cell delay = 1.667 ns ( 55.46 % )
+ Info: Total interconnect delay = 1.339 ns ( 44.54 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings
+ Info: Peak virtual memory: 136 megabytes
+ Info: Processing ended: Sat Jan 16 19:26:04 2010
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.pin
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.pin (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.pin (revision 6)
@@ -0,0 +1,558 @@
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+CHIP "uart" ASSIGNED TO AN: EP2C20F484C7
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A1 : gnd : : : :
+VCCIO3 : A2 : power : : 3.3V : 3 :
+I2C_SCLK : A3 : output : 3.3-V LVTTL : : 3 : Y
+AUD_BCLK : A4 : bidir : 3.3-V LVTTL : : 3 : Y
+AUD_DACLRCK : A5 : bidir : 3.3-V LVTTL : : 3 : Y
+AUD_ADCLRCK : A6 : bidir : 3.3-V LVTTL : : 3 : Y
+VGA_R[2] : A7 : output : 3.3-V LVTTL : : 3 : Y
+VGA_G[3] : A8 : output : 3.3-V LVTTL : : 3 : Y
+VGA_B[0] : A9 : output : 3.3-V LVTTL : : 3 : Y
+VGA_B[2] : A10 : output : 3.3-V LVTTL : : 3 : Y
+VGA_HS : A11 : output : 3.3-V LVTTL : : 3 : Y
+GND+ : A12 : : : : 4 :
+GPIO_0[0] : A13 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[2] : A14 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[4] : A15 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[6] : A16 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[8] : A17 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[10] : A18 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[12] : A19 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[14] : A20 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : A21 : power : : 3.3V : 4 :
+GND : A22 : gnd : : : :
+VCCIO1 : AA1 : power : : 3.3V : 1 :
+GND : AA2 : gnd : : : :
+SRAM_ADDR[0] : AA3 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[2] : AA4 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[4] : AA5 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[0] : AA6 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[2] : AA7 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[4] : AA8 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[6] : AA9 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_WE_N : AA10 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[6] : AA11 : output : 3.3-V LVTTL : : 8 : Y
+FL_ADDR[15] : AA12 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[13] : AA13 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[1] : AA14 : output : 3.3-V LVTTL : : 7 : Y
+FL_OE_N : AA15 : output : 3.3-V LVTTL : : 7 : Y
+FL_DQ[1] : AA16 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[3] : AA17 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[5] : AA18 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[7] : AA19 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[17] : AA20 : output : 3.3-V LVTTL : : 7 : Y
+GND : AA21 : gnd : : : :
+VCCIO6 : AA22 : power : : 3.3V : 6 :
+GND : AB1 : gnd : : : :
+VCCIO8 : AB2 : power : : 3.3V : 8 :
+SRAM_ADDR[1] : AB3 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[3] : AB4 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_CE_N : AB5 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[1] : AB6 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[3] : AB7 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[5] : AB8 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[7] : AB9 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[5] : AB10 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[7] : AB11 : output : 3.3-V LVTTL : : 8 : Y
+FL_ADDR[16] : AB12 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[14] : AB13 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[12] : AB14 : output : 3.3-V LVTTL : : 7 : Y
+IRDA_RXD : AB15 : input : 3.3-V LVTTL : : 7 : N
+FL_DQ[0] : AB16 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[2] : AB17 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[4] : AB18 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_DQ[6] : AB19 : bidir : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[0] : AB20 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : AB21 : power : : 3.3V : 7 :
+GND : AB22 : gnd : : : :
+VCCIO2 : B1 : power : : 3.3V : 2 :
+GND : B2 : gnd : : : :
+I2C_SDAT : B3 : bidir : 3.3-V LVTTL : : 3 : Y
+AUD_XCK : B4 : output : 3.3-V LVTTL : : 3 : Y
+AUD_DACDAT : B5 : output : 3.3-V LVTTL : : 3 : Y
+AUD_ADCDAT : B6 : input : 3.3-V LVTTL : : 3 : Y
+VGA_R[3] : B7 : output : 3.3-V LVTTL : : 3 : Y
+VGA_G[0] : B8 : output : 3.3-V LVTTL : : 3 : Y
+VGA_G[2] : B9 : output : 3.3-V LVTTL : : 3 : Y
+VGA_B[3] : B10 : output : 3.3-V LVTTL : : 3 : Y
+VGA_VS : B11 : output : 3.3-V LVTTL : : 3 : Y
+GND+ : B12 : : : : 4 :
+GPIO_0[1] : B13 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[3] : B14 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[5] : B15 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[7] : B16 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[9] : B17 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[11] : B18 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[13] : B19 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_0[15] : B20 : bidir : 3.3-V LVTTL : : 4 : Y
+GND : B21 : gnd : : : :
+VCCIO5 : B22 : power : : 3.3V : 5 :
+HEX2[3] : C1 : output : 3.3-V LVTTL : : 2 : Y
+HEX2[2] : C2 : output : 3.3-V LVTTL : : 2 : Y
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N
+GND : C5 : gnd : : : :
+VCCIO3 : C6 : power : : 3.3V : 3 :
+TCK : C7 : input : 3.3-V LVTTL : : 3 : Y
+GND : C8 : gnd : : : :
+VGA_R[1] : C9 : output : 3.3-V LVTTL : : 3 : Y
+VGA_G[1] : C10 : output : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : C11 : power : : 3.3V : 3 :
+VCCIO4 : C12 : power : : 3.3V : 4 :
+GND* : C13 : : : : 4 :
+GPIO_1[10] : C14 : bidir : 3.3-V LVTTL : : 4 : Y
+GND : C15 : gnd : : : :
+GND* : C16 : : : : 4 :
+GPIO_1[14] : C17 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[15] : C18 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[16] : C19 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[17] : C20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[16] : C21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[17] : C22 : bidir : 3.3-V LVTTL : : 5 : Y
+HEX1[6] : D1 : output : 3.3-V LVTTL : : 2 : Y
+HEX1[5] : D2 : output : 3.3-V LVTTL : : 2 : Y
+HEX2[6] : D3 : output : 3.3-V LVTTL : : 2 : Y
+HEX3[6] : D4 : output : 3.3-V LVTTL : : 2 : Y
+HEX3[1] : D5 : output : 3.3-V LVTTL : : 2 : Y
+HEX3[2] : D6 : output : 3.3-V LVTTL : : 2 : Y
+TDO : D7 : output : 3.3-V LVTTL : : 3 : Y
+TCS : D8 : input : 3.3-V LVTTL : : 3 : Y
+VGA_R[0] : D9 : output : 3.3-V LVTTL : : 3 : Y
+GND : D10 : gnd : : : :
+VGA_B[1] : D11 : output : 3.3-V LVTTL : : 3 : Y
+GND+ : D12 : : : : 3 :
+GND : D13 : gnd : : : :
+GPIO_1[11] : D14 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[12] : D15 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[13] : D16 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : D17 : power : : 3.3V : 4 :
+GND : D18 : gnd : : : :
+GPIO_1[18] : D19 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[19] : D20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[18] : D21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[19] : D22 : bidir : 3.3-V LVTTL : : 5 : Y
+HEX1[0] : E1 : output : 3.3-V LVTTL : : 2 : Y
+HEX0[6] : E2 : output : 3.3-V LVTTL : : 2 : Y
+HEX2[4] : E3 : output : 3.3-V LVTTL : : 2 : Y
+HEX2[5] : E4 : output : 3.3-V LVTTL : : 2 : Y
+VCCD_PLL3 : E5 : power : : 1.2V : :
+VCCA_PLL3 : E6 : power : : 1.2V : :
+GND* : E7 : : : : 3 :
+TDI : E8 : input : 3.3-V LVTTL : : 3 : Y
+GND* : E9 : : : : 3 :
+VCCIO3 : E10 : power : : 3.3V : 3 :
+SD_CLK : E11 : output : 3.3-V LVTTL : : 3 : N
+GND+ : E12 : : : : 3 :
+VCCIO4 : E13 : power : : 3.3V : 4 :
+GPIO_1[4] : E14 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[5] : E15 : bidir : 3.3-V LVTTL : : 4 : Y
+GNDA_PLL2 : E16 : gnd : : : :
+GND_PLL2 : E17 : gnd : : : :
+GPIO_1[23] : E18 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[22] : E19 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[20] : E20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[20] : E21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[21] : E22 : bidir : 3.3-V LVTTL : : 5 : Y
+HEX0[5] : F1 : output : 3.3-V LVTTL : : 2 : Y
+HEX0[4] : F2 : output : 3.3-V LVTTL : : 2 : Y
+HEX3[5] : F3 : output : 3.3-V LVTTL : : 2 : Y
+HEX3[0] : F4 : output : 3.3-V LVTTL : : 2 : Y
+GND_PLL3 : F5 : gnd : : : :
+GND_PLL3 : F6 : gnd : : : :
+GNDA_PLL3 : F7 : gnd : : : :
+GND* : F8 : : : : 3 :
+SD_DAT3 : F9 : output : 3.3-V LVTTL : : 3 : N
+CLOCK_27 : F10 : input : 3.3-V LVTTL : : 3 : N
+GND* : F11 : : : : 3 :
+GPIO_1[8] : F12 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[9] : F13 : bidir : 3.3-V LVTTL : : 4 : Y
+UART_RXD : F14 : input : 3.3-V LVTTL : : 4 : Y
+GPIO_1[6] : F15 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCA_PLL2 : F16 : power : : 1.2V : :
+VCCD_PLL2 : F17 : power : : 1.2V : :
+GND_PLL2 : F18 : gnd : : : :
+GND : F19 : gnd : : : :
+GPIO_1[21] : F20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[22] : F21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[23] : F22 : bidir : 3.3-V LVTTL : : 5 : Y
+NC : G1 : : : : :
+NC : G2 : : : : :
+HEX1[4] : G3 : output : 3.3-V LVTTL : : 2 : Y
+GND : G4 : gnd : : : :
+HEX2[0] : G5 : output : 3.3-V LVTTL : : 2 : Y
+HEX2[1] : G6 : output : 3.3-V LVTTL : : 2 : Y
+GND* : G7 : : : : 3 :
+SD_DAT : G8 : input : 3.3-V LVTTL : : 3 : N
+VCCIO3 : G9 : power : : 3.3V : 3 :
+GND : G10 : gnd : : : :
+FL_CE_N : G11 : output : 3.3-V LVTTL : : 3 : N
+UART_TXD : G12 : output : 3.3-V LVTTL : : 4 : Y
+GND : G13 : gnd : : : :
+VCCIO4 : G14 : power : : 3.3V : 4 :
+GPIO_1[3] : G15 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[7] : G16 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[26] : G17 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[25] : G18 : bidir : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : G19 : power : : 3.3V : 5 :
+GPIO_1[24] : G20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[24] : G21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[25] : G22 : bidir : 3.3-V LVTTL : : 5 : Y
+HEX0[3] : H1 : output : 3.3-V LVTTL : : 2 : Y
+HEX0[2] : H2 : output : 3.3-V LVTTL : : 2 : Y
+SD_CMD : H3 : output : 3.3-V LVTTL : : 2 : N
+HEX1[3] : H4 : output : 3.3-V LVTTL : : 2 : Y
+HEX1[2] : H5 : output : 3.3-V LVTTL : : 2 : Y
+HEX1[1] : H6 : output : 3.3-V LVTTL : : 2 : Y
+GND* : H7 : : : : 3 :
+GND* : H8 : : : : 3 :
+GND* : H9 : : : : 3 :
+GND* : H10 : : : : 3 :
+GND* : H11 : : : : 3 :
+GPIO_1[0] : H12 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[1] : H13 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[2] : H14 : bidir : 3.3-V LVTTL : : 4 : Y
+PS2_CLK : H15 : bidir : 3.3-V LVTTL : : 4 : Y
+GND* : H16 : : : : 5 :
+GPIO_1[27] : H17 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_1[29] : H18 : bidir : 3.3-V LVTTL : : 5 : Y
+GND* : H19 : : : : 5 :
+GND : H20 : gnd : : : :
+NC : H21 : : : : :
+NC : H22 : : : : :
+HEX0[1] : J1 : output : 3.3-V LVTTL : : 2 : Y
+HEX0[0] : J2 : output : 3.3-V LVTTL : : 2 : Y
+NC : J3 : : : : :
+HEX3[3] : J4 : output : 3.3-V LVTTL : : 2 : Y
+NC : J5 : : : : :
+NC : J6 : : : : :
+VCCIO2 : J7 : power : : 3.3V : 2 :
+NC : J8 : : : : :
+NC : J9 : : : : :
+VCCINT : J10 : power : : 1.2V : :
+VCCINT : J11 : power : : 1.2V : :
+VCCINT : J12 : power : : 1.2V : :
+VCCINT : J13 : power : : 1.2V : :
+PS2_DAT : J14 : bidir : 3.3-V LVTTL : : 4 : Y
+GPIO_1[28] : J15 : bidir : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : J16 : power : : 3.3V : 5 :
+GND* : J17 : : : : 5 :
+GPIO_0[32] : J18 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[30] : J19 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[31] : J20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[26] : J21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[27] : J22 : bidir : 3.3-V LVTTL : : 5 : Y
+nCE : K1 : : : : 2 :
+TCK : K2 : input : : : 2 :
+GND : K3 : gnd : : : :
+DATA0 : K4 : input : : : 2 :
+TDI : K5 : input : : : 2 :
+TMS : K6 : input : : : 2 :
+GND : K7 : gnd : : : :
+NC : K8 : : : : :
+VCCINT : K9 : power : : 1.2V : :
+GND : K10 : gnd : : : :
+GND : K11 : gnd : : : :
+GND : K12 : gnd : : : :
+GND : K13 : gnd : : : :
+VCCINT : K14 : power : : 1.2V : :
+NC : K15 : : : : :
+GND : K16 : gnd : : : :
+NC : K17 : : : : :
+NC : K18 : : : : :
+GND : K19 : gnd : : : :
+GPIO_0[33] : K20 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[28] : K21 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[29] : K22 : bidir : 3.3-V LVTTL : : 5 : Y
+CLOCK_50 : L1 : input : 3.3-V LVTTL : : 2 : Y
+SW[9] : L2 : input : 3.3-V LVTTL : : 2 : Y
+VCCIO2 : L3 : power : : 3.3V : 2 :
+nCONFIG : L4 : : : : 2 :
+TDO : L5 : output : : : 2 :
+DCLK : L6 : : : : 2 :
+NC : L7 : : : : :
+HEX3[4] : L8 : output : 3.3-V LVTTL : : 2 : Y
+VCCINT : L9 : power : : 1.2V : :
+GND : L10 : gnd : : : :
+GND : L11 : gnd : : : :
+GND : L12 : gnd : : : :
+GND : L13 : gnd : : : :
+VCCINT : L14 : power : : 1.2V : :
+NC : L15 : : : : :
+NC : L16 : : : : :
+NC : L17 : : : : :
+GPIO_0[35] : L18 : bidir : 3.3-V LVTTL : : 5 : Y
+GPIO_0[34] : L19 : bidir : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : L20 : power : : 3.3V : 5 :
+SW[1] : L21 : input : 3.3-V LVTTL : : 5 : Y
+SW[0] : L22 : input : 3.3-V LVTTL : : 5 : Y
+SW[8] : M1 : input : 3.3-V LVTTL : : 1 : Y
+SW[7] : M2 : input : 3.3-V LVTTL : : 1 : Y
+VCCIO1 : M3 : power : : 3.3V : 1 :
+GND : M4 : gnd : : : :
+DRAM_UDQM : M5 : output : 3.3-V LVTTL : : 1 : Y
+GND* : M6 : : : : 1 :
+NC : M7 : : : : :
+NC : M8 : : : : :
+VCCINT : M9 : power : : 1.2V : :
+GND : M10 : gnd : : : :
+GND : M11 : gnd : : : :
+GND : M12 : gnd : : : :
+GND : M13 : gnd : : : :
+VCCINT : M14 : power : : 1.2V : :
+NC : M15 : : : : :
+NC : M16 : : : : :
+MSEL0 : M17 : : : : 6 :
+GND* : M18 : : : : 6 :
+GND* : M19 : : : : 6 :
+VCCIO6 : M20 : power : : 3.3V : 6 :
+EXT_CLOCK : M21 : input : 3.3-V LVTTL : : 6 : Y
+SW[2] : M22 : input : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[8] : N1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[9] : N2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_CKE : N3 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[9] : N4 : output : 3.3-V LVTTL : : 1 : Y
+NC : N5 : : : : :
+DRAM_ADDR[11] : N6 : output : 3.3-V LVTTL : : 1 : Y
+GND : N7 : gnd : : : :
+NC : N8 : : : : :
+VCCINT : N9 : power : : 1.2V : :
+GND : N10 : gnd : : : :
+GND : N11 : gnd : : : :
+GND : N12 : gnd : : : :
+GND : N13 : gnd : : : :
+VCCINT : N14 : power : : 1.2V : :
+GPIO_1[33] : N15 : bidir : 3.3-V LVTTL : : 6 : Y
+GND : N16 : gnd : : : :
+MSEL1 : N17 : : : : 6 :
+CONF_DONE : N18 : : : : 6 :
+GND : N19 : gnd : : : :
+nSTATUS : N20 : : : : 6 :
+GPIO_1[31] : N21 : bidir : 3.3-V LVTTL : : 6 : Y
+GPIO_1[30] : N22 : bidir : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[10] : P1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[11] : P2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[8] : P3 : output : 3.3-V LVTTL : : 1 : Y
+NC : P4 : : : : :
+DRAM_ADDR[7] : P5 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[6] : P6 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO1 : P7 : power : : 3.3V : 1 :
+GND* : P8 : : : : 8 :
+GND* : P9 : : : : 8 :
+VCCINT : P10 : power : : 1.2V : :
+VCCINT : P11 : power : : 1.2V : :
+VCCINT : P12 : power : : 1.2V : :
+VCCINT : P13 : power : : 1.2V : :
+NC : P14 : : : : :
+GPIO_1[32] : P15 : bidir : 3.3-V LVTTL : : 6 : Y
+VCCIO6 : P16 : power : : 3.3V : 6 :
+GPIO_1[34] : P17 : bidir : 3.3-V LVTTL : : 6 : Y
+GPIO_1[35] : P18 : bidir : 3.3-V LVTTL : : 6 : Y
+NC : P19 : : : : :
+NC : P20 : : : : :
+NC : P21 : : : : :
+NC : P22 : : : : :
+DRAM_DQ[12] : R1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[13] : R2 : bidir : 3.3-V LVTTL : : 1 : Y
+GND : R3 : gnd : : : :
+NC : R4 : : : : :
+DRAM_ADDR[5] : R5 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[4] : R6 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_LDQM : R7 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_WE_N : R8 : output : 3.3-V LVTTL : : 1 : Y
+SRAM_DQ[12] : R9 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[14] : R10 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[10] : R11 : output : 3.3-V LVTTL : : 8 : Y
+FL_ADDR[10] : R12 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[21] : R13 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[8] : R14 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[3] : R15 : output : 3.3-V LVTTL : : 7 : Y
+GND* : R16 : : : : 7 :
+LEDR[9] : R17 : output : 3.3-V LVTTL : : 6 : Y
+LEDR[8] : R18 : output : 3.3-V LVTTL : : 6 : Y
+LEDR[1] : R19 : output : 3.3-V LVTTL : : 6 : Y
+LEDR[0] : R20 : output : 3.3-V LVTTL : : 6 : Y
+KEY[1] : R21 : input : 3.3-V LVTTL : : 6 : Y
+KEY[0] : R22 : input : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[14] : T1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[15] : T2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_CAS_N : T3 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO1 : T4 : power : : 3.3V : 1 :
+DRAM_RAS_N : T5 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_CS_N : T6 : output : 3.3-V LVTTL : : 1 : Y
+SRAM_ADDR[15] : T7 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_OE_N : T8 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : T9 : power : : 3.3V : 8 :
+GND : T10 : gnd : : : :
+SRAM_ADDR[11] : T11 : output : 3.3-V LVTTL : : 8 : Y
+FL_ADDR[11] : T12 : output : 3.3-V LVTTL : : 7 : Y
+GND : T13 : gnd : : : :
+VCCIO7 : T14 : power : : 3.3V : 7 :
+FL_ADDR[4] : T15 : output : 3.3-V LVTTL : : 7 : Y
+GND* : T16 : : : : 7 :
+GND_PLL4 : T17 : gnd : : : :
+LEDR[4] : T18 : output : 3.3-V LVTTL : : 6 : Y
+VCCIO6 : T19 : power : : 3.3V : 6 :
+GND : T20 : gnd : : : :
+KEY[3] : T21 : input : 3.3-V LVTTL : : 6 : Y
+KEY[2] : T22 : input : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[0] : U1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[1] : U2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_BA_0 : U3 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_CLK : U4 : output : 3.3-V LVTTL : : 1 : Y
+GND_PLL1 : U5 : gnd : : : :
+VCCD_PLL1 : U6 : power : : 1.2V : :
+VCCA_PLL1 : U7 : power : : 1.2V : :
+SRAM_DQ[15] : U8 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[11] : U9 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[13] : U10 : output : 3.3-V LVTTL : : 8 : Y
+SW[6] : U11 : input : 3.3-V LVTTL : : 8 : Y
+SW[5] : U12 : input : 3.3-V LVTTL : : 8 : Y
+FL_ADDR[20] : U13 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[18] : U14 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[5] : U15 : output : 3.3-V LVTTL : : 7 : Y
+VCCA_PLL4 : U16 : power : : 1.2V : :
+VCCD_PLL4 : U17 : power : : 1.2V : :
+LEDR[7] : U18 : output : 3.3-V LVTTL : : 6 : Y
+LEDR[2] : U19 : output : 3.3-V LVTTL : : 6 : Y
+GND* : U20 : : : : 6 :
+LEDG[1] : U21 : output : 3.3-V LVTTL : : 6 : Y
+LEDG[0] : U22 : output : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[2] : V1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[3] : V2 : bidir : 3.3-V LVTTL : : 1 : Y
+GND : V3 : gnd : : : :
+DRAM_BA_1 : V4 : output : 3.3-V LVTTL : : 1 : Y
+GND_PLL1 : V5 : gnd : : : :
+GND : V6 : gnd : : : :
+GNDA_PLL1 : V7 : gnd : : : :
+SRAM_DQ[14] : V8 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[10] : V9 : bidir : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : V10 : power : : 3.3V : 8 :
+SRAM_ADDR[8] : V11 : output : 3.3-V LVTTL : : 8 : Y
+SW[3] : V12 : input : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : V13 : power : : 3.3V : 7 :
+FL_ADDR[19] : V14 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[6] : V15 : output : 3.3-V LVTTL : : 7 : Y
+GNDA_PLL4 : V16 : gnd : : : :
+GND : V17 : gnd : : : :
+GND_PLL4 : V18 : gnd : : : :
+LEDR[5] : V19 : output : 3.3-V LVTTL : : 6 : Y
+GND* : V20 : : : : 6 :
+LEDG[3] : V21 : output : 3.3-V LVTTL : : 6 : Y
+LEDG[2] : V22 : output : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[4] : W1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[5] : W2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[10] : W3 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[0] : W4 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[1] : W5 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO8 : W6 : power : : 3.3V : 8 :
+SRAM_UB_N : W7 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[13] : W8 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_DQ[9] : W9 : bidir : 3.3-V LVTTL : : 8 : Y
+GND : W10 : gnd : : : :
+SRAM_ADDR[9] : W11 : output : 3.3-V LVTTL : : 8 : Y
+SW[4] : W12 : input : 3.3-V LVTTL : : 7 : Y
+GND : W13 : gnd : : : :
+FL_RST_N : W14 : output : 3.3-V LVTTL : : 7 : Y
+FL_ADDR[7] : W15 : output : 3.3-V LVTTL : : 7 : Y
+GND* : W16 : : : : 7 :
+VCCIO7 : W17 : power : : 3.3V : 7 :
+NC : W18 : : : : :
+GND : W19 : gnd : : : :
+~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N
+LEDG[5] : W21 : output : 3.3-V LVTTL : : 6 : Y
+LEDG[4] : W22 : output : 3.3-V LVTTL : : 6 : Y
+DRAM_DQ[6] : Y1 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_DQ[7] : Y2 : bidir : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[2] : Y3 : output : 3.3-V LVTTL : : 1 : Y
+DRAM_ADDR[3] : Y4 : output : 3.3-V LVTTL : : 1 : Y
+SRAM_ADDR[17] : Y5 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[16] : Y6 : output : 3.3-V LVTTL : : 8 : Y
+SRAM_LB_N : Y7 : output : 3.3-V LVTTL : : 8 : Y
+GND : Y8 : gnd : : : :
+SRAM_DQ[8] : Y9 : bidir : 3.3-V LVTTL : : 8 : Y
+SRAM_ADDR[12] : Y10 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : Y11 : power : : 3.3V : 8 :
+VCCIO7 : Y12 : power : : 3.3V : 7 :
+FL_ADDR[9] : Y13 : output : 3.3-V LVTTL : : 7 : Y
+FL_WE_N : Y14 : output : 3.3-V LVTTL : : 7 : Y
+GND : Y15 : gnd : : : :
+FL_ADDR[2] : Y16 : output : 3.3-V LVTTL : : 7 : Y
+GND* : Y17 : : : : 7 :
+LEDR[6] : Y18 : output : 3.3-V LVTTL : : 6 : Y
+LEDR[3] : Y19 : output : 3.3-V LVTTL : : 6 : Y
+GND* : Y20 : : : : 6 :
+LEDG[7] : Y21 : output : 3.3-V LVTTL : : 6 : Y
+LEDG[6] : Y22 : output : 3.3-V LVTTL : : 6 : Y
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.rpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.rpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.fit.rpt (revision 6)
@@ -0,0 +1,2660 @@
+Fitter report for uart
+Sat Jan 16 19:25:56 2010
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Incremental Compilation Preservation Summary
+ 5. Incremental Compilation Partition Settings
+ 6. Incremental Compilation Placement Preservation
+ 7. Pin-Out File
+ 8. Fitter Resource Usage Summary
+ 9. Input Pins
+ 10. Output Pins
+ 11. Bidir Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Control Signals
+ 19. Global & Other Fast Signals
+ 20. Non-Global High Fan-Out Signals
+ 21. Interconnect Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB-wide Signals
+ 24. LAB Signals Sourced
+ 25. LAB Signals Sourced Out
+ 26. LAB Distinct Inputs
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing
+ 30. Advanced Data - General
+ 31. Advanced Data - Placement Preparation
+ 32. Advanced Data - Placement
+ 33. Advanced Data - Routing
+ 34. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Sat Jan 16 19:25:56 2010 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; uart ;
+; Top-level Entity Name ; TOP_UART ;
+; Family ; Cyclone II ;
+; Device ; EP2C20F484C7 ;
+; Timing Models ; Final ;
+; Total logic elements ; 155 / 18,752 ( < 1 % ) ;
+; Total combinational functions ; 150 / 18,752 ( < 1 % ) ;
+; Dedicated logic registers ; 70 / 18,752 ( < 1 % ) ;
+; Total registers ; 70 ;
+; Total pins ; 281 / 315 ( 89 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 239,616 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
+; Total PLLs ; 0 / 4 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C20F484C7 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 501 ( 0.00 % ) ;
+; -- Achieved ; 0 / 501 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 501 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/altera/cores/vhdl/uart/uart.pin.
+
+
++----------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+------------------------+
+; Resource ; Usage ;
++---------------------------------------------+------------------------+
+; Total logic elements ; 155 / 18,752 ( < 1 % ) ;
+; -- Combinational with no register ; 85 ;
+; -- Register only ; 5 ;
+; -- Combinational with a register ; 65 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 81 ;
+; -- 3 input functions ; 38 ;
+; -- <=2 input functions ; 31 ;
+; -- Register only ; 5 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 150 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers* ; 70 / 19,649 ( < 1 % ) ;
+; -- Dedicated logic registers ; 70 / 18,752 ( < 1 % ) ;
+; -- I/O registers ; 0 / 897 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 13 / 1,172 ( 1 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 281 / 315 ( 89 % ) ;
+; -- Clock pins ; 6 / 8 ( 75 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 0 / 52 ( 0 % ) ;
+; Total block memory bits ; 0 / 239,616 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
+; PLLs ; 0 / 4 ( 0 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 0% / 0% / 1% ;
+; Maximum fan-out node ; CLOCK_50~clkctrl ;
+; Maximum fan-out ; 70 ;
+; Highest non-global fan-out signal ; KEY[0] ;
+; Highest non-global fan-out ; 54 ;
+; Total fan-out ; 701 ;
+; Average fan-out ; 1.37 ;
++---------------------------------------------+------------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; AUD_ADCDAT ; B6 ; 3 ; 3 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; CLOCK_27 ; F10 ; 3 ; 18 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; CLOCK_50 ; L1 ; 2 ; 0 ; 13 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; EXT_CLOCK ; M21 ; 6 ; 50 ; 14 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; IRDA_RXD ; AB15 ; 7 ; 33 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; KEY[0] ; R22 ; 6 ; 50 ; 10 ; 1 ; 54 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; KEY[1] ; R21 ; 6 ; 50 ; 10 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; KEY[2] ; T22 ; 6 ; 50 ; 9 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; KEY[3] ; T21 ; 6 ; 50 ; 9 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SD_DAT ; G8 ; 3 ; 7 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; SW[0] ; L22 ; 5 ; 50 ; 14 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[1] ; L21 ; 5 ; 50 ; 14 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[2] ; M22 ; 6 ; 50 ; 14 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[3] ; V12 ; 7 ; 26 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[4] ; W12 ; 7 ; 26 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[5] ; U12 ; 8 ; 26 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[6] ; U11 ; 8 ; 26 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[7] ; M2 ; 1 ; 0 ; 13 ; 3 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[8] ; M1 ; 1 ; 0 ; 13 ; 2 ; 3 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; SW[9] ; L2 ; 2 ; 0 ; 13 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; TCK ; C7 ; 3 ; 7 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; TCS ; D8 ; 3 ; 9 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; TDI ; E8 ; 3 ; 11 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; UART_RXD ; F14 ; 4 ; 35 ; 27 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
++------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; AUD_DACDAT ; B5 ; 3 ; 3 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; AUD_XCK ; B4 ; 3 ; 1 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[0] ; W4 ; 1 ; 0 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[10] ; W3 ; 1 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[11] ; N6 ; 1 ; 0 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[1] ; W5 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[2] ; Y3 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[3] ; Y4 ; 1 ; 0 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[4] ; R6 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[5] ; R5 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[6] ; P6 ; 1 ; 0 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[7] ; P5 ; 1 ; 0 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[8] ; P3 ; 1 ; 0 ; 10 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_ADDR[9] ; N4 ; 1 ; 0 ; 10 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_BA_0 ; U3 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_BA_1 ; V4 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_CAS_N ; T3 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_CKE ; N3 ; 1 ; 0 ; 10 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_CLK ; U4 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_CS_N ; T6 ; 1 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_LDQM ; R7 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_RAS_N ; T5 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_UDQM ; M5 ; 1 ; 0 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_WE_N ; R8 ; 1 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[0] ; AB20 ; 7 ; 48 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[10] ; R12 ; 7 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[11] ; T12 ; 7 ; 31 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[12] ; AB14 ; 7 ; 33 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[13] ; AA13 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[14] ; AB13 ; 7 ; 29 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[15] ; AA12 ; 7 ; 29 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[16] ; AB12 ; 7 ; 29 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[17] ; AA20 ; 7 ; 48 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[18] ; U14 ; 7 ; 39 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[19] ; V14 ; 7 ; 37 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[1] ; AA14 ; 7 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[20] ; U13 ; 7 ; 31 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[21] ; R13 ; 7 ; 37 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[2] ; Y16 ; 7 ; 44 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[3] ; R15 ; 7 ; 42 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[4] ; T15 ; 7 ; 39 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[5] ; U15 ; 7 ; 46 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[6] ; V15 ; 7 ; 46 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[7] ; W15 ; 7 ; 39 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[8] ; R14 ; 7 ; 42 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_ADDR[9] ; Y13 ; 7 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_CE_N ; G11 ; 3 ; 20 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; FL_OE_N ; AA15 ; 7 ; 35 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_RST_N ; W14 ; 7 ; 35 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_WE_N ; Y14 ; 7 ; 39 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX0[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX1[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX2[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; HEX3[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; I2C_SCLK ; A3 ; 3 ; 1 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[0] ; U22 ; 6 ; 50 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[1] ; U21 ; 6 ; 50 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[2] ; V22 ; 6 ; 50 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[3] ; V21 ; 6 ; 50 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[4] ; W22 ; 6 ; 50 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[5] ; W21 ; 6 ; 50 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[6] ; Y22 ; 6 ; 50 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDG[7] ; Y21 ; 6 ; 50 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[0] ; R20 ; 6 ; 50 ; 10 ; 0 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[1] ; R19 ; 6 ; 50 ; 8 ; 1 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[2] ; U19 ; 6 ; 50 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[3] ; Y19 ; 6 ; 50 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[4] ; T18 ; 6 ; 50 ; 3 ; 0 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[5] ; V19 ; 6 ; 50 ; 2 ; 2 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[6] ; Y18 ; 6 ; 50 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[7] ; U18 ; 6 ; 50 ; 3 ; 1 ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[8] ; R18 ; 6 ; 50 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; LEDR[9] ; R17 ; 6 ; 50 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SD_CLK ; E11 ; 3 ; 22 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; SD_CMD ; H3 ; 2 ; 0 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; SD_DAT3 ; F9 ; 3 ; 11 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; SRAM_ADDR[0] ; AA3 ; 8 ; 1 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[10] ; R11 ; 8 ; 20 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[11] ; T11 ; 8 ; 18 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[12] ; Y10 ; 8 ; 15 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[13] ; U10 ; 8 ; 13 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[14] ; R10 ; 8 ; 13 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[15] ; T7 ; 8 ; 5 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[16] ; Y6 ; 8 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[17] ; Y5 ; 8 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[1] ; AB3 ; 8 ; 1 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[2] ; AA4 ; 8 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[3] ; AB4 ; 8 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[4] ; AA5 ; 8 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[5] ; AB10 ; 8 ; 22 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[6] ; AA11 ; 8 ; 24 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[7] ; AB11 ; 8 ; 24 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[8] ; V11 ; 8 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_ADDR[9] ; W11 ; 8 ; 20 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_CE_N ; AB5 ; 8 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_LB_N ; Y7 ; 8 ; 5 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_OE_N ; T8 ; 8 ; 5 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_UB_N ; W7 ; 8 ; 9 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_WE_N ; AA10 ; 8 ; 22 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; TDO ; D7 ; 3 ; 9 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; UART_TXD ; G12 ; 4 ; 31 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_B[0] ; A9 ; 3 ; 15 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_B[1] ; D11 ; 3 ; 22 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_B[2] ; A10 ; 3 ; 20 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_B[3] ; B10 ; 3 ; 20 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_G[0] ; B8 ; 3 ; 13 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_G[1] ; C10 ; 3 ; 18 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_G[2] ; B9 ; 3 ; 15 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_G[3] ; A8 ; 3 ; 13 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_HS ; A11 ; 3 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_R[0] ; D9 ; 3 ; 13 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_R[1] ; C9 ; 3 ; 9 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_R[2] ; A7 ; 3 ; 11 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_R[3] ; B7 ; 3 ; 11 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; VGA_VS ; B11 ; 3 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
++---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins ;
++-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; AUD_ADCLRCK ; A6 ; 3 ; 3 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; AUD_BCLK ; A4 ; 3 ; 1 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; AUD_DACLRCK ; A5 ; 3 ; 3 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[0] ; U1 ; 1 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[10] ; P1 ; 1 ; 0 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[11] ; P2 ; 1 ; 0 ; 11 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[12] ; R1 ; 1 ; 0 ; 8 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[13] ; R2 ; 1 ; 0 ; 8 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[14] ; T1 ; 1 ; 0 ; 8 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[15] ; T2 ; 1 ; 0 ; 8 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[1] ; U2 ; 1 ; 0 ; 7 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[2] ; V1 ; 1 ; 0 ; 6 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[3] ; V2 ; 1 ; 0 ; 6 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[4] ; W1 ; 1 ; 0 ; 4 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[5] ; W2 ; 1 ; 0 ; 4 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[6] ; Y1 ; 1 ; 0 ; 4 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[7] ; Y2 ; 1 ; 0 ; 4 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[8] ; N1 ; 1 ; 0 ; 12 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; DRAM_DQ[9] ; N2 ; 1 ; 0 ; 12 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[0] ; AB16 ; 7 ; 35 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[1] ; AA16 ; 7 ; 35 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[2] ; AB17 ; 7 ; 37 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[3] ; AA17 ; 7 ; 37 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[4] ; AB18 ; 7 ; 42 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[5] ; AA18 ; 7 ; 44 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[6] ; AB19 ; 7 ; 48 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; FL_DQ[7] ; AA19 ; 7 ; 48 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[0] ; A13 ; 4 ; 26 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[10] ; A18 ; 4 ; 46 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[11] ; B18 ; 4 ; 46 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[12] ; A19 ; 4 ; 46 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[13] ; B19 ; 4 ; 46 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[14] ; A20 ; 4 ; 48 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[15] ; B20 ; 4 ; 48 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[16] ; C21 ; 5 ; 50 ; 24 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[17] ; C22 ; 5 ; 50 ; 24 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[18] ; D21 ; 5 ; 50 ; 21 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[19] ; D22 ; 5 ; 50 ; 22 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[1] ; B13 ; 4 ; 26 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[20] ; E21 ; 5 ; 50 ; 21 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[21] ; E22 ; 5 ; 50 ; 21 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[22] ; F21 ; 5 ; 50 ; 20 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[23] ; F22 ; 5 ; 50 ; 20 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[24] ; G21 ; 5 ; 50 ; 19 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[25] ; G22 ; 5 ; 50 ; 19 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[26] ; J21 ; 5 ; 50 ; 16 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[27] ; J22 ; 5 ; 50 ; 16 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[28] ; K21 ; 5 ; 50 ; 15 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[29] ; K22 ; 5 ; 50 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[2] ; A14 ; 4 ; 29 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[30] ; J19 ; 5 ; 50 ; 17 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[31] ; J20 ; 5 ; 50 ; 16 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[32] ; J18 ; 5 ; 50 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[33] ; K20 ; 5 ; 50 ; 17 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[34] ; L19 ; 5 ; 50 ; 15 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[35] ; L18 ; 5 ; 50 ; 15 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[3] ; B14 ; 4 ; 29 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[4] ; A15 ; 4 ; 33 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[5] ; B15 ; 4 ; 33 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[6] ; A16 ; 4 ; 33 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[7] ; B16 ; 4 ; 33 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[8] ; A17 ; 4 ; 37 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_0[9] ; B17 ; 4 ; 37 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[0] ; H12 ; 4 ; 31 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[10] ; C14 ; 4 ; 39 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[11] ; D14 ; 4 ; 35 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[12] ; D15 ; 4 ; 39 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[13] ; D16 ; 4 ; 42 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[14] ; C17 ; 4 ; 48 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[15] ; C18 ; 4 ; 48 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[16] ; C19 ; 5 ; 50 ; 24 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[17] ; C20 ; 5 ; 50 ; 25 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[18] ; D19 ; 5 ; 50 ; 25 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[19] ; D20 ; 5 ; 50 ; 25 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[1] ; H13 ; 4 ; 37 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[20] ; E20 ; 5 ; 50 ; 23 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[21] ; F20 ; 5 ; 50 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[22] ; E19 ; 5 ; 50 ; 25 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[23] ; E18 ; 5 ; 50 ; 25 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[24] ; G20 ; 5 ; 50 ; 23 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[25] ; G18 ; 5 ; 50 ; 22 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[26] ; G17 ; 5 ; 50 ; 22 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[27] ; H17 ; 5 ; 50 ; 20 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[28] ; J15 ; 5 ; 50 ; 18 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[29] ; H18 ; 5 ; 50 ; 20 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[2] ; H14 ; 4 ; 42 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[30] ; N22 ; 6 ; 50 ; 12 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[31] ; N21 ; 6 ; 50 ; 12 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[32] ; P15 ; 6 ; 50 ; 11 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[33] ; N15 ; 6 ; 50 ; 11 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[34] ; P17 ; 6 ; 50 ; 8 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[35] ; P18 ; 6 ; 50 ; 9 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[3] ; G15 ; 4 ; 39 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[4] ; E14 ; 4 ; 35 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[5] ; E15 ; 4 ; 42 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[6] ; F15 ; 4 ; 39 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[7] ; G16 ; 4 ; 44 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[8] ; F12 ; 4 ; 31 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; GPIO_1[9] ; F13 ; 4 ; 35 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; I2C_SDAT ; B3 ; 3 ; 1 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; PS2_CLK ; H15 ; 4 ; 44 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; PS2_DAT ; J14 ; 4 ; 42 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[0] ; AA6 ; 8 ; 7 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[10] ; V9 ; 8 ; 9 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[11] ; U9 ; 8 ; 13 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[12] ; R9 ; 8 ; 13 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[13] ; W8 ; 8 ; 9 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[14] ; V8 ; 8 ; 9 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[15] ; U8 ; 8 ; 5 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[1] ; AB6 ; 8 ; 7 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[2] ; AA7 ; 8 ; 11 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[3] ; AB7 ; 8 ; 11 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[4] ; AA8 ; 8 ; 15 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[5] ; AB8 ; 8 ; 15 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[6] ; AA9 ; 8 ; 18 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[7] ; AB9 ; 8 ; 18 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[8] ; Y9 ; 8 ; 11 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; SRAM_DQ[9] ; W9 ; 8 ; 11 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
++-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1 ; 40 / 41 ( 98 % ) ; 3.3V ; -- ;
+; 2 ; 33 / 33 ( 100 % ) ; 3.3V ; -- ;
+; 3 ; 31 / 43 ( 72 % ) ; 3.3V ; -- ;
+; 4 ; 36 / 40 ( 90 % ) ; 3.3V ; -- ;
+; 5 ; 36 / 39 ( 92 % ) ; 3.3V ; -- ;
+; 6 ; 31 / 36 ( 86 % ) ; 3.3V ; -- ;
+; 7 ; 36 / 40 ( 90 % ) ; 3.3V ; -- ;
+; 8 ; 41 / 43 ( 95 % ) ; 3.3V ; -- ;
++----------+-------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A3 ; 325 ; 3 ; I2C_SCLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A4 ; 324 ; 3 ; AUD_BCLK ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A5 ; 322 ; 3 ; AUD_DACLRCK ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A6 ; 320 ; 3 ; AUD_ADCLRCK ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A7 ; 306 ; 3 ; VGA_R[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A8 ; 304 ; 3 ; VGA_G[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A9 ; 298 ; 3 ; VGA_B[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A10 ; 293 ; 3 ; VGA_B[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A11 ; 287 ; 3 ; VGA_HS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; A13 ; 281 ; 4 ; GPIO_0[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A14 ; 279 ; 4 ; GPIO_0[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A15 ; 273 ; 4 ; GPIO_0[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A16 ; 271 ; 4 ; GPIO_0[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A17 ; 265 ; 4 ; GPIO_0[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A18 ; 251 ; 4 ; GPIO_0[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A19 ; 249 ; 4 ; GPIO_0[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A20 ; 247 ; 4 ; GPIO_0[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; 82 ; 8 ; SRAM_ADDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA4 ; 85 ; 8 ; SRAM_ADDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA5 ; 89 ; 8 ; SRAM_ADDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA6 ; 97 ; 8 ; SRAM_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA7 ; 103 ; 8 ; SRAM_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA8 ; 111 ; 8 ; SRAM_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA9 ; 114 ; 8 ; SRAM_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA10 ; 120 ; 8 ; SRAM_WE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA11 ; 122 ; 8 ; SRAM_ADDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA12 ; 128 ; 7 ; FL_ADDR[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA13 ; 130 ; 7 ; FL_ADDR[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA14 ; 136 ; 7 ; FL_ADDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA15 ; 138 ; 7 ; FL_OE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA16 ; 140 ; 7 ; FL_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA17 ; 144 ; 7 ; FL_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA18 ; 153 ; 7 ; FL_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA19 ; 162 ; 7 ; FL_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA20 ; 164 ; 7 ; FL_ADDR[17] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB3 ; 83 ; 8 ; SRAM_ADDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB4 ; 84 ; 8 ; SRAM_ADDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB5 ; 88 ; 8 ; SRAM_CE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB6 ; 96 ; 8 ; SRAM_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB7 ; 102 ; 8 ; SRAM_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB8 ; 110 ; 8 ; SRAM_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB9 ; 113 ; 8 ; SRAM_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB10 ; 119 ; 8 ; SRAM_ADDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB11 ; 121 ; 8 ; SRAM_ADDR[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB12 ; 127 ; 7 ; FL_ADDR[16] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB13 ; 129 ; 7 ; FL_ADDR[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB14 ; 135 ; 7 ; FL_ADDR[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB15 ; 137 ; 7 ; IRDA_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; AB16 ; 139 ; 7 ; FL_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB17 ; 143 ; 7 ; FL_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB18 ; 152 ; 7 ; FL_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB19 ; 161 ; 7 ; FL_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB20 ; 163 ; 7 ; FL_ADDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B3 ; 326 ; 3 ; I2C_SDAT ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B4 ; 323 ; 3 ; AUD_XCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B5 ; 321 ; 3 ; AUD_DACDAT ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B6 ; 319 ; 3 ; AUD_ADCDAT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B7 ; 305 ; 3 ; VGA_R[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B8 ; 303 ; 3 ; VGA_G[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B9 ; 297 ; 3 ; VGA_G[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B10 ; 292 ; 3 ; VGA_B[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B11 ; 286 ; 3 ; VGA_VS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; B13 ; 280 ; 4 ; GPIO_0[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B14 ; 278 ; 4 ; GPIO_0[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B15 ; 272 ; 4 ; GPIO_0[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B16 ; 270 ; 4 ; GPIO_0[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B17 ; 264 ; 4 ; GPIO_0[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B18 ; 250 ; 4 ; GPIO_0[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B19 ; 248 ; 4 ; GPIO_0[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B20 ; 246 ; 4 ; GPIO_0[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C1 ; 8 ; 2 ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C2 ; 9 ; 2 ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C7 ; 315 ; 3 ; TCK ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C9 ; 310 ; 3 ; VGA_R[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C10 ; 296 ; 3 ; VGA_G[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C14 ; 260 ; 4 ; GPIO_1[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C17 ; 245 ; 4 ; GPIO_1[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C18 ; 244 ; 4 ; GPIO_1[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; C19 ; 238 ; 5 ; GPIO_1[16] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C20 ; 239 ; 5 ; GPIO_1[17] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C21 ; 236 ; 5 ; GPIO_0[16] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; C22 ; 237 ; 5 ; GPIO_0[17] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D1 ; 14 ; 2 ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D2 ; 15 ; 2 ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D3 ; 2 ; 2 ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D4 ; 3 ; 2 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D5 ; 4 ; 2 ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D6 ; 5 ; 2 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D7 ; 311 ; 3 ; TDO ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D8 ; 309 ; 3 ; TCS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D9 ; 302 ; 3 ; VGA_R[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D11 ; 289 ; 3 ; VGA_B[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D14 ; 267 ; 4 ; GPIO_1[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D15 ; 259 ; 4 ; GPIO_1[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D16 ; 255 ; 4 ; GPIO_1[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D19 ; 240 ; 5 ; GPIO_1[18] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D20 ; 241 ; 5 ; GPIO_1[19] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D21 ; 229 ; 5 ; GPIO_0[18] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; D22 ; 230 ; 5 ; GPIO_0[19] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E1 ; 20 ; 2 ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E2 ; 21 ; 2 ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E3 ; 6 ; 2 ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E4 ; 7 ; 2 ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E8 ; 308 ; 3 ; TDI ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; E11 ; 288 ; 3 ; SD_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; E14 ; 266 ; 4 ; GPIO_1[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; E15 ; 256 ; 4 ; GPIO_1[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; E18 ; 243 ; 5 ; GPIO_1[23] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E19 ; 242 ; 5 ; GPIO_1[22] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E20 ; 234 ; 5 ; GPIO_1[20] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E21 ; 227 ; 5 ; GPIO_0[20] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; E22 ; 228 ; 5 ; GPIO_0[21] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F1 ; 22 ; 2 ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F2 ; 23 ; 2 ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F3 ; 13 ; 2 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F4 ; 10 ; 2 ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F9 ; 307 ; 3 ; SD_DAT3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; F10 ; 295 ; 3 ; CLOCK_27 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F12 ; 276 ; 4 ; GPIO_1[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; F13 ; 269 ; 4 ; GPIO_1[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; F14 ; 268 ; 4 ; UART_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; F15 ; 262 ; 4 ; GPIO_1[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F20 ; 235 ; 5 ; GPIO_1[21] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F21 ; 223 ; 5 ; GPIO_0[22] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; F22 ; 224 ; 5 ; GPIO_0[23] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; G3 ; 16 ; 2 ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G5 ; 12 ; 2 ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G6 ; 11 ; 2 ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G8 ; 313 ; 3 ; SD_DAT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G11 ; 291 ; 3 ; FL_CE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; G12 ; 277 ; 4 ; UART_TXD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G15 ; 261 ; 4 ; GPIO_1[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; G16 ; 252 ; 4 ; GPIO_1[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; G17 ; 231 ; 5 ; GPIO_1[26] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G18 ; 232 ; 5 ; GPIO_1[25] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G20 ; 233 ; 5 ; GPIO_1[24] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G21 ; 221 ; 5 ; GPIO_0[24] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; G22 ; 222 ; 5 ; GPIO_0[25] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H1 ; 24 ; 2 ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H2 ; 25 ; 2 ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H3 ; 27 ; 2 ; SD_CMD ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; H4 ; 17 ; 2 ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H5 ; 18 ; 2 ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H6 ; 19 ; 2 ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H12 ; 274 ; 4 ; GPIO_1[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; H13 ; 263 ; 4 ; GPIO_1[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; H14 ; 257 ; 4 ; GPIO_1[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; H15 ; 253 ; 4 ; PS2_CLK ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H17 ; 226 ; 5 ; GPIO_1[27] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H18 ; 225 ; 5 ; GPIO_1[29] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J1 ; 29 ; 2 ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J2 ; 30 ; 2 ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J4 ; 28 ; 2 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J14 ; 258 ; 4 ; PS2_DAT ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; J15 ; 220 ; 5 ; GPIO_1[28] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J18 ; 217 ; 5 ; GPIO_0[32] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J19 ; 216 ; 5 ; GPIO_0[30] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J20 ; 213 ; 5 ; GPIO_0[31] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J21 ; 211 ; 5 ; GPIO_0[26] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; J22 ; 212 ; 5 ; GPIO_0[27] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K20 ; 215 ; 5 ; GPIO_0[33] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; K21 ; 209 ; 5 ; GPIO_0[28] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; K22 ; 210 ; 5 ; GPIO_0[29] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L1 ; 38 ; 2 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L2 ; 39 ; 2 ; SW[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; L8 ; 26 ; 2 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; L18 ; 208 ; 5 ; GPIO_0[35] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L19 ; 207 ; 5 ; GPIO_0[34] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L21 ; 205 ; 5 ; SW[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; L22 ; 206 ; 5 ; SW[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M1 ; 41 ; 1 ; SW[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M2 ; 42 ; 1 ; SW[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M5 ; 43 ; 1 ; DRAM_UDQM ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M21 ; 203 ; 6 ; EXT_CLOCK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; M22 ; 204 ; 6 ; SW[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N1 ; 45 ; 1 ; DRAM_DQ[8] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N2 ; 46 ; 1 ; DRAM_DQ[9] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N3 ; 51 ; 1 ; DRAM_CKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N4 ; 52 ; 1 ; DRAM_ADDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; N6 ; 49 ; 1 ; DRAM_ADDR[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N15 ; 194 ; 6 ; GPIO_1[33] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; N21 ; 199 ; 6 ; GPIO_1[31] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; N22 ; 200 ; 6 ; GPIO_1[30] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P1 ; 47 ; 1 ; DRAM_DQ[10] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P2 ; 48 ; 1 ; DRAM_DQ[11] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P3 ; 50 ; 1 ; DRAM_ADDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; 55 ; 1 ; DRAM_ADDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P6 ; 56 ; 1 ; DRAM_ADDR[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; P15 ; 193 ; 6 ; GPIO_1[32] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P17 ; 186 ; 6 ; GPIO_1[34] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P18 ; 187 ; 6 ; GPIO_1[35] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; R1 ; 57 ; 1 ; DRAM_DQ[12] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R2 ; 58 ; 1 ; DRAM_DQ[13] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; R5 ; 63 ; 1 ; DRAM_ADDR[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R6 ; 64 ; 1 ; DRAM_ADDR[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R7 ; 54 ; 1 ; DRAM_LDQM ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R8 ; 53 ; 1 ; DRAM_WE_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R9 ; 109 ; 8 ; SRAM_DQ[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R10 ; 108 ; 8 ; SRAM_ADDR[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R11 ; 116 ; 8 ; SRAM_ADDR[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R12 ; 134 ; 7 ; FL_ADDR[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R13 ; 145 ; 7 ; FL_ADDR[21] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R14 ; 150 ; 7 ; FL_ADDR[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R15 ; 151 ; 7 ; FL_ADDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; R17 ; 177 ; 6 ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R18 ; 184 ; 6 ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R19 ; 185 ; 6 ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R20 ; 192 ; 6 ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R21 ; 190 ; 6 ; KEY[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; R22 ; 191 ; 6 ; KEY[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T1 ; 59 ; 1 ; DRAM_DQ[14] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T2 ; 60 ; 1 ; DRAM_DQ[15] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T3 ; 69 ; 1 ; DRAM_CAS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T5 ; 67 ; 1 ; DRAM_RAS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T6 ; 68 ; 1 ; DRAM_CS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T7 ; 91 ; 8 ; SRAM_ADDR[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; T8 ; 90 ; 8 ; SRAM_OE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; 115 ; 8 ; SRAM_ADDR[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; T12 ; 131 ; 7 ; FL_ADDR[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T15 ; 147 ; 7 ; FL_ADDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; T18 ; 171 ; 6 ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 188 ; 6 ; KEY[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; T22 ; 189 ; 6 ; KEY[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U1 ; 61 ; 1 ; DRAM_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U2 ; 62 ; 1 ; DRAM_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U3 ; 70 ; 1 ; DRAM_BA_0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U4 ; 80 ; 1 ; DRAM_CLK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U8 ; 92 ; 8 ; SRAM_DQ[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U9 ; 106 ; 8 ; SRAM_DQ[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U10 ; 107 ; 8 ; SRAM_ADDR[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U11 ; 123 ; 8 ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U12 ; 124 ; 8 ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U13 ; 132 ; 7 ; FL_ADDR[20] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U14 ; 146 ; 7 ; FL_ADDR[18] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U15 ; 157 ; 7 ; FL_ADDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U18 ; 170 ; 6 ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U19 ; 172 ; 6 ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U21 ; 182 ; 6 ; LEDG[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; U22 ; 183 ; 6 ; LEDG[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V1 ; 65 ; 1 ; DRAM_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V2 ; 66 ; 1 ; DRAM_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V4 ; 81 ; 1 ; DRAM_BA_1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V8 ; 98 ; 8 ; SRAM_DQ[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V9 ; 101 ; 8 ; SRAM_DQ[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V11 ; 118 ; 8 ; SRAM_ADDR[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V12 ; 126 ; 7 ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; V14 ; 142 ; 7 ; FL_ADDR[19] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V15 ; 158 ; 7 ; FL_ADDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; V19 ; 166 ; 6 ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V21 ; 180 ; 6 ; LEDG[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; V22 ; 181 ; 6 ; LEDG[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W1 ; 71 ; 1 ; DRAM_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W2 ; 72 ; 1 ; DRAM_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W3 ; 75 ; 1 ; DRAM_ADDR[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W4 ; 76 ; 1 ; DRAM_ADDR[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W5 ; 79 ; 1 ; DRAM_ADDR[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W7 ; 99 ; 8 ; SRAM_UB_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W8 ; 100 ; 8 ; SRAM_DQ[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W9 ; 105 ; 8 ; SRAM_DQ[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W11 ; 117 ; 8 ; SRAM_ADDR[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W12 ; 125 ; 7 ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; 141 ; 7 ; FL_RST_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W15 ; 149 ; 7 ; FL_ADDR[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
+; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; W21 ; 174 ; 6 ; LEDG[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; W22 ; 175 ; 6 ; LEDG[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y1 ; 73 ; 1 ; DRAM_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y2 ; 74 ; 1 ; DRAM_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y3 ; 77 ; 1 ; DRAM_ADDR[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y4 ; 78 ; 1 ; DRAM_ADDR[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y5 ; 86 ; 8 ; SRAM_ADDR[17] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y6 ; 87 ; 8 ; SRAM_ADDR[16] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y7 ; 93 ; 8 ; SRAM_LB_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y9 ; 104 ; 8 ; SRAM_DQ[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y10 ; 112 ; 8 ; SRAM_ADDR[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; Y13 ; 133 ; 7 ; FL_ADDR[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y14 ; 148 ; 7 ; FL_WE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y16 ; 154 ; 7 ; FL_ADDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y18 ; 165 ; 6 ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y19 ; 168 ; 6 ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; Y21 ; 178 ; 6 ; LEDG[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; Y22 ; 179 ; 6 ; LEDG[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------+--------------+
+; |TOP_UART ; 155 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 281 ; 0 ; 85 (0) ; 5 (0) ; 65 (0) ; |TOP_UART ; work ;
+; |miniUART:U1| ; 155 (25) ; 70 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 85 (20) ; 5 (0) ; 65 (11) ; |TOP_UART|miniUART:U1 ; work ;
+; |ClkUnit:ClkDiv| ; 41 (41) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 18 (18) ; |TOP_UART|miniUART:U1|ClkUnit:ClkDiv ; work ;
+; |RxUnit:RxDev| ; 52 (52) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 5 (5) ; 24 (24) ; |TOP_UART|miniUART:U1|RxUnit:RxDev ; work ;
+; |TxUnit:TxDev| ; 38 (38) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 19 (19) ; |TOP_UART|miniUART:U1|TxUnit:TxDev ; work ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++---------------+----------+---------------+---------------+-----------------------+-----+
+; LEDR[0] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[1] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[2] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[3] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[4] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[5] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[6] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[7] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_DQ[0] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[1] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[2] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[3] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[4] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[5] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[6] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[7] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; PS2_DAT ; Bidir ; 0 ; 0 ; -- ; -- ;
+; PS2_CLK ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[0] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[1] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[2] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[3] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[4] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[5] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[6] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[7] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[8] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[9] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[10] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[11] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[12] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[13] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[14] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; DRAM_DQ[15] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[0] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[1] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[2] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[3] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[4] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[5] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[6] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; FL_DQ[7] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[8] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[9] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[10] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[11] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[12] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[13] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[14] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; SRAM_DQ[15] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; I2C_SDAT ; Bidir ; 0 ; 0 ; -- ; -- ;
+; AUD_ADCLRCK ; Bidir ; 0 ; 0 ; -- ; -- ;
+; AUD_DACLRCK ; Bidir ; 0 ; 0 ; -- ; -- ;
+; AUD_BCLK ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[0] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[1] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[2] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[3] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[4] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[5] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[6] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[7] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[8] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[9] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[10] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[11] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[12] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[13] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[14] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[15] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[16] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[17] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[18] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[19] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[20] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[21] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[22] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[23] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[24] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[25] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[26] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[27] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[28] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[29] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[30] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[31] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[32] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[33] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[34] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_0[35] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[0] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[1] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[2] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[3] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[4] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[5] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[6] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[7] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[8] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[9] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[10] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[11] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[12] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[13] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[14] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[15] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[16] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[17] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[18] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[19] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[20] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[21] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[22] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[23] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[24] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[25] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[26] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[27] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[28] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[29] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[30] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[31] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[32] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[33] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[34] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; GPIO_1[35] ; Bidir ; 0 ; 0 ; -- ; -- ;
+; CLOCK_27 ; Input ; 0 ; 0 ; -- ; -- ;
+; EXT_CLOCK ; Input ; 0 ; 0 ; -- ; -- ;
+; KEY[1] ; Input ; 0 ; 0 ; -- ; -- ;
+; KEY[2] ; Input ; 0 ; 0 ; -- ; -- ;
+; KEY[3] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[3] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[4] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[5] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[6] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[9] ; Input ; 0 ; 0 ; -- ; -- ;
+; HEX0[0] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[1] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[2] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[3] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[4] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[5] ; Output ; -- ; -- ; -- ; -- ;
+; HEX0[6] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[0] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[1] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[2] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[3] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[4] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[5] ; Output ; -- ; -- ; -- ; -- ;
+; HEX1[6] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[0] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[1] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[2] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[3] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[4] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[5] ; Output ; -- ; -- ; -- ; -- ;
+; HEX2[6] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[0] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[1] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[2] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[3] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[4] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[5] ; Output ; -- ; -- ; -- ; -- ;
+; HEX3[6] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[0] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[1] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[2] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[3] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[4] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[5] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[6] ; Output ; -- ; -- ; -- ; -- ;
+; LEDG[7] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[8] ; Output ; -- ; -- ; -- ; -- ;
+; LEDR[9] ; Output ; -- ; -- ; -- ; -- ;
+; UART_TXD ; Output ; -- ; -- ; -- ; -- ;
+; IRDA_RXD ; Input ; 0 ; 0 ; -- ; -- ;
+; DRAM_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_LDQM ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_UDQM ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_WE_N ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_CAS_N ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_RAS_N ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_CS_N ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_BA_0 ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_BA_1 ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_CLK ; Output ; -- ; -- ; -- ; -- ;
+; DRAM_CKE ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[12] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[13] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[14] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[15] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[16] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[17] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[18] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[19] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[20] ; Output ; -- ; -- ; -- ; -- ;
+; FL_ADDR[21] ; Output ; -- ; -- ; -- ; -- ;
+; FL_WE_N ; Output ; -- ; -- ; -- ; -- ;
+; FL_RST_N ; Output ; -- ; -- ; -- ; -- ;
+; FL_OE_N ; Output ; -- ; -- ; -- ; -- ;
+; FL_CE_N ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[12] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[13] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[14] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[15] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[16] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_ADDR[17] ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_UB_N ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_LB_N ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_WE_N ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_CE_N ; Output ; -- ; -- ; -- ; -- ;
+; SRAM_OE_N ; Output ; -- ; -- ; -- ; -- ;
+; SD_DAT ; Input ; 0 ; 0 ; -- ; -- ;
+; SD_DAT3 ; Output ; -- ; -- ; -- ; -- ;
+; SD_CMD ; Output ; -- ; -- ; -- ; -- ;
+; SD_CLK ; Output ; -- ; -- ; -- ; -- ;
+; TDI ; Input ; 0 ; 0 ; -- ; -- ;
+; TCK ; Input ; 0 ; 0 ; -- ; -- ;
+; TCS ; Input ; 0 ; 0 ; -- ; -- ;
+; TDO ; Output ; -- ; -- ; -- ; -- ;
+; I2C_SCLK ; Output ; -- ; -- ; -- ; -- ;
+; VGA_HS ; Output ; -- ; -- ; -- ; -- ;
+; VGA_VS ; Output ; -- ; -- ; -- ; -- ;
+; VGA_R[0] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_R[1] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_R[2] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_R[3] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_G[0] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_G[1] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_G[2] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_G[3] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_B[0] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_B[1] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_B[2] ; Output ; -- ; -- ; -- ; -- ;
+; VGA_B[3] ; Output ; -- ; -- ; -- ; -- ;
+; AUD_ADCDAT ; Input ; 0 ; 0 ; -- ; -- ;
+; AUD_DACDAT ; Output ; -- ; -- ; -- ; -- ;
+; AUD_XCK ; Output ; -- ; -- ; -- ; -- ;
+; KEY[0] ; Input ; 6 ; 6 ; -- ; -- ;
+; SW[0] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[1] ; Input ; 0 ; 0 ; -- ; -- ;
+; CLOCK_50 ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[2] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[7] ; Input ; 0 ; 0 ; -- ; -- ;
+; SW[8] ; Input ; 0 ; 0 ; -- ; -- ;
+; UART_RXD ; Input ; 6 ; 6 ; -- ; -- ;
++---------------+----------+---------------+---------------+-----------------------+-----+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; SRAM_DQ[0] ; ; ;
+; SRAM_DQ[1] ; ; ;
+; SRAM_DQ[2] ; ; ;
+; SRAM_DQ[3] ; ; ;
+; SRAM_DQ[4] ; ; ;
+; SRAM_DQ[5] ; ; ;
+; SRAM_DQ[6] ; ; ;
+; SRAM_DQ[7] ; ; ;
+; PS2_DAT ; ; ;
+; PS2_CLK ; ; ;
+; DRAM_DQ[0] ; ; ;
+; DRAM_DQ[1] ; ; ;
+; DRAM_DQ[2] ; ; ;
+; DRAM_DQ[3] ; ; ;
+; DRAM_DQ[4] ; ; ;
+; DRAM_DQ[5] ; ; ;
+; DRAM_DQ[6] ; ; ;
+; DRAM_DQ[7] ; ; ;
+; DRAM_DQ[8] ; ; ;
+; DRAM_DQ[9] ; ; ;
+; DRAM_DQ[10] ; ; ;
+; DRAM_DQ[11] ; ; ;
+; DRAM_DQ[12] ; ; ;
+; DRAM_DQ[13] ; ; ;
+; DRAM_DQ[14] ; ; ;
+; DRAM_DQ[15] ; ; ;
+; FL_DQ[0] ; ; ;
+; FL_DQ[1] ; ; ;
+; FL_DQ[2] ; ; ;
+; FL_DQ[3] ; ; ;
+; FL_DQ[4] ; ; ;
+; FL_DQ[5] ; ; ;
+; FL_DQ[6] ; ; ;
+; FL_DQ[7] ; ; ;
+; SRAM_DQ[8] ; ; ;
+; SRAM_DQ[9] ; ; ;
+; SRAM_DQ[10] ; ; ;
+; SRAM_DQ[11] ; ; ;
+; SRAM_DQ[12] ; ; ;
+; SRAM_DQ[13] ; ; ;
+; SRAM_DQ[14] ; ; ;
+; SRAM_DQ[15] ; ; ;
+; I2C_SDAT ; ; ;
+; AUD_ADCLRCK ; ; ;
+; AUD_DACLRCK ; ; ;
+; AUD_BCLK ; ; ;
+; GPIO_0[0] ; ; ;
+; GPIO_0[1] ; ; ;
+; GPIO_0[2] ; ; ;
+; GPIO_0[3] ; ; ;
+; GPIO_0[4] ; ; ;
+; GPIO_0[5] ; ; ;
+; GPIO_0[6] ; ; ;
+; GPIO_0[7] ; ; ;
+; GPIO_0[8] ; ; ;
+; GPIO_0[9] ; ; ;
+; GPIO_0[10] ; ; ;
+; GPIO_0[11] ; ; ;
+; GPIO_0[12] ; ; ;
+; GPIO_0[13] ; ; ;
+; GPIO_0[14] ; ; ;
+; GPIO_0[15] ; ; ;
+; GPIO_0[16] ; ; ;
+; GPIO_0[17] ; ; ;
+; GPIO_0[18] ; ; ;
+; GPIO_0[19] ; ; ;
+; GPIO_0[20] ; ; ;
+; GPIO_0[21] ; ; ;
+; GPIO_0[22] ; ; ;
+; GPIO_0[23] ; ; ;
+; GPIO_0[24] ; ; ;
+; GPIO_0[25] ; ; ;
+; GPIO_0[26] ; ; ;
+; GPIO_0[27] ; ; ;
+; GPIO_0[28] ; ; ;
+; GPIO_0[29] ; ; ;
+; GPIO_0[30] ; ; ;
+; GPIO_0[31] ; ; ;
+; GPIO_0[32] ; ; ;
+; GPIO_0[33] ; ; ;
+; GPIO_0[34] ; ; ;
+; GPIO_0[35] ; ; ;
+; GPIO_1[0] ; ; ;
+; GPIO_1[1] ; ; ;
+; GPIO_1[2] ; ; ;
+; GPIO_1[3] ; ; ;
+; GPIO_1[4] ; ; ;
+; GPIO_1[5] ; ; ;
+; GPIO_1[6] ; ; ;
+; GPIO_1[7] ; ; ;
+; GPIO_1[8] ; ; ;
+; GPIO_1[9] ; ; ;
+; GPIO_1[10] ; ; ;
+; GPIO_1[11] ; ; ;
+; GPIO_1[12] ; ; ;
+; GPIO_1[13] ; ; ;
+; GPIO_1[14] ; ; ;
+; GPIO_1[15] ; ; ;
+; GPIO_1[16] ; ; ;
+; GPIO_1[17] ; ; ;
+; GPIO_1[18] ; ; ;
+; GPIO_1[19] ; ; ;
+; GPIO_1[20] ; ; ;
+; GPIO_1[21] ; ; ;
+; GPIO_1[22] ; ; ;
+; GPIO_1[23] ; ; ;
+; GPIO_1[24] ; ; ;
+; GPIO_1[25] ; ; ;
+; GPIO_1[26] ; ; ;
+; GPIO_1[27] ; ; ;
+; GPIO_1[28] ; ; ;
+; GPIO_1[29] ; ; ;
+; GPIO_1[30] ; ; ;
+; GPIO_1[31] ; ; ;
+; GPIO_1[32] ; ; ;
+; GPIO_1[33] ; ; ;
+; GPIO_1[34] ; ; ;
+; GPIO_1[35] ; ; ;
+; CLOCK_27 ; ; ;
+; EXT_CLOCK ; ; ;
+; KEY[1] ; ; ;
+; KEY[2] ; ; ;
+; KEY[3] ; ; ;
+; SW[3] ; ; ;
+; SW[4] ; ; ;
+; SW[5] ; ; ;
+; SW[6] ; ; ;
+; SW[9] ; ; ;
+; IRDA_RXD ; ; ;
+; SD_DAT ; ; ;
+; TDI ; ; ;
+; TCK ; ; ;
+; TCS ; ; ;
+; AUD_ADCDAT ; ; ;
+; KEY[0] ; ; ;
+; - miniUART:U1|RxUnit:RxDev|tmpDRdy ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|tmpTBufE ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|TxD ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|BitCnt[0] ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|Start ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|tmpTRegE ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|BitCnt[0] ; 1 ; 6 ;
+; - miniUART:U1|StatM~5 ; 1 ; 6 ;
+; - miniUART:U1|IntRx_N~2 ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|TReg[0]~32 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|frameErr~5 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|outErr~5 ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|BitCnt[3]~18 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux14~0 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt16~10 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt16~11 ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|BitCnt[2]~20 ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|BitCnt[1]~21 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux7~0 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[3]~29 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[3]~30 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[2]~31 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[1]~32 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|BitCnt[3]~29 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|BitCnt[1]~31 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|BitCnt[1]~32 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|tmpRxD~3 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~40 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~41 ; 1 ; 6 ;
+; - miniUART:U1|CSReg[2]~5 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~42 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~43 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~44 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~45 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~46 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|DOut~47 ; 1 ; 6 ;
+; - miniUART:U1|TxUnit:TxDev|TBuff[0]~8 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux15~0 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux17~2 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux13~1 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|ClkDiv26~1 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux11~0 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux10~0 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux9~0 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Mux8~0 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|ShtReg[0]~40 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|ShtReg~41 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~6 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~7 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~8 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~9 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~10 ; 1 ; 6 ;
+; - miniUART:U1|ClkUnit:ClkDiv|Cnt26~11 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[0]~33 ; 1 ; 6 ;
+; SW[0] ; ; ;
+; SW[1] ; ; ;
+; CLOCK_50 ; ; ;
+; SW[2] ; ; ;
+; SW[7] ; ; ;
+; SW[8] ; ; ;
+; UART_RXD ; ; ;
+; - miniUART:U1|RxUnit:RxDev|Start~9 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|SampleCnt[3]~28 ; 1 ; 6 ;
+; - miniUART:U1|RxUnit:RxDev|tmpRxD~5 ; 1 ; 6 ;
++-------------------------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++---------------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_L1 ; 70 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
+; KEY[0] ; PIN_R22 ; 54 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
+; SW[8] ; PIN_M1 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK3 ; -- ;
+; miniUART:U1|DataOut[0]_240 ; LCCOMB_X40_Y13_N26 ; 9 ; Output enable ; no ; -- ; -- ; -- ;
+; miniUART:U1|RxUnit:RxDev|ShtReg[0]~40 ; LCCOMB_X39_Y13_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
+; miniUART:U1|RxUnit:RxDev|outErr~5 ; LCCOMB_X39_Y14_N22 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
+; miniUART:U1|TxUnit:TxDev|TBuff[0]~8 ; LCCOMB_X39_Y11_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
+; miniUART:U1|TxUnit:TxDev|TReg[0]~37 ; LCCOMB_X38_Y11_N30 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
++---------------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_L1 ; 70 ; Global Clock ; GCLK2 ; -- ;
+; SW[8] ; PIN_M1 ; 8 ; Global Clock ; GCLK3 ; -- ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------------------------------------------+---------+
+; Name ; Fan-Out ;
++-----------------------------------------------+---------+
+; KEY[0] ; 54 ;
+; miniUART:U1|TxUnit:TxDev|tmpTRegE ; 13 ;
+; miniUART:U1|ClkUnit:ClkDiv|tmpEnRX ; 12 ;
+; miniUART:U1|Read ; 11 ;
+; miniUART:U1|TxUnit:TxDev|BitCnt[0] ; 11 ;
+; miniUART:U1|RxUnit:RxDev|outErr~5 ; 10 ;
+; miniUART:U1|RxUnit:RxDev|BitCnt[3] ; 10 ;
+; SW[7] ; 9 ;
+; miniUART:U1|DataOut[0]_240 ; 9 ;
+; miniUART:U1|TxUnit:TxDev|BitCnt[1] ; 9 ;
+; miniUART:U1|TxUnit:TxDev|BitCnt[3] ; 9 ;
+; miniUART:U1|RxUnit:RxDev|ShtReg[0]~40 ; 8 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[0] ; 8 ;
+; miniUART:U1|TxUnit:TxDev|TReg[6]~33 ; 8 ;
+; miniUART:U1|TxUnit:TxDev|BitCnt[2] ; 8 ;
+; miniUART:U1|RxUnit:RxDev|BitCnt[0] ; 8 ;
+; SW[0] ; 7 ;
+; miniUART:U1|TxUnit:TxDev|TReg[0]~37 ; 7 ;
+; miniUART:U1|RxUnit:RxDev|tmpRxD ; 7 ;
+; miniUART:U1|RxUnit:RxDev|BitCnt[1] ; 7 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[0] ; 6 ;
+; miniUART:U1|RxUnit:RxDev|BitCnt[2] ; 6 ;
+; miniUART:U1|RxUnit:RxDev|tmpDRdy~8 ; 6 ;
+; miniUART:U1|TxUnit:TxDev|TxD~4 ; 6 ;
+; SW[2] ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[1] ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[0] ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|ClkDiv26 ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|Add2~1 ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[2] ; 5 ;
+; miniUART:U1|Load ; 5 ;
+; miniUART:U1|RxUnit:RxDev|SampleCnt[0] ; 5 ;
+; miniUART:U1|RxUnit:RxDev|SampleCnt[3] ; 5 ;
+; miniUART:U1|ClkUnit:ClkDiv|tmpEnTX ; 5 ;
+; miniUART:U1|TxUnit:TxDev|tmpTBufE ; 5 ;
+; miniUART:U1|Equal1~0 ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[2] ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|Add2~4 ; 4 ;
+; miniUART:U1|TxUnit:TxDev|TBuff[0]~8 ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[1] ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|Add2~2 ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|Cnt16~10 ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|Add2~0 ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1] ; 4 ;
+; miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[3] ; 4 ;
+; miniUART:U1|RxUnit:RxDev|Equal1~0 ; 4 ;
+; miniUART:U1|RxUnit:RxDev|SampleCnt[1] ; 4 ;
+; miniUART:U1|TxUnit:TxDev|TReg[0]~32 ; 4 ;
+; miniUART:U1|RxUnit:RxDev|Start ; 4 ;
+; UART_RXD ; 3 ;
++-----------------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+------------------------+
+; Block interconnects ; 162 / 54,004 ( < 1 % ) ;
+; C16 interconnects ; 2 / 2,100 ( < 1 % ) ;
+; C4 interconnects ; 62 / 36,000 ( < 1 % ) ;
+; Direct links ; 68 / 54,004 ( < 1 % ) ;
+; Global clocks ; 2 / 16 ( 13 % ) ;
+; Local interconnects ; 104 / 18,752 ( < 1 % ) ;
+; R24 interconnects ; 8 / 1,900 ( < 1 % ) ;
+; R4 interconnects ; 69 / 46,920 ( < 1 % ) ;
++----------------------------+------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Logic Elements ;
++---------------------------------------------+------------------------------+
+; Number of Logic Elements (Average = 11.92) ; Number of LABs (Total = 13) ;
++---------------------------------------------+------------------------------+
+; 1 ; 1 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 1 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 8 ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+------------------------------+
+; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 13) ;
++------------------------------------+------------------------------+
+; 1 Clock ; 13 ;
+; 1 Clock enable ; 4 ;
+; 1 Sync. load ; 1 ;
++------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced (Average = 17.23) ; Number of LABs (Total = 13) ;
++----------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 1 ;
+; 3 ; 0 ;
+; 4 ; 1 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 2 ;
+; 19 ; 2 ;
+; 20 ; 0 ;
+; 21 ; 0 ;
+; 22 ; 1 ;
+; 23 ; 1 ;
+; 24 ; 1 ;
+; 25 ; 0 ;
+; 26 ; 1 ;
+; 27 ; 0 ;
+; 28 ; 0 ;
+; 29 ; 0 ;
+; 30 ; 1 ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out (Average = 6.54) ; Number of LABs (Total = 13) ;
++-------------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 2 ;
+; 2 ; 2 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 2 ;
+; 11 ; 0 ;
+; 12 ; 2 ;
+; 13 ; 1 ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs (Average = 9.38) ; Number of LABs (Total = 13) ;
++---------------------------------------------+------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
+; 6 ; 1 ;
+; 7 ; 1 ;
+; 8 ; 1 ;
+; 9 ; 1 ;
+; 10 ; 0 ;
+; 11 ; 1 ;
+; 12 ; 1 ;
+; 13 ; 2 ;
+; 14 ; 0 ;
+; 15 ; 2 ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++----------------------------+
+; Advanced Data - General ;
++--------------------+-------+
+; Name ; Value ;
++--------------------+-------+
+; Status Code ; 0 ;
+; Desired User Slack ; 0 ;
+; Fit Attempts ; 1 ;
++--------------------+-------+
+
+
++------------------------------------------------------------------------------------+
+; Advanced Data - Placement Preparation ;
++------------------------------------------------------------------+-----------------+
+; Name ; Value ;
++------------------------------------------------------------------+-----------------+
+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; -7589 ;
+; Internal Atom Count - Fit Attempt 1 ; 221 ;
+; LE/ALM Count - Fit Attempt 1 ; 156 ;
+; LAB Count - Fit Attempt 1 ; 14 ;
+; Outputs per Lab - Fit Attempt 1 ; 6.571 ;
+; Inputs per LAB - Fit Attempt 1 ; 8.643 ;
+; Global Inputs per LAB - Fit Attempt 1 ; 0.929 ;
+; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:12;1:2 ;
+; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:6;1:5;2:3 ;
+; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:6;1:5;2:3 ;
+; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:12;1:2 ;
+; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:1;1:11;2:2 ;
+; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:10;1:4 ;
+; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:6;1:7;2:1 ;
+; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:9;2:4 ;
+; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:13 ;
+; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:8;1:6 ;
+; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:11;1:3 ;
+; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:14 ;
+; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:8;2:3;3:2 ;
+; LEs in Chains - Fit Attempt 1 ; 0 ;
+; LEs in Long Chains - Fit Attempt 1 ; 0 ;
+; LABs with Chains - Fit Attempt 1 ; 0 ;
+; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------------------------------------+-----------------+
+
+
++---------------------------------------------+
+; Advanced Data - Placement ;
++-------------------------------------+-------+
+; Name ; Value ;
++-------------------------------------+-------+
+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Early Slack - Fit Attempt 1 ; -7114 ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; -4452 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; -3831 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Late Slack - Fit Attempt 1 ; -3831 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
+; Auto Fit Point 7 - Fit Attempt 1 ; ff ;
+; Time - Fit Attempt 1 ; 1 ;
+; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
++-------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Advanced Data - Routing ;
++-------------------------------------+-------------+
+; Name ; Value ;
++-------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; -3123 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 1 ;
+; Mid Slack - Fit Attempt 1 ; -3636 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
+; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047 ;
++-------------------------------------+-------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Jan 16 19:25:47 2010
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart -c uart
+Info: Selected device EP2C20F484C7 for design "uart"
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning: Feature LogicLock is not available with your current license
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C15AF484C7 is compatible
+ Info: Device EP2C35F484C7 is compatible
+ Info: Device EP2C50F484C7 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location C4
+ Info: Pin ~nCSO~ is reserved at location C3
+ Info: Pin ~LVDS91p/nCEO~ is reserved at location W20
+Warning: No exact pin location assignment(s) for 7 pins of 281 total pins
+ Info: Pin CLOCK_27 not assigned to an exact location on the device
+ Info: Pin IRDA_RXD not assigned to an exact location on the device
+ Info: Pin FL_CE_N not assigned to an exact location on the device
+ Info: Pin SD_DAT not assigned to an exact location on the device
+ Info: Pin SD_DAT3 not assigned to an exact location on the device
+ Info: Pin SD_CMD not assigned to an exact location on the device
+ Info: Pin SD_CLK not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
+Info: Automatically promoted node SW[8] (placed in PIN M1 (CLK2, LVDSCLK1p, Input))
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+ Info: Following destination nodes may be non-global or may not use global or regional clocks
+ Info: Destination node miniUART:U1|Equal1~0
+ Info: Destination node miniUART:U1|DataOut[0]_240
+Info: Starting register packing
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 3 input, 4 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used -- 1 pins available
+ Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 1 pins available
+ Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 17 pins available
+ Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 4 pins available
+ Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 3 pins available
+ Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 5 pins available
+ Info: I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used -- 5 pins available
+ Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 2 pins available
+Warning: Ignored I/O standard assignments to the following nodes
+ Warning: Ignored I/O standard assignment to node "CLOCK_24[0]"
+ Warning: Ignored I/O standard assignment to node "CLOCK_24[1]"
+ Warning: Ignored I/O standard assignment to node "CLOCK_27[1]"
+Warning: Ignored locations or region assignments to the following nodes
+ Warning: Node "CLOCK_24[0]" is assigned to location or region, but does not exist in design
+ Warning: Node "CLOCK_24[1]" is assigned to location or region, but does not exist in design
+ Warning: Node "CLOCK_27[0]" is assigned to location or region, but does not exist in design
+ Warning: Node "CLOCK_27[1]" is assigned to location or region, but does not exist in design
+Info: Fitter preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:01
+Info: Estimated most critical path is register to register delay of 4.384 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X39_Y14; Fanout = 4; REG Node = 'miniUART:U1|RxUnit:RxDev|SampleCnt[1]'
+ Info: 2: + IC(0.416 ns) + CELL(0.322 ns) = 0.738 ns; Loc. = LAB_X39_Y14; Fanout = 4; COMB Node = 'miniUART:U1|RxUnit:RxDev|Equal1~0'
+ Info: 3: + IC(0.498 ns) + CELL(0.178 ns) = 1.414 ns; Loc. = LAB_X39_Y14; Fanout = 6; COMB Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy~8'
+ Info: 4: + IC(0.131 ns) + CELL(0.512 ns) = 2.057 ns; Loc. = LAB_X39_Y14; Fanout = 2; COMB Node = 'miniUART:U1|RxUnit:RxDev|tmpDRdy~10'
+ Info: 5: + IC(0.498 ns) + CELL(0.178 ns) = 2.733 ns; Loc. = LAB_X39_Y14; Fanout = 10; COMB Node = 'miniUART:U1|RxUnit:RxDev|outErr~5'
+ Info: 6: + IC(0.893 ns) + CELL(0.758 ns) = 4.384 ns; Loc. = LAB_X39_Y11; Fanout = 2; REG Node = 'miniUART:U1|RxUnit:RxDev|frameErr'
+ Info: Total cell delay = 1.948 ns ( 44.43 % )
+ Info: Total interconnect delay = 2.436 ns ( 55.57 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X38_Y0 to location X50_Y13
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 257 output pins without output pin load capacitance assignment
+ Info: Pin "LEDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "PS2_DAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "PS2_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "I2C_SDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "AUD_ADCLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "AUD_DACLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "AUD_BCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_0[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "GPIO_1[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "HEX3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDG[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "LEDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "UART_TXD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_LDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_UDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_CAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_RAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_CS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_BA_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_BA_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "DRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_ADDR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_RST_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "FL_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_UB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_LB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SRAM_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SD_DAT3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SD_CMD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "SD_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "TDO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "I2C_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_HS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_VS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_R[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_R[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_R[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_R[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_G[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_G[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_G[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_G[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_B[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_B[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_B[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "VGA_B[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "AUD_DACDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "AUD_XCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+ Info: Pin SRAM_DQ[0] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[1] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[2] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[3] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[4] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[5] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[6] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[7] has a permanently disabled output enable
+ Info: Pin PS2_DAT has a permanently disabled output enable
+ Info: Pin PS2_CLK has a permanently disabled output enable
+ Info: Pin DRAM_DQ[0] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[1] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[2] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[3] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[4] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[5] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[6] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[7] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[8] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[9] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[10] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[11] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[12] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[13] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[14] has a permanently disabled output enable
+ Info: Pin DRAM_DQ[15] has a permanently disabled output enable
+ Info: Pin FL_DQ[0] has a permanently disabled output enable
+ Info: Pin FL_DQ[1] has a permanently disabled output enable
+ Info: Pin FL_DQ[2] has a permanently disabled output enable
+ Info: Pin FL_DQ[3] has a permanently disabled output enable
+ Info: Pin FL_DQ[4] has a permanently disabled output enable
+ Info: Pin FL_DQ[5] has a permanently disabled output enable
+ Info: Pin FL_DQ[6] has a permanently disabled output enable
+ Info: Pin FL_DQ[7] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[8] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[9] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[10] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[11] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[12] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[13] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[14] has a permanently disabled output enable
+ Info: Pin SRAM_DQ[15] has a permanently disabled output enable
+ Info: Pin I2C_SDAT has a permanently disabled output enable
+ Info: Pin AUD_ADCLRCK has a permanently disabled output enable
+ Info: Pin AUD_DACLRCK has a permanently disabled output enable
+ Info: Pin AUD_BCLK has a permanently disabled output enable
+ Info: Pin GPIO_0[0] has a permanently disabled output enable
+ Info: Pin GPIO_0[1] has a permanently disabled output enable
+ Info: Pin GPIO_0[2] has a permanently disabled output enable
+ Info: Pin GPIO_0[3] has a permanently disabled output enable
+ Info: Pin GPIO_0[4] has a permanently disabled output enable
+ Info: Pin GPIO_0[5] has a permanently disabled output enable
+ Info: Pin GPIO_0[6] has a permanently disabled output enable
+ Info: Pin GPIO_0[7] has a permanently disabled output enable
+ Info: Pin GPIO_0[8] has a permanently disabled output enable
+ Info: Pin GPIO_0[9] has a permanently disabled output enable
+ Info: Pin GPIO_0[10] has a permanently disabled output enable
+ Info: Pin GPIO_0[11] has a permanently disabled output enable
+ Info: Pin GPIO_0[12] has a permanently disabled output enable
+ Info: Pin GPIO_0[13] has a permanently disabled output enable
+ Info: Pin GPIO_0[14] has a permanently disabled output enable
+ Info: Pin GPIO_0[15] has a permanently disabled output enable
+ Info: Pin GPIO_0[16] has a permanently disabled output enable
+ Info: Pin GPIO_0[17] has a permanently disabled output enable
+ Info: Pin GPIO_0[18] has a permanently disabled output enable
+ Info: Pin GPIO_0[19] has a permanently disabled output enable
+ Info: Pin GPIO_0[20] has a permanently disabled output enable
+ Info: Pin GPIO_0[21] has a permanently disabled output enable
+ Info: Pin GPIO_0[22] has a permanently disabled output enable
+ Info: Pin GPIO_0[23] has a permanently disabled output enable
+ Info: Pin GPIO_0[24] has a permanently disabled output enable
+ Info: Pin GPIO_0[25] has a permanently disabled output enable
+ Info: Pin GPIO_0[26] has a permanently disabled output enable
+ Info: Pin GPIO_0[27] has a permanently disabled output enable
+ Info: Pin GPIO_0[28] has a permanently disabled output enable
+ Info: Pin GPIO_0[29] has a permanently disabled output enable
+ Info: Pin GPIO_0[30] has a permanently disabled output enable
+ Info: Pin GPIO_0[31] has a permanently disabled output enable
+ Info: Pin GPIO_0[32] has a permanently disabled output enable
+ Info: Pin GPIO_0[33] has a permanently disabled output enable
+ Info: Pin GPIO_0[34] has a permanently disabled output enable
+ Info: Pin GPIO_0[35] has a permanently disabled output enable
+ Info: Pin GPIO_1[0] has a permanently disabled output enable
+ Info: Pin GPIO_1[1] has a permanently disabled output enable
+ Info: Pin GPIO_1[2] has a permanently disabled output enable
+ Info: Pin GPIO_1[3] has a permanently disabled output enable
+ Info: Pin GPIO_1[4] has a permanently disabled output enable
+ Info: Pin GPIO_1[5] has a permanently disabled output enable
+ Info: Pin GPIO_1[6] has a permanently disabled output enable
+ Info: Pin GPIO_1[7] has a permanently disabled output enable
+ Info: Pin GPIO_1[8] has a permanently disabled output enable
+ Info: Pin GPIO_1[9] has a permanently disabled output enable
+ Info: Pin GPIO_1[10] has a permanently disabled output enable
+ Info: Pin GPIO_1[11] has a permanently disabled output enable
+ Info: Pin GPIO_1[12] has a permanently disabled output enable
+ Info: Pin GPIO_1[13] has a permanently disabled output enable
+ Info: Pin GPIO_1[14] has a permanently disabled output enable
+ Info: Pin GPIO_1[15] has a permanently disabled output enable
+ Info: Pin GPIO_1[16] has a permanently disabled output enable
+ Info: Pin GPIO_1[17] has a permanently disabled output enable
+ Info: Pin GPIO_1[18] has a permanently disabled output enable
+ Info: Pin GPIO_1[19] has a permanently disabled output enable
+ Info: Pin GPIO_1[20] has a permanently disabled output enable
+ Info: Pin GPIO_1[21] has a permanently disabled output enable
+ Info: Pin GPIO_1[22] has a permanently disabled output enable
+ Info: Pin GPIO_1[23] has a permanently disabled output enable
+ Info: Pin GPIO_1[24] has a permanently disabled output enable
+ Info: Pin GPIO_1[25] has a permanently disabled output enable
+ Info: Pin GPIO_1[26] has a permanently disabled output enable
+ Info: Pin GPIO_1[27] has a permanently disabled output enable
+ Info: Pin GPIO_1[28] has a permanently disabled output enable
+ Info: Pin GPIO_1[29] has a permanently disabled output enable
+ Info: Pin GPIO_1[30] has a permanently disabled output enable
+ Info: Pin GPIO_1[31] has a permanently disabled output enable
+ Info: Pin GPIO_1[32] has a permanently disabled output enable
+ Info: Pin GPIO_1[33] has a permanently disabled output enable
+ Info: Pin GPIO_1[34] has a permanently disabled output enable
+ Info: Pin GPIO_1[35] has a permanently disabled output enable
+Warning: Following 246 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
+ Info: Pin SRAM_DQ[0] has VCC driving its datain port
+ Info: Pin SRAM_DQ[1] has VCC driving its datain port
+ Info: Pin SRAM_DQ[2] has VCC driving its datain port
+ Info: Pin SRAM_DQ[3] has VCC driving its datain port
+ Info: Pin SRAM_DQ[4] has VCC driving its datain port
+ Info: Pin SRAM_DQ[5] has VCC driving its datain port
+ Info: Pin SRAM_DQ[6] has VCC driving its datain port
+ Info: Pin SRAM_DQ[7] has VCC driving its datain port
+ Info: Pin PS2_DAT has VCC driving its datain port
+ Info: Pin PS2_CLK has VCC driving its datain port
+ Info: Pin DRAM_DQ[0] has VCC driving its datain port
+ Info: Pin DRAM_DQ[1] has VCC driving its datain port
+ Info: Pin DRAM_DQ[2] has VCC driving its datain port
+ Info: Pin DRAM_DQ[3] has VCC driving its datain port
+ Info: Pin DRAM_DQ[4] has VCC driving its datain port
+ Info: Pin DRAM_DQ[5] has VCC driving its datain port
+ Info: Pin DRAM_DQ[6] has VCC driving its datain port
+ Info: Pin DRAM_DQ[7] has VCC driving its datain port
+ Info: Pin DRAM_DQ[8] has VCC driving its datain port
+ Info: Pin DRAM_DQ[9] has VCC driving its datain port
+ Info: Pin DRAM_DQ[10] has VCC driving its datain port
+ Info: Pin DRAM_DQ[11] has VCC driving its datain port
+ Info: Pin DRAM_DQ[12] has VCC driving its datain port
+ Info: Pin DRAM_DQ[13] has VCC driving its datain port
+ Info: Pin DRAM_DQ[14] has VCC driving its datain port
+ Info: Pin DRAM_DQ[15] has VCC driving its datain port
+ Info: Pin FL_DQ[0] has VCC driving its datain port
+ Info: Pin FL_DQ[1] has VCC driving its datain port
+ Info: Pin FL_DQ[2] has VCC driving its datain port
+ Info: Pin FL_DQ[3] has VCC driving its datain port
+ Info: Pin FL_DQ[4] has VCC driving its datain port
+ Info: Pin FL_DQ[5] has VCC driving its datain port
+ Info: Pin FL_DQ[6] has VCC driving its datain port
+ Info: Pin FL_DQ[7] has VCC driving its datain port
+ Info: Pin SRAM_DQ[8] has VCC driving its datain port
+ Info: Pin SRAM_DQ[9] has VCC driving its datain port
+ Info: Pin SRAM_DQ[10] has VCC driving its datain port
+ Info: Pin SRAM_DQ[11] has VCC driving its datain port
+ Info: Pin SRAM_DQ[12] has VCC driving its datain port
+ Info: Pin SRAM_DQ[13] has VCC driving its datain port
+ Info: Pin SRAM_DQ[14] has VCC driving its datain port
+ Info: Pin SRAM_DQ[15] has VCC driving its datain port
+ Info: Pin I2C_SDAT has VCC driving its datain port
+ Info: Pin AUD_ADCLRCK has VCC driving its datain port
+ Info: Pin AUD_DACLRCK has VCC driving its datain port
+ Info: Pin AUD_BCLK has VCC driving its datain port
+ Info: Pin GPIO_0[0] has VCC driving its datain port
+ Info: Pin GPIO_0[1] has VCC driving its datain port
+ Info: Pin GPIO_0[2] has VCC driving its datain port
+ Info: Pin GPIO_0[3] has VCC driving its datain port
+ Info: Pin GPIO_0[4] has VCC driving its datain port
+ Info: Pin GPIO_0[5] has VCC driving its datain port
+ Info: Pin GPIO_0[6] has VCC driving its datain port
+ Info: Pin GPIO_0[7] has VCC driving its datain port
+ Info: Pin GPIO_0[8] has VCC driving its datain port
+ Info: Pin GPIO_0[9] has VCC driving its datain port
+ Info: Pin GPIO_0[10] has VCC driving its datain port
+ Info: Pin GPIO_0[11] has VCC driving its datain port
+ Info: Pin GPIO_0[12] has VCC driving its datain port
+ Info: Pin GPIO_0[13] has VCC driving its datain port
+ Info: Pin GPIO_0[14] has VCC driving its datain port
+ Info: Pin GPIO_0[15] has VCC driving its datain port
+ Info: Pin GPIO_0[16] has VCC driving its datain port
+ Info: Pin GPIO_0[17] has VCC driving its datain port
+ Info: Pin GPIO_0[18] has VCC driving its datain port
+ Info: Pin GPIO_0[19] has VCC driving its datain port
+ Info: Pin GPIO_0[20] has VCC driving its datain port
+ Info: Pin GPIO_0[21] has VCC driving its datain port
+ Info: Pin GPIO_0[22] has VCC driving its datain port
+ Info: Pin GPIO_0[23] has VCC driving its datain port
+ Info: Pin GPIO_0[24] has VCC driving its datain port
+ Info: Pin GPIO_0[25] has VCC driving its datain port
+ Info: Pin GPIO_0[26] has VCC driving its datain port
+ Info: Pin GPIO_0[27] has VCC driving its datain port
+ Info: Pin GPIO_0[28] has VCC driving its datain port
+ Info: Pin GPIO_0[29] has VCC driving its datain port
+ Info: Pin GPIO_0[30] has VCC driving its datain port
+ Info: Pin GPIO_0[31] has VCC driving its datain port
+ Info: Pin GPIO_0[32] has VCC driving its datain port
+ Info: Pin GPIO_0[33] has VCC driving its datain port
+ Info: Pin GPIO_0[34] has VCC driving its datain port
+ Info: Pin GPIO_0[35] has VCC driving its datain port
+ Info: Pin GPIO_1[0] has VCC driving its datain port
+ Info: Pin GPIO_1[1] has VCC driving its datain port
+ Info: Pin GPIO_1[2] has VCC driving its datain port
+ Info: Pin GPIO_1[3] has VCC driving its datain port
+ Info: Pin GPIO_1[4] has VCC driving its datain port
+ Info: Pin GPIO_1[5] has VCC driving its datain port
+ Info: Pin GPIO_1[6] has VCC driving its datain port
+ Info: Pin GPIO_1[7] has VCC driving its datain port
+ Info: Pin GPIO_1[8] has VCC driving its datain port
+ Info: Pin GPIO_1[9] has VCC driving its datain port
+ Info: Pin GPIO_1[10] has VCC driving its datain port
+ Info: Pin GPIO_1[11] has VCC driving its datain port
+ Info: Pin GPIO_1[12] has VCC driving its datain port
+ Info: Pin GPIO_1[13] has VCC driving its datain port
+ Info: Pin GPIO_1[14] has VCC driving its datain port
+ Info: Pin GPIO_1[15] has VCC driving its datain port
+ Info: Pin GPIO_1[16] has VCC driving its datain port
+ Info: Pin GPIO_1[17] has VCC driving its datain port
+ Info: Pin GPIO_1[18] has VCC driving its datain port
+ Info: Pin GPIO_1[19] has VCC driving its datain port
+ Info: Pin GPIO_1[20] has VCC driving its datain port
+ Info: Pin GPIO_1[21] has VCC driving its datain port
+ Info: Pin GPIO_1[22] has VCC driving its datain port
+ Info: Pin GPIO_1[23] has VCC driving its datain port
+ Info: Pin GPIO_1[24] has VCC driving its datain port
+ Info: Pin GPIO_1[25] has VCC driving its datain port
+ Info: Pin GPIO_1[26] has VCC driving its datain port
+ Info: Pin GPIO_1[27] has VCC driving its datain port
+ Info: Pin GPIO_1[28] has VCC driving its datain port
+ Info: Pin GPIO_1[29] has VCC driving its datain port
+ Info: Pin GPIO_1[30] has VCC driving its datain port
+ Info: Pin GPIO_1[31] has VCC driving its datain port
+ Info: Pin GPIO_1[32] has VCC driving its datain port
+ Info: Pin GPIO_1[33] has VCC driving its datain port
+ Info: Pin GPIO_1[34] has VCC driving its datain port
+ Info: Pin GPIO_1[35] has VCC driving its datain port
+ Info: Pin HEX0[0] has GND driving its datain port
+ Info: Pin HEX0[1] has GND driving its datain port
+ Info: Pin HEX0[2] has GND driving its datain port
+ Info: Pin HEX0[3] has GND driving its datain port
+ Info: Pin HEX0[4] has GND driving its datain port
+ Info: Pin HEX0[5] has GND driving its datain port
+ Info: Pin HEX0[6] has GND driving its datain port
+ Info: Pin HEX1[0] has GND driving its datain port
+ Info: Pin HEX1[1] has GND driving its datain port
+ Info: Pin HEX1[2] has GND driving its datain port
+ Info: Pin HEX1[3] has GND driving its datain port
+ Info: Pin HEX1[4] has GND driving its datain port
+ Info: Pin HEX1[5] has GND driving its datain port
+ Info: Pin HEX1[6] has GND driving its datain port
+ Info: Pin HEX2[0] has GND driving its datain port
+ Info: Pin HEX2[1] has GND driving its datain port
+ Info: Pin HEX2[2] has GND driving its datain port
+ Info: Pin HEX2[3] has GND driving its datain port
+ Info: Pin HEX2[4] has GND driving its datain port
+ Info: Pin HEX2[5] has GND driving its datain port
+ Info: Pin HEX2[6] has GND driving its datain port
+ Info: Pin HEX3[0] has GND driving its datain port
+ Info: Pin HEX3[1] has GND driving its datain port
+ Info: Pin HEX3[2] has GND driving its datain port
+ Info: Pin HEX3[3] has GND driving its datain port
+ Info: Pin HEX3[4] has GND driving its datain port
+ Info: Pin HEX3[5] has GND driving its datain port
+ Info: Pin HEX3[6] has GND driving its datain port
+ Info: Pin LEDG[2] has GND driving its datain port
+ Info: Pin LEDG[3] has GND driving its datain port
+ Info: Pin LEDG[4] has GND driving its datain port
+ Info: Pin LEDG[5] has GND driving its datain port
+ Info: Pin LEDG[6] has GND driving its datain port
+ Info: Pin LEDG[7] has GND driving its datain port
+ Info: Pin LEDR[8] has GND driving its datain port
+ Info: Pin LEDR[9] has GND driving its datain port
+ Info: Pin DRAM_ADDR[0] has GND driving its datain port
+ Info: Pin DRAM_ADDR[1] has GND driving its datain port
+ Info: Pin DRAM_ADDR[2] has GND driving its datain port
+ Info: Pin DRAM_ADDR[3] has GND driving its datain port
+ Info: Pin DRAM_ADDR[4] has GND driving its datain port
+ Info: Pin DRAM_ADDR[5] has GND driving its datain port
+ Info: Pin DRAM_ADDR[6] has GND driving its datain port
+ Info: Pin DRAM_ADDR[7] has GND driving its datain port
+ Info: Pin DRAM_ADDR[8] has GND driving its datain port
+ Info: Pin DRAM_ADDR[9] has GND driving its datain port
+ Info: Pin DRAM_ADDR[10] has GND driving its datain port
+ Info: Pin DRAM_ADDR[11] has GND driving its datain port
+ Info: Pin DRAM_LDQM has GND driving its datain port
+ Info: Pin DRAM_UDQM has GND driving its datain port
+ Info: Pin DRAM_WE_N has VCC driving its datain port
+ Info: Pin DRAM_CAS_N has VCC driving its datain port
+ Info: Pin DRAM_RAS_N has VCC driving its datain port
+ Info: Pin DRAM_CS_N has VCC driving its datain port
+ Info: Pin DRAM_BA_0 has GND driving its datain port
+ Info: Pin DRAM_BA_1 has GND driving its datain port
+ Info: Pin DRAM_CLK has GND driving its datain port
+ Info: Pin DRAM_CKE has GND driving its datain port
+ Info: Pin FL_ADDR[0] has GND driving its datain port
+ Info: Pin FL_ADDR[1] has GND driving its datain port
+ Info: Pin FL_ADDR[2] has GND driving its datain port
+ Info: Pin FL_ADDR[3] has GND driving its datain port
+ Info: Pin FL_ADDR[4] has GND driving its datain port
+ Info: Pin FL_ADDR[5] has GND driving its datain port
+ Info: Pin FL_ADDR[6] has GND driving its datain port
+ Info: Pin FL_ADDR[7] has GND driving its datain port
+ Info: Pin FL_ADDR[8] has GND driving its datain port
+ Info: Pin FL_ADDR[9] has GND driving its datain port
+ Info: Pin FL_ADDR[10] has GND driving its datain port
+ Info: Pin FL_ADDR[11] has GND driving its datain port
+ Info: Pin FL_ADDR[12] has GND driving its datain port
+ Info: Pin FL_ADDR[13] has GND driving its datain port
+ Info: Pin FL_ADDR[14] has GND driving its datain port
+ Info: Pin FL_ADDR[15] has GND driving its datain port
+ Info: Pin FL_ADDR[16] has GND driving its datain port
+ Info: Pin FL_ADDR[17] has GND driving its datain port
+ Info: Pin FL_ADDR[18] has GND driving its datain port
+ Info: Pin FL_ADDR[19] has GND driving its datain port
+ Info: Pin FL_ADDR[20] has GND driving its datain port
+ Info: Pin FL_ADDR[21] has GND driving its datain port
+ Info: Pin FL_WE_N has VCC driving its datain port
+ Info: Pin FL_RST_N has GND driving its datain port
+ Info: Pin FL_OE_N has VCC driving its datain port
+ Info: Pin FL_CE_N has VCC driving its datain port
+ Info: Pin SRAM_ADDR[0] has GND driving its datain port
+ Info: Pin SRAM_ADDR[1] has GND driving its datain port
+ Info: Pin SRAM_ADDR[2] has GND driving its datain port
+ Info: Pin SRAM_ADDR[3] has GND driving its datain port
+ Info: Pin SRAM_ADDR[4] has GND driving its datain port
+ Info: Pin SRAM_ADDR[5] has GND driving its datain port
+ Info: Pin SRAM_ADDR[6] has GND driving its datain port
+ Info: Pin SRAM_ADDR[7] has GND driving its datain port
+ Info: Pin SRAM_ADDR[8] has GND driving its datain port
+ Info: Pin SRAM_ADDR[9] has GND driving its datain port
+ Info: Pin SRAM_ADDR[10] has GND driving its datain port
+ Info: Pin SRAM_ADDR[11] has GND driving its datain port
+ Info: Pin SRAM_ADDR[12] has GND driving its datain port
+ Info: Pin SRAM_ADDR[13] has GND driving its datain port
+ Info: Pin SRAM_ADDR[14] has GND driving its datain port
+ Info: Pin SRAM_ADDR[15] has GND driving its datain port
+ Info: Pin SRAM_ADDR[16] has GND driving its datain port
+ Info: Pin SRAM_ADDR[17] has GND driving its datain port
+ Info: Pin SRAM_UB_N has VCC driving its datain port
+ Info: Pin SRAM_LB_N has GND driving its datain port
+ Info: Pin SRAM_WE_N has GND driving its datain port
+ Info: Pin SRAM_CE_N has GND driving its datain port
+ Info: Pin SRAM_OE_N has GND driving its datain port
+ Info: Pin SD_DAT3 has GND driving its datain port
+ Info: Pin SD_CMD has GND driving its datain port
+ Info: Pin SD_CLK has GND driving its datain port
+ Info: Pin TDO has GND driving its datain port
+ Info: Pin I2C_SCLK has GND driving its datain port
+ Info: Pin VGA_HS has GND driving its datain port
+ Info: Pin VGA_VS has GND driving its datain port
+ Info: Pin VGA_R[0] has GND driving its datain port
+ Info: Pin VGA_R[1] has GND driving its datain port
+ Info: Pin VGA_R[2] has GND driving its datain port
+ Info: Pin VGA_R[3] has GND driving its datain port
+ Info: Pin VGA_G[0] has GND driving its datain port
+ Info: Pin VGA_G[1] has GND driving its datain port
+ Info: Pin VGA_G[2] has GND driving its datain port
+ Info: Pin VGA_G[3] has GND driving its datain port
+ Info: Pin VGA_B[0] has GND driving its datain port
+ Info: Pin VGA_B[1] has GND driving its datain port
+ Info: Pin VGA_B[2] has GND driving its datain port
+ Info: Pin VGA_B[3] has GND driving its datain port
+ Info: Pin AUD_DACDAT has GND driving its datain port
+ Info: Pin AUD_XCK has GND driving its datain port
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Quartus II Fitter was successful. 0 errors, 15 warnings
+ Info: Peak virtual memory: 205 megabytes
+ Info: Processing ended: Sat Jan 16 19:25:57 2010
+ Info: Elapsed time: 00:00:10
+ Info: Total CPU time (on all processors): 00:00:09
+
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.sof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.sof
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.sof (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.sof (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/uart.sof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart.qsf (revision 6)
@@ -0,0 +1,509 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 23:14:30 September 14, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# uart_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY top_uart
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:14:30 SEPTEMBER 14, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_global_assignment -name MISC_FILE "C:/altera/cores/uart/uart.dpf"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity uart -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity uart -section_id "Root Region"
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name VHDL_FILE decoder_7seg.vhd
+set_global_assignment -name VHDL_FILE uart.vhd
+set_global_assignment -name VHDL_FILE clkUnit.vhd
+set_global_assignment -name VHDL_FILE miniUART.vhd
+set_global_assignment -name VHDL_FILE RxUnit.vhd
+set_global_assignment -name VHDL_FILE top_uart.vhd
+set_global_assignment -name VHDL_FILE TxUnit.vhd
+set_global_assignment -name VHDL_FILE uart_lib.vhd
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/uart_assignment_defaults.qdf
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/uart_assignment_defaults.qdf (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/uart_assignment_defaults.qdf (revision 6)
@@ -0,0 +1,642 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 23:43:59 October 11, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus II software and is used
+# to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS Off
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value ON
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
+set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.kpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.kpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.kpt (revision 6)
@@ -0,0 +1,1330 @@
+
+
+
+ U1/RxDev/BitCnt[0]
+
+
+ U1/TxDev/TBuff[7]
+
+ SA0
+
+
+
+ U1/RxDev/tmpRxD
+
+
+ U1/TxDev/TReg[6]
+
+
+ U1/RxDev/ShtReg[0]
+
+
+ U1/TxDev/TBuff[3]
+
+
+ U1/CSReg[0]
+
+ SA0
+
+
+
+ U1/CSReg[4]
+
+ SA1
+
+
+
+ U1/RxDev/ShtReg[4]
+
+
+ U1/ClkDiv/DivClk10:Cnt10[3]
+
+
+ U1/TxDev/TxD
+
+
+ U1/RxDev/Start
+
+
+ U1/TxDev/TReg[1]
+
+
+ U1/RxDev/DOut[4]
+
+
+ U1/TxDev/BitCnt[2]
+
+
+ U1/RxDev/SampleCnt[1]
+
+
+ U1/TxDev/tmpTBufE
+
+
+ U1/ClkDiv/DivClk26:Cnt26[3]
+
+
+ U1/RxDev/outErr
+
+
+ U1/TxDev/tmpTRegE
+
+
+ U1/TxDev/TBuff[6]
+
+
+ U1/TxDev/TReg[5]
+
+
+ U1/RxDev/BitCnt[3]
+
+
+ U1/RxDev/ShtReg[7]
+
+
+ U1/IntTx_N
+
+
+ U1/CSReg[7]
+
+ SA1
+
+
+
+ U1/CSReg[3]
+
+
+ U1/TxDev/TBuff[2]
+
+ SA0
+
+
+
+ U1/ClkDiv/DivClk10:Cnt10[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[0]
+
+
+ U1/RxDev/ShtReg[3]
+
+
+ U1/ClkDiv/tmpEnRX
+
+
+ U1/RxDev/DOut[0]
+
+
+ U1/IntRx_N
+
+
+ U1/TxDev/TReg[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[3]
+
+
+ U1/TxDev/BitCnt[3]
+
+
+ U1/RxDev/SampleCnt[2]
+
+
+ U1/RxDev/DOut[3]
+
+
+ U1/ClkDiv/ClkDiv26
+
+
+ U1/ClkDiv/DivClk26:Cnt26[0]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[4]
+
+
+ U1/RxDev/tmpDRdy
+
+
+ U1/RxDev/DOut[7]
+
+
+ U1/RxDev/BitCnt[2]
+
+
+ U1/RxDev/ShtReg[6]
+
+
+ U1/TxDev/TReg[4]
+
+
+ U1/RxDev/frameErr
+
+
+ U1/CSReg[6]
+
+ SA1
+
+
+
+ U1/TxDev/TBuff[5]
+
+
+ U1/CSReg[2]
+
+
+ U1/TxDev/TReg[7]
+
+
+ U1/ClkDiv/DivClk10:Cnt10[1]
+
+
+ U1/RxDev/ShtReg[2]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[1]
+
+
+ U1/TxDev/TBuff[1]
+
+ SA0
+
+
+
+ U1/ClkDiv/DivClk26:Cnt26[5]
+
+
+ U1/RxDev/DOut[1]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[4]
+
+
+ U1/TxDev/BitCnt[0]
+
+
+ U1/RxDev/DOut[6]
+
+
+ U1/RxDev/DOut[2]
+
+
+ U1/RxDev/SampleCnt[3]
+
+
+ U1/RxDev/BitCnt[1]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[1]
+
+
+ U1/RxDev/ShtReg[5]
+
+
+ U1/TxDev/TReg[3]
+
+
+ U1/ClkDiv/tmpEnTX
+
+
+ U1/TxDev/TBuff[4]
+
+ SA0
+
+
+
+ U1/CSReg[5]
+
+ SA1
+
+
+
+ U1/ClkDiv/DivClk10:Cnt10[2]
+
+
+ U1/CSReg[1]
+
+ SA0
+
+
+
+ U1/RxDev/ShtReg[1]
+
+
+ U1/TxDev/TBuff[0]
+
+
+ U1/ClkDiv/DivClk16:Cnt16[2]
+
+
+ U1/TxDev/TReg[2]
+
+
+ U1/TxDev/BitCnt[1]
+
+
+ U1/RxDev/DOut[5]
+
+
+ U1/RxDev/SampleCnt[0]
+
+
+ U1/ClkDiv/DivClk26:Cnt26[2]
+
+
+
+
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[2]
+
+
+ miniUART:U1|RxUnit:RxDev|outErr
+
+
+ miniUART:U1|CSReg[2]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[5]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[5]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[2]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[0]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[3]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[3]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[1]
+
+
+ miniUART:U1|TxUnit:TxDev|tmpTBufE
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[0]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[2]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[2]
+
+
+ miniUART:U1|IntRx_N
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[4]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[3]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[5]
+
+
+ miniUART:U1|TxUnit:TxDev|tmpTRegE
+
+
+ miniUART:U1|RxUnit:RxDev|frameErr
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[6]
+
+
+ miniUART:U1|IntTx_N
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[4]
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[0]
+
+
+ miniUART:U1|RxUnit:RxDev|tmpDRdy
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[1]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[0]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[3]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[7]
+
+
+ miniUART:U1|RxUnit:RxDev|tmpRxD
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[2]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[0]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|ClkDiv26
+
+
+ miniUART:U1|TxUnit:TxDev|TxD
+
+
+ miniUART:U1|ClkUnit:ClkDiv|tmpEnTX
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[1]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[6]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[7]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[5]
+
+
+ miniUART:U1|RxUnit:RxDev|SampleCnt[3]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[0]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[7]
+
+
+ miniUART:U1|CSReg[3]
+
+
+ miniUART:U1|TxUnit:TxDev|TBuff[6]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[3]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[6]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[2]
+
+
+ miniUART:U1|RxUnit:RxDev|DOut[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk10:Cnt10[3]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[1]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|tmpEnRX
+
+
+ miniUART:U1|RxUnit:RxDev|Start
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk26:Cnt26[4]
+
+
+ miniUART:U1|ClkUnit:ClkDiv|\DivClk16:Cnt16[4]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[3]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[1]
+
+
+ miniUART:U1|TxUnit:TxDev|BitCnt[2]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[0]
+
+
+ miniUART:U1|RxUnit:RxDev|BitCnt[0]
+
+
+ miniUART:U1|TxUnit:TxDev|TReg[5]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[1]
+
+
+ miniUART:U1|RxUnit:RxDev|ShtReg[4]
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt (revision 6)
@@ -0,0 +1,10 @@
+
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Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.atm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.atm
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.atm (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.atm (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.atm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb (revision 6)
@@ -0,0 +1 @@
+v1
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi (revision 6)
z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/README
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/README (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/incremental_db/README (revision 6)
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd.bak
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd.bak (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd.bak (revision 6)
@@ -0,0 +1,181 @@
+-------------------------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity TOP_UART is
+ port(
+
+ -- Clocks
+ CLOCK_27, -- 27 MHz
+ CLOCK_50, -- 50 MHz
+ EXT_CLOCK : in std_logic; -- External Clock
+
+ -- Buttons and switches
+ KEY : in std_logic_vector(3 downto 0); -- Push buttons
+ SW : in std_logic_vector(9 downto 0); -- Switches
+
+ -- LED displays
+ HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
+ : out std_logic_vector(6 downto 0);
+ LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
+ LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
+
+ -- RS-232 interface
+ UART_TXD : out std_logic; -- UART transmitter
+ UART_RXD : in std_logic; -- UART receiver
+
+ -- IRDA interface
+
+ -- IRDA_TXD : out std_logic; -- IRDA Transmitter
+ IRDA_RXD : in std_logic; -- IRDA Receiver
+
+ -- SDRAM
+ DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
+ DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
+ DRAM_LDQM, -- Low-byte Data Mask
+ DRAM_UDQM, -- High-byte Data Mask
+ DRAM_WE_N, -- Write Enable
+ DRAM_CAS_N, -- Column Address Strobe
+ DRAM_RAS_N, -- Row Address Strobe
+ DRAM_CS_N, -- Chip Select
+ DRAM_BA_0, -- Bank Address 0
+ DRAM_BA_1, -- Bank Address 0
+ DRAM_CLK, -- Clock
+ DRAM_CKE : out std_logic; -- Clock Enable
+
+ -- FLASH
+ FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
+ FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
+ FL_WE_N, -- Write Enable
+ FL_RST_N, -- Reset
+ FL_OE_N, -- Output Enable
+ FL_CE_N : out std_logic; -- Chip Enable
+
+ -- SRAM
+ SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
+ SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
+ SRAM_UB_N, -- High-byte Data Mask
+ SRAM_LB_N, -- Low-byte Data Mask
+ SRAM_WE_N, -- Write Enable
+ SRAM_CE_N, -- Chip Enable
+ SRAM_OE_N : out std_logic; -- Output Enable
+
+ -- SD card interface
+ SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
+ SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
+ SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
+ SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
+
+ -- USB JTAG link
+ TDI, -- CPLD -> FPGA (data in)
+ TCK, -- CPLD -> FPGA (clk)
+ TCS : in std_logic; -- CPLD -> FPGA (CS)
+ TDO : out std_logic; -- FPGA -> CPLD (data out)
+
+ -- I2C bus
+ I2C_SDAT : inout std_logic; -- I2C Data
+ I2C_SCLK : out std_logic; -- I2C Clock
+
+ -- PS/2 port
+ PS2_DAT, -- Data
+ PS2_CLK : inout std_logic; -- Clock
+
+ -- VGA output
+ VGA_HS, -- H_SYNC
+ VGA_VS : out std_logic; -- SYNC
+ VGA_R, -- Red[3:0]
+ VGA_G, -- Green[3:0]
+ VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
+
+ -- Audio CODEC
+ AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
+ AUD_ADCDAT : in std_logic; -- ADC Data
+ AUD_DACLRCK : inout std_logic; -- DAC LR Clock
+ AUD_DACDAT : out std_logic; -- DAC Data
+ AUD_BCLK : inout std_logic; -- Bit-Stream Clock
+ AUD_XCK : out std_logic; -- Chip Clock
+
+ -- General-purpose I/O
+ GPIO_0, -- GPIO Connection 0
+ GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
+);
+end TOP_UART;
+
+architecture rtl of TOP_UART is
+
+ component miniUART
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+ end component;
+
+begin
+
+ U1 : miniUART PORT MAP (
+ SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
+ Reset => KEY(0), --: in Std_Logic; -- Reset input
+ CS_N => SW(0), --: in Std_Logic;
+ RD_N => SW(1), --: in Std_Logic;
+ WR_N => SW(2), --: in Std_Logic;
+ RxD => UART_RXD, --: in Std_Logic;
+ TxD => UART_TXD, --: out Std_Logic;
+ IntRx_N => LEDG(0), --: out Std_Logic; -- Receive interrupt
+ IntTx_N => LEDG(1), --: out Std_Logic; -- Transmit interrupt
+ Addr => SW(8 downto 7), --: in Std_Logic_Vector(1 downto 0); --
+ DataIn => x"69", --: in Std_Logic_Vector(7 downto 0); --
+ DataOut => LEDR(7 downto 0)--: out Std_Logic_Vector(7 downto 0)); --
+ );
+
+ --
+ SRAM_DQ(15 downto 8) <= (others => 'Z');
+ SRAM_ADDR(17 downto 16) <= "00";
+ SRAM_UB_N <= '1';
+ SRAM_LB_N <= '0';
+ SRAM_CE_N <= '0';
+ --
+ UART_TXD <= 'Z';
+ DRAM_ADDR <= (others => '0');
+ DRAM_LDQM <= '0';
+ DRAM_UDQM <= '0';
+ DRAM_WE_N <= '1';
+ DRAM_CAS_N <= '1';
+ DRAM_RAS_N <= '1';
+ DRAM_CS_N <= '1';
+ DRAM_BA_0 <= '0';
+ DRAM_BA_1 <= '0';
+ DRAM_CLK <= '0';
+ DRAM_CKE <= '0';
+ FL_ADDR <= (others => '0');
+ FL_WE_N <= '1';
+ FL_RST_N <= '0';
+ FL_OE_N <= '1';
+ FL_CE_N <= '1';
+ TDO <= '0';
+ I2C_SCLK <= '0';
+ AUD_DACDAT <= '0';
+ AUD_XCK <= '0';
+ -- Set all bidirectional ports to tri-state
+ DRAM_DQ <= (others => 'Z');
+ FL_DQ <= (others => 'Z');
+ I2C_SDAT <= 'Z';
+ AUD_ADCLRCK <= 'Z';
+ AUD_DACLRCK <= 'Z';
+ AUD_BCLK <= 'Z';
+ GPIO_0 <= (others => 'Z');
+ GPIO_1 <= (others => 'Z');
+end;
\ No newline at end of file
Index: z80control/trunk/DE1/rtl/VHDL/uart/decoder_7seg.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/decoder_7seg.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/decoder_7seg.vhd (revision 6)
@@ -0,0 +1,40 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+USE IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity decoder_7seg is
+ port
+ (
+ NUMBER : in std_logic_vector(3 downto 0);
+ HEX_DISP : out std_logic_vector(6 downto 0)
+ );
+end decoder_7seg;
+
+architecture rtl of decoder_7seg is
+begin
+process(NUMBER)
+begin
+ case NUMBER is
+ --0 to 9
+ when "0000" => HEX_DISP <= "1000000";
+ when "0001" => HEX_DISP <= "1111001";
+ when "0010" => HEX_DISP <= "0100100";
+ when "0011" => HEX_DISP <= "0110000";
+ when "0100" => HEX_DISP <= "0011001";
+ when "0101" => HEX_DISP <= "0010010";
+ when "0110" => HEX_DISP <= "0000011";
+ when "0111" => HEX_DISP <= "1111000";
+ when "1000" => HEX_DISP <= "0000000";
+ when "1001" => HEX_DISP <= "0011000";
+ -- A to F
+ when "1010" => HEX_DISP <= "0001000";
+ when "1011" => HEX_DISP <= "0000011";
+ when "1100" => HEX_DISP <= "1000110";
+ when "1101" => HEX_DISP <= "0100001";
+ when "1110" => HEX_DISP <= "0000110";
+ when "1111" => HEX_DISP <= "0001110";
+ when others => HEX_DISP <= "1111111";
+ end case;
+end process;
+end rtl;
+
Index: z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd
===================================================================
--- z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd (nonexistent)
+++ z80control/trunk/DE1/rtl/VHDL/uart/top_uart.vhd (revision 6)
@@ -0,0 +1,181 @@
+-------------------------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity TOP_UART is
+ port(
+
+ -- Clocks
+ CLOCK_27, -- 27 MHz
+ CLOCK_50, -- 50 MHz
+ EXT_CLOCK : in std_logic; -- External Clock
+
+ -- Buttons and switches
+ KEY : in std_logic_vector(3 downto 0); -- Push buttons
+ SW : in std_logic_vector(9 downto 0); -- Switches
+
+ -- LED displays
+ HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
+ : out std_logic_vector(6 downto 0);
+ LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
+ LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
+
+ -- RS-232 interface
+ UART_TXD : out std_logic; -- UART transmitter
+ UART_RXD : in std_logic; -- UART receiver
+
+ -- IRDA interface
+
+ -- IRDA_TXD : out std_logic; -- IRDA Transmitter
+ IRDA_RXD : in std_logic; -- IRDA Receiver
+
+ -- SDRAM
+ DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
+ DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
+ DRAM_LDQM, -- Low-byte Data Mask
+ DRAM_UDQM, -- High-byte Data Mask
+ DRAM_WE_N, -- Write Enable
+ DRAM_CAS_N, -- Column Address Strobe
+ DRAM_RAS_N, -- Row Address Strobe
+ DRAM_CS_N, -- Chip Select
+ DRAM_BA_0, -- Bank Address 0
+ DRAM_BA_1, -- Bank Address 0
+ DRAM_CLK, -- Clock
+ DRAM_CKE : out std_logic; -- Clock Enable
+
+ -- FLASH
+ FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
+ FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
+ FL_WE_N, -- Write Enable
+ FL_RST_N, -- Reset
+ FL_OE_N, -- Output Enable
+ FL_CE_N : out std_logic; -- Chip Enable
+
+ -- SRAM
+ SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
+ SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
+ SRAM_UB_N, -- High-byte Data Mask
+ SRAM_LB_N, -- Low-byte Data Mask
+ SRAM_WE_N, -- Write Enable
+ SRAM_CE_N, -- Chip Enable
+ SRAM_OE_N : out std_logic; -- Output Enable
+
+ -- SD card interface
+ SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
+ SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
+ SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
+ SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
+
+ -- USB JTAG link
+ TDI, -- CPLD -> FPGA (data in)
+ TCK, -- CPLD -> FPGA (clk)
+ TCS : in std_logic; -- CPLD -> FPGA (CS)
+ TDO : out std_logic; -- FPGA -> CPLD (data out)
+
+ -- I2C bus
+ I2C_SDAT : inout std_logic; -- I2C Data
+ I2C_SCLK : out std_logic; -- I2C Clock
+
+ -- PS/2 port
+ PS2_DAT, -- Data
+ PS2_CLK : inout std_logic; -- Clock
+
+ -- VGA output
+ VGA_HS, -- H_SYNC
+ VGA_VS : out std_logic; -- SYNC
+ VGA_R, -- Red[3:0]
+ VGA_G, -- Green[3:0]
+ VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
+
+ -- Audio CODEC
+ AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
+ AUD_ADCDAT : in std_logic; -- ADC Data
+ AUD_DACLRCK : inout std_logic; -- DAC LR Clock
+ AUD_DACDAT : out std_logic; -- DAC Data
+ AUD_BCLK : inout std_logic; -- Bit-Stream Clock
+ AUD_XCK : out std_logic; -- Chip Clock
+
+ -- General-purpose I/O
+ GPIO_0, -- GPIO Connection 0
+ GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
+);
+end TOP_UART;
+
+architecture rtl of TOP_UART is
+
+ component miniUART
+ port (
+ SysClk : in Std_Logic; -- System Clock
+ Reset : in Std_Logic; -- Reset input
+ CS_N : in Std_Logic;
+ RD_N : in Std_Logic;
+ WR_N : in Std_Logic;
+ RxD : in Std_Logic;
+ TxD : out Std_Logic;
+ IntRx_N : out Std_Logic; -- Receive interrupt
+ IntTx_N : out Std_Logic; -- Transmit interrupt
+ Addr : in Std_Logic_Vector(1 downto 0); --
+ DataIn : in Std_Logic_Vector(7 downto 0); --
+ DataOut : out Std_Logic_Vector(7 downto 0)); --
+ end component;
+
+begin
+
+ U1 : miniUART PORT MAP (
+ SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
+ Reset => KEY(0), --: in Std_Logic; -- Reset input
+ CS_N => SW(0), --: in Std_Logic;
+ RD_N => SW(1), --: in Std_Logic;
+ WR_N => SW(2), --: in Std_Logic;
+ RxD => UART_RXD, --: in Std_Logic;
+ TxD => UART_TXD, --: out Std_Logic;
+ IntRx_N => LEDG(0), --: out Std_Logic; -- Receive interrupt
+ IntTx_N => LEDG(1), --: out Std_Logic; -- Transmit interrupt
+ Addr => SW(8 downto 7), --: in Std_Logic_Vector(1 downto 0); --
+ DataIn => x"69", --: in Std_Logic_Vector(7 downto 0); --
+ DataOut => LEDR(7 downto 0)--: out Std_Logic_Vector(7 downto 0)); --
+ );
+
+ --
+ SRAM_DQ(15 downto 8) <= (others => 'Z');
+ SRAM_ADDR(17 downto 16) <= "00";
+ SRAM_UB_N <= '1';
+ SRAM_LB_N <= '0';
+ SRAM_CE_N <= '0';
+ --
+ UART_TXD <= 'Z';
+ DRAM_ADDR <= (others => '0');
+ DRAM_LDQM <= '0';
+ DRAM_UDQM <= '0';
+ DRAM_WE_N <= '1';
+ DRAM_CAS_N <= '1';
+ DRAM_RAS_N <= '1';
+ DRAM_CS_N <= '1';
+ DRAM_BA_0 <= '0';
+ DRAM_BA_1 <= '0';
+ DRAM_CLK <= '0';
+ DRAM_CKE <= '0';
+ FL_ADDR <= (others => '0');
+ FL_WE_N <= '1';
+ FL_RST_N <= '0';
+ FL_OE_N <= '1';
+ FL_CE_N <= '1';
+ TDO <= '0';
+ I2C_SCLK <= '0';
+ AUD_DACDAT <= '0';
+ AUD_XCK <= '0';
+ -- Set all bidirectional ports to tri-state
+ DRAM_DQ <= (others => 'Z');
+ FL_DQ <= (others => 'Z');
+ I2C_SDAT <= 'Z';
+ AUD_ADCLRCK <= 'Z';
+ AUD_DACLRCK <= 'Z';
+ AUD_BCLK <= 'Z';
+ GPIO_0 <= (others => 'Z');
+ GPIO_1 <= (others => 'Z');
+end;
\ No newline at end of file
Index: z80control/trunk/DE1/z80soc.qpf
===================================================================
--- z80control/trunk/DE1/z80soc.qpf (nonexistent)
+++ z80control/trunk/DE1/z80soc.qpf (revision 6)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "15:51:10 May 01, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "z80soc"
Index: z80control/trunk/DE1/z80soc.sof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/z80soc.sof
===================================================================
--- z80control/trunk/DE1/z80soc.sof (nonexistent)
+++ z80control/trunk/DE1/z80soc.sof (revision 6)
z80control/trunk/DE1/z80soc.sof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/ROM/Z80TEST.PRN
===================================================================
--- z80control/trunk/DE1/ROM/Z80TEST.PRN (nonexistent)
+++ z80control/trunk/DE1/ROM/Z80TEST.PRN (revision 6)
@@ -0,0 +1,170 @@
+ ;
+ MACLIB Z80
+ ;
+ 0000 ORG 0
+ ;
+ 0000 C37200 START JMP STARTU
+ ;
+ 0003 FF DB 0FFH
+ 0004 AA00 DW (CHPEND-4)
+ 0006 8C0C DW 3212
+ ;
+ 0008 01 CHIP1ID DB 1 ;CHIP I.D. NUMBER
+ ;
+ 0009 00 NOP
+ 000A 00 NOP
+ 000B 00 NOP
+ 000C 00 NOP
+ 000D 00 NOP
+ 000E 00 NOP
+ 000F 00 NOP
+ 0010 00 NOP
+ 0011 00 NOP
+ 0012 00 NOP
+ 0013 00 NOP
+ 0014 00 NOP
+ 0015 00 NOP
+ 0016 00 NOP
+ 0017 00 NOP
+ 0018 00 NOP
+ 0019 00 NOP
+ 001A 00 NOP
+ 001B 00 NOP
+ 001C 00 NOP
+ 001D 00 NOP
+ 001E 00 NOP
+ 001F 00 NOP
+ 0020 00 NOP
+ 0021 00 NOP
+ 0022 00 NOP
+ 0023 00 NOP
+ 0024 00 NOP
+ 0025 C37200 JMP SFTSTART0
+ ;
+ ;
+ 0028 00 NOP
+ 0029 00 NOP
+ 002A 00 NOP
+ 002B 00 NOP
+ 002C 00 NOP
+ 002D 00 NOP
+ 002E 00 NOP
+ 002F 00 NOP
+ 0030 00 NOP
+ 0031 00 NOP
+ 0032 00 NOP
+ 0033 00 NOP
+ 0034 00 NOP
+ 0035 00 NOP
+ 0036 00 NOP
+ 0037 00 NOP
+ 0038 00 NOP
+ 0039 00 NOP
+ 003A 00 NOP
+ 003B 00 NOP
+ 003C 00 NOP
+ 003D C37200 JMP SFTSTART2
+ ;
+ ;
+ 0040 00 NOP
+ 0041 00 NOP
+ 0042 00 NOP
+ 0043 00 NOP
+ 0044 00 NOP
+ 0045 00 NOP
+ 0046 00 NOP
+ 0047 00 NOP
+ 0048 00 NOP
+ 0049 00 NOP
+ 004A 00 NOP
+ 004B 00 NOP
+ IBMVECT
+ 004C 9A00 DW COMMAIN ;WAS CRTINP ;ARECEIVE
+ ;
+ ;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ ;
+ ; NON MASKABLE INT.
+ ;
+ 0066 ORG 66H ;TRAP
+ ;
+ 0066 C39000 JMP POWERF
+ ;
+ ;******************************
+ ;
+ 0072 ORG 72H
+ ;
+
+ SFTSTART0
+ SFTSTART2
+ ;
+ ; POWER UP START UP
+ ;
+ ; @ @ @ USED TO TEST COMM @ @ @
+ ;
+ STARTU
+ 0072 F3 DI
+
+ 0073 31EADF LXI SP,0DFEAH
+
+ IM2 ; SET Z80 INT MODE
+ 0076+ED5E DB 0EDH,5EH ;
+
+ 0078 010000 LXI B,0
+ MAINLOOP
+ 007B FB EI
+
+ 007C CDA000 CALL DELAY
+ 007F CDA000 CALL DELAY
+ 0082 CDA000 CALL DELAY
+
+
+ 0085 79 MOV A,C
+ 0086 0C INR C
+
+ 0087 D310 OUT 10H ; HEX DISPLAY 0,1
+
+ 0089 D324 OUT 024H ; COMPORT
+
+ 008B D302 OUT 002H ; LEDR
+
+ 008D C37B00 JMP MAINLOOP
+
+ ;
+ ;
+ 0090 F5 POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
+ 0091 C5 PUSH B ;+2
+ 0092 D5 PUSH D ;+3
+ 0093 E5 PUSH H ;+4
+ ;
+ 0094 E1 POP H
+ 0095 D1 POP D
+ 0096 C1 POP B
+ 0097 F1 POP PSW
+ RETN
+ 0098+ED45 DB 0EDH,45H ;RETN
+ ;
+
+
+ ;4CH
+ COMMAIN
+ 009A DB24 IN 24H ; COMMPORT
+ 009C D311 OUT 11H ; HEX DISPLAY
+ 009E FB EI
+ 009F C9 RET
+
+
+
+ 00A0 C5 DELAY PUSH B
+ 00A1 010040 LXI B,4000H
+ DELLOP
+ 00A4 0D DCR C
+ 00A5 C2A400 JNZ DELLOP
+ 00A8 05 DCR B
+ 00A9 C2A400 JNZ DELLOP
+ 00AC C1 POP B
+ 00AD C9 RET
+
+ 00AE FFFF CHPEND DW 0FFFFH
+ ;
+ 00B0 END START
+
\ No newline at end of file
Index: z80control/trunk/DE1/ROM/Z80TEST.ASM
===================================================================
--- z80control/trunk/DE1/ROM/Z80TEST.ASM (nonexistent)
+++ z80control/trunk/DE1/ROM/Z80TEST.ASM (revision 6)
@@ -0,0 +1,167 @@
+;
+MACLIB Z80
+;
+ ORG 0
+;
+START JMP STARTU
+ ;
+ DB 0FFH
+ DW (CHPEND-4)
+ DW 3212
+;
+CHIP1ID DB 1 ;CHIP I.D. NUMBER
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ JMP SFTSTART0
+;
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ JMP SFTSTART2
+;
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+IBMVECT
+ DW COMMAIN ;WAS CRTINP ;ARECEIVE
+;
+;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+;
+; NON MASKABLE INT.
+;
+ ORG 66H ;TRAP
+;
+ JMP POWERF
+;
+;******************************
+;
+ ORG 72H
+;
+
+SFTSTART0
+SFTSTART2
+;
+; POWER UP START UP
+;
+; @ @ @ USED TO TEST COMM @ @ @
+;
+STARTU
+ DI
+
+ LXI SP,0DFEAH
+
+ IM2 ; SET Z80 INT MODE
+
+ LXI B,0
+MAINLOOP
+ EI
+
+ CALL DELAY
+ CALL DELAY
+ CALL DELAY
+
+
+ MOV A,C
+ INR C
+
+ OUT 10H ; HEX DISPLAY 0,1
+
+ OUT 024H ; COMPORT
+
+ OUT 002H ; LEDR
+
+ JMP MAINLOOP
+
+;
+;
+POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
+ PUSH B ;+2
+ PUSH D ;+3
+ PUSH H ;+4
+;
+ POP H
+ POP D
+ POP B
+ POP PSW
+ RETN
+;
+
+
+;4CH
+COMMAIN
+ IN 24H ; COMMPORT
+ OUT 11H ; HEX DISPLAY
+ EI
+ RET
+
+
+
+DELAY PUSH B
+ LXI B,4000H
+DELLOP
+ DCR C
+ JNZ DELLOP
+ DCR B
+ JNZ DELLOP
+ POP B
+ RET
+
+CHPEND DW 0FFFFH
+;
+ END START
Index: z80control/trunk/DE1/ROM/Z80TEST.HEX
===================================================================
--- z80control/trunk/DE1/ROM/Z80TEST.HEX (nonexistent)
+++ z80control/trunk/DE1/ROM/Z80TEST.HEX (revision 6)
@@ -0,0 +1,12 @@
+:10000000C37200FFAA008C0C010000000000000079
+:1000100000000000000000000000000000000000E0
+:100020000000000000C3720000000000000000009B
+:1000300000000000000000000000000000C372008B
+:0E0040000000000000000000000000009A0018
+:03006600C3900044
+:10007200F331EADFED5E010000FBCDA000CDA00070
+:10008200CDA000790CD310D324D302C37B00F5C5D5
+:10009200D5E5E1D1C1F1ED45DB24D311FBC9C501A1
+:0E00A20000400DC2A40005C2A400C1C9FFFFAA
+:0000000000
+
\ No newline at end of file
Index: z80control/trunk/DE1/ROM/dostools/imac.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/ROM/dostools/imac.exe
===================================================================
--- z80control/trunk/DE1/ROM/dostools/imac.exe (nonexistent)
+++ z80control/trunk/DE1/ROM/dostools/imac.exe (revision 6)
z80control/trunk/DE1/ROM/dostools/imac.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/ROM/dostools/m.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/ROM/dostools/m.exe
===================================================================
--- z80control/trunk/DE1/ROM/dostools/m.exe (nonexistent)
+++ z80control/trunk/DE1/ROM/dostools/m.exe (revision 6)
z80control/trunk/DE1/ROM/dostools/m.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/ROM/dostools/tools.ini
===================================================================
--- z80control/trunk/DE1/ROM/dostools/tools.ini (nonexistent)
+++ z80control/trunk/DE1/ROM/dostools/tools.ini (revision 6)
@@ -0,0 +1,156 @@
+; TOOLS.INI file for QUICK configuration
+
+[M]
+Arg:Alt+A
+Assign:Alt+=
+Backtab:Shift+Tab
+Begline:Home
+Cancel:Esc
+Cdelete:Ctrl+G
+Compile:Shift+F3
+Copy:Ctrl+Ins
+Down:Down
+Down:Ctrl+X
+Emacscdel:Bksp
+Emacsnewl:Enter
+Endline:End
+Execute:f10
+Exit:Alt+X
+exit:f10
+Help:F1
+Home:Ctrl+Home
+Information:Shift+F1
+Initialize:Alt+F10
+Insertmode:Ins
+Insertmode:Ctrl+V
+Lasttext:Alt+L
+Ldelete:Ctrl+Y
+Left:Left
+Linsert:Ctrl+N
+Mark:Alt+M
+Meta:F9
+Mlines:Ctrl+W
+Mpage:Pgup
+Mpage:Ctrl+R
+Mpara:Ctrl+Pgup
+Msearch:F4
+Mword:Ctrl+Left
+Paste:Shift+Ins
+Pbal:Ctrl+[
+Plines:Ctrl+Z
+Ppage:Pgdn
+Ppage:Ctrl+C
+Ppara:Ctrl+Pgdn
+Psearch:F3
+Pword:Ctrl+Right
+Pword:Ctrl+F
+Qreplace:Alt+F3
+Quote:Alt+Q
+Refresh:Alt+R
+Replace:Ctrl+L
+Right:Right
+Right:Ctrl+D
+Sdelete:Del
+Setfile:F2
+Setwindow:Ctrl+]
+Shell:Shift+F9
+Sinsert:Alt+Ins
+Tab:Tab
+Undo:Alt+Bksp
+Up:Up
+Up:Ctrl+E
+Window:F6
+;
+; to load the wordstar extension to enable ctrl+QS and ctrl+QD
+; remove the semicolon from the following line and fill in the correct
+; path
+; load:ws.zxt
+Tabstops:10
+Fgcolor:17
+Rmargin:80
+Vscroll:1
+Hscroll:1
+Hike:1
+Backup:bak
+
+donot:=META CURDAY " " CURDATE " " CURTIME
+donot:f5
+
+Curtime:Alt+T
+
+DTATE:=META CURDAY " " CURDATE " " CURTIME
+DTATE:ALT+D
+
+
+ONEDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
+ONEDEL:CTRL+O
+
+BACKDEL:=META CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE
+BACKDEL:CTRL+B
+
+COP2LIN:= DOWN Ldelete Ldelete Ldelete Ldelete
+COP2LIN:ALT+Y
+
+COPYADR:=ARG RIGHT RIGHT RIGHT RIGHT RIGHT SDELETE
+COPYADR:ALT+C
+
+MOVADR:=COPYADR RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT DOWN LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT
+MOVADR:ALT+V
+
+SSWLB2:=DOWN LEFT LEFT LEFT LEFT " "
+SSWLB2:ALT+S
+
+SSWDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
+SSWDEL:ALT+W
+
+ISWDEL:=DOWN META BEGLINE ";"
+ISWDEL:ALT+N
+
+SLDD:=DOWN BEGLINE " "
+SLDD:ALT+U
+
+
+PLACE00:=META "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT
+PLACE00:ALT+`
+
+PLACE1:=META "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT
+PLACE1:ALT+1
+
+PLACE2:=META "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT
+PLACE2:ALT+2
+
+PLACE3:=META "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT
+PLACE3:ALT+3
+
+PLACE4:=META "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT
+PLACE4:ALT+4
+
+PLACE5:=META "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT
+PLACE5:ALT+5
+
+PLACE6:=META "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT
+PLACE6:ALT+6
+
+PLACE7:=META "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT
+PLACE7:ALT+7
+
+PLACE8:=META "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT
+PLACE8:ALT+8
+
+PLACE9:=META "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT
+PLACE9:ALT+9
+
+PLACE0:=META "0" DOWN LEFT "1" DOWN LEFT "2" DOWN LEFT "3" DOWN LEFT "4" DOWN LEFT "5" DOWN LEFT "6" DOWN LEFT "7" DOWN LEFT "8" DOWN LEFT "9" DOWN LEFT
+PLACE0:ALT+0
+;
+PCHEK:=META PPAGE SETFILE PPAGE
+PCHEK:ALT+G
+;
+CHWIN:=META SETFILE
+CHWIN:ALT+F
+;
+MOVAD:=BEGLINE ARG TAB SDELETE DOWN TAB "EQU " PASTE DOWN
+MOVAD:ALT+J
+;
+DOIT:=ARG TAB TAB TAB RIGHT RIGHT SDELETE BEGLINE DOWN DOWN
+DOIT:CTRL+P
Index: z80control/trunk/DE1/ROM/z80.lib
===================================================================
--- z80control/trunk/DE1/ROM/z80.lib (nonexistent)
+++ z80control/trunk/DE1/ROM/z80.lib (revision 6)
@@ -0,0 +1,475 @@
+; @CHK MACRO USED FOR CHECKING 8 BIT DISPLACMENTS
+;
+@CHK MACRO ?DD ; USED FOR CHECKING RANGE OF 8-BIT DISP.S
+ IF (?DD GT 7FH) AND (?DD LT 0FF80H)
+ 'DISPLACEMENT RANGE ERROR - Z80 LIB'
+ ENDIF
+ ENDM
+LDX MACRO ?R,?D
+ @CHK ?D
+ DB 0DDH,?R*8+46H,?D ;LDX
+ ENDM
+LDY MACRO ?R,?D
+ @CHK ?D
+ DB 0FDH,?R*8+46H,?D ;LDY
+ ENDM
+STX MACRO ?R,?D
+ @CHK ?D
+ DB 0DDH,70H+?R,?D ;STX
+ ENDM
+STY MACRO ?R,?D
+ @CHK ?D
+ DB 0FDH,70H+?R,?D ;STY
+ ENDM
+;
+;MVIX MACRO ?N,?D
+; @CHK ?D
+; DB 0DDH,36H,?D,?N ;MVIX
+; ENDM
+;MVIY MACRO ?N,?D
+; @CHK ?D
+; DB 0FDH,36H,?D,?N ;MVIY
+; ENDM
+
+LDAI MACRO
+ DB 0EDH,57H ;LDAI
+ ENDM
+LDAR MACRO
+ DB 0EDH,5FH ;LDAR
+ ENDM
+STAI MACRO
+ DB 0EDH,47H ;STAI
+ ENDM
+STAR MACRO
+ DB 0EDH,4FH ;STAR
+ ENDM
+
+LXIX MACRO ?NNNN
+ DB 0DDH,21H ;LXIX
+ DW ?NNNN
+ ENDM
+LXIY MACRO ?NNNN
+ DB 0FDH,21H ;LXIY
+ DW ?NNNN
+ ENDM
+LDED MACRO ?NNNN
+ DB 0EDH,5BH ;LDED
+ DW ?NNNN
+ ENDM
+LBCD MACRO ?NNNN
+ DB 0EDH,4BH ;LBCD
+ DW ?NNNN
+ ENDM
+;
+;LSPD MACRO ?NNNN
+; DB 0EDH,07BH ;LSPD
+; DW ?NNNN
+; ENDM
+;LIXD MACRO ?NNNN
+; DB 0DDH,2AH ;LIXD
+; DW ?NNNN
+; ENDM
+;
+;LIYD MACRO ?NNNN
+; DB 0FDH,2AH ;LIYD
+; DW ?NNNN
+; ENDM
+;
+SBCD MACRO ?NNNN
+ DB 0EDH,43H ;SBCD
+ DW ?NNNN
+ ENDM
+SDED MACRO ?NNNN
+ DB 0EDH,53H ;SDED
+ DW ?NNNN
+ ENDM
+;
+;SSPD MACRO ?NNNN
+; DB 0EDH,73H ;SSPD
+; DW ?NNNN
+; ENDM
+;SIXD MACRO ?NNNN
+; DB 0DDH,22H ;SIXD
+; DW ?NNNN
+; ENDM
+;SIYD MACRO ?NNNN
+; DB 0FDH,22H ;SIYD
+; DW ?NNNN
+; ENDM
+;SPIX MACRO
+; DB 0DDH,0F9H ;SPIX
+; ENDM
+;SPIY MACRO
+; DB 0FDH,0F9H ;SPIY
+; ENDM
+;
+PUSHIX MACRO
+ DB 0DDH,0E5H ;PUSHIX
+ ENDM
+PUSHIY MACRO
+ DB 0FDH,0E5H ;PUSHIY
+ ENDM
+POPIX MACRO
+ DB 0DDH,0E1H ;POPIX
+ ENDM
+POPIY MACRO
+ DB 0FDH,0E1H ;POPIY
+ ENDM
+EXAF MACRO
+ DB 08H ;EXAF
+ ENDM
+EXX MACRO
+ DB 0D9H ;EXX
+ ENDM
+;
+;XTIX MACRO
+; DB 0DDH,0E3H ;XTIX
+; ENDM
+;XTIY MACRO
+; DB 0FDH,0E3H ;XTIY
+; ENDM
+;
+LDI MACRO
+ DB 0EDH,0A0H ;LDI
+ ENDM
+LDIR MACRO
+ DB 0EDH,0B0H ;LDIR
+ ENDM
+LDD MACRO
+ DB 0EDH,0A8H ;LDD
+ ENDM
+LDDR MACRO
+ DB 0EDH,0B8H ;LDDR
+ ENDM
+CCI MACRO
+ DB 0EDH,0A1H ;CCI
+ ENDM
+CCIR MACRO
+ DB 0EDH,0B1H ;CCIR
+ ENDM
+CCD MACRO
+ DB 0EDH,0A9H ;CCD
+ ENDM
+CCDR MACRO
+ DB 0EDH,0B9H ;CCDR
+ ENDM
+;
+;ADDX MACRO ?D
+; @CHK ?D
+; DB 0DDH,86H,?D ;ADDX
+; ENDM
+;ADDY MACRO ?D
+; @CHK ?D
+; DB 0FDH,86H,?D ;ADDY
+; ENDM
+;ADCX MACRO ?D
+; @CHK ?D
+; DB 0DDH,8EH,?D ;ADCX
+; ENDM
+;ADCY MACRO ?D
+; @CHK ?D
+; DB 0FDH,8EH,?D ;ADCY
+; ENDM
+;SUBX MACRO ?D
+; @CHK ?D
+; DB 0DDH,96H,?D ;SUBX
+; ENDM
+;SUBY MACRO ?D
+; @CHK ?D
+; DB 0FDH,96H,?D ;SUBY
+; ENDM
+;SBCX MACRO ?D
+; @CHK ?D
+; DB 0DDH,9EH,?D ;SBCX
+; ENDM
+;SBCY MACRO ?D
+; @CHK ?D
+; DB 0FDH,9EH,?D ;SBCY
+; ENDM
+;ANDX MACRO ?D
+; @CHK ?D
+; DB 0DDH,0A6H,?D ;ANDX
+; ENDM
+;ANDY MACRO ?D
+; @CHK ?D
+; DB 0FDH,0A6H,?D ;ANDY
+; ENDM
+;XORX MACRO ?D
+; @CHK ?D
+; DB 0DDH,0AEH,?D ;XORX
+; ENDM
+;XORY MACRO ?D
+; @CHK ?D
+; DB 0FDH,0AEH,?D ;XORY
+; ENDM
+;ORX MACRO ?D
+; @CHK ?D
+; DB 0DDH,0B6H,?D ;ORX
+; ENDM
+;ORY MACRO ?D
+; @CHK ?D
+; DB 0FDH,0B6H,?D ;ORY
+; ENDM
+;CMPX MACRO ?D
+; @CHK ?D
+; DB 0DDH,0BEH,?D ;CMPX
+; ENDM
+;CMPY MACRO ?D
+; @CHK ?D
+; DB 0FDH,0BEH,?D CMPY
+; ENDM
+;INRX MACRO ?D
+; @CHK ?D
+; DB 0DDH,34H,?D ;INRX
+; ENDM
+;INRY MACRO ?D
+; @CHK ?D
+; DB 0FDH,34H,?D ;INRY
+; ENDM
+;DCRX MACRO ?D
+; @CHK ?D
+; DB 0DDH,035H,?D ;DCRX
+; ENDM
+;DCRY MACRO ?D
+; @CHK ?D
+; DB 0FDH,35H,?D ;DCRY
+; ENDM
+;
+NEG MACRO
+ DB 0EDH,44H ;NEG
+ ENDM
+IM0 MACRO
+ DB 0EDH,46H ;IM0
+ ENDM
+IM1 MACRO
+ DB 0EDH,56H ;IM1
+ ENDM
+IM2 MACRO
+ DB 0EDH,5EH ;
+ ENDM
+;
+BC EQU 0
+DE EQU 2
+HL EQU 4
+IX EQU 4
+IY EQU 4
+;
+DADC MACRO ?R
+ DB 0EDH,?R*8+4AH ;DADC
+ ENDM
+DSBC MACRO ?R
+ DB 0EDH,?R*8+42H ;DSBC
+ ENDM
+;
+;DADX MACRO ?R
+; DB 0DDH,?R*8+09H ;DADX
+; ENDM
+;DADY MACRO ?R
+; DB 0FDH,?R*8+09H ;DADY
+; ENDM
+;
+INXIX MACRO
+ DB 0DDH,23H ;INXIX
+ ENDM
+INXIY MACRO
+ DB 0FDH,23H ;INXIY
+ ENDM
+DCXIX MACRO
+ DB 0DDH,2BH ;DCXIX
+ ENDM
+DCXIY MACRO
+ DB 0FDH,2BH ;DCXIY
+ ENDM
+
+BIT MACRO ?N,?R
+ DB 0CBH,?N*8+?R+40H ;BIT
+ ENDM
+SETB MACRO ?N,?R
+ DB 0CBH,?N*8+?R+0C0H ;SETB
+ ENDM
+RESB MACRO ?N,?R
+ DB 0CBH,?N*8+?R+80H ;RESB
+ ENDM
+
+BITH MACRO ?N
+ DB 0CBH,?N*8+46H ;BITH
+ ENDM
+BITX MACRO ?N,?D
+ @CHK ?D
+ DB 0DDH,0CBH,?D,?N*8+46H ;BITX
+ ENDM
+BITY MACRO ?N,?D
+ @CHK ?D
+ DB 0FDH,0CBH,?D,?N*8+46H ;BITY
+ ENDM
+SETH MACRO ?N
+ DB 0CBH,?N*8+0C6H ;SETH
+ ENDM
+SETX MACRO ?N,?D
+ @CHK ?D
+ DB 0DDH,0CBH,?D,?N*8+0C6H ;SETX
+ ENDM
+SETY MACRO ?N,?D
+ @CHK ?D
+ DB 0FDH,0CBH,?D,?N*8+0C6H ;SETY
+ ENDM
+RESH MACRO ?N
+ DB 0CBH,?N*8+86H ;RESH
+ ENDM
+RESX MACRO ?N,?D
+ @CHK ?D
+ DB 0DDH,0CBH,?D,?N*8+86H ;RESX
+ ENDM
+RESY MACRO ?N,?D
+ @CHK ?D
+ DB 0FDH,0CBH,?D,?N*8+86H ;RESY
+ ENDM
+
+JR MACRO ?N
+ DB 18H,?N-$-1 ;JR
+ ENDM
+JRC MACRO ?N
+ DB 38H,?N-$-1 ;JRC
+ ENDM
+JRNC MACRO ?N
+ DB 30H,?N-$-1 ;JRNC
+ ENDM
+JRZ MACRO ?N
+ DB 28H,?N-$-1 ;JRZ
+ ENDM
+JRNZ MACRO ?N
+ DB 20H,?N-$-1 ;JRNZ
+ ENDM
+DJNZ MACRO ?N
+ DB 10H,?N-$-1 ;DJNZ
+ ENDM
+;
+;PCIX MACRO
+; DB 0DDH,0E9H ;PCIX
+; ENDM
+;PCIY MACRO
+; DB 0FDH,0E9H ;PCIY
+; ENDM
+;
+RETI MACRO
+ DB 0EDH,4DH ;RETI
+ ENDM
+RETN MACRO
+ DB 0EDH,45H ;RETN
+ ENDM
+
+INP MACRO ?R
+ DB 0EDH,?R*8+40H ;INP
+ ENDM
+OUTP MACRO ?R
+ DB 0EDH,?R*8+41H ;OUTP
+ ENDM
+INI MACRO
+ DB 0EDH,0A2H ;INI
+ ENDM
+INIR MACRO
+ DB 0EDH,0B2H ;INIR
+ ENDM
+IND MACRO
+ DB 0EDH,0AAH ;IND
+ ENDM
+INDR MACRO
+ DB 0EDH,0BAH ;INDR
+ ENDM
+OUTI MACRO
+ DB 0EDH,0A3H ;OUTI
+ ENDM
+OUTIR MACRO
+ DB 0EDH,0B3H ;OUTIR
+ ENDM
+OUTD MACRO
+ DB 0EDH,0ABH ;OUTD
+ ENDM
+OUTDR MACRO
+ DB 0EDH,0BBH ;OUTDR
+ ENDM
+;
+;RLCR MACRO ?R
+; DB 0CBH, 00H + ?R ;RLCR
+; ENDM
+;RLCX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 06H ;RLCX
+; ENDM
+;RLCY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 06H ;RLCY
+; ENDM
+;RALR MACRO ?R
+; DB 0CBH, 10H+?R ;RALR
+; ENDM
+;RALX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 16H ;RALX
+; ENDM
+;RALY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 16H ;RALY
+; ENDM
+;RRCR MACRO ?R
+; DB 0CBH, 08H + ?R ;RRCR
+; ENDM
+;RRCX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 0EH ;RRCX
+; ENDM
+;RRCY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 0EH ;RRCY
+; ENDM
+;RARR MACRO ?R
+; DB 0CBH, 18H + ?R ;RARR
+; ENDM
+;RARX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 1EH ;RARX
+; ENDM
+;RARY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 1EH ;RARY
+; ENDM
+;SLAR MACRO ?R
+; DB 0CBH, 20H + ?R ;SLAR
+; ENDM
+;SLAX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 26H ;SLAX
+; ENDM
+;SLAY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 26H ;SLAY
+; ENDM
+;SRAR MACRO ?R
+; DB 0CBH, 28H+?R ;SRAR
+; ENDM
+;SRAX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 2EH ;SRAX
+; ENDM
+;SRAY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 2EH ;SRAY
+; ENDM
+;SRLR MACRO ?R
+; DB 0CBH, 38H + ?R ;SRLR
+; ENDM
+;SRLX MACRO ?D
+; @CHK ?D
+; DB 0DDH, 0CBH, ?D, 3EH ;SRLX
+; ENDM
+;SRLY MACRO ?D
+; @CHK ?D
+; DB 0FDH, 0CBH, ?D, 3EH ;SRLY
+; ENDM
+;RLD MACRO
+; DB 0EDH, 6FH ;RLD
+; ENDM
+RRD MACRO
+ DB 0EDH, 67H ;RRD
+ ENDM
+
Index: z80control/trunk/DE1/ROM/z80test.bat
===================================================================
--- z80control/trunk/DE1/ROM/z80test.bat (nonexistent)
+++ z80control/trunk/DE1/ROM/z80test.bat (revision 6)
@@ -0,0 +1,4 @@
+m z80test.asm
+imac z80test
+copy z80test.hex HexFiles\z80test.hex
+pause
\ No newline at end of file
Index: z80control/trunk/DE1/ROM/HexFiles/rom.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/ROM/HexFiles/rom.bin
===================================================================
--- z80control/trunk/DE1/ROM/HexFiles/rom.bin (nonexistent)
+++ z80control/trunk/DE1/ROM/HexFiles/rom.bin (revision 6)
z80control/trunk/DE1/ROM/HexFiles/rom.bin
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/ROM/HexFiles/z80test.hex
===================================================================
--- z80control/trunk/DE1/ROM/HexFiles/z80test.hex (nonexistent)
+++ z80control/trunk/DE1/ROM/HexFiles/z80test.hex (revision 6)
@@ -0,0 +1,12 @@
+:10000000C37200FFAA008C0C010000000000000079
+:1000100000000000000000000000000000000000E0
+:100020000000000000C3720000000000000000009B
+:1000300000000000000000000000000000C372008B
+:0E0040000000000000000000000000009A0018
+:03006600C3900044
+:10007200F331EADFED5E010000FBCDA000CDA00070
+:10008200CDA000790CD310D324D302C37B00F5C5D5
+:10009200D5E5E1D1C1F1ED45DB24D311FBC9C501A1
+:0E00A20000400DC2A40005C2A400C1C9FFFFAA
+:0000000000
+
\ No newline at end of file
Index: z80control/trunk/DE1/ROM/HexFiles/rom.vhd
===================================================================
--- z80control/trunk/DE1/ROM/HexFiles/rom.vhd (nonexistent)
+++ z80control/trunk/DE1/ROM/HexFiles/rom.vhd (revision 6)
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity rom is
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(13 downto 0);
+ D : out std_logic_vector(7 downto 0)
+ );
+end rom;
+architecture rtl of rom is
+begin
+process (Clk)
+begin
+ if Clk'event and Clk = '1' then
+ case A is
+ when "00000000000000" => D <= x"C3";
+ when "00000000000001" => D <= x"72";
+ when "00000000000010" => D <= x"00";
+ when "00000000000011" => D <= x"FF";
+ when "00000000000100" => D <= x"AA";
+ when "00000000000101" => D <= x"00";
+ when "00000000000110" => D <= x"8C";
+ when "00000000000111" => D <= x"0C";
+ when "00000000001000" => D <= x"01";
+ when "00000000001001" => D <= x"00";
+ when "00000000001010" => D <= x"00";
+ when "00000000001011" => D <= x"00";
+ when "00000000001100" => D <= x"00";
+ when "00000000001101" => D <= x"00";
+ when "00000000001110" => D <= x"00";
+ when "00000000001111" => D <= x"00";
+ when "00000000010000" => D <= x"00";
+ when "00000000010001" => D <= x"00";
+ when "00000000010010" => D <= x"00";
+ when "00000000010011" => D <= x"00";
+ when "00000000010100" => D <= x"00";
+ when "00000000010101" => D <= x"00";
+ when "00000000010110" => D <= x"00";
+ when "00000000010111" => D <= x"00";
+ when "00000000011000" => D <= x"00";
+ when "00000000011001" => D <= x"00";
+ when "00000000011010" => D <= x"00";
+ when "00000000011011" => D <= x"00";
+ when "00000000011100" => D <= x"00";
+ when "00000000011101" => D <= x"00";
+ when "00000000011110" => D <= x"00";
+ when others => D <= "ZZZZZZZZ";
+ end case;
+ end if;
+end process;
+end;
Index: z80control/trunk/DE1/ROM/Z80TEST.SYM
===================================================================
--- z80control/trunk/DE1/ROM/Z80TEST.SYM (nonexistent)
+++ z80control/trunk/DE1/ROM/Z80TEST.SYM (revision 6)
@@ -0,0 +1,5 @@
+0000 BC 0008 CHIP1ID 00AE CHPEND 009A COMMAIN 0002 DE
+00A0 DELAY 00A4 DELLOP 0004 HL 004C IBMVECT 0004 IX
+0004 IY 007B MAINLOOP 0090 POWERF 0072 SFTSTART0 0072 SFTSTART2
+0000 START 0072 STARTU
+
\ No newline at end of file
Index: z80control/trunk/DE1/ROM/HexToBinary.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: z80control/trunk/DE1/ROM/HexToBinary.exe
===================================================================
--- z80control/trunk/DE1/ROM/HexToBinary.exe (nonexistent)
+++ z80control/trunk/DE1/ROM/HexToBinary.exe (revision 6)
z80control/trunk/DE1/ROM/HexToBinary.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: z80control/trunk/DE1/ROM/Z80TEST.BAK
===================================================================
--- z80control/trunk/DE1/ROM/Z80TEST.BAK (nonexistent)
+++ z80control/trunk/DE1/ROM/Z80TEST.BAK (revision 6)
@@ -0,0 +1,167 @@
+;
+MACLIB Z80
+;
+ ORG 0
+;
+START JMP STARTU
+ ;
+ DB 0FFH
+ DW (CHPEND-4)
+ DW 3212
+;
+CHIP1ID DB 1 ;CHIP I.D. NUMBER
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ JMP SFTSTART0
+;
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ JMP SFTSTART2
+;
+;
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+IBMVECT
+ DW COMMAIN ;WAS CRTINP ;ARECEIVE
+;
+;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+;
+; NON MASKABLE INT.
+;
+ ORG 66H ;TRAP
+;
+ JMP POWERF
+;
+;******************************
+;
+ ORG 72H
+;
+
+SFTSTART0
+SFTSTART2
+;
+; POWER UP START UP
+;
+; @ @ @ USED TO TEST COMM @ @ @
+;
+STARTU
+ DI
+
+ LXI SP,0DFEAH
+
+ IM2 ; SET Z80 INT MODE
+
+ LXI B,0
+MAINLOOP
+ EI
+
+ CALL DELAY
+ CALL DELAY
+ CALL DELAY
+
+
+ MOV A,C
+ INR C
+
+ OUT 10H ; HEX DISPLAY 0,1
+
+ OUT 024H ; COMPORT
+
+ OUT 002H ; LEDG
+
+ JMP MAINLOOP
+
+;
+;
+POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
+ PUSH B ;+2
+ PUSH D ;+3
+ PUSH H ;+4
+;
+ POP H
+ POP D
+ POP B
+ POP PSW
+ RETN
+;
+
+
+;4CH
+COMMAIN
+ IN 24H ; COMMPORT
+ OUT 11H ; HEX DISPLAY
+ EI
+ RET
+
+
+
+DELAY PUSH B
+ LXI B,4000H
+DELLOP
+ DCR C
+ JNZ DELLOP
+ DCR B
+ JNZ DELLOP
+ POP B
+ RET
+
+CHPEND DW 0FFFFH
+;
+ END START
Index: z80control/trunk/DE1/ROM/tools.ini
===================================================================
--- z80control/trunk/DE1/ROM/tools.ini (nonexistent)
+++ z80control/trunk/DE1/ROM/tools.ini (revision 6)
@@ -0,0 +1,156 @@
+; TOOLS.INI file for QUICK configuration
+
+[M]
+Arg:Alt+A
+Assign:Alt+=
+Backtab:Shift+Tab
+Begline:Home
+Cancel:Esc
+Cdelete:Ctrl+G
+Compile:Shift+F3
+Copy:Ctrl+Ins
+Down:Down
+Down:Ctrl+X
+Emacscdel:Bksp
+Emacsnewl:Enter
+Endline:End
+Execute:f10
+Exit:Alt+X
+exit:f10
+Help:F1
+Home:Ctrl+Home
+Information:Shift+F1
+Initialize:Alt+F10
+Insertmode:Ins
+Insertmode:Ctrl+V
+Lasttext:Alt+L
+Ldelete:Ctrl+Y
+Left:Left
+Linsert:Ctrl+N
+Mark:Alt+M
+Meta:F9
+Mlines:Ctrl+W
+Mpage:Pgup
+Mpage:Ctrl+R
+Mpara:Ctrl+Pgup
+Msearch:F4
+Mword:Ctrl+Left
+Paste:Shift+Ins
+Pbal:Ctrl+[
+Plines:Ctrl+Z
+Ppage:Pgdn
+Ppage:Ctrl+C
+Ppara:Ctrl+Pgdn
+Psearch:F3
+Pword:Ctrl+Right
+Pword:Ctrl+F
+Qreplace:Alt+F3
+Quote:Alt+Q
+Refresh:Alt+R
+Replace:Ctrl+L
+Right:Right
+Right:Ctrl+D
+Sdelete:Del
+Setfile:F2
+Setwindow:Ctrl+]
+Shell:Shift+F9
+Sinsert:Alt+Ins
+Tab:Tab
+Undo:Alt+Bksp
+Up:Up
+Up:Ctrl+E
+Window:F6
+;
+; to load the wordstar extension to enable ctrl+QS and ctrl+QD
+; remove the semicolon from the following line and fill in the correct
+; path
+; load:ws.zxt
+Tabstops:10
+Fgcolor:17
+Rmargin:80
+Vscroll:1
+Hscroll:1
+Hike:1
+Backup:bak
+
+donot:=META CURDAY " " CURDATE " " CURTIME
+donot:f5
+
+Curtime:Alt+T
+
+DTATE:=META CURDAY " " CURDATE " " CURTIME
+DTATE:ALT+D
+
+
+ONEDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
+ONEDEL:CTRL+O
+
+BACKDEL:=META CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE
+BACKDEL:CTRL+B
+
+COP2LIN:= DOWN Ldelete Ldelete Ldelete Ldelete
+COP2LIN:ALT+Y
+
+COPYADR:=ARG RIGHT RIGHT RIGHT RIGHT RIGHT SDELETE
+COPYADR:ALT+C
+
+MOVADR:=COPYADR RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT DOWN LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT
+MOVADR:ALT+V
+
+SSWLB2:=DOWN LEFT LEFT LEFT LEFT " "
+SSWLB2:ALT+S
+
+SSWDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
+SSWDEL:ALT+W
+
+ISWDEL:=DOWN META BEGLINE ";"
+ISWDEL:ALT+N
+
+SLDD:=DOWN BEGLINE " "
+SLDD:ALT+U
+
+
+PLACE00:=META "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT
+PLACE00:ALT+`
+
+PLACE1:=META "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT
+PLACE1:ALT+1
+
+PLACE2:=META "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT
+PLACE2:ALT+2
+
+PLACE3:=META "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT
+PLACE3:ALT+3
+
+PLACE4:=META "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT
+PLACE4:ALT+4
+
+PLACE5:=META "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT
+PLACE5:ALT+5
+
+PLACE6:=META "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT
+PLACE6:ALT+6
+
+PLACE7:=META "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT
+PLACE7:ALT+7
+
+PLACE8:=META "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT
+PLACE8:ALT+8
+
+PLACE9:=META "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT
+PLACE9:ALT+9
+
+PLACE0:=META "0" DOWN LEFT "1" DOWN LEFT "2" DOWN LEFT "3" DOWN LEFT "4" DOWN LEFT "5" DOWN LEFT "6" DOWN LEFT "7" DOWN LEFT "8" DOWN LEFT "9" DOWN LEFT
+PLACE0:ALT+0
+;
+PCHEK:=META PPAGE SETFILE PPAGE
+PCHEK:ALT+G
+;
+CHWIN:=META SETFILE
+CHWIN:ALT+F
+;
+MOVAD:=BEGLINE ARG TAB SDELETE DOWN TAB "EQU " PASTE DOWN
+MOVAD:ALT+J
+;
+DOIT:=ARG TAB TAB TAB RIGHT RIGHT SDELETE BEGLINE DOWN DOWN
+DOIT:CTRL+P
Index: z80control/trunk/DE1/z80soc.qsf
===================================================================
--- z80control/trunk/DE1/z80soc.qsf (nonexistent)
+++ z80control/trunk/DE1/z80soc.qsf (revision 6)
@@ -0,0 +1,514 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# z80soc_caps_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY top_de1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:43:12 MAY 01, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105"
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_global_assignment -name END_TIME "10000 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE "C:/altera/Kits/CycloneII_Starter_Kit-v1.0.0/Labs/z80soc/DE1/z80soc.dpf"
+set_global_assignment -name MISC_FILE "C:/altera/cores/z80soc/DE1/z80soc.dpf"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
+set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "C:/altera/cores/vhdl/z80soc/DE1" -section_id eda_board_design_boundary_scan
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
+set_global_assignment -name LL_ROOT_REGION ON -entity TOP_DE1 -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity TOP_DE1 -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity TOP_DE1 -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -entity TOP_DE1 -section_id Top
+set_global_assignment -name MISC_FILE "C:/altera/cores/vhdl/z80soc/DE1/z80soc.dpf"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VHDL_FILE rtl/VHDL/t80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/uart/uart_lib.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/uart/miniUART.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/clkUnit.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/uart/RxUnit.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/uart/TxUnit.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/clk_div.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/clock_357mhz.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/top_de1.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/decoder_7seg.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Reg.vhd
\ No newline at end of file