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/modular_oscilloscope/trunk/hdl/modular_oscilloscope.vhd
0,0 → 1,252
-------------------------------------------------------------------------------------------------100 |
--| Modular Oscilloscope |
--| UNSL - Argentine |
--| |
--| File: modullar_oscilloscope_tbench_text.vhd |
--| Version: 0.1 |
--| Tested in: Actel A3PE1500 |
--| Board: RVI Prototype Board + LP Data Conversion Daughter Board |
--|------------------------------------------------------------------------------------------------- |
--| Description: |
--| MODULAR OSCILLOSCOPE - Main |
--| This is the top top module. |
--| |
--|------------------------------------------------------------------------------------------------- |
--| File history: |
--| 0.1 | aug-2009 | First testing |
---------------------------------------------------------------------------------------------------- |
|
--| |
--| This VHDL design file is an open design; you can redistribute it and/or |
--| modify it and/or implement it after contacting the author. |
---------------------------------------------------------------------------------------------------- |
|
|
-- NOTES: |
|
|
--================================================================================================== |
-- TO DO |
|
--================================================================================================== |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use ieee.math_real.all; |
|
use work.ctrl_pkg.all; |
use work.daq_pkg.all; |
use work.memory_pkg.all; |
use work.eppwbn_pkg.all; |
|
entity modular_oscilloscope is |
port( |
-- ADC |
adc_data_I: in std_logic_vector (9 downto 0); |
adc_sel_O: out std_logic; |
adc_clk_O: out std_logic; |
adc_sleep_O: out std_logic; |
adc_chip_sel_O: out std_logic; |
|
-- EPP |
nStrobe_I: in std_logic; -- HostClk/nWrite |
Data_IO: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8) |
nAck_O: out std_logic; -- PtrClk/PeriphClk/Intr |
busy_O: out std_logic; -- PtrBusy/PeriphAck/nWait |
PError_O: out std_logic; -- AckData/nAckReverse |
Sel_O: out std_logic; -- XFlag (Select) |
nAutoFd_I: in std_logic; -- HostBusy/HostAck/nDStrb |
PeriphLogicH_O: out std_logic; -- (Periph Logic High) |
nInit_I: in std_logic; -- nReverseRequest |
nFault_O: out std_logic; -- nDataAvail/nPeriphRequest |
nSelectIn_I: in std_logic; -- 1284 Active/nAStrb |
|
-- Peripherals |
reset_I: in std_logic; |
pll_clk_I: in std_logic -- clock signal go to pll, and is divided in two clocks |
|
); |
end entity modular_oscilloscope; |
|
architecture structural1 of modular_oscilloscope is |
|
------------------------------------------------------------------------------------------------ |
-- From port |
signal ctrl_dat_i_port: std_logic_vector (15 downto 0); |
signal ctrl_dat_o_port: std_logic_vector (15 downto 0); |
signal ctrl_adr_i_port: std_logic_vector (7 downto 0); |
signal ctrl_cyc_i_port: std_logic; |
signal ctrl_stb_i_port: std_logic; |
signal ctrl_ack_o_port: std_logic ; |
signal ctrl_we_i_port: std_logic; |
|
signal ctrl_dat_i_daq: std_logic_vector (15 downto 0); |
signal ctrl_dat_o_daq: std_logic_vector (15 downto 0); |
signal ctrl_adr_o_daq: std_logic_vector (1 downto 0); |
signal ctrl_cyc_o_daq: std_logic; |
signal ctrl_stb_o_daq: std_logic; |
signal ctrl_ack_i_daq: std_logic ; |
signal ctrl_we_o_daq: std_logic; |
|
signal ctrl_dat_o_memw: std_logic_vector (15 downto 0); |
signal ctrl_adr_o_memw: std_logic_vector (13 downto 0); |
signal ctrl_cyc_o_memw: std_logic; |
signal ctrl_stb_o_memw: std_logic; |
signal ctrl_ack_i_memw: std_logic ; |
signal ctrl_we_o_memw: std_logic; |
|
signal ctrl_dat_i_memr: std_logic_vector (15 downto 0); |
signal ctrl_adr_o_memr: std_logic_vector (13 downto 0); |
signal ctrl_cyc_o_memr: std_logic; |
signal ctrl_stb_o_memr: std_logic; |
signal ctrl_ack_i_memr: std_logic ; |
signal ctrl_we_o_memr: std_logic; |
|
signal clk_daq, clk_port: std_logic; |
|
begin |
|
U_DAQ: daq |
generic map( |
DEFALT_CONFIG => "0000101000000000" |
-- 5432109876543210 |
--: std_logic_vector := "0000100000000000" |
-- bits 8 a 0 clk_pre_scaler |
-- bits 9 clk_pre_scaler_ena |
-- bit 10 adc sleep |
-- bit 11 adc_chip_sel |
-- bits 12 a 15 sin usar |
|
-- si clk_pre_scaler_ena = 1 |
-- frecuencia_adc = frecuencia_wbn / ((clk_pre_scaler+1)*2) |
-- sino frecuencia_adc = frecuencia_wbn |
) |
port map( |
-- Externo |
adc_data_I => adc_data_I, |
adc_sel_O => adc_sel_O, |
adc_clk_O => adc_clk_O, |
adc_sleep_O => adc_sleep_O, |
adc_chip_sel_O => adc_chip_sel_O, |
-- Interno |
RST_I => reset_I, |
CLK_I => clk_daq, |
DAT_I => ctrl_dat_o_daq, |
ADR_I => ctrl_adr_o_daq, |
CYC_I => ctrl_cyc_o_daq, |
STB_I => ctrl_stb_o_daq, |
WE_I => ctrl_we_o_daq, |
DAT_O => ctrl_dat_i_daq, |
ACK_O => ctrl_ack_i_daq, |
|
adc_clk_I => clk_daq |
); |
|
|
U_EPP16: eppwbn_16bit |
port map ( |
-- TEMPORAL |
--epp_mode_monitor: out std_logic_vector (1 downto 0); |
-- Externo |
nStrobe => nStrobe_I, |
Data => Data_IO, |
nAck => nAck_O, |
busy => busy_O, |
PError => PError_O, |
Sel => Sel_O, |
nAutoFd => nAutoFd_I, |
PeriphLogicH => PeriphLogicH_O, |
nInit => nInit_I, |
nFault => nFault_O, |
nSelectIn => nSelectIn_I, |
-- Interno |
RST_I => reset_I, |
CLK_I => clk_port, |
DAT_I => ctrl_dat_o_port, |
DAT_O => ctrl_dat_i_port, |
ADR_O => ctrl_adr_i_port, |
CYC_O => ctrl_cyc_i_port, |
STB_O => ctrl_stb_i_port, |
ACK_I => ctrl_ack_o_port, |
WE_O => ctrl_we_i_port |
); |
|
U_CTRL: ctrl |
port map( |
|
DAT_I_port => ctrl_dat_i_port, |
DAT_O_port => ctrl_dat_o_port, |
ADR_I_port => ctrl_adr_i_port(3 downto 0), |
CYC_I_port => ctrl_cyc_i_port, |
STB_I_port => ctrl_stb_i_port, |
ACK_O_port => ctrl_ack_o_port, |
WE_I_port => ctrl_we_i_port, |
CLK_I_port => clk_port, |
RST_I_port => reset_I, |
|
DAT_I_daq => ctrl_dat_i_daq, |
DAT_O_daq => ctrl_dat_o_daq, |
ADR_O_daq => ctrl_adr_o_daq, |
CYC_O_daq => ctrl_cyc_o_daq, |
STB_O_daq => ctrl_stb_o_daq, |
ACK_I_daq => ctrl_ack_i_daq, |
WE_O_daq => ctrl_we_o_daq, |
CLK_I_daq => clk_daq, |
RST_I_daq => reset_I, |
|
DAT_O_memw => ctrl_dat_o_memw, |
ADR_O_memw => ctrl_adr_o_memw, |
CYC_O_memw => ctrl_cyc_o_memw, |
STB_O_memw => ctrl_stb_o_memw, |
ACK_I_memw => ctrl_ack_i_memw, |
WE_O_memw => ctrl_we_o_memw, |
|
DAT_I_memr => ctrl_dat_i_memr, |
ADR_O_memr => ctrl_adr_o_memr, |
CYC_O_memr => ctrl_cyc_o_memr, |
STB_O_memr => ctrl_stb_o_memr, |
ACK_I_memr => ctrl_ack_i_memr, |
WE_O_memr => ctrl_we_o_memr |
); |
|
U_DPORTMEM: dual_port_memory_wb |
port map( |
-- Puerto A (Higer prioriry) |
RST_I_a => reset_I, |
CLK_I_a => clk_daq, |
DAT_I_a => ctrl_dat_o_memw, |
DAT_O_a => open, |
ADR_I_a => ctrl_adr_o_memw, |
CYC_I_a => ctrl_cyc_o_memw, |
STB_I_a => ctrl_stb_o_memw, |
ACK_O_a => ctrl_ack_i_memw, |
WE_I_a => ctrl_we_o_memw, |
-- Puerto B (Lower prioriry) |
RST_I_b => reset_I, |
CLK_I_b => clk_port, |
DAT_I_b => X"0000", |
DAT_O_b => ctrl_dat_i_memr, |
ADR_I_b => ctrl_adr_o_memr, |
CYC_I_b => ctrl_cyc_o_memr, |
STB_I_b => ctrl_stb_o_memr, |
ACK_O_b => ctrl_ack_i_memr, |
WE_I_b => ctrl_we_o_memr |
); |
|
U_PLL0: entity work.A3PE_pll_2clk |
port map( |
POWERDOWN => '0', |
CLKA => pll_clk_I, |
LOCK => open, |
--SDIN => '0', |
--SCLK => '0', |
--SSHIFT => '0', |
--SUPDATE => '0', |
--MODE => '0', |
GLA => clk_daq, |
GLB => clk_port |
--SDOUT => open |
); |
|
end architecture; |
|
modular_oscilloscope/trunk/hdl/modular_oscilloscope.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: modular_oscilloscope/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
===================================================================
--- modular_oscilloscope/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd (nonexistent)
+++ modular_oscilloscope/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd (revision 53)
@@ -0,0 +1,363 @@
+-------------------------------------------------------------------------------------------------100
+--| Modular Oscilloscope
+--| UNSL - Argentine
+--|
+--| File: modullar_oscilloscope_tbench_text.vhd
+--| Version: 0.1
+--| Tested in: Actel A3PE1500
+--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
+--|-------------------------------------------------------------------------------------------------
+--| Description:
+--| This file is only for test purposes.
+--|
+--|-------------------------------------------------------------------------------------------------
+--| File history:
+--| 0.1 | aug-2009 | First release
+----------------------------------------------------------------------------------------------------
+--| Copyright © 2009, Facundo Aguilera.
+--|
+--| This VHDL design file is an open design; you can redistribute it and/or
+--| modify it and/or implement it after contacting the author.
+----------------------------------------------------------------------------------------------------
+
+--==================================================================================================
+-- TO DO
+-- · Full full test
+--==================================================================================================
+
+
+
+-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+
+
+entity ctrl_tb_simple_clock is
+ port (
+ CLK_PERIOD: in time;-- := 20 ns;
+ CLK_DUTY: in real; -- := 0.5;
+ active: in boolean;
+ clk_o: out std_logic
+ );
+end entity ctrl_tb_simple_clock ;
+
+architecture beh of ctrl_tb_simple_clock is
+begin
+ P_main: process
+ begin
+ wait until active;
+ while (active = true) loop
+ clk_o <= '0';
+ wait for CLK_PERIOD * (100.0 - clk_Duty)/100.0;
+ clk_o <= '1';
+ wait for CLK_PERIOD * clk_Duty/100.0;
+ end loop;
+ clk_o <= '0';
+ wait;
+ end process;
+end architecture beh;
+
+
+
+-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+library ieee, std;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.NUMERIC_STD.ALL;
+use ieee.math_real.all;
+
+
+-- Additional libraries used by Model Under Test.
+use work.ctrl_pkg.all;
+use work.daq_pkg.all;
+use work.memory_pkg.all;
+use work.eppwbn_pkg.all;
+
+entity stimulus is
+ port(
+ -- ADC
+ adc_data_I: inout std_logic_vector (9 downto 0) := 0;
+ adc_sel_O: in std_logic;
+ adc_clk_O: in std_logic;
+ adc_sleep_O: in std_logic;
+ adc_chip_sel_O: in std_logic;
+
+ -- EPP
+ nStrobe_I: inout std_logic; -- HostClk/nWrite
+ Data_IO: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
+ nAck_O: in std_logic; -- PtrClk/PeriphClk/Intr
+ busy_O: in std_logic; -- PtrBusy/PeriphAck/nWait
+ PError_O: in std_logic; -- AckData/nAckReverse
+ Sel_O: in std_logic; -- XFlag (Select)
+ nAutoFd_I: inout std_logic; -- HostBusy/HostAck/nDStrb
+ PeriphLogicH_O: in std_logic; -- (Periph Logic High)
+ nInit_I: inout std_logic; -- nReverseRequest
+ nFault_O: in std_logic; -- nDataAvail/nPeriphRequest
+ nSelectIn_I: inout std_logic; -- 1284 Active/nAStrb
+
+ -- Peripherals
+ reset_I: inout std_logic;
+ pll_clk_I: inout std_logic -- clock signal go to pll, and is divided in two clocks
+ );
+
+end stimulus;
+
+architecture STIMULATOR of stimulus is
+
+ -- Control Signal Declarations
+ signal tb_InitFlag : boolean := false;
+ signal tb_ParameterInitFlag : boolean := false;
+ signal i: std_logic;
+
+ -- Parm Declarations
+ signal clk_Duty : real := 0.0;
+ signal clk_Period : time := 0 ns;
+
+begin
+ --------------------------------------------------------------------------------------------------
+ -- Parm Assignment Block
+ P_AssignParms : process
+ variable clk_Duty_real : real;
+ variable clk_Period_real : real;
+ begin
+ -- Basic parameters
+ clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
+ clk_Period <= clk_Period_real * 1 ns;
+ clk_Duty_real := 50.0;
+ clk_Duty <= clk_Duty_real;
+
+ tb_ParameterInitFlag <= true;
+
+ wait;
+ end process;
+
+
+ --------------------------------------------------------------------------------------------------
+ -- Clocks
+ -- Clock Instantiation
+ tb_clk: entity work.tb_simple_clock
+ port map (
+ clk_Period => clk_Period,
+ clk_Duty => clk_Duty,
+ active => tb_InitFlag,
+ clk_o => pll_clk_I
+ );
+
+
+ --------------------------------------------------------------------------------------------------
+ -- Clocked Sequences
+ P_virtual_adc: process (adc_clk_O)
+ variable data1: std_logic_vector(9 downto 0) := 1; -- odd
+ variable data2: std_logic_vector(9 downto 0) := 0; -- pair
+ begin
+ if adc_clk_O'event and adc_clk_O = '1' then
+ data1 <= data1 + 2;
+ data2 <= data2 + 2;
+ end if;
+
+
+ case adc_sel_O is
+ when '0' =>
+ adc_data_I <= data1;
+ when others =>
+ adc_data_I <= data2;
+ end case;
+ end process;
+
+
+ --------------------------------------------------------------------------------------------------
+ -- Sequence: Unclocked
+ P_Unclocked : process
+
+ begin
+ wait until tb_ParameterInitFlag;
+ tb_InitFlag <= true;
+
+ load_I <= '0';
+ RST_I <= '1';
+ STB_I_port <= '1';
+ CYC_I_port <= '1';
+ WE_I_port <= '0';
+ initial_address_I <= B"01_0000_0000_0000";
+ biggest_address_I <= B"11_1100_0000_0000";
+ pause_address_I <= B"00_0000_1000_0000";
+ enable_I <= '1';
+ wait for 1.5 * clk_Period;
+
+ RST_I <= '0';
+ wait for 1.0 * clk_Period;
+
+ load_I <= '1';
+ wait for 1.0 * clk_Period;
+
+
+
+
+ load_I <= '0';
+ wait until ADR_O_mem = B"00_0000_1000_0000";
+ wait for 8.0 * clk_Period;
+
+ pause_address_I <= B"01_0000_0000_0000";
+ wait for 20.0 * clk_Period;
+
+ enable_I <= '0';
+ wait for 8.0 * clk_Period;
+
+ enable_I <= '1';
+
+
+ wait until finish_O = '1';
+ wait for 2.0 * clk_Period;
+
+ tb_InitFlag <= false;
+ wait;
+
+
+ end process;
+
+
+
+ --------------------------------------------------------------------------------------------------
+ -- Conditional signals
+
+ P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i)
+
+ begin
+ if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
+ ACK_I_mem <= '1';
+ else
+ ACK_I_mem <= '0';
+ end if;
+
+ if CLK_I'event and CLK_I = '1' then
+ if RST_I = '1' then
+ DAT_I_mem <= (others => '0');
+ elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
+ DAT_I_mem <= DAT_I_mem + 1;
+ end if;
+ end if;
+
+ if CLK_I'event and CLK_I = '1' then
+ if RST_I = '1' then
+ i <= '0';
+ elsif STB_O_mem = '1' and CYC_O_mem = '1' then
+ i <= not(i);
+ end if;
+ end if;
+
+ end process;
+
+
+
+end architecture STIMULATOR;
+
+
+
+
+
+
+
+
+
+-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+ library ieee, std;
+ use ieee.std_logic_1164.all;
+
+
+
+-- Additional libraries used by Model Under Test.
+-- ...
+
+entity testbench is
+ generic (
+ MEM_ADD_WIDTH: integer := 14
+ );
+end testbench;
+
+architecture tbGeneratedCode of testbench is
+ -- ADC
+ signal adc_data_I: std_logic_vector (9 downto 0);
+ signal adc_sel_O: std_logic;
+ signal adc_clk_O: std_logic;
+ signal adc_sleep_O: std_logic;
+ signal adc_chip_sel_O: std_logic;
+ -- EPP
+ signal nStrobe_I: std_logic;
+ signal Data_IO: std_logic_vector (7 downto 0);
+ signal nAck_O: std_logic;
+ signal busy_O: std_logic;
+ signal PError_O: std_logic;
+ signal Sel_O: std_logic;
+ signal nAutoFd_I: std_logic;
+ signal PeriphLogicH_O: std_logic;
+ signal nInit_I: std_logic;
+ signal nFault_O: std_logic;
+ signal nSelectIn_I: std_logic;
+ -- Peripherals
+ signal reset_I: std_logic;
+ signal pll_clk_I: std_logic;
+begin
+ --------------------------------------------------------------------------------------------------
+ -- Instantiation of Stimulus.
+ U_stimulus_0 : entity work.stimulus
+ generic map (
+ MEM_ADD_WIDTH=> MEM_ADD_WIDTH
+ )
+ port map (
+ -- ADC
+ adc_data_I => adc_data_I,
+ adc_sel_O => adc_sel_O,
+ adc_clk_O => adc_clk_O,
+ adc_sleep_O => adc_sleep_O,
+ adc_chip_sel_O => adc_chip_sel_O,
+ -- EPP
+ nStrobe_I => nStrobe_I,
+ Data_IO => Data_IO,
+ nAck_O => nAck_O,
+ busy_O => busy_O,
+ PError_O => PError_O,
+ Sel_O => Sel_O,
+ nAutoFd_I => nAutoFd_I,
+ PeriphLogicH_O =>PeriphLogicH_O ,
+ nInit_I => nInit_I,
+ nFault_O => nFault_O,
+ nSelectIn_I => nSelectIn_I,
+ -- Peripherals
+ reset_I => reset_I,
+ pll_clk_I => pll_clk_I
+ );
+
+ --------------------------------------------------------------------------------------------------
+ -- Instantiation of Model Under Test.
+ U_outman_0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
+ generic map (
+ MEM_ADD_WIDTH=> MEM_ADD_WIDTH
+ )
+ port map (
+ -- ADC
+ adc_data_I => adc_data_I,
+ adc_sel_O => adc_sel_O,
+ adc_clk_O => adc_clk_O,
+ adc_sleep_O => adc_sleep_O,
+ adc_chip_sel_O => adc_chip_sel_O,
+ -- EPP
+ nStrobe_I => nStrobe_I,
+ Data_IO => Data_IO,
+ nAck_O => nAck_O,
+ busy_O => busy_O,
+ PError_O => PError_O,
+ Sel_O => Sel_O,
+ nAutoFd_I => nAutoFd_I,
+ PeriphLogicH_O =>PeriphLogicH_O ,
+ nInit_I => nInit_I,
+ nFault_O => nFault_O,
+ nSelectIn_I => nSelectIn_I,
+ -- Peripherals
+ reset_I => reset_I,
+ pll_clk_I => pll_clk_I
+ );
+
+end tbGeneratedCode;
+----------------------------------------------------------------------------------------------------
modular_oscilloscope/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property