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Rev 54 → Rev 55

/modular_oscilloscope/trunk/hdl/tbench/modullar_oscilloscope_tbench_text.vhd
318,7 → 318,7
nAutoFd_I <= '1';
nStrobe_I <= '1';
wait until (nAck_O = '1' and Sel_O = '1');
wait until (nAck_O = '1' and Sel_O = '1');
------------------------------------------------------------------------------------------------
-- Test 1
347,44 → 347,96
--
-- 09 Error_O R [ | | | | | | | |
-- | | | | | ErrN02| ErrN01| ErrN00]
test_number <= 1;
-- test_number <= 1;
--
-- WriteData(X"00", X"FFFE", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- WriteData(X"01", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- WriteData(X"02", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- WriteData(X"03", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- WriteData(X"04", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
--
-- ReadData(runflag, X"00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"01", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"02", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"03", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"04", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
--
-- wait for 50 ns;
-- ------------------------------------------------------------------------------------------------
-- -- Test 2 - DAQ Config
-- -- Writing in daq config register
-- test_number <= 2;
--
-- WriteData(X"05", X"07FF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
--
-- WriteData(X"05", X"0A00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
--
-- wait for 50 ns;
-- ------------------------------------------------------------------------------------------------
-- -- Test 3 - Test basic
-- -- daq freq = ctrl freq/2 (default), w/o trigger, w/o skipper, channels 1 and 2,
-- -- buffer size = 50h, continuous
-- test_number <= 3;
--
-- WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
-- WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (runflag = '1') loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- end loop;
--
-- wait for 50 ns;
-- ------------------------------------------------------------------------------------------------
-- -- Test 4 - Skipper
-- -- daq freq = ctrl freq/2 (default), w/o trigger, skipper = 3, channels 1 and 2,
-- -- buffer size = 80h, no continuous
-- test_number <= 4;
--
-- WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
-- WriteData(X"02", X"0080", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
-- WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
-- WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
-- WriteData(X"00", B"00000_00011_1_0_0_0_0_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
--
--
--
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- while (runflag = '1') loop
-- ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
-- end loop;
--
-- -- Some samples
-- -- 011011001 0 217
-- -- 011110110 1 246
-- -- 011111001 0 249 32
-- -- 100010110 1 278 32
-- -- 100011001 0 281 32
-- -- 100110110 1 310 32
-- -- 100111001 0 313 32
-- -- 101010110 1 342 32
--
--
WriteData(X"00", X"FFFE", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"01", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"02", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"03", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"04", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag,X"01", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"02", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"03", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"04", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 2 - DAQ Config
-- Writing in daq config register
test_number <= 2;
WriteData(X"05", X"07FF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
WriteData(X"05", X"0A00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 3 - Test basic
-- daq freq = ctrl freq/2 (default), w/o trigger, w/o skipper, channels 1 and 2,
-- buffer size = 50h, continuous
test_number <= 3;
-- Test 5 - Trigger - one shot
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
-- channels 1 and 2, buffer size = 100h, rissing edge, trigg offset = 0
test_number <= 5;
WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"02", X"0100", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
WriteData(X"03", X"0133", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
WriteData(X"00", B"00000_00101_1_1_0_1_0_1", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
392,20 → 444,8
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
end loop;
wait for 50 ns;
------------------------------------------------------------------------------------------------
-- Test 4 - Skipper
-- daq freq = ctrl freq/2 (default), w/o trigger, skipper = 3, channels 1 and 2,
-- buffer size = 80, no continuous
------------------------------------------------------------------------------------------------
-- Test 5 - Trigger - one shot
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
-- channels 1 and 2, buffer size = 100
------------------------------------------------------------------------------------------------
-- Test 6 - Trigger
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
-- channels 1, buffer size = 50
/modular_oscilloscope/trunk/hdl/ctrl/ctrl.vhd
132,9 → 132,10
--signal memwr_continuous: std_logic;
signal memwr_out_stb_daq: std_logic;
signal memwr_in_ack_mem: std_logic;
signal memwr_out_cyc_daq: std_logic;
signal memwr_out_cyc_daq: std_logic;
signal memwr_out_adr: std_logic_vector (13 downto 0);
signal memwr_in_dat: std_logic_vector (15 downto 0);
signal memwr_out_dat: std_logic_vector (15 downto 0);
-- Outmgr
--signal outmgr_reset: std_logic;
207,7 → 208,7
)
port map(
-- to memory
DAT_O_mem => DAT_O_memw, -- direct
DAT_O_mem => memwr_out_dat, -- direct
ADR_O_mem => memwr_out_adr,
CYC_O_mem => CYC_O_memw, -- direct
STB_O_mem => STB_O_memw, -- direct
267,8 → 268,8
CHANNELS_WIDTH => 1 --: integer := 4
)
port map(
data_I => DAT_I_daq(9 downto 0),
channel_I => chsel_channel,
data_I => memwr_out_dat(9 downto 0), -- values beign writed in memory
channel_I => memwr_out_dat(10 downto 10),
trig_channel_I => reg_trigger_channel,
address_I => memwr_out_adr,
final_address_I => reg_buffer_size,
327,8 → 328,10
------------------------------------------------------------------------------------------------
-- Assignments
ADR_O_memw <= memwr_out_adr;
DAT_O_memw <= memwr_out_dat;
ADR_O_daq <= '0' & chsel_channel(0) when strobe_adc = '0'
else "10";
else "10";
DAT_O_daq <= dat_to_adc;
CYC_O_daq <= strobe_adc or memwr_out_cyc_daq;
STB_O_daq <= strobe_adc or memwr_out_stb_daq;
368,7 → 371,7
when ST_RUNNING =>
 
memwr_reset <= '0';
if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr then
if reg_trigger_en = '1' and trigger_out_adr = memwr_out_adr and trigger_act = '1' then
memwr_en <= '0';
else
memwr_en <= '1';
/modular_oscilloscope/trunk/hdl/ctrl/memory_writer.vhd
89,7 → 89,7
type DataStatusType is (
FINISHED,
INIT,
-- INIT,
WORKING
);
115,8 → 115,8
reset_I => reset_count,
enable_I => enable_count
);
--------------------------------------------------------------------------------------------------
-- Combinational
128,7 → 128,7
ACK_I_mem = '1'
else
'0';
reset_count <= '1' when reset_I = '1' or s_finished = '1' else
reset_count <= '1' when reset_I = '1' or (s_finished = '1' and enable_count = '1') else
'0';
 
-- outputs
162,21 → 162,22
 
if CLK_I'event and CLK_I = '1' then
if reset_I = '1' or RST_I = '1' then
data_status <= INIT;
data_status <= WORKING;
s_STB_adc <= '0';
s_STB_mem <= '0';
data <= (others => '0');
elsif enable_I = '1' then
case data_status is
when INIT =>
-- this state is only necessary when there are adc convertions in every clock
-- (for the first convertion)
s_STB_adc <= '1';
s_STB_mem <= '1';
data_status <= WORKING;
-- when INIT =>
-- -- this state is only necessary when there are adc convertions in every clock
-- -- (for the first convertion)
-- s_STB_adc <= '1';
-- s_STB_mem <= '1';
-- data_status <= WORKING;
-- data <= DAT_I_adc; -- save data
when WORKING =>
if s_STB_adc = '1' and ACK_I_adc = '1' then
if ACK_I_adc = '1' then
s_STB_mem <= '1'; -- strobe when adc ack
data <= DAT_I_adc; -- save data
elsif s_STB_mem = '1' and ACK_I_mem = '1' then
183,13 → 184,13
s_STB_mem <= '0';
end if;
if s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_adc <= '1'; -- strobe when mem ack
elsif s_STB_adc = '1' and ACK_I_adc = '1' then
s_STB_adc <= '0';
end if;
-- if s_STB_mem = '1' and ACK_I_mem = '1' then
s_STB_adc <= '1'; -- strobe when mem ack
-- elsif s_STB_adc = '1' and ACK_I_adc = '1' then
-- s_STB_adc <= '0';
-- end if;
if continuous_I = '0' and s_finished = '1' then
if continuous_I = '0' and reset_count = '1' then
data_status <= FINISHED;
end if;
/modular_oscilloscope/trunk/hdl/ctrl/output_manager.vhd
29,10 → 29,10
 
--==================================================================================================
-- TO DO
-- NO Speed up address_counter
-- OK Full test of new architecture
-- OK Fix default value of s_finish signal
 
 
 
 
 
--==================================================================================================
 
 
107,8 → 107,10
signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
signal enable_read: std_logic;
signal enable_count: std_logic;
signal enable_strobe: std_logic;
signal s_finish: std_logic; -- register previous (and equal) to output
signal init: std_logic; -- register
signal same_address: std_logic;
 
begin
124,33 → 126,46
--------------------------------------------------------------------------------------------------
-- Status signals
-- there is an init signal because in the first read, address_counter may be = to pause_address_I
enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
(address_counter /= pause_address_I or init = '1')
P_pause: process (CLK_I, RST_I, address_counter, pause_address_I)
begin
if CLK_I'event and CLK_I = '1' then
if RST_I = '1' then
same_address <= '0';
elsif address_counter = pause_address_I then
same_address <= '1';
else
same_address <= '0';
end if;
end if;
end process;
P_flags: process(CLK_I, RST_I, enable_I, enable_count, load_I)
begin
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
-- when enable is '0', finish_O must be 0 again
if RST_I = '1' or enable_I = '0' then
init <= '1';
enable_strobe <= '0';
elsif (load_I = '1' and enable_I = '1') then
enable_strobe <= '1';
init <= '1';
elsif enable_count = '1' then
init <= '0';
end if;
end if;
end process;
enable_read <= '1' when WE_I_port = '0' and s_finish = '0' and
(same_address = '0' or init = '1') and enable_strobe = '1'
else '0';
 
enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
finish_O <= s_finish;
s_finish <= '1' when address_counter = initial_address_I and init = '0' else
'0';
 
-- P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
-- begin
-- if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
-- if RST_I = '1' then
-- --s_finish <= '0'; -- !! enable signal must be '0' until load
-- init <= '0';
-- elsif load_I = '1' then
-- --s_finish <= '0';
-- init <= '1';
-- -- elsif address_counter + 1 = initial_address_I then
-- -- s_finish <= '1';
-- -- init <= '0';
-- elsif enable_count = '1' then
-- init <= '0';
-- end if;
-- end if;
-- end process;
finish_O <= s_finish;
--------------------------------------------------------------------------------------------------
-- Address counter
159,15 → 174,12
if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
if RST_I = '1' then
address_counter <= (others => '0');
init <= '1';
elsif load_I = '1' then
elsif load_I = '1' and enable_I = '1' then
address_counter <= initial_address_I;
init <= '1';
elsif enable_count = '1' and address_counter >= biggest_address_I then
address_counter <= (others => '0');
elsif enable_count = '1' then
address_counter <= address_counter + 1;
init <= '0';
end if;
end if;
end process;
/modular_oscilloscope/trunk/hdl/ctrl/trigger_manager.vhd
79,6 → 79,7
signal selected_address: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
signal selected_address_reg: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
signal full_buffer: std_logic;
begin
100,7 → 101,6
truncate <= (offset_sign and add_plus_off_sign) or
(not(offset_sign) and not(add_plus_off_plus_fa_sign));
with truncate select
selected_address <= std_logic_vector(add_plus_off_plus_fa(MEM_ADD_WIDTH - 1 downto 0))
108,11 → 108,11
std_logic_vector(add_plus_off(MEM_ADD_WIDTH - 1 downto 0))
when others;
 
address_O <= selected_address_reg;
address_O <= selected_address_reg;
--------------------------------------------------------------------------------------------------
-- Trigger
higher <= '1' when data_I >= level_I else '0';
higher <= '1' when data_I >= level_I else '0';
P_trigger: process (clk_I, reset_I, enable_I, channel_I, trig_channel_I, higher_reg,
falling_I, higher, address_I, offset_sign, selected_address)
127,7 → 127,7
 
if channel_I = trig_channel_I then
if (higher_reg = '0' xor falling_I = '1') and
(higher = '1' xor falling_I = '1') and pre_trigger = '0'
(higher = '1' xor falling_I = '1') and pre_trigger = '0' and full_buffer = '1'
then -- trigger!
pre_trigger <= '1';
selected_address_reg <= selected_address;
135,7 → 135,7
trigger_O <= '1';
end if;
end if;
higher_reg <= higher;
higher_reg <= higher; -- higher_reg will be the previous higher
end if;
if pre_trigger = '1' and selected_address_reg = address_I then
147,7 → 147,18
end if;
end process;
-- When using negative offset for buffer, buffer must be filled before set trigger
P_wait_buffer_full: process (clk_I)
begin
if clk_I'event and clk_I = '1' then
if reset_I = '1' then
full_buffer <= '0';
elsif enable_I = '1' and (offset_sign = '0' or add_plus_off_sign = '0') and
full_buffer <= '0' then
full_buffer <= '1';
end if;
end if;
end process;
-- t pt f /f xor1 xor2 and
-- 000 1 0 1
159,15 → 170,4
-- 110 1 1 0
-- 111 0 0 1
 
 
 
end architecture;

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