URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
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- This comparison shows the changes necessary to convert path
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- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/trunk/rtl/verilog/uart_receiver.v
63,6 → 63,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.20 2001/12/10 19:52:05 gorban |
// Igor fixed break condition bugs |
// |
// Revision 1.19 2001/12/06 14:51:04 gorban |
// Bug in LSR[0] is fixed. |
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
426,7 → 429,7
if (wb_rst_i) |
counter_t <= #1 10'd639; // 10 bits for the default 8N1 |
else |
if(rf_push || rf_pop || rda_int || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level |
if(rf_push || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level |
counter_t <= #1 toc_value; |
else |
if (enable && counter_t != 10'b0) // we don't want to underflow |