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URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

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Rev 57 → Rev 58

/trunk/rtl/vhdl/rx_phase_det.vhd
46,6 → 46,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/12 17:06:41 gedra
-- Fixed bug with lock event generation.
--
-- Revision 1.3 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
117,7 → 120,7
spdif_in <= '0';
trans_cnt <= 0;
minpulse <= 0;
minp <= 0;
minp <= 8 * WISHBONE_FREQ;
last_cnt <= 0;
trans <= '0';
valid <= '0';
130,16 → 133,18
-- find the longest pulse, which is the bi-phase violation
-- also find the shortest pulse
zspdif_in <= spdif_in;
if zspdif_in /= spdif_in then
if zspdif_in /= spdif_in then -- input transition
mp_cnt <= 0;
trans <= '1';
last_cnt <= mp_cnt;
if mp_cnt > maxp then
maxp <= mp_cnt;
if trans_cnt > 0 then
if mp_cnt > maxp then
maxp <= mp_cnt;
end if;
if mp_cnt < minp then
minp <= mp_cnt;
end if;
end if;
if mp_cnt < minp then
minp <= mp_cnt;
end if;
else
trans <= '0';
if mp_cnt < 16 * WISHBONE_FREQ then
/trunk/rtl/vhdl/rx_cap_reg.vhd
45,6 → 45,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.2 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
104,10 → 107,8
ctrl_dout => cap_ctrl_dout,
ctrl_bits => cap_ctrl_bits);
bitlen <= to_integer(unsigned(cap_ctrl_bits(5 downto 0)));
chid <= cap_ctrl_bits(6);
cdata <= cap_ctrl_bits(7);
bitpos <= to_integer(unsigned(cap_ctrl_bits(15 downto 8)));
-- capture data register
CDAT: process (clk, rst)
120,6 → 121,8
cap_evt <= '0';
else
if rising_edge(clk) then
bitlen <= to_integer(unsigned(cap_ctrl_bits(5 downto 0)));
bitpos <= to_integer(unsigned(cap_ctrl_bits(15 downto 8)));
if bitlen > 0 then -- bitlen = 0 disables the capture function
-- bit counter, 0 to 191
if rx_block_start = '1' then
135,26 → 138,22
case d_enable is
when "0001" => -- user data channel A
if cdata = '0' and chid = '0' then
cap_new(0) <= ch_data;
cap_new(31 downto 1) <= cap_new(30 downto 0);
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0010" => -- user data channel B
if cdata = '0' and chid = '1' then
cap_new(0) <= ch_data;
cap_new(31 downto 1) <= cap_new(30 downto 0);
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0100" => -- channel status ch. A
if cdata = '1' and chid = '0' then
cap_new(0) <= ch_data;
cap_new(31 downto 1) <= cap_new(30 downto 0);
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "1000" => -- channel status ch. B
if cdata = '1' and chid = '1' then
cap_new(0) <= ch_data;
cap_new(31 downto 1) <= cap_new(30 downto 0);
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when others => null;
/trunk/rtl/vhdl/rx_spdif.vhd
45,6 → 45,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/12 17:06:41 gedra
-- Fixed bug with lock event generation.
--
-- Revision 1.3 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
61,10 → 64,10
use work.rx_package.all;
 
entity rx_spdif is
generic (DATA_WIDTH: integer range 16 to 32 := 16;
ADDR_WIDTH: integer range 8 to 64 := 8;
CH_ST_CAPTURE: integer range 0 to 8 := 0;
WISHBONE_FREQ: natural:= 33);
generic (DATA_WIDTH: integer range 16 to 32;
ADDR_WIDTH: integer range 8 to 64;
CH_ST_CAPTURE: integer range 0 to 8;
WISHBONE_FREQ: natural);
port (
-- Wishbone interface
wb_clk_i: in std_logic;
122,7 → 125,7
DB32: if DATA_WIDTH = 32 generate
data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout or
cap_dout(1) or cap_dout(2) or cap_dout(3) or cap_dout(4) or
cap_dout(5) or cap_dout(6) or cap_dout(7) when
cap_dout(5) or cap_dout(6) or cap_dout(7) or cap_dout(0) when
wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
end generate DB32;
 
276,7 → 279,7
istat_events(15 downto 5) <= (others => '0');
IS32: if DATA_WIDTH = 32 generate
istat_events(23 downto 16) <= istat_cap(7 downto 0);
istat_events(32 downto 24) <= (others => '0');
istat_events(31 downto 24) <= (others => '0');
end generate IS32;
 
-- capture registers
301,7 → 304,7
end generate CAPR;
-- unused capture registers set to zero
UCAPR: if CH_ST_CAPTURE < 8 generate
UC: for k in CH_ST_CAPTURE - 1 to 7 generate
UC: for k in CH_ST_CAPTURE to 7 generate
cap_dout(k) <= (others => '0');
end generate UC;
end generate UCAPR;
/trunk/rtl/vhdl/tx_bitbuf.vhd
45,6 → 45,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/17 17:21:11 gedra
-- Fixed bug.
--
-- Revision 1.1 2004/07/14 17:58:19 gedra
-- Transmitter channel status buffer.
--
69,6 → 72,9
 
architecture rtl of tx_bitbuf is
 
type buf_type is array (0 to 23) of std_logic_vector(7 downto 0);
signal buffer_a, buffer_b: buf_type;
begin
 
-- the byte buffer is 192 bits (24 bytes) for each channel
76,17 → 82,21
WBUF: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
buf_data_a(191 downto 0) <= (others => '0');
buf_data_b(191 downto 0) <= (others => '0');
for i in 0 to 23 loop
buffer_a(i) <= (others => '0');
buffer_b(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
if buf_wr = '1' and to_integer(unsigned(wb_adr_i)) < 24 then
buf_data_a(8*to_integer(unsigned(wb_adr_i)) + 7 downto to
8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
buf_data_b(8*to_integer(unsigned(wb_adr_i)) + 7 downto
8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
buffer_a(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
buffer_b(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
end if;
end if;
end process WBUF;
VGEN: for k in 0 to 23 generate
buf_data_a(8 * k + 7 downto 8 * k) <= buffer_a(k);
buf_data_b(8 * k + 7 downto 8 * k) <= buffer_b(k);
end generate VGEN;
end generate EB;
-- if the byte buffer is not enabled, set all bits to zero

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