OpenCores
URL https://opencores.org/ocsvn/mb-jpeg/mb-jpeg/trunk

Subversion Repositories mb-jpeg

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/tags/STEP1_2/system.log
0,0 → 1,6392
Xilinx Platform Studio (XPS)
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
 
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Copied file bitgen.ut from $XILINX_EDK/data/xflow directory to etc directory
Copied file bitgen_spartan3.ut from $XILINX_EDK/data directory to etc directory
Copied file fast_runtime.opt from $XILINX_EDK/data/xflow directory to etc directory
WARNING:MDT - Created an empty D:\mb-jpeg\data\system.ucf. If your design needs any constraints, please make changes to this UCF file.
Project Opened.
No changes to be saved in XMP file
Xilinx Platform Studio (XPS)
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
 
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
At Local date and time: Wed Nov 01 18:28:08 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/ system.mss
libgen
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/
system.mss
 
Output Directory (-od) : D:\mb-jpeg\
Part (-p) : virtex2p
 
Software Specification file : system.mss
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x00001fff) dlmb_cntlr dlmb
(0x00000000-0x00001fff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:74 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:100 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:108 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 8192
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
WARNING:MDT - Peripheral sysclk_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. sysclk_inv is not connected to any of the buses connected to a processor.
2. sysclk_inv does not have adresses set correctly.
3. sysclk_inv's address is not within any of the bridge windows connected to
a processor.
WARNING:MDT - Peripheral clk90_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. clk90_inv is not connected to any of the buses connected to a processor.
2. clk90_inv does not have adresses set correctly.
3. clk90_inv's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral ddr_clk90_inv is not connected to any of the processors
in the system. Check for the following reasons.
1. ddr_clk90_inv is not connected to any of the buses connected to a
processor.
2. ddr_clk90_inv does not have adresses set correctly.
3. ddr_clk90_inv's address is not within any of the bridge windows connected
to a processor.
WARNING:MDT - Peripheral dcm_0 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_0 is not connected to any of the buses connected to a processor.
2. dcm_0 does not have adresses set correctly.
3. dcm_0's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral dcm_1 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_1 is not connected to any of the buses connected to a processor.
2. dcm_1 does not have adresses set correctly.
3. dcm_1's address is not within any of the bridge windows connected to a
processor.
INFO:MDT - List of peripherals addressable from processor instance microblaze_0
:
- dlmb_cntlr
- ilmb_cntlr
- debug_module
- RS232_Uart_1
- SysACE_CompactFlash
- DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 
Building Directory Structure for microblaze_0
 
Generating platform libraries and device drivers ...
 
Running CopyFiles ...
 
Copying files for os standalone_v1_00_a from
C:\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\standalone_v1_00_a\ ...
 
Copying files for driver uartlite_v1_00_b from
C:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_00_b\src\ to
D:\mb-jpeg\microblaze_0\libsrc\uartlite_v1_00_b\ ...
 
Copying files for driver sysace_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\sysace_v1_00_a\ ...
 
Copying files for driver cpu_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\cpu_v1_00_a\ ...
 
Running DRCs for OSes, Drivers and Libraries ...
 
Running generate for OS'es, Drivers and Libraries ...
Copying Library Files ...
 
Running post_generate for OS'es, Drivers and Libraries ...
 
Running make for Drivers and Libraries ...
 
Configuring make for target include using:
 
make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
 
Configuring make for target libs using:
 
make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
Compiling commo
Compiling microblaze_disable_dcache.
Compiling microblaze_disable_exceptions.
Compiling microblaze_disable_icache.
Compiling microblaze_disable_interrupts.
Compiling microblaze_enable_dcache.
Compiling microblaze_enable_exceptions.
Compiling microblaze_enable_icache.
Compiling microblaze_enable_interrupts.
Compiling microblaze_init_dcache_range.
Compiling microblaze_init_icache_range.
Compiling microblaze_update_dcache.
Compiling microblaze_update_icache.
Compiling inbyte.
Compiling microblaze_exception_handler.
Compiling microblaze_exceptions_g.
Compiling microblaze_interrupt_handler.
Compiling microblaze_interrupts_g.
Compiling outbyte.
Compiling hw_exception_handler.
Compiling uartlit
Compiling sysac
Compiling cp
 
Libraries generated in D:\mb-jpeg\microblaze_0\lib\ directory
 
Running execs_generate for OS'es, Drivers and Libraries ...
 
LibGen Done.
mb-gcc -O2 TestApp_Memory/src/TestApp_Memory.c -o TestApp_Memory/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,TestApp_Memory/src/TestApp_Memory_LinkScr -g -I./microblaze_0/include/ -L./microblaze_0/lib/ \
-xl-mode-executable \
mb-size TestApp_Memory/executable.elf
text data bss dec hex filename
3768 324 8 4100 1004 TestApp_Memory/executable.elf
Done.
At Local date and time: Wed Nov 01 18:28:27 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
make: Nothing to be done for `program'.
Done.
At Local date and time: Wed Nov 01 18:28:36 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst system.mhs
 
Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst
system.mhs
Parse system.mhs ...
 
Read MPD definitions ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x00001fff) dlmb_cntlr dlmb
(0x00000000-0x00001fff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:74 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:100 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:108 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 8192
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
INFO: The DDR_256MB_32MX64_rank1_row13_col10_cl2_5 core has constraints automatically generated by XPS in implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
 
 
Modify defaults ...
 
Processing licensed instances ...
Completion time: 0.00 seconds
 
Creating hardware output directories ...
 
Managing hardware (BBD-specified) netlist files ...
 
Managing cache ...
 
Elaborating instances ...
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:134 - elaborating IP
 
Writing HDL for elaborated instances ...
 
Inserting wrapper level ...
Completion time: 4.00 seconds
 
Constructing platform-level signal connectivity ...
Completion time: 3.00 seconds
 
Writing (top-level) BMM ...
Writing BMM - D:\mb-jpeg\implementation\system.bmm
 
Writing (top-level and wrappers) HDL ...
 
Generating synthesis project file ...
 
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
microblaze_0_wrapper (microblaze_0) - D:\mb-jpeg\system.mhs:54 - Running XST
synthesis
mb_opb_wrapper (mb_opb) - D:\mb-jpeg\system.mhs:74 - Running XST synthesis
debug_module_wrapper (debug_module) - D:\mb-jpeg\system.mhs:82 - Running XST
synthesis
ilmb_wrapper (ilmb) - D:\mb-jpeg\system.mhs:100 - Running XST synthesis
dlmb_wrapper (dlmb) - D:\mb-jpeg\system.mhs:108 - Running XST synthesis
dlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:116 - Running XST
synthesis
ilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:125 - Running XST
synthesis
lmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:134 - Running XST synthesis
rs232_uart_1_wrapper (rs232_uart_1) - D:\mb-jpeg\system.mhs:141 - Running XST
synthesis
sysace_compactflash_wrapper (sysace_compactflash) - D:\mb-jpeg\system.mhs:157 -
Running XST synthesis
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - Running
XST synthesis
sysclk_inv_wrapper (sysclk_inv) - D:\mb-jpeg\system.mhs:218 - Running XST
synthesis
clk90_inv_wrapper (clk90_inv) - D:\mb-jpeg\system.mhs:227 - Running XST
synthesis
ddr_clk90_inv_wrapper (ddr_clk90_inv) - D:\mb-jpeg\system.mhs:236 - Running XST
synthesis
dcm_0_wrapper (dcm_0) - D:\mb-jpeg\system.mhs:245 - Running XST synthesis
dcm_1_wrapper (dcm_1) - D:\mb-jpeg\system.mhs:261 - Running XST synthesis
 
Running NGCBUILD ...
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - Running
NGCBUILD
 
Rebuilding cache ...
Total run time: 282.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh; cd .."
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Release 7.1.02i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input Format : MIXED
Input File Name : "system_xst.prj"
 
---- Target Parameters
Target Device : xc2vp30ff896-7
Output File Name : "../implementation/system.ngc"
 
---- Source Options
Top Module Name : system
 
---- Target Options
Add IO Buffers : NO
 
---- General Options
Optimization Goal : speed
RTL Output : YES
Hierarchy Separator : /
 
=========================================================================
 
WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort : 1
 
=========================================================================
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.
Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1452: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1458: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1464: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1470: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1476: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1482: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1488: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1494: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1500: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1506: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1512: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1520: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1528: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1536: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1544: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1552: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1560: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1568: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1576: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1584: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1592: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1600: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1608: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1616: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1624: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1632: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1640: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1646: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1652: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1658: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1664: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1670: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1676: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1682: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1688: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1694: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1700: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1706: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1712: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1718: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1724: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1730: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1736: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1742: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1748: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1754: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1760: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1766: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1772: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1778: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1784: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1790: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1796: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1802: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1808: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1814: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1820: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1826: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1832: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1838: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1844: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1850: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1856: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1864: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1872: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1880: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1888: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1896: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1904: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1912: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1920: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1928: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1936: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1944: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1952: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1960: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1968: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1976: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1984: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1992: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2000: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2008: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2016: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2024: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2032: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2040: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2048: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2056: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2064: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2072: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2080: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2088: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2096: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2104: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2112: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2120: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2128: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2136: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2144: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2152: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2160: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2168: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2176: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2184: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2192: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2200: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2208: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2216: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2224: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2232: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2240: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2248: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2256: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2264: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2272: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2280: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2288: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2296: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2304: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2312: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2320: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2328: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2336: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2344: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2352: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2360: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2368: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2376: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2384: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2392: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2400: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2408: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2416: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2424: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2432: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2438: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2444: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2450: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2456: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2462: Generating a Black Box for component <IBUF>.
Entity <system> analyzed. Unit <system> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Synthesizing Unit <system>.
Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".
WARNING:Xst:646 - Signal <pgassign2<3>> is assigned but never used.
WARNING:Xst:646 - Signal <pgassign3<0>> is assigned but never used.
Unit <system> synthesized.
 
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
=========================================================================
HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
Loading device for application Rf_Device from file '2vp30.nph' in environment c:/Xilinx.
 
Optimizing unit <system> ...
 
Mapping all equations...
Building and optimizing final netlist ...
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ../implementation/system.ngr
Top Level Output File Name : ../implementation/system.ngc
Output Format : ngc
Optimization Goal : speed
Keep Hierarchy : no
 
Design Statistics
# IOs : 140
 
Cell Usage :
# BELS : 2
# GND : 1
# VCC : 1
# IO Buffers : 140
# IBUF : 5
# IBUFG : 1
# IOBUF : 88
# OBUF : 46
# Others : 16
# clk90_inv_wrapper : 1
# dcm_0_wrapper : 1
# dcm_1_wrapper : 1
# ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper: 1
# ddr_clk90_inv_wrapper : 1
# debug_module_wrapper : 1
# dlmb_cntlr_wrapper : 1
# dlmb_wrapper : 1
# ilmb_cntlr_wrapper : 1
# ilmb_wrapper : 1
# lmb_bram_wrapper : 1
# mb_opb_wrapper : 1
# microblaze_0_wrapper : 1
# rs232_uart_1_wrapper : 1
# sysace_compactflash_wrapper : 1
# sysclk_inv_wrapper : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2vp30ff896-7
 
Number of bonded IOBs: 140 out of 556 25%
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
No clock signals found in this design
 
Timing Summary:
---------------
Speed Grade: -7
 
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.924ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1594 / 1506
-------------------------------------------------------------------------
Delay: 2.924ns (Levels of Logic = 1)
Source: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> (PAD)
Destination: fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> (PAD)
 
Data Path: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> to fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper:DDR_DQS_O<7> 1 0.000 0.332 ddr_256mb_32mx64_rank1_row13_col10_cl2_5 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_O<7>)
IOBUF:I->IO 2.592 iobuf_69 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>)
----------------------------------------
Total 2.924ns (2.592ns logic, 0.332ns route)
(88.7% logic, 11.3% route)
 
=========================================================================
CPU : 10.42 / 10.64 s | Elapsed : 10.00 / 10.00 s
-->
 
Total memory usage is 161848 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 144 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Copying Xilinx Implementation tool scripts..
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc
Release 7.1.02i - Xflow H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt
system.ngc
.... Copying flowfile c:/Xilinx/xilinx/data/fpga.flw into working directory
D:/mb-jpeg/implementation
 
Using Flow File: D:/mb-jpeg/implementation/fpga.flw
Using Option File(s):
D:/mb-jpeg/implementation/fast_runtime.opt
 
Creating Script File ...
 
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm
D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd
#----------------------------------------------#
Release 7.1.02i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc
system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd
 
Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...
Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ngc"
...
Loading design module "D:/mb-jpeg/implementation/sysclk_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ddr_clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_1_wrapper.ngc"...
 
Applying constraints in "system.ucf" to the design...
 
Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
"TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The
following new TNM groups and period specifications were generated at the DCM
output(s):
CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF
TS_sys_clk_pin*1.000000 HIGH 50.000000%
CLK90: TS_dcm_0_dcm_0_CLK90_BUF=PERIOD dcm_0_dcm_0_CLK90_BUF
TS_sys_clk_pin*1.000000 PHASE + 2.500000 nS HIGH 50.000000%
 
Processing BMM file ...
 
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I0/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I4/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I3/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I2/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I1/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_ADDR_CNTR/I_UP_DWN_COUNTER
/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM0REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM1REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM2REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM3REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM4REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_
5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM5REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM6REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM7REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM8REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM9REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM10REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM11REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM12REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM13REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM14REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM15REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM16REG_SP/REG' has unconnected
output p
in
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM17REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM18REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM19REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM20REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM21REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM22REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM23REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM24REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM25REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM26REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM27REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM28REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM29REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM30REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM31REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM32REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM33REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM34REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM35REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM36REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM37REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM38REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM39REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM40REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM41REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM42REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM43REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM44REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM45REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM46REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM47REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM48REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM49REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM50REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM51REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM52REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM53REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM54REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM55REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM56REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM57REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM58REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM59REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM60REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM61REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM62REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM63REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM64REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM65REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM66REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM67REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM68REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM69REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM70REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM71REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM72REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM73REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM74REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM75REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM76REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM77REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM78REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM79REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM80REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM81REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM82REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM83REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM84REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM85REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM86REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM87REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM88REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM89REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM90REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM91REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM92REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM93REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM94REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM95REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM96REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM97REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM98REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM99REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM100REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM101REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM102REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM103REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM104REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM105REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM106REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM107REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM108REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM109REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM110REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM111REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM112REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM113REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM114REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM115REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM116REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM117REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM118REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM119REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM120REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM121REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM122REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM123REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM124REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM125REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM126REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM127REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/read_blk/read_cnt/empty_blk/empty_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/write_blk/write_cnt/full_blk/full_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_r2_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_imm_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/halfword_unalignment' has no driver
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
debug_module/debug_module/BUFG_DRCK1 drives no clock pins
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 140
 
Writing NGD file "system.ngd" ...
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 
 
 
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b system.ngd system.pcf
#----------------------------------------------#
Release 7.1.02i - Map H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "2vp30ff896-7".
Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Writing design file "system_map.ncd"...
 
Design Summary:
Number of errors: 0
Number of warnings: 8
Logic Utilization:
Number of Slice Flip Flops: 1,541 out of 27,392 5%
Number of 4 input LUTs: 1,804 out of 27,392 6%
Logic Distribution:
Number of occupied Slices: 1,727 out of 13,696 12%
Number of Slices containing only related logic: 1,727 out of 1,727 100%
Number of Slices containing unrelated logic: 0 out of 1,727 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 2,502 out of 27,392 9%
Number used as logic: 1,804
Number used as a route-thru: 22
Number used for Dual Port RAMs: 512
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 164
 
Number of bonded IOBs: 139 out of 556 25%
IOB Flip Flops: 288
IOB Dual-Data Rate Flops: 87
Number of PPC405s: 0 out of 2 0%
Number of Block RAMs: 4 out of 136 2%
Number of MULT18X18s: 3 out of 136 2%
Number of GCLKs: 5 out of 16 31%
Number of DCMs: 2 out of 8 25%
Number of BSCANs: 1 out of 1 100%
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Number of RPM macros: 5
Total equivalent gate count for design: 393,895
Additional JTAG gate count for IOBs: 6,672
Peak Memory Usage: 199 MB
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Mapping completed.
See MAP report file "system_map.mrp" for details.
 
 
 
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - par H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
 
Constraints file: system.pcf.
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000
Celsius)
Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)
 
Device speed data version: "PRODUCTION 1.91 2005-07-22".
 
 
Device Utilization Summary:
 
Number of BSCANs 1 out of 1 100%
Number of BUFGMUXs 5 out of 16 31%
Number of DCMs 2 out of 8 25%
Number of External IOBs 139 out of 556 25%
Number of LOCed IOBs 139 out of 139 100%
 
Number of MULT18X18s 3 out of 136 2%
Number of RAMB16s 4 out of 136 2%
Number of SLICEs 1727 out of 13696 12%
 
 
Overall effort level (-ol): High (set by user)
Placer effort level (-pl): High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): High (set by user)
 
Starting initial Timing Analysis. REAL time: 7 secs
Finished initial Timing Analysis. REAL time: 7 secs
 
 
Starting Placer
 
Phase 1.1
Phase 1.1 (Checksum:9c1d97) REAL time: 9 secs
 
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 9 secs
 
WARNING:Place:414 - The input design contains local clock signal(s). To get the
better result, we recommend users run map with the "-timing" option set
before starting the placement.
Phase 3.2
...
...
 
 
Phase 3.2 (Checksum:98de91) REAL time: 16 secs
 
Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 16 secs
 
Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 16 secs
 
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 16 secs
 
Phase 7.8
....................................................................
...............................................................................
....
.................
......
...........
.......
Phase 7.8 (Checksum:f317bb) REAL time: 30 secs
 
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 30 secs
 
Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 36 secs
 
Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 36 secs
 
Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 38 secs
 
Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 38 secs
Writing design to file system.ncd
 
 
Total REAL time to Placer completion: 40 secs
Total CPU time to Placer completion: 39 secs
 
Starting Router
Phase 1: 17320 unrouted; REAL time: 51 secs
Phase 2: 15409 unrouted; REAL time: 53 secs
Phase 3: 4358 unrouted; REAL time: 55 secs
Phase 4: 4358 unrouted; (67802) REAL time: 56 secs
Phase 5: 4380 unrouted; (3513) REAL time: 1 mins
 
Phase 6: 4382 unrouted; (0) REAL time: 1 mins 1 secs
Phase 7: 0 unrouted; (0) REAL time: 1 mins 14 secs
Phase 8: 0 unrouted; (0) REAL time: 1 mins 16 secs
 
Total REAL time to Router completion: 1 mins 19 secs
Total CPU time to Router completion: 1 mins 17 secs
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| dlmb_port_BRAM_Clk | BUFGMUX5S| No | 1197 | 0.280 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| DBG_CLK_s | BUFGMUX4P| No | 139 | 0.280 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| ddr_clk_90_s | BUFGMUX3P| No | 275 | 0.147 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| clk_90_s | BUFGMUX0P| No | 38 | 0.145 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_SysACE_Compac | | | | | |
| tFlash_SysACE_CLK | Local| | 65 | 0.288 | 2.490 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/bscan_u | | | | | |
| pdate | Local| | 1 | 0.000 | 0.356 |
+---------------------+--------------+------+------+------------+-------------+
 
Timing Score: 0
 
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
NET "fpga_0_SysACE_CompactFlash_SysACE_CL | 30.000ns | 4.993ns | 2
K" PERIOD = 30 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TSCLK2CLK90_DDR_256MB_32MX64_rank1_row13_ | 2.500ns | 2.389ns | 0
col10_cl2_5 = MAXDELAY FROM TIMEGRP | | |
"OPB_Clk_DDR_256MB_32MX64_rank1_row13_ | | |
col10_cl2_5" TO TIMEGRP "Device_C | | |
lk90_in_DDR_256MB_32MX64_rank1_row13_col1 | | |
0_cl2_5" 2.5 ns | | |
--------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A | N/A
pin" 10 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.869ns | 10
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 5.328ns | 0
"dcm_0_dcm_0_CLK90_BUF" TS_sys_c | | |
lk_pin PHASE 2.5 ns HIGH 50% | | |
--------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 1 mins 22 secs
Total CPU time to PAR completion: 1 mins 19 secs
 
Peak Memory Usage: 239 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0
 
Writing design to file system.ncd
 
PAR done!
 
 
 
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
--------------------------------------------------------------------------------
Release 7.1.02i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
trce -e 3 -xml system.twx system.ncd system.pcf
 
 
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc2vp30,-7 (PRODUCTION 1.91 2005-07-22)
Report level: error report
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 224855 paths, 0 nets, and 13152 connections
 
Design statistics:
Minimum period: 9.869ns (Maximum frequency: 101.327MHz)
Maximum path delay from/to any node: 2.389ns
 
 
Analysis completed Wed Nov 01 18:35:51 2006
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 0
Number of info messages: 1
Total time: 8 secs
 
 
xflow done!
cd implementation; bitgen -w -f bitgen.ut system
Release 7.1.02i - Bitgen H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
Opened constraints file system.pcf.
 
Wed Nov 01 18:35:56 2006
 
Running DRC.
WARNING:PhysDesignRules:367 - The signal <lmb_bram/lmb_bram/BRAM_Clk_B> is
incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Creating bit mask...
Saving mask bit stream in "system.msk".
Bitstream generation is complete.
Done.
At Local date and time: Wed Nov 01 19:05:53 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...
make: Nothing to be done for `bits'.
Done.
At Local date and time: Wed Nov 01 19:05:57 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make init_bram; exit;" Started...
*********************************************
Initializing BRAM contents of the bitstream
*********************************************
bitinit system.mhs -lp D:/XilinxXUP/lib/ -pe microblaze_0 TestApp_Memory/executable.elf \
-bt implementation/system.bit -o implementation/download.bit
 
bitinit version Xilinx EDK 7.1.2 Build EDK_H.12.5.1
Copyright (c) Xilinx Inc. 2002.
 
Parsing MHS File system.mhs...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x00001fff) dlmb_cntlr dlmb
(0x00000000-0x00001fff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Initializing Memory...
Checking ELFs associated with MICROBLAZE instance microblaze_0 for overlap...
 
 
Analyzing file TestApp_Memory/executable.elf...
INFO:MDT - BRAM lmb_bram will be initialized with ELF of processor microblaze_0
Running Data2Mem with the following command:
data2mem -bm implementation/system_bd -bt implementation/system.bit -bd
TestApp_Memory/executable.elf tag lmb_bram -o b implementation/download.bit
Memory Initialization completed successfully.
Done.
WARNING:Portability:111 - Message file "MDT.msg" wasn't found.
 
Saving MSS changes, if any.
 
Loading Project File..
Linker Script generated successfully.
 
Saving MSS changes, if any.
 
Loading Project File..
At Local date and time: Wed Nov 01 19:09:15 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make init_bram; exit;" Started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst system.mhs
 
Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst
system.mhs
 
Parse system.mhs ...
 
Read MPD definitions ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x0000ffff) dlmb_cntlr dlmb
(0x00000000-0x0000ffff) ilmb_cntlr ilmb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
(0x70000000-0x7fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 65536
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
INFO: The DDR_256MB_32MX64_rank1_row13_col10_cl2_5 core has constraints automatically generated by XPS in implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
 
 
Modify defaults ...
 
Processing licensed instances ...
Completion time: 0.00 seconds
 
Creating hardware output directories ...
 
Managing hardware (BBD-specified) netlist files ...
 
Managing cache ...
microblaze (microblaze_0) - D:\mb-jpeg\system.mhs:48 - Copying cache
implementation netlist
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - Copying cache implementation
netlist
opb_mdm (debug_module) - D:\mb-jpeg\system.mhs:76 - Copying cache implementation
netlist
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - Copying cache implementation netlist
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - Copying cache implementation
netlist
opb_uartlite (rs232_uart_1) - D:\mb-jpeg\system.mhs:135 - Copying cache
implementation netlist
opb_sysace (sysace_compactflash) - D:\mb-jpeg\system.mhs:151 - Copying cache
implementation netlist
util_vector_logic (sysclk_inv) - D:\mb-jpeg\system.mhs:212 - Copying cache
implementation netlist
util_vector_logic (clk90_inv) - D:\mb-jpeg\system.mhs:221 - Copying cache
implementation netlist
util_vector_logic (ddr_clk90_inv) - D:\mb-jpeg\system.mhs:230 - Copying cache
implementation netlist
dcm_module (dcm_0) - D:\mb-jpeg\system.mhs:239 - Copying cache implementation
netlist
dcm_module (dcm_1) - D:\mb-jpeg\system.mhs:255 - Copying cache implementation
netlist
 
Elaborating instances ...
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:128 - elaborating IP
 
Writing HDL for elaborated instances ...
 
Inserting wrapper level ...
Completion time: 3.00 seconds
 
Constructing platform-level signal connectivity ...
Completion time: 4.00 seconds
 
Writing (top-level) BMM ...
Writing BMM - D:\mb-jpeg\implementation\system.bmm
 
Writing (top-level and wrappers) HDL ...
 
Generating synthesis project file ...
 
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
dlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:110 - Running XST
synthesis
ilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:119 - Running XST
synthesis
lmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:128 - Running XST synthesis
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:168 - Running
XST synthesis
 
Running NGCBUILD ...
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:168 - Running
NGCBUILD
 
Rebuilding cache ...
Total run time: 104.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh; cd .."
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Release 7.1.02i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input Format : MIXED
Input File Name : "system_xst.prj"
 
---- Target Parameters
Target Device : xc2vp30ff896-7
Output File Name : "../implementation/system.ngc"
 
---- Source Options
Top Module Name : system
 
---- Target Options
Add IO Buffers : NO
 
---- General Options
Optimization Goal : speed
RTL Output : YES
Hierarchy Separator : /
 
=========================================================================
 
WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort : 1
 
=========================================================================
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.
Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1452: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1458: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1464: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1470: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1476: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1482: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1488: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1494: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1500: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1506: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1512: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1520: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1528: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1536: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1544: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1552: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1560: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1568: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1576: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1584: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1592: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1600: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1608: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1616: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1624: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1632: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1640: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1646: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1652: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1658: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1664: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1670: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1676: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1682: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1688: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1694: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1700: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1706: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1712: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1718: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1724: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1730: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1736: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1742: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1748: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1754: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1760: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1766: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1772: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1778: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1784: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1790: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1796: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1802: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1808: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1814: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1820: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1826: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1832: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1838: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1844: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1850: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1856: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1864: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1872: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1880: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1888: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1896: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1904: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1912: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1920: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1928: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1936: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1944: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1952: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1960: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1968: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1976: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1984: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1992: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2000: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2008: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2016: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2024: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2032: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2040: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2048: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2056: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2064: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2072: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2080: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2088: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2096: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2104: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2112: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2120: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2128: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2136: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2144: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2152: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2160: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2168: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2176: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2184: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2192: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2200: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2208: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2216: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2224: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2232: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2240: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2248: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2256: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2264: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2272: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2280: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2288: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2296: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2304: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2312: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2320: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2328: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2336: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2344: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2352: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2360: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2368: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2376: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2384: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2392: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2400: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2408: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2416: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2424: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2432: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2438: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2444: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2450: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2456: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2462: Generating a Black Box for component <IBUF>.
Entity <system> analyzed. Unit <system> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Synthesizing Unit <system>.
Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".
WARNING:Xst:646 - Signal <pgassign2<3>> is assigned but never used.
WARNING:Xst:646 - Signal <pgassign3<0>> is assigned but never used.
Unit <system> synthesized.
 
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
=========================================================================
HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
Loading device for application Rf_Device from file '2vp30.nph' in environment c:/Xilinx.
 
Optimizing unit <system> ...
 
Mapping all equations...
Building and optimizing final netlist ...
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ../implementation/system.ngr
Top Level Output File Name : ../implementation/system.ngc
Output Format : ngc
Optimization Goal : speed
Keep Hierarchy : no
 
Design Statistics
# IOs : 140
 
Cell Usage :
# BELS : 2
# GND : 1
# VCC : 1
# IO Buffers : 140
# IBUF : 5
# IBUFG : 1
# IOBUF : 88
# OBUF : 46
# Others : 16
# clk90_inv_wrapper : 1
# dcm_0_wrapper : 1
# dcm_1_wrapper : 1
# ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper: 1
# ddr_clk90_inv_wrapper : 1
# debug_module_wrapper : 1
# dlmb_cntlr_wrapper : 1
# dlmb_wrapper : 1
# ilmb_cntlr_wrapper : 1
# ilmb_wrapper : 1
# lmb_bram_wrapper : 1
# mb_opb_wrapper : 1
# microblaze_0_wrapper : 1
# rs232_uart_1_wrapper : 1
# sysace_compactflash_wrapper : 1
# sysclk_inv_wrapper : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2vp30ff896-7
 
Number of bonded IOBs: 140 out of 556 25%
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
No clock signals found in this design
 
Timing Summary:
---------------
Speed Grade: -7
 
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.924ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1594 / 1506
-------------------------------------------------------------------------
Delay: 2.924ns (Levels of Logic = 1)
Source: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> (PAD)
Destination: fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> (PAD)
 
Data Path: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> to fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper:DDR_DQS_O<7> 1 0.000 0.332 ddr_256mb_32mx64_rank1_row13_col10_cl2_5 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_O<7>)
IOBUF:I->IO 2.592 iobuf_69 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>)
----------------------------------------
Total 2.924ns (2.592ns logic, 0.332ns route)
(88.7% logic, 11.3% route)
 
=========================================================================
CPU : 11.23 / 11.37 s | Elapsed : 11.00 / 11.00 s
-->
 
Total memory usage is 161848 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 144 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
Copying Xilinx Implementation tool scripts..
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc
Release 7.1.02i - Xflow H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt
system.ngc
 
Using Flow File: D:/mb-jpeg/implementation/fpga.flw
Using Option File(s):
D:/mb-jpeg/implementation/fast_runtime.opt
 
Creating Script File ...
 
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm
D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd
#----------------------------------------------#
Release 7.1.02i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc
system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd
 
Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...
Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ngc"
...
Loading design module "D:/mb-jpeg/implementation/sysclk_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ddr_clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_1_wrapper.ngc"...
 
Applying constraints in "system.ucf" to the design...
 
Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
"TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The
following new TNM groups and period specifications were generated at the DCM
output(s):
CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF
TS_sys_clk_pin*1.000000 HIGH 50.000000%
CLK90: TS_dcm_0_dcm_0_CLK90_BUF=PERIOD dcm_0_dcm_0_CLK90_BUF
TS_sys_clk_pin*1.000000 PHASE + 2.500000 nS HIGH 50.000000%
 
Processing BMM file ...
 
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I0/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I4/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I3/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I2/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I1/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_ADDR_CNTR/I_UP_DWN_COUNTER
/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM0REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM1REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM2REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM3REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM4REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_
5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM5REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM6REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM7REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM8REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM9REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM10REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM11REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM12REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM13REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM14REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM15REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM16REG_SP/REG' has unconnected
output p
in
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM17REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM18REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM19REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM20REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM21REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM22REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM23REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM24REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM25REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM26REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM27REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM28REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM29REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM30REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM31REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM32REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM33REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM34REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM35REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM36REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM37REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM38REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM39REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM40REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM41REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM42REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM43REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM44REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM45REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM46REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM47REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM48REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM49REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM50REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM51REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM52REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM53REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM54REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM55REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM56REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM57REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM58REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM59REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM60REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM61REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM62REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM63REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM64REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM65REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM66REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM67REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM68REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM69REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM70REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM71REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM72REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM73REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM74REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM75REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM76REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM77REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM78REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM79REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM80REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM81REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM82REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM83REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM84REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM85REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM86REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM87REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM88REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM89REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM90REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM91REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM92REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM93REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM94REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM95REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM96REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM97REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM98REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM99REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM100REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM101REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM102REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM103REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM104REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM105REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM106REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM107REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM108REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM109REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM110REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM111REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM112REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM113REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM114REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM115REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM116REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM117REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM118REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM119REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM120REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM121REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM122REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM123REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM124REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM125REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM126REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM127REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/read_blk/read_cnt/empty_blk/empty_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/write_blk/write_cnt/full_blk/full_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_r2_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_imm_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/halfword_unalignment' has no driver
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
debug_module/debug_module/BUFG_DRCK1 drives no clock pins
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 140
 
Writing NGD file "system.ngd" ...
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 
 
 
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b system.ngd system.pcf
#----------------------------------------------#
Release 7.1.02i - Map H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "2vp30ff896-7".
Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Writing design file "system_map.ncd"...
 
Design Summary:
Number of errors: 0
Number of warnings: 8
Logic Utilization:
Number of Slice Flip Flops: 1,541 out of 27,392 5%
Number of 4 input LUTs: 1,804 out of 27,392 6%
Logic Distribution:
Number of occupied Slices: 1,730 out of 13,696 12%
Number of Slices containing only related logic: 1,730 out of 1,730 100%
Number of Slices containing unrelated logic: 0 out of 1,730 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 2,502 out of 27,392 9%
Number used as logic: 1,804
Number used as a route-thru: 22
Number used for Dual Port RAMs: 512
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 164
 
Number of bonded IOBs: 139 out of 556 25%
IOB Flip Flops: 288
IOB Dual-Data Rate Flops: 87
Number of PPC405s: 0 out of 2 0%
Number of Block RAMs: 32 out of 136 23%
Number of MULT18X18s: 3 out of 136 2%
Number of GCLKs: 5 out of 16 31%
Number of DCMs: 2 out of 8 25%
Number of BSCANs: 1 out of 1 100%
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Number of RPM macros: 5
Total equivalent gate count for design: 2,228,903
Additional JTAG gate count for IOBs: 6,672
Peak Memory Usage: 201 MB
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Mapping completed.
See MAP report file "system_map.mrp" for details.
 
 
 
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - par H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
 
Constraints file: system.pcf.
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000
Celsius)
Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)
 
Device speed data version: "PRODUCTION 1.91 2005-07-22".
 
 
Device Utilization Summary:
 
Number of BSCANs 1 out of 1 100%
Number of BUFGMUXs 5 out of 16 31%
Number of DCMs 2 out of 8 25%
Number of External IOBs 139 out of 556 25%
Number of LOCed IOBs 139 out of 139 100%
 
Number of MULT18X18s 3 out of 136 2%
Number of RAMB16s 32 out of 136 23%
Number of SLICEs 1730 out of 13696 12%
 
 
Overall effort level (-ol): High (set by user)
Placer effort level (-pl): High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): High (set by user)
 
Starting initial Timing Analysis. REAL time: 7 secs
Finished initial Timing Analysis. REAL time: 7 secs
 
 
Starting Placer
 
Phase 1.1
Phase 1.1 (Checksum:9c2fff) REAL time: 9 secs
 
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 9 secs
 
WARNING:Place:414 - The input design contains local clock signal(s). To get the
better result, we recommend users run map with the "-timing" option set
before starting the placement.
Phase 3.2
.
.....
 
 
Phase 3.2 (Checksum:98de91) REAL time: 16 secs
 
Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 16 secs
 
Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 17 secs
 
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 17 secs
 
Phase 7.8
.........
..............
.......
....
................
.......
...
.......
Phase 7.8 (Checksum:f66cb1) REAL time: 29 secs
 
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 29 secs
 
Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 36 secs
 
Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 36 secs
 
Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 37 secs
 
Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 37 secs
Writing design to file system.ncd
 
Total REAL time to Placer completion: 40 secs
Total CPU time to Placer completion: 38 secs
 
Starting Router
Phase 1: 18351 unrouted; REAL time: 51 secs
Phase 2: 16336 unrouted; REAL time: 52 secs
Phase 3: 4547 unrouted; REAL time: 55 secs
Phase 4: 4547 unrouted; (20747) REAL time: 56 secs
 
Phase 5: 4558 unrouted; (5758) REAL time: 57 secs
Phase 6: 4558 unrouted; (0) REAL time: 58 secs
Phase 7: 0 unrouted; (0) REAL time: 1 mins 9 secs
Phase 8: 0 unrouted; (0) REAL time: 1 mins 12 secs
 
Total REAL time to Router completion: 1 mins 16 secs
Total CPU time to Router completion: 1 mins 13 secs
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| dlmb_port_BRAM_Clk | BUFGMUX5S| No | 1254 | 0.280 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| DBG_CLK_s | BUFGMUX4P| No | 139 | 0.279 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| ddr_clk_90_s | BUFGMUX3P| No | 275 | 0.154 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| clk_90_s | BUFGMUX0P| No | 38 | 0.140 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_SysACE_Compac | | | | | |
| tFlash_SysACE_CLK | Local| | 65 | 0.276 | 2.478 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/bscan_u | | | | | |
| pdate | Local| | 1 | 0.000 | 0.356 |
+---------------------+--------------+------+------+------------+-------------+
 
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
NET "fpga_0_SysACE_CompactFlash_SysACE_CL | 30.000ns | 5.134ns | 2
K" PERIOD = 30 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TSCLK2CLK90_DDR_256MB_32MX64_rank1_row13_ | 2.500ns | 2.171ns | 0
col10_cl2_5 = MAXDELAY FROM TIMEGRP | | |
"OPB_Clk_DDR_256MB_32MX64_rank1_row13_ | | |
col10_cl2_5" TO TIMEGRP "Device_C | | |
lk90_in_DDR_256MB_32MX64_rank1_row13_col1 | | |
0_cl2_5" 2.5 ns | | |
--------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A | N/A
pin" 10 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.813ns | 10
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 5.846ns | 0
"dcm_0_dcm_0_CLK90_BUF" TS_sys_c | | |
lk_pin PHASE 2.5 ns HIGH 50% | | |
--------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 1 mins 19 secs
Total CPU time to PAR completion: 1 mins 16 secs
 
Peak Memory Usage: 242 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0
 
Writing design to file system.ncd
 
 
PAR done!
 
 
 
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
--------------------------------------------------------------------------------
Release 7.1.02i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
trce -e 3 -xml system.twx system.ncd system.pcf
 
 
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc2vp30,-7 (PRODUCTION 1.91 2005-07-22)
Report level: error report
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 299723 paths, 0 nets, and 14046 connections
 
Design statistics:
Minimum period: 9.813ns (Maximum frequency: 101.906MHz)
Maximum path delay from/to any node: 2.171ns
 
 
Analysis completed Wed Nov 01 19:13:31 2006
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 0
Number of info messages: 1
Total time: 9 secs
 
 
xflow done!
cd implementation; bitgen -w -f bitgen.ut system
Release 7.1.02i - Bitgen H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
Opened constraints file system.pcf.
 
Wed Nov 01 19:13:36 2006
Running DRC.
WARNING:PhysDesignRules:367 - The signal <lmb_bram/lmb_bram/BRAM_Clk_B> is
incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Creating bit mask...
Saving mask bit stream in "system.msk".
Bitstream generation is complete.
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/ system.mss
libgen
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/
system.mss
Output Directory (-od) : D:\mb-jpeg\
Part (-p) : virtex2p
 
Software Specification file : system.mss
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x0000ffff) dlmb_cntlr dlmb
(0x00000000-0x0000ffff) ilmb_cntlr ilmb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
(0x70000000-0x7fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 65536
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
WARNING:MDT - Peripheral sysclk_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. sysclk_inv is not connected to any of the buses connected to a processor.
2. sysclk_inv does not have adresses set correctly.
3. sysclk_inv's address is not within any of the bridge windows connected to
a processor.
WARNING:MDT - Peripheral clk90_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. clk90_inv is not connected to any of the buses connected to a processor.
2. clk90_inv does not have adresses set correctly.
3. clk90_inv's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral ddr_clk90_inv is not connected to any of the processors
in the system. Check for the following reasons.
1. ddr_clk90_inv is not connected to any of the buses connected to a
processor.
2. ddr_clk90_inv does not have adresses set correctly.
3. ddr_clk90_inv's address is not within any of the bridge windows connected
to a processor.
WARNING:MDT - Peripheral dcm_0 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_0 is not connected to any of the buses connected to a processor.
2. dcm_0 does not have adresses set correctly.
3. dcm_0's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral dcm_1 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_1 is not connected to any of the buses connected to a processor.
2. dcm_1 does not have adresses set correctly.
3. dcm_1's address is not within any of the bridge windows connected to a
processor.
INFO:MDT - List of peripherals addressable from processor instance microblaze_0
:
- dlmb_cntlr
- ilmb_cntlr
- debug_module
- RS232_Uart_1
- SysACE_CompactFlash
- DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 
Building Directory Structure for microblaze_0
 
Generating platform libraries and device drivers ...
 
Running CopyFiles ...
 
Copying files for os standalone_v1_00_a from
C:\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\standalone_v1_00_a\ ...
 
Copying files for driver uartlite_v1_00_b from
C:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_00_b\src\ to
D:\mb-jpeg\microblaze_0\libsrc\uartlite_v1_00_b\ ...
 
Copying files for driver sysace_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\sysace_v1_00_a\ ...
 
Copying files for driver cpu_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\cpu_v1_00_a\ ...
 
Copying files for library xilfatfs_v1_00_a from
C:\EDK\sw\lib\sw_services\xilfatfs_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\xilfatfs_v1_00_a\ ...
 
Running DRCs for OSes, Drivers and Libraries ...
 
Running generate for OS'es, Drivers and Libraries ...
Copying Library Files ...
 
Running post_generate for OS'es, Drivers and Libraries ...
 
Running make for Drivers and Libraries ...
 
Configuring make for target include using:
 
make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
 
Configuring make for target libs using:
 
make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
Compiling commo
Compiling microblaze_disable_dcache.
Compiling microblaze_disable_exceptions.
Compiling microblaze_disable_icache.
Compiling microblaze_disable_interrupts.
Compiling microblaze_enable_dcache.
Compiling microblaze_enable_exceptions.
Compiling microblaze_enable_icache.
Compiling microblaze_enable_interrupts.
Compiling microblaze_init_dcache_range.
Compiling microblaze_init_icache_range.
Compiling microblaze_update_dcache.
Compiling microblaze_update_icache.
Compiling inbyte.
Compiling microblaze_exception_handler.
Compiling microblaze_exceptions_g.
Compiling microblaze_interrupt_handler.
Compiling microblaze_interrupts_g.
Compiling outbyte.
Compiling hw_exception_handler.
Compiling src/xilfatfs_alloc.
Compiling src/xilfatfs_close.
Compiling src/xilfatfs_directory.
Compiling src/xilfatfs_fat.
Compiling src/xilfatfs_fat16.
Compiling src/xilfatfs_fat32.
Compiling src/xilfatfs_filespec.
Compiling src/xilfatfs_filestatus.
Compiling src/xilfatfs_open.
Compiling src/xilfatfs_part.
Compiling src/xilfatfs_read.
Compiling src/xilfatfs_wd.
Compiling src/xilfatfs_stats.
Compiling src/xilfatfs_bufcache.
Compiling src/xilfatfs_write.
Compiling src/xilfatfs_sysace.
make clea
Compiling uartlit
Compiling sysac
Compiling cp
 
Libraries generated in D:\mb-jpeg\microblaze_0\lib\ directory
 
Running execs_generate for OS'es, Drivers and Libraries ...
 
LibGen Done.
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -g -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .data)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .data)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 00000657] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [00000658 -> 00000937] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000938 -> 00002077] overlaps section .text [00000000 -> 000118ab]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
At Local date and time: Wed Nov 01 19:15:16 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -g -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .data)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .data)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 00000657] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [00000658 -> 00000937] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000938 -> 00002077] overlaps section .text [00000000 -> 000118ab]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
At Local date and time: Wed Nov 01 19:15:23 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...
make: Nothing to be done for `bits'.
Done.
Linker Script generated successfully.
At Local date and time: Wed Nov 01 19:17:12 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -g -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 00000657] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [00000658 -> 00000937] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000938 -> 00002077] overlaps section .text [00000000 -> 000118a3]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
 
Saving MSS changes, if any.
 
Loading Project File..
 
Saving MSS changes, if any.
 
Loading Project File..
At Local date and time: Wed Nov 01 19:19:54 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/ system.mss
libgen
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/
system.mss
 
Output Directory (-od) : D:\mb-jpeg\
Part (-p) : virtex2p
 
Software Specification file : system.mss
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x0000ffff) dlmb_cntlr dlmb
(0x00000000-0x0000ffff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 65536
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
WARNING:MDT - Peripheral sysclk_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. sysclk_inv is not connected to any of the buses connected to a processor.
2. sysclk_inv does not have adresses set correctly.
3. sysclk_inv's address is not within any of the bridge windows connected to
a processor.
WARNING:MDT - Peripheral clk90_inv is not connected to any of the processors in
the system. Check for the following reasons.
1. clk90_inv is not connected to any of the buses connected to a processor.
2. clk90_inv does not have adresses set correctly.
3. clk90_inv's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral ddr_clk90_inv is not connected to any of the processors
in the system. Check for the following reasons.
1. ddr_clk90_inv is not connected to any of the buses connected to a
processor.
2. ddr_clk90_inv does not have adresses set correctly.
3. ddr_clk90_inv's address is not within any of the bridge windows connected
to a processor.
WARNING:MDT - Peripheral dcm_0 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_0 is not connected to any of the buses connected to a processor.
2. dcm_0 does not have adresses set correctly.
3. dcm_0's address is not within any of the bridge windows connected to a
processor.
WARNING:MDT - Peripheral dcm_1 is not connected to any of the processors in the
system. Check for the following reasons.
1. dcm_1 is not connected to any of the buses connected to a processor.
2. dcm_1 does not have adresses set correctly.
3. dcm_1's address is not within any of the bridge windows connected to a
processor.
INFO:MDT - List of peripherals addressable from processor instance microblaze_0
:
- dlmb_cntlr
- ilmb_cntlr
- debug_module
- RS232_Uart_1
- SysACE_CompactFlash
- DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 
Building Directory Structure for microblaze_0
 
Generating platform libraries and device drivers ...
 
Running CopyFiles ...
 
Copying files for os standalone_v1_00_a from
C:\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\standalone_v1_00_a\ ...
 
Copying files for driver uartlite_v1_00_b from
C:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_00_b\src\ to
D:\mb-jpeg\microblaze_0\libsrc\uartlite_v1_00_b\ ...
 
Copying files for driver sysace_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\sysace_v1_00_a\ ...
 
Copying files for driver cpu_v1_00_a from
C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\cpu_v1_00_a\ ...
 
Copying files for library xilfatfs_v1_00_a from
C:\EDK\sw\lib\sw_services\xilfatfs_v1_00_a\src\ to
D:\mb-jpeg\microblaze_0\libsrc\xilfatfs_v1_00_a\ ...
 
Running DRCs for OSes, Drivers and Libraries ...
 
Running generate for OS'es, Drivers and Libraries ...
Copying Library Files ...
 
Running post_generate for OS'es, Drivers and Libraries ...
 
Running make for Drivers and Libraries ...
 
Configuring make for target include using:
 
make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
 
Configuring make for target libs using:
 
make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
Compiling commo
Compiling microblaze_disable_dcache.
Compiling microblaze_disable_exceptions.
Compiling microblaze_disable_icache.
Compiling microblaze_disable_interrupts.
Compiling microblaze_enable_dcache.
Compiling microblaze_enable_exceptions.
Compiling microblaze_enable_icache.
Compiling microblaze_enable_interrupts.
Compiling microblaze_init_dcache_range.
Compiling microblaze_init_icache_range.
Compiling microblaze_update_dcache.
Compiling microblaze_update_icache.
Compiling inbyte.
Compiling microblaze_exception_handler.
Compiling microblaze_exceptions_g.
Compiling microblaze_interrupt_handler.
Compiling microblaze_interrupts_g.
Compiling outbyte.
Compiling hw_exception_handler.
Compiling src/xilfatfs_alloc.
Compiling src/xilfatfs_close.
Compiling src/xilfatfs_directory.
Compiling src/xilfatfs_fat.
Compiling src/xilfatfs_fat16.
Compiling src/xilfatfs_fat32.
Compiling src/xilfatfs_filespec.
Compiling src/xilfatfs_filestatus.
Compiling src/xilfatfs_open.
Compiling src/xilfatfs_part.
Compiling src/xilfatfs_read.
Compiling src/xilfatfs_wd.
Compiling src/xilfatfs_stats.
Compiling src/xilfatfs_bufcache.
Compiling src/xilfatfs_write.
Compiling src/xilfatfs_sysace.
make clea
Compiling uartlit
Compiling sysac
Compiling cp
 
Libraries generated in D:\mb-jpeg\microblaze_0\lib\ directory
 
Running execs_generate for OS'es, Drivers and Libraries ...
 
LibGen Done.
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 00000657] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [00000658 -> 00000937] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000938 -> 00002077] overlaps section .text [00000000 -> 000118a3]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
No changes to be saved in XMP file
Project Opened.
At Local date and time: Wed Nov 01 19:21:51 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 00000657] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [00000658 -> 00000937] overlaps section .text [00000000 -> 000118a3]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000938 -> 00002077] overlaps section .text [00000000 -> 000118a3]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
At Local date and time: Wed Nov 01 19:23:16 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (mb-bmp2jpg/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000000 -> 0000065b] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .sdata2 [0000065c -> 0000093f] overlaps section .text [00000000 -> 000118ab]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real: section .data [00000940 -> 0000207f] overlaps section .text [00000000 -> 000118ab]
collect2: ld returned 1 exit status
make: *** [mb-bmp2jpg/executable.elf] Error 1
Done.
At Local date and time: Wed Nov 01 19:24:50 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P -D__MICROBLAZE
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:290: warning: comparison is always true due to limited range of data type
mb-bmp2jpg/xupv2p.c:12:1: warning: "__MICROBLAZE" redefined
<command line>:5:1: warning: this is the location of the previous definition
mb-size mb-bmp2jpg/executable.elf
text data bss dec hex filename
25636 5293 7892 38821 97a5 mb-bmp2jpg/executable.elf
Done.
No changes to be saved in XMP file
Xilinx Platform Studio (XPS)
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
 
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
At Local date and time: Wed Nov 01 19:40:37 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P -D__MICROBLAZE
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:285: warning: comparison is always true due to limited range of data type
mb-bmp2jpg/xupv2p.c:12:1: warning: "__MICROBLAZE" redefined
<command line>:5:1: warning: this is the location of the previous definition
mb-size mb-bmp2jpg/executable.elf
text data bss dec hex filename
25544 5161 7892 38597 96c5 mb-bmp2jpg/executable.elf
Done.
At Local date and time: Wed Nov 01 19:40:55 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:285: warning: comparison is always true due to limited range of data type
mb-size mb-bmp2jpg/executable.elf
text data bss dec hex filename
25544 5161 7892 38597 96c5 mb-bmp2jpg/executable.elf
Done.
At Local date and time: Wed Nov 01 19:41:02 2006
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make init_bram; exit;" Started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst system.mhs
 
Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst
system.mhs
 
Parse system.mhs ...
 
Read MPD definitions ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to virtex2p
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to virtex2p
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to virtex2p
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to virtex2p
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x0000ffff) dlmb_cntlr dlmb
(0x00000000-0x0000ffff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Check platform configuration ...
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - 2 master(s) : 4 slave(s)
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - 1 master(s) : 1 slave(s)
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - 1 master(s) : 1 slave(s)
 
Check port drivers...
 
Check platform address map ...
 
Overriding system level properties ...
opb_v20 (mb_opb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
- tool overriding c_num_masters value 4 to 2
lmb_v10 (ilmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_v10 (dlmb) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
- tool overriding c_lmb_num_slaves value 4 to 1
lmb_bram_if_cntlr (dlmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
lmb_bram_if_cntlr (ilmb_cntlr) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:35 - tool overriding c_memsize value 2048 to 65536
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
 
Performing System level DRCs on properties...
 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...
INFO: The DDR_256MB_32MX64_rank1_row13_col10_cl2_5 core has constraints automatically generated by XPS in implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
 
 
Modify defaults ...
 
Processing licensed instances ...
Completion time: 0.00 seconds
 
Creating hardware output directories ...
 
Managing hardware (BBD-specified) netlist files ...
 
Managing cache ...
microblaze (microblaze_0) - D:\mb-jpeg\system.mhs:48 - Copying cache
implementation netlist
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:68 - Copying cache implementation
netlist
opb_mdm (debug_module) - D:\mb-jpeg\system.mhs:76 - Copying cache implementation
netlist
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:94 - Copying cache implementation netlist
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:102 - Copying cache implementation
netlist
lmb_bram_if_cntlr (dlmb_cntlr) - D:\mb-jpeg\system.mhs:110 - Copying cache
implementation netlist
lmb_bram_if_cntlr (ilmb_cntlr) - D:\mb-jpeg\system.mhs:119 - Copying cache
implementation netlist
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:128 - Copying cache implementation
netlist
opb_uartlite (rs232_uart_1) - D:\mb-jpeg\system.mhs:135 - Copying cache
implementation netlist
opb_sysace (sysace_compactflash) - D:\mb-jpeg\system.mhs:151 - Copying cache
implementation netlist
util_vector_logic (sysclk_inv) - D:\mb-jpeg\system.mhs:212 - Copying cache
implementation netlist
util_vector_logic (clk90_inv) - D:\mb-jpeg\system.mhs:221 - Copying cache
implementation netlist
util_vector_logic (ddr_clk90_inv) - D:\mb-jpeg\system.mhs:230 - Copying cache
implementation netlist
dcm_module (dcm_0) - D:\mb-jpeg\system.mhs:239 - Copying cache implementation
netlist
dcm_module (dcm_1) - D:\mb-jpeg\system.mhs:255 - Copying cache implementation
netlist
 
Elaborating instances ...
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:128 - elaborating IP
 
Writing HDL for elaborated instances ...
 
Inserting wrapper level ...
Completion time: 3.00 seconds
 
Constructing platform-level signal connectivity ...
Completion time: 4.00 seconds
 
Writing (top-level) BMM ...
Writing BMM - D:\mb-jpeg\implementation\system.bmm
 
Writing (top-level and wrappers) HDL ...
 
Generating synthesis project file ...
 
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:168 - Running
XST synthesis
 
Running NGCBUILD ...
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper
(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:168 - Running
NGCBUILD
 
Rebuilding cache ...
Total run time: 77.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh; cd .."
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Release 7.1.02i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input Format : MIXED
Input File Name : "system_xst.prj"
 
---- Target Parameters
Target Device : xc2vp30ff896-7
Output File Name : "../implementation/system.ngc"
 
---- Source Options
Top Module Name : system
 
---- Target Options
Add IO Buffers : NO
 
---- General Options
Optimization Goal : speed
RTL Output : YES
Hierarchy Separator : /
 
=========================================================================
 
WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Effort : 1
 
=========================================================================
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.
Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1452: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1458: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1464: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1470: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1476: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1482: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1488: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1494: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1500: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1506: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1512: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1520: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1528: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1536: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1544: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1552: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1560: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1568: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1576: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1584: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1592: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1600: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1608: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1616: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1624: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1632: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1640: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1646: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1652: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1658: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1664: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1670: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1676: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1682: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1688: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1694: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1700: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1706: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1712: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1718: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1724: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1730: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1736: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1742: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1748: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1754: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1760: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1766: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1772: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1778: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1784: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1790: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1796: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1802: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1808: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1814: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1820: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1826: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1832: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1838: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1844: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1850: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1856: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1864: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1872: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1880: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1888: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1896: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1904: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1912: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1920: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1928: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1936: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1944: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1952: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1960: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1968: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1976: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1984: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1992: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2000: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2008: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2016: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2024: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2032: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2040: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2048: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2056: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2064: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2072: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2080: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2088: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2096: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2104: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2112: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2120: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2128: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2136: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2144: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2152: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2160: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2168: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2176: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2184: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2192: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2200: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2208: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2216: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2224: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2232: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2240: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2248: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2256: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2264: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2272: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2280: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2288: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2296: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2304: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2312: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2320: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2328: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2336: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2344: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2352: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2360: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2368: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2376: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2384: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2392: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2400: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2408: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2416: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2424: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2432: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2438: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2444: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2450: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2456: Generating a Black Box for component <IBUFG>.
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 2462: Generating a Black Box for component <IBUF>.
Entity <system> analyzed. Unit <system> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Synthesizing Unit <system>.
Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".
WARNING:Xst:646 - Signal <pgassign2<3>> is assigned but never used.
WARNING:Xst:646 - Signal <pgassign3<0>> is assigned but never used.
Unit <system> synthesized.
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
=========================================================================
HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
Loading device for application Rf_Device from file '2vp30.nph' in environment c:/Xilinx.
 
Optimizing unit <system> ...
 
Mapping all equations...
Building and optimizing final netlist ...
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ../implementation/system.ngr
Top Level Output File Name : ../implementation/system.ngc
Output Format : ngc
Optimization Goal : speed
Keep Hierarchy : no
 
Design Statistics
# IOs : 140
 
Cell Usage :
# BELS : 2
# GND : 1
# VCC : 1
# IO Buffers : 140
# IBUF : 5
# IBUFG : 1
# IOBUF : 88
# OBUF : 46
# Others : 16
# clk90_inv_wrapper : 1
# dcm_0_wrapper : 1
# dcm_1_wrapper : 1
# ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper: 1
# ddr_clk90_inv_wrapper : 1
# debug_module_wrapper : 1
# dlmb_cntlr_wrapper : 1
# dlmb_wrapper : 1
# ilmb_cntlr_wrapper : 1
# ilmb_wrapper : 1
# lmb_bram_wrapper : 1
# mb_opb_wrapper : 1
# microblaze_0_wrapper : 1
# rs232_uart_1_wrapper : 1
# sysace_compactflash_wrapper : 1
# sysclk_inv_wrapper : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2vp30ff896-7
 
Number of bonded IOBs: 140 out of 556 25%
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
No clock signals found in this design
 
Timing Summary:
---------------
Speed Grade: -7
 
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.924ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1594 / 1506
-------------------------------------------------------------------------
Delay: 2.924ns (Levels of Logic = 1)
Source: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> (PAD)
Destination: fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> (PAD)
 
Data Path: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> to fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper:DDR_DQS_O<7> 1 0.000 0.332 ddr_256mb_32mx64_rank1_row13_col10_cl2_5 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_O<7>)
IOBUF:I->IO 2.592 iobuf_69 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>)
----------------------------------------
Total 2.924ns (2.592ns logic, 0.332ns route)
(88.7% logic, 11.3% route)
 
=========================================================================
CPU : 11.04 / 11.20 s | Elapsed : 11.00 / 11.00 s
-->
 
Total memory usage is 161848 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 144 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Copying Xilinx Implementation tool scripts..
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc
Release 7.1.02i - Xflow H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt
system.ngc
 
Using Flow File: D:/mb-jpeg/implementation/fpga.flw
Using Option File(s):
D:/mb-jpeg/implementation/fast_runtime.opt
 
Creating Script File ...
 
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm
D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd
#----------------------------------------------#
Release 7.1.02i - ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc
system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd
 
Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...
Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...
Loading design module
"D:/mb-jpeg/implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ngc"
...
Loading design module "D:/mb-jpeg/implementation/sysclk_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/ddr_clk90_inv_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...
Loading design module "D:/mb-jpeg/implementation/dcm_1_wrapper.ngc"...
 
Applying constraints in "system.ucf" to the design...
 
Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
"TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The
following new TNM groups and period specifications were generated at the DCM
output(s):
CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF
TS_sys_clk_pin*1.000000 HIGH 50.000000%
CLK90: TS_dcm_0_dcm_0_CLK90_BUF=PERIOD dcm_0_dcm_0_CLK90_BUF
TS_sys_clk_pin*1.000000 PHASE + 2.500000 nS HIGH 50.000000%
 
Processing BMM file ...
 
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I0/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I4/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I3/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I2/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I1/FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_ADDR_CNTR/I_UP_DWN_COUNTER
/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM0REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM1REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM2REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM3REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM4REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_
5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM5REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM6REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM7REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM8REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM9REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM10REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM11REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM12REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM13REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM14REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM15REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM16REG_SP/REG' has unconnected
output p
in
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM17REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM18REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM19REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM20REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM21REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM22REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM23REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM24REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM25REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM26REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM27REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM28REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM29REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM30REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM31REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM32REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM33REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM34REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM35REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM36REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM37REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM38REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM39REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM40REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM41REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM42REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM43REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM44REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM45REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM46REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM47REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM48REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM49REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM50REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM51REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM52REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM53REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM54REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM55REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM56REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM57REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM58REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM59REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM60REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM61REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM62REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM63REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM64REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM65REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM66REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM67REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM68REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM69REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM70REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM71REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM72REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM73REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM74REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM75REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM76REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM77REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM78REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM79REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM80REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM81REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM82REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM83REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM84REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM85REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM86REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM87REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM88REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM89REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM90REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM91REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM92REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM93REG_SP/REG' has unconnected
outp
ut pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM94REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM95REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM96REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM97REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM98REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM99REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM100REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM101REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM102REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM103REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM104REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM105REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM106REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM107REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM108REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM109REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM110REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM111REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM112REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM113REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM114REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM115REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM116REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM117REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM118REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM119REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM120REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM121REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM122REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM123REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM124REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM125REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM126REG_SP/REG' has unconnec
ted
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM127REG_SP/REG' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/read_blk/read_cnt/empty_blk/empty_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp
er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi
fo_v4_0/control/write_blk/write_cnt/full_blk/full_flag_logic/almst_flag_blk/m
odule_gen/2/carry_gen/skip_one/spacer_fdce' has unconnected output pin
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_r2_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_imm_unalignment' has no driver
WARNING:NgdBuild:452 - logical net
'microblaze_0/microblaze_0/Data_Flow_I/halfword_unalignment' has no driver
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
debug_module/debug_module/BUFG_DRCK1 drives no clock pins
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 140
 
Writing NGD file "system.ngd" ...
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 
 
 
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b system.ngd system.pcf
#----------------------------------------------#
Release 7.1.02i - Map H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Using target part "2vp30ff896-7".
Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Writing design file "system_map.ncd"...
 
Design Summary:
Number of errors: 0
Number of warnings: 8
Logic Utilization:
Number of Slice Flip Flops: 1,541 out of 27,392 5%
Number of 4 input LUTs: 1,804 out of 27,392 6%
Logic Distribution:
Number of occupied Slices: 1,730 out of 13,696 12%
Number of Slices containing only related logic: 1,730 out of 1,730 100%
Number of Slices containing unrelated logic: 0 out of 1,730 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 2,502 out of 27,392 9%
Number used as logic: 1,804
Number used as a route-thru: 22
Number used for Dual Port RAMs: 512
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 164
 
Number of bonded IOBs: 139 out of 556 25%
IOB Flip Flops: 288
IOB Dual-Data Rate Flops: 87
Number of PPC405s: 0 out of 2 0%
Number of Block RAMs: 32 out of 136 23%
Number of MULT18X18s: 3 out of 136 2%
Number of GCLKs: 5 out of 16 31%
Number of DCMs: 2 out of 8 25%
Number of BSCANs: 1 out of 1 100%
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Number of RPM macros: 5
Total equivalent gate count for design: 2,228,903
Additional JTAG gate count for IOBs: 6,672
Peak Memory Usage: 201 MB
 
NOTES:
 
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
 
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
 
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
 
Mapping completed.
See MAP report file "system_map.mrp" for details.
 
 
 
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - par H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
 
Constraints file: system.pcf.
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 17
days, this program will not operate. For more information about this product,
please refer to the Evaluation Agreement, which was shipped to you along with
the Evaluation CDs.
To purchase an annual license for this software, please contact your local
Field Applications Engineer (FAE) or salesperson. If you have any questions,
or if we can assist in any way, please send an email to: eval@xilinx.com
Thank You!
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000
Celsius)
Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)
 
Device speed data version: "PRODUCTION 1.91 2005-07-22".
 
 
Device Utilization Summary:
 
Number of BSCANs 1 out of 1 100%
Number of BUFGMUXs 5 out of 16 31%
Number of DCMs 2 out of 8 25%
Number of External IOBs 139 out of 556 25%
Number of LOCed IOBs 139 out of 139 100%
 
Number of MULT18X18s 3 out of 136 2%
Number of RAMB16s 32 out of 136 23%
Number of SLICEs 1730 out of 13696 12%
 
 
Overall effort level (-ol): High (set by user)
Placer effort level (-pl): High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): High (set by user)
 
Starting initial Timing Analysis. REAL time: 7 secs
Finished initial Timing Analysis. REAL time: 7 secs
 
 
Starting Placer
 
Phase 1.1
Phase 1.1 (Checksum:9c2fff) REAL time: 9 secs
 
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 9 secs
 
WARNING:Place:414 - The input design contains local clock signal(s). To get the
better result, we recommend users run map with the "-timing" option set
before starting the placement.
Phase 3.2
.
.....
 
 
Phase 3.2 (Checksum:98de91) REAL time: 16 secs
 
Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 16 secs
 
Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 16 secs
 
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 16 secs
 
Phase 7.8
................
.......
.......
....
................
.......
...
.......
Phase 7.8 (Checksum:f667c5) REAL time: 29 secs
 
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 29 secs
 
Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 36 secs
 
Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 36 secs
 
Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 38 secs
 
Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 38 secs
Writing design to file system.ncd
 
 
Total REAL time to Placer completion: 40 secs
Total CPU time to Placer completion: 38 secs
 
Starting Router
Phase 1: 18351 unrouted; REAL time: 53 secs
Phase 2: 16337 unrouted; REAL time: 54 secs
Phase 3: 4435 unrouted; REAL time: 57 secs
 
Phase 4: 4435 unrouted; (9599) REAL time: 58 secs
 
Phase 5: 4440 unrouted; (5758) REAL time: 59 secs
Phase 6: 4440 unrouted; (0) REAL time: 1 mins
Phase 7: 0 unrouted; (0) REAL time: 1 mins 12 secs
Phase 8: 0 unrouted; (0) REAL time: 1 mins 15 secs
 
Total REAL time to Router completion: 1 mins 19 secs
Total CPU time to Router completion: 1 mins 15 secs
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| dlmb_port_BRAM_Clk | BUFGMUX5S| No | 1254 | 0.280 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| DBG_CLK_s | BUFGMUX4P| No | 139 | 0.279 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| ddr_clk_90_s | BUFGMUX3P| No | 275 | 0.154 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
| clk_90_s | BUFGMUX0P| No | 38 | 0.140 | 1.257 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_SysACE_Compac | | | | | |
| tFlash_SysACE_CLK | Local| | 65 | 0.276 | 2.478 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/bscan_u | | | | | |
| pdate | Local| | 1 | 0.000 | 0.356 |
+---------------------+--------------+------+------+------------+-------------+
 
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
NET "fpga_0_SysACE_CompactFlash_SysACE_CL | 30.000ns | 5.134ns | 2
K" PERIOD = 30 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TSCLK2CLK90_DDR_256MB_32MX64_rank1_row13_ | 2.500ns | 2.171ns | 0
col10_cl2_5 = MAXDELAY FROM TIMEGRP | | |
"OPB_Clk_DDR_256MB_32MX64_rank1_row13_ | | |
col10_cl2_5" TO TIMEGRP "Device_C | | |
lk90_in_DDR_256MB_32MX64_rank1_row13_col1 | | |
0_cl2_5" 2.5 ns | | |
--------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A | N/A
pin" 10 ns HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.912ns | 16
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
HIGH 50% | | |
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 5.846ns | 0
"dcm_0_dcm_0_CLK90_BUF" TS_sys_c | | |
lk_pin PHASE 2.5 ns HIGH 50% | | |
--------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 1 mins 23 secs
Total CPU time to PAR completion: 1 mins 19 secs
 
Peak Memory Usage: 242 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0
 
Writing design to file system.ncd
 
 
PAR done!
 
 
 
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 7.1.02i - Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
 
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
--------------------------------------------------------------------------------
Release 7.1.02i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
trce -e 3 -xml system.twx system.ncd system.pcf
 
 
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc2vp30,-7 (PRODUCTION 1.91 2005-07-22)
Report level: error report
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 299723 paths, 0 nets, and 14046 connections
 
Design statistics:
Minimum period: 9.912ns (Maximum frequency: 100.888MHz)
Maximum path delay from/to any node: 2.171ns
 
 
Analysis completed Wed Nov 01 19:44:56 2006
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 0
Number of info messages: 1
Total time: 10 secs
 
 
xflow done!
cd implementation; bitgen -w -f bitgen.ut system
Release 7.1.02i - Bitgen H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2vp30.nph' in environment
c:/Xilinx.
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
Opened constraints file system.pcf.
 
Wed Nov 01 19:45:02 2006
 
Running DRC.
WARNING:PhysDesignRules:367 - The signal <lmb_bram/lmb_bram/BRAM_Clk_B> is
incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Creating bit mask...
Saving mask bit stream in "system.msk".
Bitstream generation is complete.
mb-gcc -O2 mb-bmp2jpg/bmp2jpg.c mb-bmp2jpg/ColorConversion.c mb-bmp2jpg/dct.c mb-bmp2jpg/huffman.c mb-bmp2jpg/jpeg.c mb-bmp2jpg/xupv2p.c mb-bmp2jpg/zzq.c -o mb-bmp2jpg/executable.elf \
-mno-xl-soft-mul -Wl,-T -Wl,mb-bmp2jpg_linker_script -I./microblaze_0/include/ -Imb-bmp2jpg/ -L./microblaze_0/lib/ \
-xl-mode-executable \
-D__XUPV2P
mb-bmp2jpg/huffman.c: In function `HuffmanEncodeFinishSend':
mb-bmp2jpg/huffman.c:285: warning: comparison is always true due to limited range of data type
mb-size mb-bmp2jpg/executable.elf
text data bss dec hex filename
25544 5161 7892 38597 96c5 mb-bmp2jpg/executable.elf
*********************************************
Initializing BRAM contents of the bitstream
*********************************************
bitinit system.mhs -lp D:/XilinxXUP/lib/ -pe microblaze_0 mb-bmp2jpg/executable.elf \
-bt implementation/system.bit -o implementation/download.bit
 
bitinit version Xilinx EDK 7.1.2 Build EDK_H.12.5.1
Copyright (c) Xilinx Inc. 2002.
 
Parsing MHS File system.mhs...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
_cntlr_v2_1_0.tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
tcl ...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl
...
 
Overriding IP level properties ...
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:60 - tool overriding c_family value virtex2 to
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
microblaze (microblaze_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
opb_mdm (debug_module) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
- tool overriding c_family value virtex2 to
bram_block (lmb_bram) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
mpd:39 - tool overriding c_family value virtex2 to
opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42
- tool overriding c_family value virtex2 to
dcm_module (dcm_0) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to
dcm_module (dcm_1) -
C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
mpd:56 - tool overriding c_family value virtex2 to
 
Performing IP level DRCs on properties...
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0x00000000-0x0000ffff) dlmb_cntlr dlmb
(0x00000000-0x0000ffff) ilmb_cntlr ilmb
(0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb
(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
 
Initializing Memory...
Checking ELFs associated with MICROBLAZE instance microblaze_0 for overlap...
 
 
Analyzing file mb-bmp2jpg/executable.elf...
INFO:MDT - BRAM lmb_bram will be initialized with ELF of processor microblaze_0
Running Data2Mem with the following command:
data2mem -bm implementation/system_bd -bt implementation/system.bit -bd
mb-bmp2jpg/executable.elf tag lmb_bram -o b implementation/download.bit
Memory Initialization completed successfully.
Done.
No changes to be saved in XMP file
/tags/STEP1_2/system.xmp
0,0 → 1,74
#Please do not modify this file by hand
XmpVersion: 7.1
IntStyle: default
ModuleSearchPath: D:/XilinxXUP/lib/
MHS File: system.mhs
MSS File: system.mss
NPL File: projnav/system.ise
Architecture: virtex2p
Device: xc2vp30
Package: ff896
SpeedGrade: -7
UseProjNav: 0
AddToNPL: 0
PNImportBitFile:
PNImportBmmFile:
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
SynProj: xst
ReloadPbde: 0
MainMhsEditor: 0
InsertNoPads: 0
HdlLang: VHDL
Simulator: mti
SimModel: BEHAVIORAL
SimXLib:
SimEdkLib:
MixLangSim: 1
UcfFile: data/system.ucf
Processor: microblaze_0
BootLoop: 0
XmdStub: 0
SwProj: TestApp_Memory
Processor: microblaze_0
Executable: TestApp_Memory/executable.elf
Source: TestApp_Memory/src/TestApp_Memory.c
DefaultInit: EXECUTABLE
InitBram: 1
Active: 0
CompilerOptLevel: 2
GlobPtrOpt: 0
DebugSym: 1
AsmOpt:
LinkOpt:
ProgStart:
StackSize:
HeapSize:
LinkerScript: TestApp_Memory/src/TestApp_Memory_LinkScr
ProgCCFlags:
SwProj: mb-bmp2jpg
Processor: microblaze_0
Executable: mb-bmp2jpg/executable.elf
Source: mb-bmp2jpg/bmp2jpg.c
Source: mb-bmp2jpg/ColorConversion.c
Source: mb-bmp2jpg/dct.c
Source: mb-bmp2jpg/huffman.c
Source: mb-bmp2jpg/jpeg.c
Source: mb-bmp2jpg/xupv2p.c
Source: mb-bmp2jpg/zzq.c
Header: mb-bmp2jpg/ejpgl.h
DefaultInit: EXECUTABLE
InitBram: 1
Active: 1
CompilerOptLevel: 2
GlobPtrOpt: 0
DebugSym: 0
AsmOpt:
LinkOpt:
ProgStart:
StackSize:
HeapSize:
LinkerScript: mb-bmp2jpg_linker_script
ProgCCFlags: -D__XUPV2P
/tags/STEP1_2/mb-bmp2jpg/xupv2p.c
0,0 → 1,181
#ifdef __XUPV2P
 
// Microblaze related declaration
 
#include <xparameters.h>
#include <sysace_stdio.h>
 
#include "xio.h"
 
#include "ejpgl.h"
 
#define __MICROBLAZE
#define __BIGENDIAN
 
// XUPV2P board related declaration
 
#define BMP_ADDRESS 0x30000000
#define BMP_MAXSIZE 4*1024*1024
 
 
SYSACE_FILE *infile;
SYSACE_FILE *outfile;
 
char* bmpimage;
int bmpsize;
 
INFOHEADER _bmpheader;
INFOHEADER *bmpheader;
JPEGHEADER _jpegheader;
 
int getbmpheader(INFOHEADER *header);
void writejpegfooter();
 
 
unsigned long htonl(unsigned long x) {
 
return ((((x)&0xff000000)>>24) | (((x)&0x00ff0000)>>8) | (((x)&0x0000ff00)<<8) | (((x)&0x000000ff)<<24));
}
 
unsigned short hton(unsigned short x) {
 
return ((((x) & 0xff00)>>8) | (((x) &0x00ff)<<8));
 
}
 
 
int openBMPJPG(int argc, char* bmpfilename, char* jpgfilename) {
int jpegheadersize;
bmpimage=(unsigned char*)BMP_ADDRESS;
bmpsize=0;
 
xil_printf("\r\nBMP2JPG Code Compiled at %s %s\r\n", __DATE__, __TIME__);
bmpfilename = "image01.bmp"; // argc argv is not accepted on XUPV2P yet
jpgfilename = "image01.jpg";
 
bmpheader=&_bmpheader;
 
if ((infile = sysace_fopen(bmpfilename, "r")) == NULL) { // not "rb"
xil_printf("\n\r%s is not a valid BMP-file",bmpfilename);
exit(0);
}
 
bmpsize = sysace_fread(bmpimage, 1, BMP_MAXSIZE, infile);
xil_printf("bmpsize %d\r\n", bmpsize);
if (bmpsize==BMP_MAXSIZE) {
xil_printf("\n\r%s is too large",bmpfilename);
exit(0);
}
 
 
if (getbmpheader(bmpheader) == 0) { //File is a valid BMP
xil_printf("\r\n%s is not a valid BMP-file",bmpfilename);
exit(0);
}
xil_printf("Image width: %d pixels\r\n", bmpheader->width);
xil_printf("Image height: %d pixels\r\n", bmpheader->height);
 
outfile = sysace_fopen(jpgfilename, "w"); // not "wb"
if (outfile == NULL) {
xil_printf("\r\nerror in writing jpg header");
exit(0);
}
jpegheadersize = writejpegheader(bmpheader, &_jpegheader);
if (jpegheadersize == 0) return 0;
sysace_fwrite(&_jpegheader,jpegheadersize,1,outfile);
return 1;
 
}
 
int closeBMPJPG() {
unsigned int col, cols, row, rows;
 
rows = bmpheader->height>>4;
cols = bmpheader->width>>4;
xil_printf("\r\nProcessed more than %d %dx%d-blocks.",(row-1)*cols,MATRIX_SIZE,MATRIX_SIZE); // +col
writejpegfooter();
 
sysace_fclose(outfile);
sysace_fclose(infile);
 
return 0;
}
 
static unsigned char buffer[MACRO_BLOCK_SIZE*3]; // move array on main memory
 
void get_MB(int mb_row, int mb_col, signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3]) {
unsigned int row, col;
int offset;
for(row = 0;row < MACRO_BLOCK_SIZE; row++) {
// offset = bmpsize-3*bmpheader->width*(row + 1 + mb_row*MATRIX_SIZE)+MATRIX_SIZE*3*mb_col;
// memcpy(pixelmatrix[row], bmpimage + offset, MATRIX_SIZE*3);
offset = bmpsize-3*bmpheader->width*(row + 1 + mb_row*MACRO_BLOCK_SIZE)+MACRO_BLOCK_SIZE*3*mb_col;
memcpy(buffer, bmpimage + offset, MACRO_BLOCK_SIZE*3);
for(col = 0; col < MACRO_BLOCK_SIZE*3; col++) {
pixelmatrix[row][col] = buffer[col]- 128;
}
}
 
}
 
void put_char(unsigned char c) {
 
sysace_fwrite(&c, 1, 1, outfile);
 
}
 
 
int getbmpheader(INFOHEADER *header)
{
memcpy(header, bmpimage+14, sizeof(INFOHEADER));
 
#if defined(__BIGENDIAN) // for Big Endian processors
 
header->size = htonl(header->size);
header->width = htonl(header->width);
header->height = htonl(header->height);
header->planes = hton(header->planes);
header->bits = hton(header->bits);
header->compression = htonl(header->compression);
header->imagesize = htonl(header->imagesize);
header->xresolution = htonl(header->xresolution);
header->yresolution= htonl(header->yresolution);
header->ncolours= htonl(header->ncolours);
header->importantcolours= htonl(header->importantcolours);
 
#endif
 
return 1;
 
}
 
void writejpegfooter()
{
unsigned char footer[2];
footer[0] = 0xff;
footer[1] = 0xd9;
// fseek(file,0,SEEK_END);
sysace_fwrite(footer,sizeof(footer),1, outfile);
 
}
 
 
 
 
 
 
 
#endif
 
 
 
/tags/STEP1_2/mb-bmp2jpg/bmp2jpg.c
0,0 → 1,50
#include <stdio.h>
#include "ejpgl.h"
 
extern INFOHEADER *bmpheader;
 
signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3];
signed char YMatrix[MATRIX_SIZE][MATRIX_SIZE];
signed char CrMatrix[MATRIX_SIZE][MATRIX_SIZE];
signed char CbMatrix[MATRIX_SIZE][MATRIX_SIZE];
 
 
int main(int argc, char* argv[])
{
int compression,sample;
unsigned int col, cols, row, rows;
 
openBMPJPG(argc, argv[1], argv[2]);
rows = bmpheader->height>>4;
cols = bmpheader->width>>4;
 
dct_init_start();
zzq_encode_init_start(compression);
vlc_init_start();
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
get_MB(row, col, pixelmatrix);
for(sample=0;sample<5;sample++) {
if(sample<4) {
RGB2YCrCb(pixelmatrix,YMatrix,CrMatrix,CbMatrix,sample);
dct(YMatrix,0);
} else {
dct(CrMatrix,1);
dct(CbMatrix,2);
}
}
}
}
dct_stop_done();
zzq_encode_stop_done();
vlc_stop_done();
 
closeBMPJPG();
return 0;
}
 
 
/tags/STEP1_2/mb-bmp2jpg/huffman.c
0,0 → 1,365
/*
Only encoder
This version works correctly, it is tested with testcase.jpg
The translation into real huffman codes works.
Changed: If huffman wants to send 0xFFxx (FF in one byte) than there must be 0x00 inserted between FF and xx
possible fault in finish send:
-must it be filled up with zeros? YES
-must it be filled up to one bye? or 2 byte? --> in this code there is filled up to 2 bytes, but I (joris) thinks this must be filled up to 1 byte.
still dont know
- 24-11-05 code clean up
- 24-11-05 tables added for color
 
 
 
Block numbers:
Y = 0
cb =1
cr= 2
*/
//---------------------------------------------------------------------------
 
#include "ejpgl.h"
 
static unsigned int vlc_remaining;
static unsigned char vlc_amount_remaining;
static unsigned char dcvalue[4]; // 3 is enough
 
int vlc_init_start() {
 
vlc_remaining=0x00;
vlc_amount_remaining=0x00;
memset(dcvalue, 0, 4);
return 0;
}
 
int vlc_stop_done() {
 
HuffmanEncodeFinishSend();
 
}
 
#define vlc_output_byte(c) put_char(c)
 
 
static unsigned char convertDCMagnitudeCLengthTable[16] = {
0x02, 0x02, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x00, 0x00, 0x00, 0x00
};
 
static unsigned short convertDCMagnitudeCOutTable[16] = {
0x0000, 0x0001, 0x0002, 0x0006, 0x000e, 0x001e, 0x003e, 0x007e,
0x00fe, 0x01fe, 0x03fe, 0x07fe, 0x0000, 0x0000, 0x0000, 0x0000
};
 
void ConvertDCMagnitudeC(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght)
{
unsigned char len;
/* if ((magnitude>16) || ((len=convertDCMagnitudeCLengthTable[magnitude])==0)) {
printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");
} */
*lenght = len;
*out = convertDCMagnitudeCOutTable[magnitude];
 
}
 
static unsigned char convertACMagnitudeCLengthTable[256] = {
0x02, 0x02, 0x03, 0x04, 0x05, 0x05, 0x06, 0x07, 0x09, 0x0a, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, // 00 - 0f
0x00, 0x04, 0x06, 0x08, 0x09, 0x0b, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 10 - 1f
0x00, 0x05, 0x08, 0x0a, 0x0c, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 20 - 2f
0x00, 0x05, 0x08, 0x0a, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 30 - 3f
0x00, 0x06, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 40 - 4f
0x00, 0x06, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 - 5f
0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 6f
0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 7f
0x00, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 8f
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 9f
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // a0 - af
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // b0 - bf
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // c0 - cf
0x00, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // d0 - df
0x00, 0x0e, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // e0 - ef
0x0a, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00
};
 
static unsigned short convertACMagnitudeCOutTable[256] = {
0x0000, 0x0001, 0x0004, 0x000a, 0x0018, 0x0019, 0x0038, 0x0078, 0x01f4, 0x03f6, 0x0ff4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 00 - 0f
0x0000, 0x000b, 0x0039, 0x00f6, 0x01f5, 0x07f6, 0x0ff5, 0xff88, 0xff89, 0xff8a, 0xff8b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 10 - 1f
0x0000, 0x001a, 0x00f7, 0x03f7, 0x0ff6, 0x7fc2, 0xff8c, 0xff8d, 0xff8e, 0xff8f, 0xff90, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 20 - 2f
0x0000, 0x001b, 0x00f8, 0x03f8, 0x0ff7, 0xff91, 0xff92, 0xff93, 0xff94, 0xff95, 0xff96, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 30 - 3f
0x0000, 0x003a, 0x01f6, 0xff97, 0xff98, 0xff99, 0xff9a, 0xff9b, 0xff9c, 0xff9d, 0xff9e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 40 - 4f
0x0000, 0x003b, 0x03f9, 0xff9f, 0xffa0, 0xffa1, 0xFFA2, 0xFFA3, 0xFFA4, 0xFFA5, 0xFFA6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 50 - 5f
0x0000, 0x0079, 0x07f7, 0xffa7, 0xffa8, 0xffa9, 0xffaa, 0xffab, 0xFFAc, 0xFFAf, 0xFFAe, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 60 - 6f
0x0000, 0x007a, 0x07f8, 0xffaf, 0xffb0, 0xFFB1, 0xFFB2, 0xFFB3, 0xFFB4, 0xFFB5, 0xFFB6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 70 - 7f
0x0000, 0x00f9, 0xffb7, 0xFFB8, 0xFFB9, 0xFFBa, 0xFFBb, 0xFFBc, 0xFFBd, 0xFFBe, 0xFFBf, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 80 - 8f
0x0000, 0x01f7, 0xffc0, 0xffc1, 0xFFC2, 0xFFC3, 0xFFC4, 0xFFC5, 0xFFC6, 0xFFC7, 0xFFC8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 90 - 9f
0x0000, 0x01f8, 0xffc9, 0xFFCa, 0xFFCb, 0xFFCc, 0xFFCd, 0xFFCe, 0xFFCf, 0xFFd0, 0xFFd1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // a0 - af
0x0000, 0x01f9, 0xFFD2, 0xFFD3, 0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7, 0xFFD8, 0xFFD9, 0xFFDa, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // b0 - bf
0x0000, 0x01fa, 0xFFDb, 0xFFDc, 0xFFDd, 0xFFDe, 0xFFDf, 0xFFe0, 0xFFe1, 0xFFe2, 0xFFe3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // c0 - cf
0x0000, 0x07f9, 0xFFE4, 0xFFE5, 0xFFE6, 0xFFE7, 0xFFE8, 0xFFE9, 0xFFEa, 0xFFEb, 0xFFEc, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // d0 - df
0x0000, 0x3fe0, 0xffed, 0xFFEe, 0xFFEf, 0xFFf0, 0xFFF1, 0xFFF2, 0xFFF3, 0xFFF4, 0xFFF5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // e0 - ef
0x03fa, 0x7fc3, 0xFFF6, 0xFFF7, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
 
//===========================================================================
void ConvertACMagnitudeC(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght)
{
unsigned char len;
len = convertACMagnitudeCLengthTable[magnitude];
/* if (!len) {
printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");
} */
*lenght = len;
*out = convertACMagnitudeCOutTable[magnitude];
}
 
static unsigned char convertDCMagnitudeYLengthTable[16] = {
0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x05,
0x06, 0x07, 0x08, 0x09, 0x00, 0x00, 0x00, 0x00
};
 
static unsigned short convertDCMagnitudeYOutTable[16] = {
0x0000, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x000e, 0x001e,
0x003e, 0x007e, 0x00fe, 0x01fe, 0x0000, 0x0000, 0x0000, 0x0000
};
 
//===========================================================================
void ConvertDCMagnitudeY(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght)
{
unsigned char len;
/* if ((magnitude>16) || ((len=convertDCMagnitudeYLengthTable[magnitude])==0)) {
printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");
} */
*lenght = len;
*out = convertDCMagnitudeYOutTable[magnitude];
}
 
static unsigned char convertACMagnitudeYLength[256] = {
0x04, 0x02, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x0a, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 00 - 0f
0x00, 0x04, 0x05, 0x07, 0x09, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 10 - 1f
0x00, 0x05, 0x08, 0x0a, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 20 - 2f
0x00, 0x06, 0x09, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 30 - 3f
0x00, 0x06, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 40 - 4f
0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 - 5f
0x00, 0x07, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 6f
0x00, 0x08, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 7f
0x00, 0x09, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 8f
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 9f
0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // a0 - af
0x00, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // b0 - bf
0x00, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // c0 - cf
0x00, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // d0 - df
0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // e0 - ef
0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00
};
 
static unsigned short convertACMagnitudeYOut[256] = {
0xFFFA, 0xFFF0, 0xFFF1, 0xFFF4, 0xFFFB, 0xFFFA, 0xFFF8, 0xFFF8, 0xFFF6, 0xFF82, 0xFF83, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 00 - 0f
0x0000, 0xFFFC, 0xFFFB, 0xFFF9, 0xFFF6, 0xFFF6, 0xFF84, 0xFF85, 0xFF86, 0xFF87, 0xFF88, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 10 - 1f
0x0000, 0xFFFC, 0xFFF9, 0xFFF7, 0xFFF4, 0xFF89, 0xFF8A, 0xFF8B, 0xFF8C, 0xFF8D, 0xFF8E, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 20 - 2f
0x0000, 0xFFFA, 0xFFF7, 0xFFF5, 0xFF8F, 0xFF90, 0xFF91, 0xFF92, 0xFF93, 0xFF94, 0xFF95, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 30 - 3f
0x0000, 0xFFFB, 0xFFF8, 0xFF96, 0xFF97, 0xFF98, 0xFF99, 0xFF9A, 0xFF9B, 0xFF9C, 0xFF9D, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 40 - 4f
0x0000, 0xFFFA, 0xFFF7, 0xFF9E, 0xFF9F, 0xFFA0, 0xFFA1, 0xFFA2, 0xFFA3, 0xFFA4, 0xFFA5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 50 - 5f
0x0000, 0xFFFB, 0xFFF6, 0xFFA6, 0xFFA7, 0xFFA8, 0xFFA9, 0xFFAA, 0xFFAB, 0xFFAC, 0xFFAD, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 60 - 6f
0x0000, 0xFFFA, 0xFFF7, 0xFFAE, 0xFFAF, 0xFFB0, 0xFFB1, 0xFFB2, 0xFFB3, 0xFFB4, 0xFFB5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 70 - 7f
0x0000, 0xFFF8, 0xFFC0, 0xFFB6, 0xFFB7, 0xFFB8, 0xFFB9, 0xFFBA, 0xFFBB, 0xFFBC, 0xFFBD, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 80 - 8f
0x0000, 0xFFF9, 0xFFBE, 0xFFBF, 0xFFC0, 0xFFC1, 0xFFC2, 0xFFC3, 0xFFC4, 0xFFC5, 0xFFC6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 90 - 9f
0x0000, 0xFFFA, 0xFFC7, 0xFFC8, 0xFFC9, 0xFFCA, 0xFFCB, 0xFFCC, 0xFFCD, 0xFFCE, 0xFFCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // a0 - af
0x0000, 0xFFF9, 0xFFD0, 0xFFD1, 0xFFD2, 0xFFD3, 0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7, 0xFFD8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // b0 - bf
0x0000, 0xFFFA, 0xFFD9, 0xFFDA, 0xFFDB, 0xFFDC, 0xFFDD, 0xFFDE, 0xFFDF, 0xFFE0, 0xFFE1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // c0 - cf
0x0000, 0xFFF8, 0xFFE2, 0xFFE3, 0xFFE4, 0xFFE5, 0xFFE6, 0xFFE7, 0xFFE8, 0xFFE9, 0xFFEA, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // d0 - df
0x0000, 0xFFEB, 0xFFEC, 0xFFED, 0xFFEE, 0xFFEF, 0xFFF0, 0xFFF1, 0xFFF2, 0xFFF3, 0xFFF4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // e0 - ef
0xFFF9, 0xFFF5, 0xFFF6, 0xFFF7, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};
 
//===========================================================================
void ConvertACMagnitudeY(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght)
{
unsigned char len;
 
len = convertACMagnitudeYLength[magnitude];
/* if (!len) {
#ifndef __MICROBLAZE
printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");
#endif
} */
*lenght = len;
*out = convertACMagnitudeYOut[magnitude];
}
 
char Extend (char additional, unsigned char magnitude)
{
int vt= 1 << (magnitude-1);
if ( additional < vt ) return (additional + (-1 << magnitude) + 1);
else return additional;
}
 
void ReverseExtend (char value, unsigned char *magnitude, unsigned char *bits)
{
// printf("reverseextend value= %d\n",*magnitude);
if (value >=0)
{
*bits=value;
}
else
{
value=-value;
*bits=~value;
}
*magnitude=0;
while (value !=0)
{
value>>=1;
++*magnitude;
}
// printf("reverseextend magnitude= %d bits= %d",magnitude,bits);
return;
}
 
void WriteRawBits16(unsigned char amount_bits, unsigned int bits) //*remaining needs bo be more than 8 bits because 8 bits could be added and ther ecould already be up ot 7 bits in *remaining
// this function collects bits to send
// if there less than 16 bits collected, nothing is send and these bits are stored in *remaining. In *amount_remaining there is stated how much bits are stored in *remaining
// if more than 16 bits are collected, 16 bits are send and the remaining bits are stored again
{
unsigned short int send;
unsigned int mask;
unsigned char send2;
int count;
mask=0x00; //init mask
vlc_remaining=(vlc_remaining<<amount_bits); //shift to make place for the new bits
for (count=amount_bits; count>0; count--) mask=(mask<<1)|0x01; //create mask for adding bit
vlc_remaining=vlc_remaining | (bits&mask); //add bits
vlc_amount_remaining=vlc_amount_remaining + amount_bits; //change *amount_remaining to the correct new value
if (vlc_amount_remaining >= 16) //are there more than 16 bits in buffer, send 16 bits
{
/* #ifndef __MICROBLAZE
if (vlc_amount_remaining >= 32 ) printf("ERROR, more bits to send %d",vlc_amount_remaining);
#endif */
send=vlc_remaining>>(vlc_amount_remaining-16); //this value can be send/stored (in art this can be dony by selecting bits)
send2=(send & 0xFF00) >>8;
vlc_output_byte(send2);
if (send2==0xFF)
{
send2=0x00;
vlc_output_byte(send2);
}
send2=send & 0xFF;
vlc_output_byte(send2);
if (send2==0xFF)
{
send2=0x00;
vlc_output_byte(send2);
}
vlc_amount_remaining=vlc_amount_remaining-16; //descrease by 16 because these are send
}
return;
}
 
void HuffmanEncodeFinishSend()
// There are still some bits left to send at the end of the 8x8 matrix (or maybe the file),
// the remaining bits are filled up with ones and send
// possible fault: -must it be filled up with ones?
{
unsigned short int send;
unsigned int mask;
int count;
mask=0x00; //init mask
if (vlc_amount_remaining >= 8) //2 bytes to send, send first byte
{
send=vlc_remaining>>(vlc_amount_remaining-8); //shift so that first byte is ready to send
vlc_output_byte(send&0xff);
if (send==0xFF) //is this still needed????
{
send=0x00;
vlc_output_byte(send&0xff);
}
vlc_amount_remaining=vlc_amount_remaining -8; // lower the value to the amount of bits that still needs to be send
}
if (vlc_amount_remaining >= 0) //there is a last byte to send
{
send=vlc_remaining<<(8-vlc_amount_remaining); //shift the last bits to send to the front of the byte
mask=0x00; //init mask
for (count=(8-vlc_amount_remaining); count>0; count--) mask=(mask<<1)|0x01; //create mask to fill byte up with ones
send=send | mask; //add the ones to the byte
vlc_output_byte(send&0xff);
vlc_amount_remaining=0x00; //is this needed?
}
return;
}
 
void HuffmanEncodeUsingDCTable(unsigned char magnitude)
// Translate magnitude into needed data (from table) and send it
{
unsigned char send;
unsigned short int huffmancode, huffmanlengt;
ConvertDCMagnitudeY(magnitude, &huffmancode, &huffmanlengt);
WriteRawBits16(huffmanlengt,huffmancode);
//printf("Write DC magnitude= %2x \n",magnitude);
//WriteRawBits16(0x08,magnitude,remaining,amount_remaining, file);
return;
}
 
void HuffmanEncodeUsingACTable(unsigned char mag)
// Translate magnitude into needed data (from table) and send it
{
unsigned char send;
unsigned short int huffmancode, huffmanlengt;
ConvertACMagnitudeY(mag, &huffmancode, &huffmanlengt);
WriteRawBits16(huffmanlengt,huffmancode);
return;
}
 
char EncodeDataUnit(char dataunit[64], unsigned int color)
{
char difference;
unsigned char magnitude,zerorun,ii,ert;
unsigned int bits;
unsigned char bit_char;
char last_dc_value;
//init
// PrintMatrix(dataunit) ;
last_dc_value = dcvalue[color];
difference = dataunit[0] - last_dc_value;
last_dc_value=dataunit[0];
ReverseExtend(difference, &magnitude,&bit_char);
bits = bit_char;
HuffmanEncodeUsingDCTable(magnitude);
WriteRawBits16(magnitude,bits);
zerorun=0;
ii=1;
while ( ii < 64 )
{
if (dataunit[ii] != 0 )
{
while ( zerorun >= 16 )
{
HuffmanEncodeUsingACTable(0xF0);
zerorun=zerorun-16;
// printf("16 zeros: %d\n",zerorun);
}
ReverseExtend(dataunit[ii],&magnitude,&bit_char);
bits=bit_char;
ert= ((int)zerorun *16); //ERROR !!!!!!!!!!!
ert=ert + magnitude;
HuffmanEncodeUsingACTable(ert);
WriteRawBits16(magnitude,bits);
zerorun=0;
}
else zerorun=zerorun+1;
ii++;
}
if ( zerorun != 0 )
{
HuffmanEncodeUsingACTable(0x00);
}
dcvalue[color] = last_dc_value;
return 0;
}
 
/tags/STEP1_2/mb-bmp2jpg/ejpgl.h
0,0 → 1,122
#ifndef _EJPGL_H
#define _EJPGL_H
 
#define MATRIX_SIZE 8
#define MACRO_BLOCK_SIZE 16
#define NUMBER_OF_PIXELS MATRIX_SIZE*MATRIX_SIZE
 
 
typedef struct {
unsigned int size; /* Header size in bytes */
int width,height; /* Width and height of image */
unsigned short int planes; /* Number of colour planes */
unsigned short int bits; /* Bits per pixel */
unsigned int compression; /* Compression type */
unsigned int imagesize; /* Image size in bytes */
int xresolution,yresolution; /* Pixels per meter */
unsigned int ncolours; /* Number of colours */
unsigned int importantcolours; /* Important colours */
unsigned char palette[1024]; /* Storage for palette */
} INFOHEADER;
 
typedef struct {
int restofheader; //TODO
INFOHEADER info; /* Information header */
} BMPHEADER;
 
typedef struct {
unsigned int row; /* Width and height of image */
unsigned int col; /* Width and height of image */
} BLOCKINFO;
 
typedef struct {
unsigned char QTMarker[2];
unsigned char Length[2];
unsigned char QTInfo[130]; //bit 0..3: number of QT (0..3, otherwise error)
// bit 4..7: precision of QT, 0 = 8 bit, otherwise 16 bit
// unsigned char ValuesQT[]; //max 192 values. 64*(precision+1) bytes
} QTINFO;
 
typedef struct {
unsigned char HTMarker[2];
unsigned char Length[2];
unsigned char HuffmanInfo[416]; //Array containing ALL huffman information
//For each color component holds:
//First byte is used as info byte, followed by 16 bytes with values used
//for counting the different huffman codes, finally the corresponding
//huffman codes will follow. This sequence can repeat it self for
//different Huffman tables, both DC or AC tables.
 
//The structure of the information byte is as follows:
//bit 0..3 : number of HT (0..3, otherwise error)
//bit 4 : type of HT, 0 = DC table, 1 = AC table
//bit 5..7 : not used, must be 0 (Used for progressive scan JPEG)
} HTINFO;
 
 
typedef struct {
unsigned char APP0Marker[2];
unsigned char Length[2];
unsigned char Identifier[5];
unsigned char Version[2];
unsigned char Units;
unsigned char XDensity[2];
unsigned char YDensity[2];
unsigned char ThumbWidth;
unsigned char ThumbHeight;
} APP0INFO;
 
typedef struct {
unsigned char SOF0Marker[2];
unsigned char Length[2];
unsigned char DataPrecision; //This is in bits/sample, usually 8 (12 and 16 not supported by most software).
unsigned char ImageHeight[2];
unsigned char ImageWidth[2];
unsigned char Components; //Usually 1 = grey scaled, 3 = color YcbCr or YIQ 4 = color CMYK
unsigned char ComponentInfo[3][3]; //Read each component data of 3 bytes. It contains,
//(component Id(1byte)(1 = Y, 2 = Cb, 3 = Cr, 4 = I, 5 = Q),
//sampling factors (1byte) (bit 0-3 vertical., 4-7 horizontal.),
//quantization table number (1 byte)).
} SOF0INFO;
 
typedef struct {
unsigned char SOSMarker[2];
unsigned char Length[2]; //This must be equal to 6+2*(number of components in scan).
unsigned char ComponentCount; //This must be >= 1 and <=4 (otherwise error), usually 1 or 3
unsigned char Component[3][2]; // For each component, read 2 bytes. It contains,
//1 byte Component Id (1=Y, 2=Cb, 3=Cr, 4=I, 5=Q),
//1 byte Huffman table to use :
//bit 0..3 : AC table (0..3)
//bit 4..7 : DC table (0..3)
unsigned char Ignore[3]; //We have to skip 3 bytes
} SOSINFO;
 
typedef struct {
unsigned char DRIMarker[2];
unsigned char Length[2];
unsigned char RestartInteral[2]; // Interval of the restart markers
} DRIINFO;
 
typedef struct {
unsigned char SOIMarker[2]; //Start of image marker
APP0INFO app0;
QTINFO qt;
SOF0INFO sof0;
HTINFO ht;
// DRIINFO dri;
SOSINFO sos;
} JPEGHEADER;
 
 
int openBMPJPG(int argc, char* bmpfilename, char* jpgfilename);
int closeBMPJPG();
 
 
void HuffmanEncodeFinishSend();
 
 
 
int idct8x8(int* fblock, char* sblock);
 
#endif
 
/tags/STEP1_2/mb-bmp2jpg/ColorConversion.c
0,0 → 1,27
#include "ejpgl.h"
 
#define RGB2Y(r, g, b) (((66*r + 129*g + 25*b + 128)>>8)+128)
#define RGB2Cr(r, g, b) (((-38*r - 74*g + 112*b + 128)>>8)+128)
#define RGB2Cb(r, g, b) (((112*r - 94*g - 18*b + 128)>>8)+128)
 
void RGB2YCrCb(signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3],signed char YMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CrMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CbMatrix[MATRIX_SIZE][MATRIX_SIZE], unsigned int sample)
{
unsigned int row, col, rowoffset, coloffset, xoffset, yoffset;
for(row = 0;row < MATRIX_SIZE; row++) {
for(col = 0; col < MATRIX_SIZE; col++) {
coloffset = (sample&0x01)*8;
rowoffset = (sample&0x02)*4;
YMatrix[row][col] = RGB2Y(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128;
if (col%2==0) {
yoffset = (sample&0x01)*4;
xoffset = (sample&0x02)*2;
if (row%2==0) {
CrMatrix[xoffset+(row>>1)][yoffset+(col>>1)] = RGB2Cr(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128;
} else {
CbMatrix[xoffset+((row)>>2)][yoffset+(col>>2)] = RGB2Cb(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128;
}
}
}
}
}
 
/tags/STEP1_2/mb-bmp2jpg/zzq.c
0,0 → 1,84
#include "ejpgl.h"
 
unsigned char quantization_table[MATRIX_SIZE][MATRIX_SIZE] ={
{4, 3, 3, 4, 4, 5, 6, 6},
{3, 3, 4, 4, 5, 6, 6, 6},
{4, 4, 4, 4, 5, 6, 6, 6},
{4, 4, 4, 5, 6, 6, 6, 6},
{4, 4, 5, 6, 6, 7, 7, 6},
{4, 5, 6, 6, 6, 7, 7, 6},
{6, 6, 6, 6, 7, 7, 7, 7},
{6, 6, 6, 7, 7, 7, 7, 7}
};
 
signed char bitstream[NUMBER_OF_PIXELS] ;
 
int zzq_encode_init_start(int compression) {
 
return 0;
}
 
int zzq_encode_stop_done() {
 
 
}
 
void zzq_encode(signed short pixelmatrix[MATRIX_SIZE][MATRIX_SIZE], int color)
{
int i, x, y, jumped, deltax, deltay;
x = y = deltax = deltay = jumped = 0;
 
for(i=0;i<NUMBER_OF_PIXELS;i++)
{
if(pixelmatrix[y][x]>0)
bitstream[i] = (pixelmatrix[y][x]>>quantization_table[y][x]);
else
bitstream[i] = -((-pixelmatrix[y][x])>>quantization_table[y][x]);
 
if((y == 0) || (y == MATRIX_SIZE-1)) { //on top or bottom side of matrix
if(!jumped) { //first jump to element on the right
x++;
jumped = 1;
} else { //modify direction
if(i<(NUMBER_OF_PIXELS>>1)) {
deltax = -1;
deltay = 1;
} else {
deltax = 1;
deltay = -1;
}
x += deltax;
y += deltay;
jumped = 0;
}
} else if ((x == 0) || (x == MATRIX_SIZE-1)) { //on left or right side of matrix
if(!jumped) { //jump to element below
y++;
jumped = 1;
} else { //modify direction
if(i<(NUMBER_OF_PIXELS>>1)) {
deltax = 1;
deltay = -1;
} else {
deltax = -1;
deltay = 1;
}
x += deltax;
y += deltay;
jumped = 0;
}
}
else {//not on the edges of the matrix
x += deltax;
y += deltay;
}
}
 
EncodeDataUnit(bitstream, color);
 
return;
 
}
/tags/STEP1_2/mb-bmp2jpg/jpeg.c
0,0 → 1,170
#include "ejpgl.h"
 
unsigned char qtable[64] = {16, 8, 8, 16, 12, 8, 16, 16, 16, 16, 16, 16, 16, 16,
16, 32, 32, 16, 16, 16, 16, 32, 32, 32, 32, 32, 64, 64, 64, 64, 64, 64, 64, 64, 64,
64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 128, 64, 64, 128, 128, 128, 128, 128, 64, 64,
128, 128, 128, 128, 128, 64, 128, 128, 128};
 
unsigned char huffmancount[4][16] = {{0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, //standard DC table count
{0x00,0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05,0x05,0x04,0x04,0x00,0x00,0x01,0x7D}, //standard AC table count
{0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, //standard DC table count
{0x00,0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05,0x05,0x04,0x04,0x00,0x00,0x01,0x7D}}; //standard AC table count
 
unsigned char huffDCvalues[12] ={0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b};// {0x00, 0x02, 0x03, 0x04, 0x05, 0x06, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E};
unsigned char huffACvalues[162] = {0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71,
0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64,
0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9,
0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9,
0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA};
 
int writejpegheader(INFOHEADER *header, JPEGHEADER *jpegheader)
{
unsigned int huffmantablesize, previoussize;
unsigned char QTcount, i, j, components, id, huffmantablecount;
unsigned short length, headerlength;
 
//Number of Quatization Tables
QTcount = 2;
headerlength = 12; //12 bytes are needed for the markers
huffmantablecount = 4; //2 AC and 2 DC tables
huffmantablesize = 0;
jpegheader->SOIMarker[0] = 0xff;
jpegheader->SOIMarker[1] = 0xd8;
 
//APP0 segment
jpegheader->app0.APP0Marker[0] = 0xff;
jpegheader->app0.APP0Marker[1] = 0xe0;
 
headerlength += 16; //APP0 marker is always 16 bytes long
jpegheader->app0.Length[0] = 0x00;
jpegheader->app0.Length[1] = 0x10;
jpegheader->app0.Identifier[0] = 0x4a;
jpegheader->app0.Identifier[1] = 0x46;
jpegheader->app0.Identifier[2] = 0x49;
jpegheader->app0.Identifier[3] = 0x46;
jpegheader->app0.Identifier[4] = 0x00;
jpegheader->app0.Version[0] = 0x01;
jpegheader->app0.Version[1] = 0x00;
jpegheader->app0.Units = 0x00;
jpegheader->app0.XDensity[0] = 0x00;
jpegheader->app0.XDensity[1] = 0x01;
jpegheader->app0.YDensity[0] = 0x00;
jpegheader->app0.YDensity[1] = 0x01;
jpegheader->app0.ThumbWidth = 0x00;
jpegheader->app0.ThumbHeight = 0x00;
 
//Quantization Table Segment
jpegheader->qt.QTMarker[0] = 0xff;
jpegheader->qt.QTMarker[1] = 0xdb;
length = (QTcount<<6) + QTcount + 2;
headerlength += length;
jpegheader->qt.Length[0] = (length & 0xff00)>>8;
jpegheader->qt.Length[1] = length & 0xff;
// jpegheader->qt.QTInfo = 0x00; // index = 0, precision = 0
//write Quantization table to header
i = 0;
 
for (id=0; id<QTcount; id++) {
jpegheader->qt.QTInfo[(id<<6)+id] = id;
for(i=0;i<64;i++) {
jpegheader->qt.QTInfo[i+1+id+(id<<6)] = qtable[i];
}
}
 
//Start of Frame segment
jpegheader->sof0.SOF0Marker[0] = 0xff;
jpegheader->sof0.SOF0Marker[1] = 0xc0;
if(header->bits == 8) {
components = 0x01;
}
else {
components = 0x03;
}
length = 8 + 3*components;
headerlength += length;
jpegheader->sof0.Length[0] = (length & 0xff00) >> 8;
jpegheader->sof0.Length[1] = length & 0xff;
jpegheader->sof0.DataPrecision = 0x08;
jpegheader->sof0.ImageHeight[0] = (header->height & 0xff00) >> 8;
jpegheader->sof0.ImageHeight[1] = header->height & 0xff;
jpegheader->sof0.ImageWidth[0] = (header->width & 0xff00) >> 8;
jpegheader->sof0.ImageWidth[1] = header->width & 0xff;
jpegheader->sof0.Components = components;
for (i=0; i < components; i++) {
jpegheader->sof0.ComponentInfo[i][0] = i+1; //color component
if(i==0) {
jpegheader->sof0.ComponentInfo[i][1] = 0x22; //4:2:0 subsampling
} else {
jpegheader->sof0.ComponentInfo[i][1] = 0x11; //4:2:0 subsampling
}
jpegheader->sof0.ComponentInfo[i][2] = (i==0)? 0x00 : 0x01; //quantization table ID
}
//Start of Huffman Table Segment
 
jpegheader->ht.HTMarker[0] = 0xff;
jpegheader->ht.HTMarker[1] = 0xc4;
 
//Set dummy HT segment length
length = 0;//tablecount*17;
jpegheader->ht.Length[0] = (length & 0xff00) >> 8;
jpegheader->ht.Length[1] = length & 0xff;
previoussize = 0;
for (id=0; id < huffmantablecount; id++) {
huffmantablesize = 0;
switch (id) {
case 0 : jpegheader->ht.HuffmanInfo[previoussize] = 0x00;
break;
case 1 : jpegheader->ht.HuffmanInfo[previoussize] = 0x10;
break;
case 2 : jpegheader->ht.HuffmanInfo[previoussize] = 0x01;
break;
case 3 : jpegheader->ht.HuffmanInfo[previoussize] = 0x11;
break;
}
for (i=1; i <= 16; i++) {
jpegheader->ht.HuffmanInfo[i+previoussize] = huffmancount[id][i-1];
huffmantablesize += huffmancount[id][i-1];
}
 
for (i=0; i < huffmantablesize; i++) {
jpegheader->ht.HuffmanInfo[i+previoussize+17] = (id%2 == 1)? huffACvalues[i] : huffDCvalues[i];
}
previoussize += huffmantablesize + 17;
}
//Set real HT segment length
length = 2+previoussize;
headerlength += length;
jpegheader->ht.Length[0] = (length & 0xff00) >> 8;
jpegheader->ht.Length[1] = length & 0xff;
//Reset marker segment
 
//Start of Scan Header Segment
jpegheader->sos.SOSMarker[0] = 0xff;
jpegheader->sos.SOSMarker[1] = 0xda;
length = 6 + (components<<1);
headerlength += length;
jpegheader->sos.Length[0] = (length & 0xff00) >> 8;
jpegheader->sos.Length[1] = length & 0xff;
jpegheader->sos.ComponentCount = components; //number of color components in the image
jpegheader->sos.Component[0][0] = 0x01; //Y component
jpegheader->sos.Component[0][1] = 0x00; //indexes of huffman tables for Y-component
if (components == 0x03) {
jpegheader->sos.Component[1][0] = 0x02; //the CB component
jpegheader->sos.Component[1][1] = 0x11; //indexes of huffman tables for CB-component
jpegheader->sos.Component[2][0] = 0x03; //The CR component
jpegheader->sos.Component[2][1] = 0x11; //indexes of huffman tables for CR-component
}
//following bytes are ignored since progressive scan is not to be implemented
jpegheader->sos.Ignore[0] = 0x00;
jpegheader->sos.Ignore[1] = 0x3f;
jpegheader->sos.Ignore[2] = 0x00;
 
return headerlength;
 
}
 
/tags/STEP1_2/mb-bmp2jpg/dct.c
0,0 → 1,584
#include "ejpgl.h"
 
extern signed int weights[512];
signed short dctresult[MATRIX_SIZE][MATRIX_SIZE];
 
int dct_init_start() {
 
return 0;
 
}
 
int dct_stop_done() {
 
return 0;
}
 
/*
Function Name: dct
 
Operation: Find the 8x8 DCT of an array using separable DCT
First, finds 1-d DCT along rows, storing the result in inter[][]
Then, 1-d DCT along columns of inter[][] is found
 
Input: pixels is the 8x8 input array
 
Output: dct is the 8x8 output array
*/
 
void dct(signed char pixels[8][8], int color)
{
int inr, inc; /* rows and columns of input image */
int intr, intc; /* rows and columns of intermediate image */
int outr, outc; /* rows and columns of dct */
int f_val; /* cumulative sum */
int inter[8][8]; /* stores intermediate result */
int i,j,k;
k=0;
 
for (intr=0; intr<8; intr++)
for (intc=0; intc<8; intc++) {
for (i=0,f_val=0; i<8; i++) {
f_val += (pixels[intr][i]* weights[k]);//cos((double)(2*i+1)*(double)intc*PI/16);
k++;
}
if (intc!=0) inter[intr][intc] = f_val>>15;
else inter[intr][intc] = (11585*(f_val>>14))>>15;
 
}
 
/* find 1-d dct along columns */
 
for (outc=0, k=0; outc<8; outc++)
for (outr=0; outr<8; outr++) {
for (i=0,f_val=0; i<8; i++) {
f_val += (inter[i][outc] *weights[k]);
k++;
}
if (outr!=0) dctresult[outr][outc] = f_val>>15;
else dctresult[outr][outc] = (11585*(f_val>>14)>>15);
}
 
zzq_encode(dctresult, color);
return;
 
}
 
 
signed int weights[512] = {
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16384,
16069,
13623,
9102,
3196,
-3196,
-9102,
-13623,
-16069,
15137,
6270,
-6270,
-15137,
-15137,
-6270,
6270,
15137,
13623,
-3196,
-16069,
-9103,
9102,
16069,
3196,
-13623,
11585,
-11585,
-11585,
11585,
11585,
-11585,
-11585,
11585,
9102,
-16069,
3196,
13623,
-13623,
-3197,
16069,
-9102,
6270,
-15137,
15137,
-6270,
-6270,
15137,
-15137,
6270,
3196,
-9103,
13623,
-16069,
16069,
-13623,
9102,
-3196
};
 
 
/tags/STEP1_2/system.mss
0,0 → 1,104
 
PARAMETER VERSION = 2.2.0
 
 
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = RS232_Uart_1
PARAMETER STDOUT = RS232_Uart_1
END
 
 
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
 
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart_1
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysace
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = SysACE_CompactFlash
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddr
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sysclk_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = clk90_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ddr_clk90_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_1
END
 
 
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilfatfs
PARAMETER LIBRARY_VER = 1.00.a
PARAMETER CONFIG_WRITE = true
PARAMETER CONFIG_MAXFILES = 2
PARAMETER CONFIG_BUFCACHE_SIZE = 2560
END
 
/tags/STEP1_2/mb-bmp2jpg_linker_script
0,0 → 1,119
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 7.1.2EDK_H.12.5.1 */
/* */
/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
 
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
 
/* Define Memories in the system */
 
MEMORY
{
DDR_256MB_32MX64_rank1_row13_col10_cl2_5_C_MEM0_BASEADDR : ORIGIN = 0x70000000, LENGTH = 0x0FFFFFFF
ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x0000FFFF
}
 
/* Specify the default entry point to the program */
 
ENTRY(_start)
 
/* Define the sections, and where they are mapped in memory */
 
SECTIONS
{
.text : {
__text_start = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
__text_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
__rodata_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
. = ALIGN(8);
__sdata2_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
__sbss2_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
__data_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
__sdata_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.sbss : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
. = ALIGN(8);
__sbss_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
.eh_frame : {
__eh_frame_start = .;
*(.eh_frame)
__eh_frame_end = .;
} > ilmb_cntlr_dlmb_cntlr
 
PROVIDE (_SDA_BASE_ = __sdata_start + (__sbss_end - __sdata_start / 2 ));
 
PROVIDE (_SDA2_BASE_ = __sdata2_start + (__sbss2_end - __sdata2_start / 2 ));
 
/* Generate Stack and Heap definitions */
 
bss_stack : {
. = ALIGN(8);
_heap = .;
_heap_start = _heap;
. += _HEAP_SIZE;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > ilmb_cntlr_dlmb_cntlr
 
}
 
/tags/STEP1_2/system.mhs
0,0 → 1,272
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
# Wed Nov 01 18:23:34 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 8 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
# ##############################################################################
 
 
PARAMETER VERSION = 2.1.0
 
 
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
 
 
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
 
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
 
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
 
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
 
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
 
BEGIN opb_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.00.c
PARAMETER C_MEM_WIDTH = 16
PARAMETER C_BASEADDR = 0x41800000
PARAMETER C_HIGHADDR = 0x4180ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
PARAMETER HW_VER = 2.00.b
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CLK_PAIRS = 4
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_MEM0_BASEADDR = 0x30000000
PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
 
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
 
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_PHASE_SHIFT = 60
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
 
/tags/STEP1_2/TestApp_Memory/src/TestApp_Memory.c
0,0 → 1,88
/*
* * Copyright (c) 2004 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
 
/*
* Xilinx EDK 7.1.2 EDK_H.12.5.1
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* D:\mb-jpeg
*/
 
 
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
 
#include "xutil.h"
 
//====================================================
 
int main (void) {
 
 
print("-- Entering main() --\r\n");
 
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
 
 
/* Testing DDR Memory (DDR_256MB_32MX64_rank1_row13_col10_cl2_5)*/
{
XStatus status;
 
print("Starting MemoryTest for DDR_256MB_32MX64_rank1_row13_col10_cl2_5:\r\n");
print(" Running 32-bit test...");
status = XUtil_MemoryTest32((Xuint32*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 16-bit test...");
status = XUtil_MemoryTest16((Xuint16*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 8-bit test...");
status = XUtil_MemoryTest8((Xuint8*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
}
 
print("-- Exiting main() --\r\n");
return 0;
}
 
/tags/STEP1_2/TestApp_Memory/src/TestApp_Memory_LinkScr
0,0 → 1,99
 
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
 
/* Define all the memory regions in the system */
MEMORY
{
ilmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x1fff
}
 
/*
* Specify the default entry point to the program
*/
ENTRY(_start)
 
/*
* Define the sections, and where they are mapped in memory
*/
SECTIONS
{
 
.text : {
_ftext = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
_etext = .;
} > ilmb_cntlr
 
.rodata : {
_frodata = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
_erodata = .;
} > ilmb_cntlr
 
/* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */
.sdata2 : {
. = ALIGN(8);
_sdata2_start = .;
*(.sdata2)
. = ALIGN(8);
_sdata2_end = .;
} > ilmb_cntlr
_sdata2_size = _sdata2_end - _sdata2_start;
PROVIDE (_SDA2_BASE_ = _sdata2_start + (_sdata2_size / 2 ));
 
.data : {
. = ALIGN(4);
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
_edata = .;
} > ilmb_cntlr
 
.eh_frame : {
*(.eh_frame)
} > ilmb_cntlr
 
/* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */
/* Note that .sdata and .sbss must be contiguous */
 
.sdata : {
. = ALIGN(8);
_ssro = .;
*(.sdata)
} > ilmb_cntlr
.sbss : {
. = ALIGN(4);
PROVIDE (__sbss_start = .);
*(.sbss)
. = ALIGN(8);
_essro = .;
} > ilmb_cntlr
PROVIDE (__sbss_end = _essro);
_ssro_size = _essro - _ssro;
PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 ));
 
.bss : {
. = ALIGN(4);
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
} > ilmb_cntlr
 
.bss_stack : {
. = ALIGN(8);
_heap = .;
_heap_start = _heap;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > ilmb_cntlr
}
 
/tags/STEP1_2/data/system.ucf
0,0 → 1,347
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
 
Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin IOSTANDARD = LVCMOS25;
Net sys_rst_pin LOC=AH5;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
 
## FPGA pin constraints
Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH15;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AF21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AG21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AC19;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD19;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AE22;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AE21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AH22;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AE15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AD15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AF14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AE14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AD14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AC15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AB15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AH9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AE9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AD12;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AC12;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AG10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AF10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB16;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AD17;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AC16;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD16;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin LOC=L27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin LOC=R26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin LOC=R24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin LOC=N29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin LOC=N26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB LOC=C16;
Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB_OUT LOC=G23;
Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;
/tags/STEP1_2/system.bsb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/tags/STEP1_2/system.bsb
tags/STEP1_2/system.bsb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/STEP1_2/etc/bitgen.ut =================================================================== --- tags/STEP1_2/etc/bitgen.ut (nonexistent) +++ tags/STEP1_2/etc/bitgen.ut (revision 59) @@ -0,0 +1,21 @@ +-g ConfigRate:4 +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No Index: tags/STEP1_2/etc/fast_runtime.opt =================================================================== --- tags/STEP1_2/etc/fast_runtime.opt (nonexistent) +++ tags/STEP1_2/etc/fast_runtime.opt (revision 59) @@ -0,0 +1,80 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + Index: tags/STEP1_2/etc/download.cmd =================================================================== --- tags/STEP1_2/etc/download.cmd (nonexistent) +++ tags/STEP1_2/etc/download.cmd (revision 59) @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit Index: tags/STEP1_2/etc/bitgen_spartan3.ut =================================================================== --- tags/STEP1_2/etc/bitgen_spartan3.ut (nonexistent) +++ tags/STEP1_2/etc/bitgen_spartan3.ut (revision 59) @@ -0,0 +1,15 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g StartUpClk:JTAGCLK +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No

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