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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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Rev 6 → Rev 7

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/top_de115.v File deleted
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/testbench.v File deleted
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/cross_bar.v
30,6 → 30,8
 
module cross_bar #(
parameter VC_NUM_PER_PORT = 4,
parameter X_NODE_NUM = 3,
parameter Y_NODE_NUM = 3,
parameter PORT_NUM = 5,
parameter PYLD_WIDTH = 32,
parameter FLIT_TYPE_WIDTH = 2,
52,8 → 54,10
output[FLIT_ARRAY_WIDTH-1 : 0] flit_out_array
);
`LOG2
localparam MUX_IN_WIDTH = FLIT_ARRAY_WIDTH-FLIT_WIDTH;
localparam PORT_SEL_BCD_WIDTH =log2(PORT_SEL_WIDTH);
localparam MUX_IN_WIDTH = FLIT_ARRAY_WIDTH-FLIT_WIDTH;
localparam PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH);
localparam X_NODE_NUM_WIDTH = log2(X_NODE_NUM);
localparam Y_NODE_NUM_WIDTH = log2(Y_NODE_NUM);
wire [MUX_IN_WIDTH-1 : 0] flit_in_mux_array [PORT_NUM-1 : 0];
wire [PORT_NUM-1 : 0] header_flit;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/router.v
206,6 → 206,8
//cross_bar
cross_bar #(
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.PORT_NUM (PORT_NUM),
.PYLD_WIDTH (PYLD_WIDTH),
.FLIT_TYPE_WIDTH (FLIT_TYPE_WIDTH)
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/tasks.v
1,7 → 1,7
// synthesis translate_off
task automatic cpu_write_data (
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [CPU_ADR_WIDTH-1 : 0] addr_i,
input [31 : 0] data_i
);
23,8 → 23,8
endtask
 
task automatic cpu_read_data (
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [CPU_ADR_WIDTH-1 : 0] addr_i,
output[31 : 0] data_o
46,10 → 46,10
 
task automatic send_pck(
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [X_NODE_NUM_WIDTH-1 : 0] des_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] des_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_y_addr,
input [`NI_PCK_SIZE_WIDTH-1 : 0] pck_size,
input [`NI_PTR_WIDTH-1 : 0] pck_ptr
 
74,8 → 74,8
 
 
task automatic send_pck_cmd (
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [`NI_PCK_SIZE_WIDTH-1 : 0] pck_size,
input [`NI_PTR_WIDTH-1 : 0] pck_ptr
92,10 → 92,10
////////////////////////////////////
 
task automatic write_hdr (
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [X_NODE_NUM_WIDTH-1 : 0] des_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] des_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_y_addr,
input [`NI_PTR_WIDTH-1 : 0] pck_ptr
 
 
106,7 → 106,7
begin : hdr1
addr_i = pck_ptr>>2;
data_i = {{PORT_NUM_BCD_WIDTH{1'b0}},des_x_addr,des_y_addr,{(32-PORT_NUM_BCD_WIDTH-X_NODE_NUM_WIDTH-Y_NODE_NUM_WIDTH){1'b0}}};
data_i = {{PORT_NUM_BCD_WIDTH{1'b0}},des_x_addr,des_y_addr,{(32-PORT_NUM_BCD_WIDTH-`X_Y_ADDR_WIDTH_IN_HDR-`X_Y_ADDR_WIDTH_IN_HDR){1'b0}}};
cpu_write_data ( src_x_addr, src_y_addr, addr_i,data_i);
end
115,8 → 115,8
///////////////////////////////////
 
task automatic recive_pck(
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [12 : 0] pck_size,
input [18 : 0] pck_ptr
 
148,15 → 148,15
/*
task automatic write_prog_hdr (
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [X_NODE_NUM_WIDTH-1 : 0] des_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] des_y_addr
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_y_addr
 
);
begin : hdr2
ni_s_addr_i [`CORE_NUM(src_x_addr,src_y_addr)] = SLAVE_WR_PCK_ADDR;
ram_data[`CORE_NUM(src_x_addr,src_y_addr)]= {{PORT_NUM_BCD_WIDTH{1'b0}},des_x_addr,des_y_addr,{(32-PORT_NUM_BCD_WIDTH-X_NODE_NUM_WIDTH-Y_NODE_NUM_WIDTH-1){1'b0}}, 1'b1 };
ram_data[`CORE_NUM(src_x_addr,src_y_addr)]= {{PORT_NUM_BCD_WIDTH{1'b0}},des_x_addr,des_y_addr,{(32-PORT_NUM_BCD_WIDTH-`X_Y_ADDR_WIDTH_IN_HDR-`X_Y_ADDR_WIDTH_IN_HDR-1){1'b0}}, 1'b1 };
ram_addr[`CORE_NUM(src_x_addr,src_y_addr)]= 0;
@ (posedge clk) # 1 ram_we[`CORE_NUM(src_x_addr,src_y_addr)] = 1'b1;
@ (posedge clk) # 1 ram_we[`CORE_NUM(src_x_addr,src_y_addr)] = 1'b0;
168,10 → 168,10
///////////////////////////////////////////////
 
task automatic send_prog_pck(
input [X_NODE_NUM_WIDTH-1 : 0] src_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] src_y_addr,
input [X_NODE_NUM_WIDTH-1 : 0] des_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] des_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] src_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_y_addr,
input [12 : 0] pck_size,
input [18 : 0] pck_ptr
 
189,8 → 189,8
////////////////////////////////////////////////
 
task automatic update_cmd_mem (
input [X_NODE_NUM_WIDTH-1 : 0] des_x_addr,
input [Y_NODE_NUM_WIDTH-1 : 0] des_y_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_x_addr,
input [`X_Y_ADDR_WIDTH_IN_HDR-1 : 0] des_y_addr,
input [31 : 0] jtag_mem_start_addr,
input [31 : 0] pckt_size,
input [31 : 0] sdram_start_addr
198,7 → 198,7
begin : update
@(posedge clk) # 1 cmd_we = 1'b1;
cmd_addr = 1;
cmd_data ={{(32-X_NODE_NUM_WIDTH-Y_NODE_NUM_WIDTH){1'b0}},des_x_addr,des_y_addr};
cmd_data ={{(32-`X_Y_ADDR_WIDTH_IN_HDR-`X_Y_ADDR_WIDTH_IN_HDR){1'b0}},des_x_addr,des_y_addr};
@(posedge clk) # 1 cmd_we = 1'b1;
cmd_addr = 2;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/ext_ram_nic.v
72,7 → 72,7
localparam PORT_NUM_BCD_WIDTH = log2(PORT_NUM);
localparam X_NODE_NUM_WIDTH = log2(X_NODE_NUM);
localparam Y_NODE_NUM_WIDTH = log2(Y_NODE_NUM);
localparam HDR_ZERO_NUM = (32 - (2*(X_NODE_NUM_WIDTH+Y_NODE_NUM_WIDTH)) - PORT_NUM_BCD_WIDTH);
localparam HDR_ZERO_NUM = (32 - (4*`X_Y_ADDR_WIDTH_IN_HDR) - PORT_NUM_BCD_WIDTH);
localparam STATUSE_NUM = 8;
localparam IDEAL = 1;
104,6 → 104,7
reg src_en,addr_capture_en, pck_size_en,pck_size_dec;
reg [X_NODE_NUM_WIDTH-1 :0] dest_x_addr,dest_x_addr_next;
reg [Y_NODE_NUM_WIDTH-1 :0] dest_y_addr,dest_y_addr_next;
wire [`X_Y_ADDR_WIDTH_IN_HDR-1 :0] dest_x_addr_hdr,dest_y_addr_hdr;
reg wr_reg,wr_reg_next; // 1 : write, 0 : read
reg ack_reg,ack_reg_next; // 1: ack required 0: no need
reg ovc_wr;
132,7 → 133,7
assign in_vc_num = flit_in [`FLIT_IN_VC_LOC ];
//assign fifo_vc_num = fifo_flit_out [`FLIT_IN_VC_LOC ];
//assign fifo_hdr_flg = fifo_flit_out [`FLIT_HDR_FLG_LOC ];
//assign fifo_hdr_flg = fifo_flit_out [`FLIT_HDR_FLG_LOC ];
assign fifo_tail_flg = fifo_flit_out [`FLIT_TAIL_FLAG_LOC ];
assign cand_ivc_selected = |candidate_ivc;
141,12 → 142,22
assign all_ovc_full = & full_ovc;
assign cand_ovc_full = |(full_ovc & cand_ovc) ;
assign flit_out_wr = (ram_readdatavalid | wr_hdr | wr_tail);
assign flit_out = (wr_hdr) ? {`HDR_FLIT,cand_ovc,port_num,dest_x_addr,dest_y_addr,SW_X_ADDR[X_NODE_NUM_WIDTH-1 : 0],SW_Y_ADDR[Y_NODE_NUM_WIDTH-1 : 0],{HDR_ZERO_NUM {1'b0}}}:
assign flit_out = (wr_hdr) ? {`HDR_FLIT,cand_ovc,port_num,dest_x_addr_hdr,dest_y_addr_hdr,SW_X_ADDR[`X_Y_ADDR_WIDTH_IN_HDR-1 : 0],SW_Y_ADDR[`X_Y_ADDR_WIDTH_IN_HDR-1 : 0],{HDR_ZERO_NUM {1'b0}}}:
{flit_type,cand_ovc,ram_readdata};
assign flit_type = (wr_tail ||(rd_valid_counter == 1 && rd_busy)) ? `TAIL_FLIT : `BODY_FLIT;
assign ram_address = addr_counter;
assign credit_out =(fifo_rd) ? candidate_ivc : {VC_NUM_PER_PORT{1'b0}};
assign ram_byteenable_n = 4'd0;
assign ram_byteenable_n = 4'd0;
generate
if(X_NODE_NUM_WIDTH == `X_Y_ADDR_WIDTH_IN_HDR) assign dest_x_addr_hdr = dest_x_addr;
else assign dest_x_addr_hdr = {{(`X_Y_ADDR_WIDTH_IN_HDR-X_NODE_NUM_WIDTH){1'b0}},dest_x_addr};
if(Y_NODE_NUM_WIDTH == `X_Y_ADDR_WIDTH_IN_HDR) assign dest_y_addr_hdr = dest_y_addr;
else assign dest_y_addr_hdr = {{(`X_Y_ADDR_WIDTH_IN_HDR-Y_NODE_NUM_WIDTH){1'b0}},dest_y_addr};
endgenerate
 
//assign fifo_not_empty & ~ivc_busy;
fifo_buffer #(
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/ni.v
28,7 → 28,7
must be updated by cpu in the first word of the packet
3-status register: provide information about the current status of the router
status_reg = {all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
status_reg = {all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
RD/WR registers ={pck_size_next,memory_ptr_next}
Info: monemi@fkegraduate.utm.my
121,13 → 121,14
localparam SLAVE_WR_PCK_ADDR = 1;
localparam SLAVE_STATUS_ADDR = 2;
localparam NUMBER_OF_STATUS = 6;
localparam NUMBER_OF_STATUS = 7;
localparam IDEAL = 1;
localparam READ_MEM_PCK_HDR = 2;
localparam ASSIGN_PORT_VC = 4;
localparam WR_ON_FIFO = 8;
localparam WR_ON_RAM = 16;
localparam PROG_WR = 32;
localparam SEND_HDR = 8;
localparam WR_ON_FIFO = 16;
localparam WR_ON_RAM = 32;
localparam PROG_WR = 64;
localparam PORT_NUM_BCD_WIDTH = log2(PORT_NUM);
140,6 → 141,7
//avalon slave interface signals
wire s_chipselect, s_write,s_read, s_waitrequest;
wire [WS_ADDR_WIDTH-1 :0] s_address;
263,8 → 265,8
assign flit_out = {wr_flit_type,cand_wr_vc,m_pyld};
//assign s_waitrequest = s_write & (ps!= IDEAL ) & (s_address==SLAVE_RD_PCK_ADDR | s_address==SLAVE_WR_PCK_ADDR );
assign dest_x_addr = m_readdata[32-PORT_NUM_BCD_WIDTH-1 : 32-PORT_NUM_BCD_WIDTH-X_NODE_NUM_WIDTH ];
assign dest_y_addr = m_readdata[32-PORT_NUM_BCD_WIDTH-X_NODE_NUM_WIDTH-1 : 32-PORT_NUM_BCD_WIDTH-X_NODE_NUM_WIDTH-Y_NODE_NUM_WIDTH ];
assign dest_x_addr = m_readdata[`DES_X_ADDR_LOC ];
assign dest_y_addr = m_readdata[`DES_Y_ADDR_LOC ];
assign m_pyld = (port_num_en_del )? {port_num_reg,m_readdata[32-PORT_NUM_BCD_WIDTH-1: 0]} : m_readdata;
278,7 → 280,7
//status register
assign status_reg = {all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
assign s_readdata = status_reg;
assign prog_mode_en_next = flit_in_hdr_flg & (flit_in [`JTAG_PROG_LOC]== 1'b1);
assign prog_mode_en_next = flit_in_hdr_flg & (flit_in [`FLIT_IN_WR_RAM_LOC]== 1'b1);
generate
if(WM_ADDR_WIDTH > PTR_WIDTH) assign m_address = memory_ptr+counter+(~m_waitrequest & read_burst);
448,22 → 450,22
end //READ_MEM_PCK_HDR:
ASSIGN_PORT_VC : begin
if(~m_waitrequest) begin
ns = WR_ON_FIFO;
ns = SEND_HDR;
rd_mem_en = 1'b1;
counter_increase = 1'b1;
cand_wr_vc_en = 1'b1;
port_num_en = 1'b1;
hdr_write_next = 1'b1;
end else rd_mem_en = 1'b1;
end else rd_mem_en = 1'b1;
end
SEND_HDR: begin
ns = WR_ON_FIFO;
wr_flit_type = HDR_FLIT;
hdr_write_next = 1'b0;
flit_out_wr = 1'b1;
end
WR_ON_FIFO: begin
read_burst = 1'b1;
if(hdr_write)begin
wr_flit_type = HDR_FLIT ;
hdr_write_next = 1'b0;
flit_out_wr = 1'b1;
end
if(!m_waitrequest) begin
if(pck_eq_counter) begin
flit_out_wr = 1'b1;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/aeMB_IP_top.v File deleted
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/aeMB_IP.v
19,6 → 19,7
Purpose:
SoC with one aeMB processor, wishbone bus,ni,ext_int, gpio and timer
 
Info: monemi@fkegraduate.utm.my
35,31 → 36,49
parameter NI_CTRL_SIMULATION = "aeMB",
parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF,
parameter RAM_EN = 1,
parameter NOC_EN = 1,
parameter NOC_EN = 0,
parameter GPIO_EN = 1,
parameter GPIO_PORT_NUM = 8,
parameter GPIO_PORT_WIDTH = 7,
parameter GPIO_WIDTH = GPIO_PORT_NUM * GPIO_PORT_WIDTH,
parameter EXT_INT_EN = 1,
parameter TIMER_EN = 1,
parameter INT_CTRL_EN = 1,
//wishbone bus parameters
parameter DATA_WIDTH = 32, // maximum data width
parameter ADDR_WIDTH = 32,
parameter SEL_WIDTH = 4,
parameter TAG_WIDTH = 3, // CTI
//aeMB parameter
parameter AEMB_IWB = 32, ///< INST bus width
parameter AEMB_DWB = 32, ///< DATA bus width
parameter AEMB_XWB = 7, ///< XCEL bus width
//external int parameters
parameter EXT_INT_NUM = 3,//max 32
parameter EXT_INT_ADDR_WIDTH = 3,
 
// CACHE PARAMETERS
parameter AEMB_ICH = 11, ///< instruction cache size
parameter AEMB_IDX = 6,///< cache index size
//timet parameters
parameter TIMER_ADDR_WIDTH =3,
parameter TIMER_INT_NUM =1,
 
// OPTIONAL HARDWARE
parameter AEMB_BSF = 1, ///< optional barrel shift
parameter AEMB_MUL = 1, ///< optional multiplier
//int_ctrl parameters
parameter INT_CTRL_INT_NUM = (EXT_INT_EN*EXT_INT_NUM) + (TIMER_EN * TIMER_INT_NUM),
parameter INT_CTRL_ADDR_WIDTH =3,
// noc parameter
//gpio parameters
parameter IO_EN = 0,
parameter I_EN = 0,
parameter O_EN = 1,
parameter IO_PORT_WIDTH = "0",
parameter I_PORT_WIDTH = "0",
parameter O_PORT_WIDTH = "7,7,7,7,7,7,7,7",
parameter IO_WIDTH =(IO_EN)? sum_of_all(IO_PORT_WIDTH) : 1,
parameter I_WIDTH =(I_EN )? sum_of_all(I_PORT_WIDTH) : 1,
parameter O_WIDTH =(O_EN )? sum_of_all(O_PORT_WIDTH) : 1,
parameter EXT_INT_WIDTH =(EXT_INT_EN)? EXT_INT_NUM : 1,
parameter GPIO_ADDR_WIDTH = 15,
 
// noc parameter
parameter TOPOLOGY = "TORUS", // "MESH" or "TORUS"
parameter ROUTE_ALGRMT = "XY", //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = 2,
68,19 → 87,37
parameter PORT_NUM = 5,
parameter X_NODE_NUM = 4,
parameter Y_NODE_NUM = 3,
parameter SW_X_ADDR = 2,
parameter SW_Y_ADDR = 1,
parameter SW_X_ADDR = 0,
parameter SW_Y_ADDR = 0,
parameter NOC_S_ADDR_WIDTH = 3,
parameter CORE_NUMBER = `CORE_NUM(SW_X_ADDR,SW_Y_ADDR),
parameter NIC_CONNECT_PORT = 0, // 0:Local 1:East, 2:North, 3:West, 4:South
parameter FLIT_TYPE_WIDTH = 2,
parameter VC_ID_WIDTH = VC_NUM_PER_PORT,
parameter FLIT_WIDTH = PYLD_WIDTH+FLIT_TYPE_WIDTH+VC_ID_WIDTH
parameter FLIT_WIDTH = PYLD_WIDTH+FLIT_TYPE_WIDTH+VC_ID_WIDTH,
//aeMB parameters
parameter AEMB_IWB = 32, ///< INST bus width
parameter AEMB_DWB = 32, ///< DATA bus width
parameter AEMB_XWB = 7, ///< XCEL bus width
 
// CACHE PARAMETERS
parameter AEMB_ICH = 11, ///< instruction cache size
parameter AEMB_IDX = 6,///< cache index size
 
// OPTIONAL HARDWARE
parameter AEMB_BSF = 1, ///< optional barrel shift
parameter AEMB_MUL = 1 ///< optional multiplier
)(
input clk,reset_in,sys_int_i,sys_ena_i,
output [GPIO_WIDTH-1:0] gpio,
input clk,reset_in,sys_ena_i,
input [EXT_INT_WIDTH-1 :0] ext_int_i,
inout [IO_WIDTH-1 :0] gpio_io,
input [I_WIDTH-1 :0] gpio_i,
output [O_WIDTH-1 :0] gpio_o,
// NOC interfaces
output [FLIT_WIDTH-1 :0] flit_out,
output flit_out_wr,
114,6 → 151,9
`define ADD_BUS_LOCALPARAM 1
`include "../parameter.v"
 
`define ADD_FUNCTION 1
`include "../my_functions.v"
 
//synthesis translate_off
`define SIMULATION_CODE 1
//synthesis translate_on
141,7 → 181,10
 
 
wire sys_int_i,timer_irq;
wire [EXT_INT_NUM-1 : 0 ] ext_int_o;
wire [INT_CTRL_INT_NUM-1 : 0 ] int_ctrl_in;
wire [SLAVE_ADDR_ARRAY_WIDTH-1 : 0 ] bus_slave_adr_o;
wire [SLAVE_DATA_ARRAY_WIDTH-1 : 0 ] bus_slave_dat_o;
wire [SLAVE_SEL_ARRAY_WIDTH-1 : 0 ] bus_slave_sel_o;
332,12 → 375,18
if(GPIO_EN) begin : gpio_gen
 
localparam GPIO_ADDR_WIDTH = (GPIO_PORT_NUM==1) ? 2 : log2(GPIO_PORT_NUM*2);
output_port #(
.PORT_NUM (GPIO_PORT_NUM),
.PORT_WIDTH (GPIO_PORT_WIDTH)
gpio #(
.DATA_WIDTH (DATA_WIDTH),
.SEL_WIDTH (SEL_WIDTH),
.IO_EN (IO_EN),
.I_EN (I_EN),
.O_EN (O_EN),
.IO_PORT_WIDTH (IO_PORT_WIDTH),
.I_PORT_WIDTH (I_PORT_WIDTH),
.O_PORT_WIDTH (O_PORT_WIDTH)
)
the_seven_segment
the_gpio
(
.clk (clk),
.reset (reset),
348,62 → 397,156
.sa_we_i (slave_we_i [GPIO_ID]),
.sa_ack_o (slave_ack_o [GPIO_ID]),
.sa_dat_o (slave_dat_o [GPIO_ID]),
.gpio_out (gpio )
.gpio_io (gpio_io),
.gpio_i (gpio_i),
.gpio_o (gpio_o)
);
end //GPIO_EN
if(NOC_EN) begin : noc_gen
end //GPIO_EN
else begin
assign gpio_io = {IO_WIDTH{1'bX}};
assign gpio_o = {O_WIDTH{1'bX}};
end
if(NOC_EN) begin : noc_gen
ni #(
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
.PORT_NUM (PORT_NUM),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.SW_X_ADDR (SW_X_ADDR),
.SW_Y_ADDR (SW_Y_ADDR),
.NIC_CONNECT_PORT (NIC_CONNECT_PORT),
.RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
.W_DATA_WIDTH (DATA_WIDTH ),
.WS_ADDR_WIDTH (NOC_S_ADDR_WIDTH)
)
ni_inst
(
.reset (reset),
.clk (clk) ,
.flit_out (flit_out) ,
.flit_out_wr (flit_out_wr) ,
.credit_in (credit_in) ,
.flit_in (flit_in) ,
.flit_in_wr (flit_in_wr) ,
.credit_out (credit_out) ,
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.PYLD_WIDTH (PYLD_WIDTH),
.BUFFER_NUM_PER_VC (BUFFER_NUM_PER_VC),
.PORT_NUM (PORT_NUM),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.SW_X_ADDR (SW_X_ADDR),
.SW_Y_ADDR (SW_Y_ADDR),
.NIC_CONNECT_PORT (NIC_CONNECT_PORT),
.RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
.W_DATA_WIDTH (DATA_WIDTH ),
.WS_ADDR_WIDTH (NOC_S_ADDR_WIDTH)
)
ni_inst
(
.reset (reset),
.clk (clk) ,
.flit_out (flit_out) ,
.flit_out_wr (flit_out_wr) ,
.credit_in (credit_in) ,
.flit_in (flit_in) ,
.flit_in_wr (flit_in_wr) ,
.credit_out (credit_out) ,
.s_dat_i (slave_dat_i [NOC_S_ID]) ,
.s_addr_i (slave_addr_i [NOC_S_ID][`NOC_S_ADDR_RANG]) ,
.s_stb_i (slave_stb_i [NOC_S_ID]) ,
.s_we_i (slave_we_i [NOC_S_ID]) ,
.s_dat_o (slave_dat_o [NOC_S_ID]) ,
.s_ack_o (slave_ack_o [NOC_S_ID]) ,
.m_sel_o (master_sel_o [NOC_M_ID]),
.m_dat_o (master_dat_o [NOC_M_ID]) ,
.m_addr_o (master_adr_o [NOC_M_ID][AEMB_RAM_WIDTH_IN_WORD-1 : 0]) ,
.m_cti_o (master_tag_o [NOC_M_ID]) ,
.m_stb_o (master_stb_o [NOC_M_ID]) ,
.m_cyc_o (master_cyc_o [NOC_M_ID]) ,
.m_we_o (master_wre_o [NOC_M_ID]) ,
.m_dat_i (master_dat_i [NOC_M_ID]) ,
.m_ack_i (master_ack_i [NOC_M_ID])
);
 
assign master_adr_o [NOC_M_ID] [ADDR_WIDTH-1 : AEMB_RAM_WIDTH_IN_WORD] = {ADDR_WIDTH-AEMB_RAM_WIDTH_IN_WORD{1'b0}};
end // NOC_EN
else begin
assign flit_out ={FLIT_WIDTH{1'bX}};
assign flit_out_wr = 1'bX;
assign credit_out ={VC_NUM_PER_PORT{1'bX}};
end
if(EXT_INT_EN) begin : ext_in_gen
.s_dat_i (slave_dat_i [NOC_S_ID]) ,
.s_addr_i (slave_addr_i [NOC_S_ID][`NOC_S_ADDR_RANG]) ,
.s_stb_i (slave_stb_i [NOC_S_ID]) ,
.s_we_i (slave_we_i [NOC_S_ID]) ,
.s_dat_o (slave_dat_o [NOC_S_ID]) ,
.s_ack_o (slave_ack_o [NOC_S_ID]) ,
ext_int #(
.EXT_INT_NUM (EXT_INT_NUM),//max 32
.ADDR_WIDTH (EXT_INT_ADDR_WIDTH)
)the_ext_int
(
.clk (clk),
.reset (reset),
.sa_dat_i (slave_dat_i [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_sel_i (slave_sel_i [EXT_INT_ID]),
.sa_addr_i (slave_addr_i [EXT_INT_ID][EXT_INT_ADDR_WIDTH-1 :0]) ,
.sa_stb_i (slave_stb_i [EXT_INT_ID]) ,
.sa_we_i (slave_we_i [EXT_INT_ID]) ,
.sa_dat_o (slave_dat_o [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_ack_o (slave_ack_o [EXT_INT_ID]) ,
.m_sel_o (master_sel_o [NOC_M_ID]),
.m_dat_o (master_dat_o [NOC_M_ID]) ,
.m_addr_o (master_adr_o [NOC_M_ID][AEMB_RAM_WIDTH_IN_WORD-1 : 0]) ,
.m_cti_o (master_tag_o [NOC_M_ID]) ,
.m_stb_o (master_stb_o [NOC_M_ID]) ,
.m_cyc_o (master_cyc_o [NOC_M_ID]) ,
.m_we_o (master_wre_o [NOC_M_ID]) ,
.m_dat_i (master_dat_i [NOC_M_ID]) ,
.m_ack_i (master_ack_i [NOC_M_ID])
);
.ext_int_i (ext_int_i),
.ext_int_o (ext_int_o)//output to the interrupt controller
);
assign slave_dat_o [EXT_INT_ID][DATA_WIDTH-1 :EXT_INT_NUM] = {(DATA_WIDTH-EXT_INT_NUM){1'b0}};
end // EXT_INT_EN
if(TIMER_EN) begin :timer_gen
// wire timer_irq;
timer #(
.ADDR_WIDTH (TIMER_ADDR_WIDTH)
)
the_timer
(
.clk (clk),
.reset (reset),
.sa_dat_i (slave_dat_i [TIMER_ID]) ,
.sa_sel_i (slave_sel_i [TIMER_ID]),
.sa_addr_i (slave_addr_i [TIMER_ID][TIMER_ADDR_WIDTH-1 :0]) ,
.sa_stb_i (slave_stb_i [TIMER_ID]) ,
.sa_we_i (slave_we_i [TIMER_ID]) ,
.sa_dat_o (slave_dat_o [TIMER_ID]) ,
.sa_ack_o (slave_ack_o [TIMER_ID]),
.irq (timer_irq)
);
end //TIMER_EN
if(INT_CTRL_EN) begin : int_ctrl_gen
int_ctrl #(
.INT_NUM (INT_CTRL_INT_NUM),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (INT_CTRL_ADDR_WIDTH)
)
int_ctrl_gen
(
.clk (clk),
.reset (reset),
.sa_dat_i (slave_dat_i [INT_CTRL_ID]) ,
.sa_sel_i (slave_sel_i [INT_CTRL_ID]),
.sa_addr_i (slave_addr_i [INT_CTRL_ID][INT_CTRL_ADDR_WIDTH-1 :0]) ,
.sa_stb_i (slave_stb_i [INT_CTRL_ID]) ,
.sa_we_i (slave_we_i [INT_CTRL_ID]) ,
.sa_dat_o (slave_dat_o [INT_CTRL_ID]) ,
.sa_ack_o (slave_ack_o [INT_CTRL_ID]),
.int_i (int_ctrl_in),
.int_o (sys_int_i)
);
if(EXT_INT_EN && TIMER_EN) assign int_ctrl_in = {timer_irq,ext_int_o};
else if(EXT_INT_EN) assign int_ctrl_in = ext_int_o;
else assign int_ctrl_in = timer_irq;
end //INT_CTRL_EN
else begin
assign sys_int_i= 1'b0;
end
 
assign master_adr_o [NOC_M_ID] [ADDR_WIDTH-1 : AEMB_RAM_WIDTH_IN_WORD] = {ADDR_WIDTH-AEMB_RAM_WIDTH_IN_WORD{1'b0}};
 
 
 
end // NOC_EN
endgenerate
 
wishbone_bus #(
411,6 → 554,10
.RAM_EN (RAM_EN),
.NOC_EN (NOC_EN),
.GPIO_EN (GPIO_EN),
.EXT_INT_EN (EXT_INT_EN),
.TIMER_EN (TIMER_EN),
.INT_CTRL_EN (INT_CTRL_EN),
.MASTER_NUM_ (MASTER_NUM),
.SLAVE_NUM_ (SLAVE_NUM),
.ADDR_WIDTH (ADDR_WIDTH),
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/gpio.v
19,66 → 19,245
Purpose:
a simple wishbone compatible output port
 
a simple wishbone compatible output/input port
each port has three registers.
addr
0 DIR_REG
1 WRITE_REG port 0
2 READ_REG
32 DIR_REG
33 WRITE_REG port 1
34 READ_REG
.
.
.
Info: monemi@fkegraduate.utm.my
 
****************************************************************/
 
 
`include "../define.v"
`include "../define.v"
 
module output_port #(
parameter DATA_WIDTH = 32,
parameter PORT_WIDTH = 7,
parameter PORT_NUM = 4,
parameter SEL_WIDTH = 4,
parameter ADDR_WIDTH = (PORT_NUM==1) ? 2 : log2(PORT_NUM*2),
parameter OUT_WIDTH = PORT_NUM * PORT_WIDTH
`define PORT_WIDTH(PORT,i) extract_value(PORT,i)
`define PORT_LOC_START(PORT,i) start_loc(PORT,i)
`define PORT_LOC_END(PORT,i) `PORT_LOC_START(PORT,i)+ `PORT_WIDTH(PORT,i) -1'b1
`define PORT_LOC(PORT,i) `PORT_LOC_END(PORT,i) : `PORT_LOC_START(PORT,i)
 
module gpio #(
parameter DATA_WIDTH = 32,
parameter SEL_WIDTH = 4,
parameter IO_EN = 0,
parameter I_EN = 0,
parameter O_EN = 1,
// port(n-1) ... port0
parameter IO_PORT_WIDTH = "17,4,10,30",
parameter I_PORT_WIDTH = "17,4",
parameter O_PORT_WIDTH = "10",
 
parameter ADDR_TYPE_WIDTH = 5,
parameter ADDR_PORT_WIDTH = 5,
parameter ADDR_REG_WIDTH = 5,
parameter IO_WIDTH =(IO_EN)? sum_of_all(IO_PORT_WIDTH) : 1,
parameter I_WIDTH =(I_EN )? sum_of_all(I_PORT_WIDTH) : 1,
parameter O_WIDTH =(O_EN )? sum_of_all(O_PORT_WIDTH) : 1,
parameter ADDR_WIDTH = ADDR_TYPE_WIDTH+ADDR_PORT_WIDTH+ADDR_REG_WIDTH
)
(
input clk,
input reset,
input [ DATA_WIDTH-1 : 0] sa_dat_i,
input [DATA_WIDTH-1 : 0] sa_dat_i,
input [SEL_WIDTH-1 : 0] sa_sel_i,
input [ADDR_WIDTH-1 : 0] sa_addr_i,
input sa_stb_i,
input sa_we_i,
 
output [ DATA_WIDTH-1 : 0] sa_dat_o,
output sa_ack_o,
output [OUT_WIDTH-1 : 0] gpio_out
 
 
output [DATA_WIDTH-1 : 0] sa_dat_o,
output reg sa_ack_o,
inout [IO_WIDTH-1 : 0] gpio_io,
input [I_WIDTH-1 : 0] gpio_i,
output [O_WIDTH-1 : 0] gpio_o
);
`LOG2
`define ADD_FUNCTION 1
`include "../my_functions.v"
reg [PORT_WIDTH-1 : 0 ] gpio_reg [PORT_NUM-1 : 0];
//port type
localparam GPIO_TYPE_NUM =3;
localparam IO_ADDR_NUM =0;
localparam I_ADDR_NUM =1;
localparam O_ADDR_NUM =2;
assign sa_ack_o = sa_stb_i;
assign sa_dat_o = { {(DATA_WIDTH-PORT_WIDTH){1'b0}}, gpio_reg [sa_addr_i[ADDR_WIDTH-1 : 1] ] };
 
//register per port
localparam DIR_REG =0;
localparam WRITE_REG =1;
localparam READ_REG =2;
genvar i;
localparam IO_PORT_NUM =number_of_port(IO_PORT_WIDTH);
localparam I_PORT_NUM =number_of_port(I_PORT_WIDTH);
localparam O_PORT_NUM =number_of_port(O_PORT_WIDTH);
localparam IO_REG_PER_PORT =3;//dir write read
localparam O_REG_PER_PORT =1;//write
localparam I_REG_PER_PORT =1;//read
localparam IO_ADDR_WIDTH =log2(IO_PORT_NUM*IO_REG_PER_PORT );
localparam I_ADDR_WIDTH =log2(O_PORT_NUM*I_REG_PER_PORT );
localparam O_ADDR_WIDTH =log2(I_PORT_NUM*O_REG_PER_PORT );
wire [DATA_WIDTH-1 : 0] read_mux_in [GPIO_TYPE_NUM-1 :0];
wire [ADDR_TYPE_WIDTH-1 : 0] addr_gpio_type;
wire [ADDR_PORT_WIDTH-1 : 0] addr_gpio_port;
wire [ADDR_REG_WIDTH-1 : 0] addr_gpio_reg;
assign {addr_gpio_type,addr_gpio_port,addr_gpio_reg} = sa_addr_i;
genvar i,j;
generate
for (i=0; i<PORT_NUM; i=i+1'b1) begin : port_lp
always @ (posedge clk or posedge reset) begin
if(reset) begin
gpio_reg[i] <= {PORT_WIDTH{1'b0}};
end else begin
if(sa_stb_i & sa_we_i & i== sa_addr_i[ADDR_WIDTH-1 : 1]) gpio_reg[i] <= sa_dat_i[PORT_WIDTH-1 : 0];
/**********************************
GPIO
*********************************/
 
if(IO_EN)begin : gpio_gen_blk
reg [IO_WIDTH-1 : 0] io_dir;
reg [IO_WIDTH-1 : 0] io_write;
wire [DATA_WIDTH-1 : 0] io_read_mux_in [IO_PORT_NUM-1 :0][IO_REG_PER_PORT-1 : 0];
wire io_addr;
assign io_addr = addr_gpio_type == IO_ADDR_NUM;
for(i=0; i<IO_PORT_NUM ; i=i+1'b1) begin : internal_reg_blk0
always @ (posedge clk or posedge reset) begin
if(reset) begin
io_dir [`PORT_LOC(IO_PORT_WIDTH,i)] <= {`PORT_WIDTH(IO_PORT_WIDTH,i){1'b0}};
io_write [`PORT_LOC(IO_PORT_WIDTH,i)] <= {`PORT_WIDTH(IO_PORT_WIDTH,i){1'b0}};
end else begin
if(sa_stb_i && sa_we_i && io_addr) begin
if( addr_gpio_port == i) begin
if( addr_gpio_reg == DIR_REG ) io_dir [`PORT_LOC(IO_PORT_WIDTH,i)] <= sa_dat_i[`PORT_WIDTH(IO_PORT_WIDTH,i)-1'b1 : 0];
if( addr_gpio_reg == WRITE_REG ) io_write [`PORT_LOC(IO_PORT_WIDTH,i)] <= sa_dat_i[`PORT_WIDTH(IO_PORT_WIDTH,i)-1'b1 : 0];
end
end //sa_stb_i && sa_we_i
end //reset
end//always
assign io_read_mux_in[i][DIR_REG] = {{(DATA_WIDTH-`PORT_WIDTH(IO_PORT_WIDTH,i)){1'b0}},io_dir [`PORT_LOC(IO_PORT_WIDTH,i)]};
assign io_read_mux_in[i][WRITE_REG] = {{(DATA_WIDTH-`PORT_WIDTH(IO_PORT_WIDTH,i)){1'b0}},io_write [`PORT_LOC(IO_PORT_WIDTH,i)]};
assign io_read_mux_in[i][READ_REG] = {{(DATA_WIDTH-`PORT_WIDTH(IO_PORT_WIDTH,i)){1'b0}},gpio_io [`PORT_LOC(IO_PORT_WIDTH,i)]};
for(j=0;j<`PORT_WIDTH(IO_PORT_WIDTH,i); j=j+1'b1) begin: out_pin_assign0
assign gpio_io[`PORT_LOC_START(IO_PORT_WIDTH,i)+j] = (io_dir[`PORT_LOC_START(IO_PORT_WIDTH,i)+j]) ? io_write [`PORT_LOC_START(IO_PORT_WIDTH,i)+j] : 1'bZ;
end
end
end//for
assign read_mux_in[IO_ADDR_NUM] = io_read_mux_in[addr_gpio_port ][addr_gpio_reg];
end // GPIO_EN
else assign read_mux_in[IO_ADDR_NUM] = 'hX;
assign gpio_out [(i+1)*PORT_WIDTH-1 : i*PORT_WIDTH] = gpio_reg[i];
/**********************************
GPI
*********************************/
if(I_EN) begin : gpi_gen_blk
wire [DATA_WIDTH-1 : 0] i_read_mux_in [I_PORT_NUM-1 : 0];
for(i=0; i<I_PORT_NUM ; i=i+1'b1) begin : internal_reg_blk1
assign i_read_mux_in[i] = {{(DATA_WIDTH-`PORT_WIDTH(I_PORT_WIDTH,i)){1'b0}},gpio_i [`PORT_LOC(I_PORT_WIDTH,i)]};
end//for
assign read_mux_in[I_ADDR_NUM] = i_read_mux_in[addr_gpio_port];
end//GPI_EN
else assign read_mux_in[I_ADDR_NUM] = 'hX;
/**********************************
GPO
*********************************/
 
if(O_EN)begin : gpo_gen_blk
wire [DATA_WIDTH-1 : 0] o_read_mux_in [O_PORT_NUM-1 : 0];
wire o_addr;
reg [O_WIDTH-1 : 0] o_write;
assign o_addr = addr_gpio_type==O_ADDR_NUM ;
for(i=0; i<O_PORT_NUM ; i=i+1'b1) begin : internal_reg_blk2
always @ (posedge clk or posedge reset) begin
if(reset) begin
o_write [`PORT_LOC(O_PORT_WIDTH,i)] <= {`PORT_WIDTH(O_PORT_WIDTH,i){1'b0}};
end else begin
if(sa_stb_i && sa_we_i && o_addr) begin
if( addr_gpio_port == i && addr_gpio_reg == WRITE_REG ) o_write [`PORT_LOC(O_PORT_WIDTH,i)] <= sa_dat_i[`PORT_WIDTH(O_PORT_WIDTH,i)-1'b1 : 0];
end //sa_stb_i && sa_we_i
end //reset
end//always
assign o_read_mux_in[i]= {{(DATA_WIDTH-`PORT_WIDTH(O_PORT_WIDTH,i)){1'b0}},o_write [`PORT_LOC(O_PORT_WIDTH,i)]};
for(j=0;j<`PORT_WIDTH(O_PORT_WIDTH,i); j=j+1'b1) begin: out_pin_assign2
assign gpio_o[`PORT_LOC_START(O_PORT_WIDTH,i)+j] = o_write [`PORT_LOC_START(O_PORT_WIDTH,i)+j];
end
end//for
assign read_mux_in[O_ADDR_NUM] = o_read_mux_in[addr_gpio_port ];
end // GPIO_EN
else assign read_mux_in[O_ADDR_NUM] = 'hX;
endgenerate
 
 
 
reg [DATA_WIDTH-1 : 0] read_reg;
always @(posedge clk) begin
if(reset)begin
read_reg <= {DATA_WIDTH{1'b0}};
sa_ack_o <= 1'b0;
end else begin
if(sa_stb_i && ~sa_we_i) read_reg <= read_mux_in[addr_gpio_type];
sa_ack_o <= sa_stb_i && ~sa_ack_o;
end
end
assign sa_dat_o = read_reg;
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/int_ctrl.v
0,0 → 1,97
module int_ctrl #(
parameter INT_NUM = 4,
parameter DATA_WIDTH = 32,
parameter SEL_WIDTH = 4,
parameter ADDR_WIDTH = 3
 
 
)
(
input clk,
input reset,
// wishbone interface
input [DATA_WIDTH-1 : 0] sa_dat_i,
input [SEL_WIDTH-1 : 0] sa_sel_i,
input [ADDR_WIDTH-1 : 0] sa_addr_i,
input sa_stb_i,
input sa_we_i,
output [DATA_WIDTH-1 : 0] sa_dat_o,
output reg sa_ack_o,
//intruupt interface
input [INT_NUM-1 : 0 ] int_i,
output int_o
);
localparam [ADDR_WIDTH-1 : 0] MER_REG_ADDR = 0;
localparam [ADDR_WIDTH-1 : 0] IER_REG_ADDR = 1;
localparam [ADDR_WIDTH-1 : 0] IAR_REG_ADDR = 2;
localparam [ADDR_WIDTH-1 : 0] IPR_REG_ADDR = 3;
//internal register
reg [INT_NUM-1 : 0] ipr,ier,iar;
reg [INT_NUM-1 : 0] ipr_next,ier_next,iar_next;
reg [INT_NUM-1 : 0] read,read_next;
reg [1:0] mer,mer_next;
always@(*) begin
mer_next = mer;
ier_next = ier;
iar_next = iar & ~int_i;
ipr_next = (ipr | int_i) & ier;
read_next = read;
if(sa_stb_i )
if(sa_we_i ) begin
case(sa_addr_i)
MER_REG_ADDR: mer_next = sa_dat_i[1:0];
IER_REG_ADDR: ier_next = sa_dat_i[INT_NUM-1 : 0];
IAR_REG_ADDR: begin
iar_next = iar | sa_dat_i[INT_NUM-1 : 0];//set iar by writting 1
ipr_next = ipr & ~sa_dat_i[INT_NUM-1 : 0];//reset ipr by writting 1
end
default: ipr_next = ipr | int_i;
endcase
end//we
else begin
case(sa_addr_i)
MER_REG_ADDR: read_next = mer;
IER_REG_ADDR: read_next = ier;
IAR_REG_ADDR: read_next = iar;
IPR_REG_ADDR: read_next = ipr;
default: read_next = read;
endcase
end
end//stb
always @(posedge clk) begin
if(reset)begin
mer <= 2'b0;
ier <= {INT_NUM{1'b0}};
iar <= {INT_NUM{1'b0}};
ipr <= {INT_NUM{1'b0}};
read <= {INT_NUM{1'b0}};
sa_ack_o <= 1'b0;
end else begin
mer <= mer_next;
ier <= ier_next;
iar <= iar_next;
ipr <= ipr_next;
read <= read_next;
sa_ack_o <= sa_stb_i && ~sa_ack_o;
end
end
assign int_o = ((mer == 2'b11) && (ier & ipr) ) ? 1'b1 :1'b0;
assign sa_dat_o = {{(DATA_WIDTH-INT_NUM){1'b0}},read};
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/timer.v
0,0 → 1,154
 
`include "../define.v"
 
module timer #(
parameter DATA_WIDTH = 32,
parameter COUNTER_WIDTH = 32,
parameter SEL_WIDTH = 4,
parameter ADDR_WIDTH = 3
 
 
)(
input clk,
input reset,
// wishbone interface
input [DATA_WIDTH-1 : 0] sa_dat_i,
input [SEL_WIDTH-1 : 0] sa_sel_i,
input [ADDR_WIDTH-1 : 0] sa_addr_i,
input sa_stb_i,
input sa_we_i,
output [DATA_WIDTH-1 : 0] sa_dat_o,
output reg sa_ack_o,
//intruupt interface
output irq
);
 
`LOG2
 
localparam TCSR_REG_ADDR = 0; //timer control register
localparam TLR_REG_ADDR = 1; //timer load register
localparam TCMP_REG_ADDR = 2;// timer compare value register
 
localparam MAX_CLK_DEV = 256;
localparam DEV_COUNT_WIDTH= log2(MAX_CLK_DEV);
localparam DEV_CTRL_WIDTH = log2(DEV_COUNT_WIDTH);
 
localparam TCSR_REG_WIDTH = 4+DEV_CTRL_WIDTH;
localparam TCR_REG_WIDTH = TCSR_REG_WIDTH-1;
/***************************
tcr: timer control register
bit
 
6-3: clk_dev_ctrl
3 : timer_isr
2 : rst_on_cmp_value
1 : int_enble_on_cmp_value
0 : timer enable
 
 
 
 
***************************/
reg [TCSR_REG_WIDTH-1 : 0] tcsr;
wire [TCSR_REG_WIDTH-1 : 0] tcsr_next; //timer control register
reg [TCR_REG_WIDTH-1 : 0] tcr_next;
reg timer_isr_next;
 
reg [DEV_COUNT_WIDTH-1 : 0] clk_dev_counter,clk_dev_counter_next;
 
wire [DEV_COUNT_WIDTH-1 : 0] dev_one_hot;
wire [DEV_COUNT_WIDTH-2 : 0] dev_cmp_val;
 
wire timer_en,int_en,rst_on_cmp,timer_isr;
wire clk_dev_rst,counter_rst;
wire [DEV_CTRL_WIDTH-1 : 0] clk_dev_ctrl;
 
 
 
reg [COUNTER_WIDTH-1 : 0] counter,counter_next,cmp,cmp_next,read,read_next;
 
 
 
assign {timer_isr,clk_dev_ctrl,rst_on_cmp,int_en,timer_en} = tcsr;
assign dev_cmp_val = dev_one_hot[DEV_COUNT_WIDTH-1 : 1];
assign clk_dev_rst = clk_dev_counter == dev_cmp_val;
assign counter_rst = (rst_on_cmp)? (counter == cmp) : 1'b0;
assign sa_dat_o = read;
assign irq = timer_isr;
assign tcsr_next ={timer_isr_next,tcr_next};
bcd_to_one_hot #(
.BCD_WIDTH (DEV_CTRL_WIDTH),
.ONE_HOT_WIDTH (DEV_COUNT_WIDTH)
)
conv
(
.bcd_code (clk_dev_ctrl),
.one_hot_code (dev_one_hot)
);
 
always @(posedge clk or posedge reset) begin
if(reset) begin
counter <= {COUNTER_WIDTH{1'b0}};
cmp <= {COUNTER_WIDTH{1'b1}};
clk_dev_counter <= {DEV_COUNT_WIDTH{1'b0}};
tcsr <= {TCR_REG_WIDTH{1'b0}};
read <= {COUNTER_WIDTH{1'b0}};
sa_ack_o <= 1'b0;
end else begin
counter <= counter_next;
cmp <= cmp_next;
clk_dev_counter <= clk_dev_counter_next;
tcsr <= tcsr_next;
read <= read_next;
sa_ack_o <= sa_stb_i && ~sa_ack_o;
end
end
always@(*)begin
counter_next = counter;
clk_dev_counter_next = clk_dev_counter;
timer_isr_next =(timer_isr | (counter_rst & clk_dev_rst) ) & int_en;
tcr_next = tcsr[TCR_REG_WIDTH-1 : 0];
cmp_next = cmp;
read_next = read;
//counters
if(timer_en)begin
if(clk_dev_rst) begin
clk_dev_counter_next = {DEV_COUNT_WIDTH{1'b0}};
if(counter_rst) begin
counter_next = {COUNTER_WIDTH{1'b0}};
end else begin
counter_next = counter +1'b1;
end // count_rst
end else begin
clk_dev_counter_next = clk_dev_counter +1'b1;
end //dev_rst
end//time_en
if(sa_stb_i )begin
if(sa_we_i ) begin
case(sa_addr_i)
TCSR_REG_ADDR: begin
tcr_next = sa_dat_i[TCR_REG_WIDTH-1 : 0];
timer_isr_next = timer_isr & ~sa_dat_i[TCSR_REG_WIDTH-1];// reset isr by writting 1
end
TLR_REG_ADDR: counter_next = sa_dat_i[COUNTER_WIDTH-1 : 0];
TCMP_REG_ADDR: cmp_next = sa_dat_i[COUNTER_WIDTH-1 : 0];
default: cmp_next = cmp;
endcase
end//we
else begin
case(sa_addr_i)
TCSR_REG_ADDR: read_next = tcsr;
TLR_REG_ADDR: read_next = counter;
TCMP_REG_ADDR: read_next = cmp;
default: read_next = read;
endcase
end
end//stb
end//always
 
 
 
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/bus_addr_cmp.v
2,6 → 2,10
parameter RAM_EN = 1,
parameter NOC_EN = 1,
parameter GPIO_EN = 1,
parameter EXT_INT_EN = 1,
parameter TIMER_EN = 1,
parameter INT_CTRL_EN = 1,
parameter ADDR_PERFIX_ = 8,
parameter SLAVE_NUM_ = 3
)
32,6 → 36,18
end else if(k == GPIO_ID) begin
assign base_start_addr [k] = GPIO_ADDR_START;
assign base_end_addr [k] = GPIO_ADDR_START+ GPIO_BK_NUM;
end else if(k == EXT_INT_ID) begin
assign base_start_addr [k] = EXT_INT_ADDR_START;
assign base_end_addr [k] = EXT_INT_ADDR_START+ EXT_INT_BK_NUM;
end else if(k == TIMER_ID) begin
assign base_start_addr [k] = TIMER_ADDR_START;
assign base_end_addr [k] = TIMER_ADDR_START+ TIMER_BK_NUM;
end else if(k == INT_CTRL_ID) begin
assign base_start_addr [k] = INT_CTRL_ADDR_START;
assign base_end_addr [k] = INT_CTRL_ADDR_START+ INT_CTRL_BK_NUM;
end
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/aeMB_mpsoc.v
70,7 → 70,6
`include "../define.v"
 
 
 
module aeMB_mpsoc #(
parameter NI_CTRL_SIMULATION = "aeMB",
/*"aeMB" or "testbench".
79,18 → 78,19
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.V file */
//noc parameter
parameter TOPOLOGY = `TOPOLOGY_DEF,
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF, //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = `VC_NUM_PER_PORT_DEF ,
parameter PYLD_WIDTH = `PYLD_WIDTH_DEF,
parameter BUFFER_NUM_PER_VC = `BUFFER_NUM_PER_VC_DEF,
parameter X_NODE_NUM = `X_NODE_NUM_DEF,
parameter Y_NODE_NUM = `Y_NODE_NUM_DEF,
parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF,
parameter NOC_S_ADDR_WIDTH = `NOC_S_ADDR_WIDTH_DEF,
parameter SW_OUTPUT_REGISTERED = 0,// 1: registered , 0 not registered
// external sdram parameter
parameter SDRAM_EN = `SDRAM_EN_DEF,// 0 : disabled 1: enabled
parameter SDRAM_SW_X_ADDR = `SDRAM_SW_X_ADDR_DEF,
parameter SDRAM_SW_Y_ADDR = `SDRAM_SW_Y_ADDR_DEF,
98,20 → 98,36
parameter SDRAM_ADDR_WIDTH = `SDRAM_ADDR_WIDTH_DEF,
parameter CAND_VC_SEL_MODE = 0,
//aeMB parameter
parameter RAM_EN = 1,
parameter NOC_EN = 1,
parameter GPIO_EN = 1,
parameter GPIO_PORT_WIDTH = 1,
parameter GPIO_PORT_NUM = 1,
// processors parameter
//parameter DEV_EN_ARRAY ="IPn:[the specefic value for nth IP];Def:[default value for the rest of IPs]"
parameter RAM_EN_ARRAY = "Def:1",
parameter NOC_EN_ARRAY = "Def:1",
parameter GPIO_EN_ARRAY = "Def:1",
parameter EXT_INT_EN_ARRAY = "IP0_0:1;Def:0",
parameter TIMER_EN_ARRAY = "IP0_0:1;Def:0",
parameter INT_CTRL_EN_ARRAY = "IP0_0:1;Def:0",
//gpio parameters
parameter IO_EN_ARRAY = "IP0_0:1;Def:0",
parameter I_EN_ARRAY = "Def:0",
parameter O_EN_ARRAY = "IP0_1:0;Def:1",
parameter EXT_INT_NUM_ARRAY = "IP0_0:3;Def:0",//max 32
parameter IO_PORT_WIDTH_ARRAY = "Def:1",
parameter I_PORT_WIDTH_ARRAY = "Def:0",
parameter O_PORT_WIDTH_ARRAY = "IP0_0:7,7,7,7,7,7,7,7;IP0_1:0;Def:1",
parameter TOTAL_EXT_INT_NUM = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,EXT_INT_NUM_ARRAY)+1,
parameter TOTAL_IO_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,IO_PORT_WIDTH_ARRAY)+1,
parameter TOTAL_I_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,I_PORT_WIDTH_ARRAY)+1,
parameter TOTAL_O_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,O_PORT_WIDTH_ARRAY)+1,
parameter AEMB_IWB = 32, ///< INST bus width
parameter AEMB_DWB = 32, ///< DATA bus width
//parameter JTAG_INTERFACE_EN = 1, // if disabled the jtag can just send packet but can not recieve any packet
//parameter JTAG_SW_X_ADDR = 0,
//parameter JTAG_SW_Y_ADDR = 0,
//parameter JTAG_ni_CONNECT_PORT = 0,
parameter PORT_NUM = 5,
parameter FLIT_TYPE_WIDTH = 2,
parameter PORT_SEL_WIDTH = PORT_NUM-1,//assum that no port whants to send a packet to itself!
124,14 → 140,18
parameter CPU_ADR_WIDTH = AEMB_DWB-2,
parameter CPU_ADDR_ARRAY_WIDTH = CPU_ADR_WIDTH * TOTAL_ROUTERS_NUM,
parameter CPU_DATA_ARRAY_WIDTH = 32 * TOTAL_ROUTERS_NUM
//parameter RAM_ARRAY_ADDR_WIDTH = M_ADDR_SIZE*TOTAL_ROUTERS_NUM
 
)(
input reset,
input clk,
output [TOTAL_ROUTERS_NUM-1 :0] led,
input [TOTAL_EXT_INT_NUM-1 :0] ext_int_i,
inout [TOTAL_IO_WIDTH-1 :0] gpio_io,
input [TOTAL_I_WIDTH-1 :0] gpio_i,
output [TOTAL_O_WIDTH-1 :0] gpio_o,
output [12 :0] sdram_addr, // sdram_wire.addr
output [1 :0] sdram_ba, // .ba
output sdram_cas_n, // .cas_n
167,8 → 187,11
);
`define ADD_FUNCTION 1
`include "../my_functions.v"
 
 
wire [TOTAL_O_WIDTH-1 : 0] gpio_o_array [TOTAL_ROUTERS_NUM-1 :0];
wire [FLIT_ARRAY_WIDTH-1 : 0] router_flit_in_array [TOTAL_ROUTERS_NUM-1 :0];
wire [PORT_NUM-1 : 0] router_wr_in_en_array [TOTAL_ROUTERS_NUM-1 :0];
189,10 → 212,10
//synthesis translate_off
//In case we want to handle NI interface using testbench not aeMB
wire [AEMB_DWB-1 :2] cpu_adr_i [TOTAL_ROUTERS_NUM-1 :0];
wire [31 :0] cpu_dat_i [TOTAL_ROUTERS_NUM-1 :0];
wire [3 :0] cpu_sel_i [TOTAL_ROUTERS_NUM-1 :0];
wire [31 :0] cpu_dat_o [TOTAL_ROUTERS_NUM-1 :0];
wire [AEMB_DWB-1 : 2] cpu_adr_i [TOTAL_ROUTERS_NUM-1 :0];
wire [31 : 0] cpu_dat_i [TOTAL_ROUTERS_NUM-1 :0];
wire [3 : 0] cpu_sel_i [TOTAL_ROUTERS_NUM-1 :0];
wire [31 : 0] cpu_dat_o [TOTAL_ROUTERS_NUM-1 :0];
//synthesis translate_on
 
205,6 → 228,28
 
for (x=0; x<X_NODE_NUM; x=x+1) begin :x_loop
for (y=0; y<Y_NODE_NUM; y=y+1) begin: y_loop
localparam RAM_EN = s2i(ip_value(x,y,RAM_EN_ARRAY));
localparam NOC_EN = s2i(ip_value(x,y,NOC_EN_ARRAY));
localparam GPIO_EN = s2i(ip_value(x,y,GPIO_EN_ARRAY));
localparam EXT_INT_EN = s2i(ip_value(x,y,EXT_INT_EN_ARRAY));
localparam EXT_INT_NUM = s2i(ip_value(x,y,EXT_INT_NUM_ARRAY));
localparam TIMER_EN = s2i(ip_value(x,y,TIMER_EN_ARRAY));
localparam INT_CTRL_EN = s2i(ip_value(x,y,INT_CTRL_EN_ARRAY));
localparam IO_EN = s2i(ip_value(x,y,IO_EN_ARRAY));
localparam I_EN = s2i(ip_value(x,y,I_EN_ARRAY));
localparam O_EN = s2i(ip_value(x,y,O_EN_ARRAY));
localparam IO_PORT_WIDTH = ip_value(x,y,IO_PORT_WIDTH_ARRAY);
localparam I_PORT_WIDTH = ip_value(x,y,I_PORT_WIDTH_ARRAY);
localparam O_PORT_WIDTH = ip_value(x,y,O_PORT_WIDTH_ARRAY);
localparam EXT_INT_END = end_loc_in_array (x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY);
localparam EXT_INT_STRT = start_loc_in_array (x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY);
localparam IO_END = end_loc_in_array (x,y,X_NODE_NUM,IO_PORT_WIDTH_ARRAY);
localparam IO_STRT = start_loc_in_array (x,y,X_NODE_NUM,IO_PORT_WIDTH_ARRAY);
localparam I_END = end_loc_in_array (x,y,X_NODE_NUM,I_PORT_WIDTH_ARRAY);
localparam I_STRT = start_loc_in_array (x,y,X_NODE_NUM,I_PORT_WIDTH_ARRAY);
localparam O_END = end_loc_in_array (x,y,X_NODE_NUM,O_PORT_WIDTH_ARRAY);
localparam O_STRT = start_loc_in_array (x,y,X_NODE_NUM,O_PORT_WIDTH_ARRAY);
localparam IP_NUM = `CORE_NUM(x,y);
if( SDRAM_EN == 1 && x == SDRAM_SW_X_ADDR && y == SDRAM_SW_Y_ADDR) begin : sdram_gen
230,13 → 275,13
.clk (clk) ,
// NOC interfaces
.flit_out (ni_flit_out [`CORE_NUM(x,y)]),
.flit_out_wr (ni_flit_out_wr [`CORE_NUM(x,y)]),
.credit_in (ni_credit_in [`CORE_NUM(x,y)]),
.flit_out (ni_flit_out [IP_NUM]),
.flit_out_wr (ni_flit_out_wr [IP_NUM]),
.credit_in (ni_credit_in [IP_NUM]),
.flit_in (ni_flit_in [`CORE_NUM(x,y)]),
.flit_in_wr (ni_flit_in_wr [`CORE_NUM(x,y)]),
.credit_out (ni_credit_out [`CORE_NUM(x,y)]) ,
.flit_in (ni_flit_in [IP_NUM]),
.flit_in_wr (ni_flit_in_wr [IP_NUM]),
.credit_out (ni_credit_out [IP_NUM]) ,
.sdram_addr (sdram_addr) ,
.sdram_ba (sdram_ba) ,
252,13 → 297,22
end else begin : aeMB_core_gen
 
 
aeMB_IP #(
.RAM_EN (RAM_EN),
.RAM_EN (RAM_EN),
.NOC_EN (NOC_EN),
.GPIO_EN (GPIO_EN),
.GPIO_PORT_WIDTH (GPIO_PORT_WIDTH),
.GPIO_PORT_NUM (GPIO_PORT_NUM),
.EXT_INT_EN (EXT_INT_EN),
.TIMER_EN (TIMER_EN),
.INT_CTRL_EN (INT_CTRL_EN),
.IO_EN (IO_EN),
.I_EN (I_EN),
.O_EN (O_EN),
.IO_PORT_WIDTH (IO_PORT_WIDTH),
.I_PORT_WIDTH (I_PORT_WIDTH),
.O_PORT_WIDTH (O_PORT_WIDTH),
.EXT_INT_NUM (EXT_INT_NUM),
.AEMB_IWB (AEMB_IWB), ///< INST bus width
.AEMB_DWB (AEMB_DWB), ///< DATA bus width
.NI_CTRL_SIMULATION (NI_CTRL_SIMULATION),
276,35 → 330,41
.SW_Y_ADDR (y),
.NIC_CONNECT_PORT (0), // 0:Local 1:East, 2:North, 3:West, 4:South
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
.CORE_NUMBER (`CORE_NUM(x,y))
.CORE_NUMBER (IP_NUM)
)
ip_core
(
.reset_in (reset) ,
.clk (clk) ,
.sys_int_i (1'b0),
.sys_ena_i (1'b1),
.gpio (led [`CORE_NUM(x,y)]),
// .ext_int_i (`assign_mpsoc_pin(ext_int_i,x,y,EXT_INT_NUM_ARRAY)), //((end_loc_in_array(x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY)+1 != start_loc_in_array(x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY))? ext_int_i [end_loc_in_array(x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY) :start_loc_in_array(x,y,X_NODE_NUM,EXT_INT_NUM_ARRAY)]:'hx),
// .gpio_io (`assign_mpsoc_pin(gpio_io,x,y,IO_PORT_WIDTH_ARRAY)),//( [end_loc_in_array(x,y,X_NODE_NUM,IO_PORT_WIDTH_ARRAY) :start_loc_in_array(x,y,X_NODE_NUM,IO_PORT_WIDTH_ARRAY)]),
// .gpio_i (`assign_mpsoc_pin(gpio_i,x,y,I_PORT_WIDTH_ARRAY)),//[end_loc_in_array(x,y,X_NODE_NUM,I_PORT_WIDTH_ARRAY) :start_loc_in_array(x,y,X_NODE_NUM,I_PORT_WIDTH_ARRAY)]),
// .gpio_o (`assign_mpsoc_pin(gpio_o,x,y,O_PORT_WIDTH_ARRAY)), //(gpio_o [end_loc_in_array(x,y,X_NODE_NUM,O_PORT_WIDTH_ARRAY) :start_loc_in_array(x,y,X_NODE_NUM,O_PORT_WIDTH_ARRAY)]),
.ext_int_i (ext_int_i[EXT_INT_END: EXT_INT_STRT]),
.gpio_io (gpio_io [IO_END : IO_STRT]),
.gpio_i (gpio_i [I_END : I_STRT]),
.gpio_o (gpio_o_array[IP_NUM][O_END-O_STRT : 0]),//((O_EN) ? gpio_o [O_END : O_STRT]: 1'bZ)),
// NOC interfaces
.flit_out (ni_flit_out [`CORE_NUM(x,y)]),
.flit_out_wr (ni_flit_out_wr [`CORE_NUM(x,y)]),
.credit_in (ni_credit_in [`CORE_NUM(x,y)]),
.flit_out (ni_flit_out [IP_NUM]),
.flit_out_wr (ni_flit_out_wr [IP_NUM]),
.credit_in (ni_credit_in [IP_NUM]),
.flit_in (ni_flit_in [`CORE_NUM(x,y)]),
.flit_in_wr (ni_flit_in_wr [`CORE_NUM(x,y)]),
.credit_out (ni_credit_out [`CORE_NUM(x,y)])
.flit_in (ni_flit_in [IP_NUM]),
.flit_in_wr (ni_flit_in_wr [IP_NUM]),
.credit_out (ni_credit_out [IP_NUM])
//synthesis translate_off
,
.cpu_dat_i (cpu_dat_i [`CORE_NUM(x,y)]),
.cpu_sel_i (cpu_sel_i [`CORE_NUM(x,y)]),
.cpu_adr_i (cpu_adr_i [`CORE_NUM(x,y)]),
.cpu_stb_i (cpu_stb_i [`CORE_NUM(x,y)]),
.cpu_wre_i (cpu_wre_i [`CORE_NUM(x,y)]),
.cpu_cyc_i (cpu_cyc_i [`CORE_NUM(x,y)]),
.cpu_dat_o (cpu_dat_o [`CORE_NUM(x,y)]),
.cpu_ack_o (cpu_ack_o [`CORE_NUM(x,y)])
.cpu_dat_i (cpu_dat_i [IP_NUM]),
.cpu_sel_i (cpu_sel_i [IP_NUM]),
.cpu_adr_i (cpu_adr_i [IP_NUM]),
.cpu_stb_i (cpu_stb_i [IP_NUM]),
.cpu_wre_i (cpu_wre_i [IP_NUM]),
.cpu_cyc_i (cpu_cyc_i [IP_NUM]),
.cpu_dat_o (cpu_dat_o [IP_NUM]),
.cpu_ack_o (cpu_ack_o [IP_NUM])
//synthesis translate_on
312,6 → 372,8
);
if(O_EN) assign gpio_o [O_END : O_STRT] = gpio_o_array[IP_NUM][O_END-O_STRT : 0];
end
router#(
332,12 → 394,12
)
the_router
(
.wr_in_en_array (router_wr_in_en_array [`CORE_NUM(x,y)]),
.flit_in_array (router_flit_in_array [`CORE_NUM(x,y)]),
.credit_out_array (router_credit_out_array [`CORE_NUM(x,y)]),
.wr_out_en_array (router_wr_out_en_array [`CORE_NUM(x,y)]),
.flit_out_array (router_flit_out_array [`CORE_NUM(x,y)]),
.credit_in_array (router_credit_in_array [`CORE_NUM(x,y)]),
.wr_in_en_array (router_wr_in_en_array [IP_NUM]),
.flit_in_array (router_flit_in_array [IP_NUM]),
.credit_out_array (router_credit_out_array [IP_NUM]),
.wr_out_en_array (router_wr_out_en_array [IP_NUM]),
.flit_out_array (router_flit_out_array [IP_NUM]),
.credit_in_array (router_credit_in_array [IP_NUM]),
.clk (clk),
.reset (reset)
);
355,16 → 417,16
if(x < X_NODE_NUM-1) begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE((x+1),y,3,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((x+1),y,3,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = router_wr_out_en_array [`CORE_NUM((x+1),y)][3];
assign router_wr_in_en_array [IP_NUM][1] = router_wr_out_en_array [`CORE_NUM((x+1),y)][3];
end else begin
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = 1'b0;
assign router_wr_in_en_array [IP_NUM][1] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,1,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(0,y,3,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(0,y,3,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][1] = router_wr_out_en_array [`CORE_NUM(0,y)][3];
assign router_wr_in_en_array [IP_NUM][1] = router_wr_out_en_array [`CORE_NUM(0,y)][3];
end //topology
end
372,16 → 434,16
if(y>0) begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,(y-1),4,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(y-1),4,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = router_wr_out_en_array [`CORE_NUM(x,(y-1))][4];
assign router_wr_in_en_array [IP_NUM][2] = router_wr_out_en_array [`CORE_NUM(x,(y-1))][4];
end else begin
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = 1'b0;
assign router_wr_in_en_array [IP_NUM][2] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,2,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,(Y_NODE_NUM-1),4,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(Y_NODE_NUM-1),4,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][2] = router_wr_out_en_array [`CORE_NUM(x,(Y_NODE_NUM-1))][4];
assign router_wr_in_en_array [IP_NUM][2] = router_wr_out_en_array [`CORE_NUM(x,(Y_NODE_NUM-1))][4];
end//topology
end//y>0
389,16 → 451,16
if(x>0)begin
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE((x-1),y,1,FLIT_WIDTH)] ;
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((x-1),y,1,VC_NUM_PER_PORT)] ;
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = router_wr_out_en_array [`CORE_NUM((x-1),y)][1];
assign router_wr_in_en_array [IP_NUM][3] = router_wr_out_en_array [`CORE_NUM((x-1),y)][1];
end else begin
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = 1'b0;
assign router_wr_in_en_array [IP_NUM][3] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,3,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE((X_NODE_NUM-1),y,1,FLIT_WIDTH)] ;
assign router_credit_in_array [`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE((X_NODE_NUM-1),y,1,VC_NUM_PER_PORT)] ;
assign router_wr_in_en_array [`CORE_NUM(x,y)][3] = router_wr_out_en_array [`CORE_NUM((X_NODE_NUM-1),y)][1];
assign router_wr_in_en_array [IP_NUM][3] = router_wr_out_en_array [`CORE_NUM((X_NODE_NUM-1),y)][1];
end//topology
end
405,29 → 467,29
if(y < Y_NODE_NUM-1)begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,(y+1),2,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,(y+1),2,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = router_wr_out_en_array [`CORE_NUM(x,(y+1))][2];
assign router_wr_in_en_array [IP_NUM][4] = router_wr_out_en_array [`CORE_NUM(x,(y+1))][2];
end else begin
if(TOPOLOGY == "MESH") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = {FLIT_WIDTH{1'b0}};
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = {VC_NUM_PER_PORT{1'b0}};
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = 1'b0;
assign router_wr_in_en_array [IP_NUM][4] = 1'b0;
end else if(TOPOLOGY == "TORUS") begin
assign router_flit_in_array [`SELECT_WIRE(x,y,4,FLIT_WIDTH)] = router_flit_out_array [`SELECT_WIRE(x,0,2,FLIT_WIDTH)];
assign router_credit_in_array [`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)] = router_credit_out_array [`SELECT_WIRE(x,0,2,VC_NUM_PER_PORT)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][4] = router_wr_out_en_array [`CORE_NUM(x,0)][2];
assign router_wr_in_en_array [IP_NUM][4] = router_wr_out_en_array [`CORE_NUM(x,0)][2];
end//topology
end
//connection to the ip_core
assign router_flit_in_array [`SELECT_WIRE(x,y,0,FLIT_WIDTH)] = ni_flit_out [`CORE_NUM(x,y)];
assign router_credit_in_array [`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)] = ni_credit_out [`CORE_NUM(x,y)];
assign router_wr_in_en_array [`CORE_NUM(x,y)][0] = ni_flit_out_wr [`CORE_NUM(x,y)];
assign router_flit_in_array [`SELECT_WIRE(x,y,0,FLIT_WIDTH)] = ni_flit_out [IP_NUM];
assign router_credit_in_array [`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)] = ni_credit_out [IP_NUM];
assign router_wr_in_en_array [IP_NUM][0] = ni_flit_out_wr [IP_NUM];
assign ni_flit_in [`CORE_NUM(x,y)] = router_flit_out_array [`SELECT_WIRE(x,y,0,FLIT_WIDTH)];
assign ni_flit_in_wr [`CORE_NUM(x,y)] = router_wr_out_en_array [`CORE_NUM(x,y)][0];
assign ni_credit_in [`CORE_NUM(x,y)] = router_credit_out_array[`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)];
assign ni_flit_in [IP_NUM] = router_flit_out_array [`SELECT_WIRE(x,y,0,FLIT_WIDTH)];
assign ni_flit_in_wr [IP_NUM] = router_wr_out_en_array [IP_NUM][0];
assign ni_credit_in [IP_NUM] = router_credit_out_array [`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)];
 
434,10 → 496,10
 
//synthesis translate_off
assign cpu_adr_i [`CORE_NUM(x,y)] = cpu_adr_i_array [(`CORE_NUM(x,y)+1)*(CPU_ADR_WIDTH)-1 : `CORE_NUM(x,y)*CPU_ADR_WIDTH];
assign cpu_dat_i [`CORE_NUM(x,y)] = cpu_dat_i_array [(`CORE_NUM(x,y)+1)*32-1 : `CORE_NUM(x,y)*32 ];
assign cpu_sel_i [`CORE_NUM(x,y)] = cpu_sel_i_array [(`CORE_NUM(x,y)+1)*4-1 : `CORE_NUM(x,y)*4 ];
assign cpu_dat_o_array [(`CORE_NUM(x,y)+1)*32-1 : `CORE_NUM(x,y)*32] = cpu_dat_o [`CORE_NUM(x,y)];
assign cpu_adr_i [IP_NUM] = cpu_adr_i_array [(IP_NUM+1)*(CPU_ADR_WIDTH)-1 : IP_NUM*CPU_ADR_WIDTH];
assign cpu_dat_i [IP_NUM] = cpu_dat_i_array [(IP_NUM+1)*32-1 : IP_NUM*32 ];
assign cpu_sel_i [IP_NUM] = cpu_sel_i_array [(IP_NUM+1)*4-1 : IP_NUM*4 ];
assign cpu_dat_o_array [(IP_NUM+1)*32-1 : IP_NUM*32] = cpu_dat_o [IP_NUM];
//synthesis translate_on
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/wishbone_bus.v
35,6 → 35,10
parameter RAM_EN = 1,
parameter NOC_EN = 0,
parameter GPIO_EN = 1,
parameter EXT_INT_EN = 1,
parameter TIMER_EN = 1,
parameter INT_CTRL_EN = 1,
parameter GPIO_WIDTH = 56,
parameter MASTER_NUM_ = 4, //number of master port
parameter SLAVE_NUM_ = 4, //number of slave port
173,6 → 177,10
.RAM_EN (RAM_EN),
.NOC_EN (NOC_EN),
.GPIO_EN (GPIO_EN),
.EXT_INT_EN (EXT_INT_EN),
.TIMER_EN (TIMER_EN),
.INT_CTRL_EN (INT_CTRL_EN),
.ADDR_PERFIX_ (ADDR_PERFIX),
.SLAVE_NUM_ (SLAVE_NUM)
)
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/reset_jtag.v
0,0 → 1,107
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
 
// ============================================================
// File Name: reset_jtag.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module reset_jtag (
probe,
source);
 
input [0:0] probe;
output [0:0] source;
 
wire [0:0] sub_wire0;
wire [0:0] source = sub_wire0[0:0];
 
altsource_probe altsource_probe_component (
.probe (probe),
.source (sub_wire0)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "NO",
altsource_probe_component.instance_id = "RST",
altsource_probe_component.probe_width = 1,
altsource_probe_component.sld_auto_instance_index = "NO",
altsource_probe_component.sld_instance_index = 127,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "127"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]"
// Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]"
// Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0
// Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/ext_int.v
0,0 → 1,99
module ext_int #(
parameter EXT_INT_NUM = 3,//max 32
parameter ADDR_WIDTH = 3,
parameter SEL_WIDTH = 4,
parameter DATA_WIDTH = EXT_INT_NUM
 
)(
input clk,
input reset,
//wishbone bus interface
input [DATA_WIDTH-1 : 0] sa_dat_i,
input [SEL_WIDTH-1 : 0] sa_sel_i,
input [ADDR_WIDTH-1 : 0] sa_addr_i,
input sa_stb_i,
input sa_we_i,
output [DATA_WIDTH-1 : 0] sa_dat_o,
output reg sa_ack_o,
//interrupt ports
input [EXT_INT_NUM-1 : 0] ext_int_i,
output [EXT_INT_NUM-1 : 0] ext_int_o //output to the interrupt controller
);
 
//interrupt registers
localparam [ADDR_WIDTH-1 : 0] GER_REG_ADDR = 0;
localparam [ADDR_WIDTH-1 : 0] IER_RISING_REG_ADDR = 1;
localparam [ADDR_WIDTH-1 : 0] IER_FALLING_REG_ADDR = 2;
localparam [ADDR_WIDTH-1 : 0] ISR_REG_ADDR = 3;
localparam [ADDR_WIDTH-1 : 0] PIN_REG_ADDR = 4;
reg ger,ger_next;
reg [EXT_INT_NUM-1 : 0] ier_rise,ier_fall,isr,read,int_reg1,int_reg2;//2
reg [EXT_INT_NUM-1 : 0] ier_rise_next,ier_fall_next,isr_next,read_next,int_reg1_next,int_reg2_next;
wire [EXT_INT_NUM-1 : 0] triggered,rise_edge,fall_edge;
assign rise_edge = (ger)? ier_rise & ~int_reg2 & int_reg1 : {EXT_INT_NUM{1'b0}};
assign fall_edge = (ger)? ier_fall & int_reg2 & ~int_reg1 : {EXT_INT_NUM{1'b0}};
assign triggered = rise_edge | fall_edge;
always @ (posedge clk or posedge reset) begin
if(reset) begin
ger <= 1'b0;
ier_rise <= {EXT_INT_NUM{1'b0}};
ier_fall <= {EXT_INT_NUM{1'b0}};
isr <= {EXT_INT_NUM{1'b0}};
read <= {EXT_INT_NUM{1'b0}};
int_reg1 <= {EXT_INT_NUM{1'b0}};
int_reg2 <= {EXT_INT_NUM{1'b0}};
sa_ack_o <= 1'b0;
end else begin
ger <= ger_next;
ier_rise <= ier_rise_next;
ier_fall <= ier_fall_next;
isr <= isr_next;
read <= read_next;
int_reg1 <= int_reg1_next;
int_reg2 <= int_reg2_next;
sa_ack_o <= sa_stb_i && ~sa_ack_o;
end//
end//always
always@(*) begin
int_reg2_next = int_reg1;
int_reg1_next = ext_int_i;
ger_next = ger;
ier_rise_next = ier_rise;
ier_fall_next = ier_fall;
isr_next = isr | triggered; // set isr if the intrrupt is triggered
read_next = read;
if(sa_stb_i && sa_we_i ) begin
if( sa_addr_i == GER_REG_ADDR ) ger_next = sa_dat_i[0];
if( sa_addr_i == IER_RISING_REG_ADDR ) ier_rise_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0];
if( sa_addr_i == IER_FALLING_REG_ADDR ) ier_fall_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0];
if( sa_addr_i == ISR_REG_ADDR ) isr_next = isr & ~sa_dat_i[EXT_INT_NUM-1'b1 : 0];// reset isr by writting 1
end
if(sa_stb_i && ~sa_we_i) begin
case(sa_addr_i)
GER_REG_ADDR: read_next = {{(EXT_INT_NUM-1){1'b0}},ger};
IER_RISING_REG_ADDR: read_next = ier_rise;
IER_FALLING_REG_ADDR: read_next = ier_fall;
ISR_REG_ADDR: read_next = isr;
PIN_REG_ADDR: read_next = ext_int_i;
default read_next = read;
endcase
end
end//always
assign sa_dat_o = read;
assign ext_int_o= isr;
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/my_functions.v
0,0 → 1,264
/* Add
"`define ADD_FUNCTION "
before calling the function `include "../my_function.v".
*/
 
`ifdef ADD_FUNCTION
/*****************************
extract the nth value of an string as a decemila value. the values inside
the string parameter must be seperated by "," e.g
parameter mystring = "12,3,8"
then extract_value(mystring,2) is integer 12
*****************************/
 
function integer extract_value;
input reg[1000:0] port_size_string;
input integer value_loc;
integer end_char;
integer i,j,width;
reg[7:0] tmp;
reg[1000:0] buffer;
begin
width=0;
i=0;
j=0;
if(value_loc>0) begin //locate the start ','
while(j<value_loc) begin
buffer=(port_size_string >>(i*8));
tmp = buffer[7:0];
if(tmp ==",") begin
j=j+1'b1;
end
i=i+1'b1;
end//while
end
end_char=0;
j=0;
while(end_char==0)begin
buffer=(port_size_string >>(i*8));
tmp = buffer[7:0];
if(tmp =="," || tmp ==0) begin
end_char=1;
end else begin
width= (j==0)? tmp-"0" : width + ((j*10)*(tmp-"0"));
end
i=i+1'b1;
j=j+1'b1;
end//while
extract_value = width;
end
endfunction
 
/*****************************
 
return the sum of all values in string
 
*****************************/
 
function integer sum_of_all;
input reg[1000:0] port_size_string;
integer total_port_num;
integer i;
begin
total_port_num=number_of_port(port_size_string) ;
sum_of_all=0;
for (i=0; i< total_port_num; i=i+1'b1) begin
sum_of_all = sum_of_all+ extract_value(port_size_string,i);
end//for
end
endfunction
function integer start_loc;
input reg[1000:0] port_size_string;
input integer value_num;
integer i;
begin
start_loc=0;
for (i=0; i< value_num; i=i+1'b1) begin
start_loc = start_loc + extract_value(port_size_string,i);
end//for
end
endfunction
 
function integer number_of_port;
input reg[1000:0] port_size_string;
integer i;
begin
number_of_port=1;
while(port_size_string[7:0]!=8'h0) begin
if (port_size_string[7:0]==",") number_of_port=number_of_port+1'b1;
port_size_string = port_size_string >>8;
end//while
end
endfunction
/************************
parameter DEV_EN_ARRAY ="IPx_y:[the specefic value for IP(x,y)];Def:[default value for the rest of IPs]"
ip_value(ip_x,ip_y,DEV_EN_ARRAY) : will extract the defined value for IP(x,y)
eg:
parameter O_PORT_WIDTH_ARRAY ="IP0_0:7,7,7,7,7,7,7,7;Def:1";
parameter O_PORT_WIDTH_0 = ip_value(0,0,O_PORT_WIDTH_ARRAY); // will load "7,7,7,7,7,7,7,7" in O_PORT_WIDTH_0
parameter O_PORT_WIDTH_5 = ip_value(5,0,O_PORT_WIDTH_ARRAY); // will load "1" in O_PORT_WIDTH_5
**************************/
function integer string_size;
input reg [1000:0] string_i;
begin
string_size = 0;
while ( string_i[7:0]!= 0) begin
string_size = string_size+ 1'b1;
string_i = string_i >> 8;
end
end
endfunction
 
function reg [1000:0] mask;
input integer size;
begin
mask=0;
while (size >0) begin
mask = mask<<8;
mask = mask +8'hFF;
size = size-1'b1;
end
end
endfunction
 
 
function integer find_loc;
input reg [1000:0] string_i;
input reg [1000:0] array;
input integer end_loc;
integer str_size;
integer loc;
begin
loc=0;
str_size = string_size(string_i);
find_loc = -1;
while ( array[7:0]!=0 && loc!=end_loc) begin
if((array & mask(str_size)) == (string_i & mask(str_size))) find_loc=loc;
array = array >> 8;
loc = loc +1'b1;
end
end
endfunction
 
function reg [1000:0] cut_string;
input reg [1000:0] string_i;
input integer start_loc;
input integer end_loc;
integer tmp;
begin
if(end_loc < start_loc ) begin //swap
tmp=start_loc;
start_loc = end_loc;
end_loc = tmp;
end
string_i = string_i & mask(end_loc);
string_i = string_i >> (start_loc*8);
cut_string = string_i;
end
endfunction
 
 
 
function reg [1000:0] ip_value;
input integer ip_x,ip_y;
input reg [1000:0] ip_array;
reg [1000:0] ip_name;
integer tmp,i,ip_loc,end_ip_value,size;
begin
//make IPnum string
ip_name = "IP";
i=1;
while(i)begin
tmp= ip_x;
i=0;
while(tmp>9)begin tmp= tmp/10; i=i+1; end
ip_name = (ip_name << 8 )+ tmp+"0";
ip_x = ip_x % (10**i);
end
ip_name = (ip_name << 8 )+ "_";
i=1;
while(i)begin
tmp= ip_y;
i=0;
while(tmp>9)begin tmp= tmp/10; i=i+1; end
ip_name = (ip_name << 8 )+ tmp+"0";
ip_y = ip_y % (10**i);
end
ip_name = (ip_name << 8 )+ ":";
size=string_size(ip_array);
ip_loc= find_loc (ip_name,ip_array,size);
if(ip_loc == -1) ip_loc= find_loc("Def:",ip_array,size);
end_ip_value =find_loc (";",ip_array,ip_loc);
ip_value = cut_string(ip_array,ip_loc,end_ip_value+1);
end
endfunction
function integer s2i;
input [1000:0] string_i;
integer i;
begin
s2i =0;
i=0;
while (string_i [7:0]!=0) begin
s2i = s2i+(string_i [7:0]-"0")* (10**i);
string_i = string_i >> 8;
i=i+1'b1;
end
end
endfunction
 
 
function integer start_loc_in_array;
input integer ip_x,ip_y;
input integer max_x_num;
input [1000: 0] string_i;
integer x,y,sum;
begin
start_loc_in_array =0;
for (y=0; y<ip_y; y=y+1) begin
for(x=0; x<max_x_num; x=x+1 ) begin
sum = sum_of_all(ip_value(x,y,string_i));
// if(sum==0) sum =1;
start_loc_in_array = start_loc_in_array + sum;
end
end//for y
for(x=0; x<ip_x; x=x+1 ) begin
sum = sum_of_all(ip_value(x,y,string_i));
// if(sum==0) sum =1;
start_loc_in_array = start_loc_in_array + sum;
end
end
endfunction
 
 
function integer end_loc_in_array;
input integer ip_x,ip_y;
input integer max_x_num;
input [1000: 0] string_i;
integer sum;
begin
end_loc_in_array = start_loc_in_array(ip_x,ip_y,max_x_num,string_i);
sum = sum_of_all(ip_value(ip_x,ip_y,string_i));
if(sum==0) sum =1;
end_loc_in_array = end_loc_in_array + sum-1;
end
endfunction
 
 
 
`endif
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/testbench_noc.v
54,27 → 54,60
parameter CPU_ADR_WIDTH = AEMB_DWB-2;
parameter CPU_ADDR_ARRAY_WIDTH = CPU_ADR_WIDTH * TOTAL_ROUTERS_NUM;
parameter CPU_DATA_ARRAY_WIDTH = 32 * TOTAL_ROUTERS_NUM;
parameter RAM_EN = 1;
parameter NOC_EN = 1;
parameter GPIO_EN = 1;
parameter GPIO_PORT_WIDTH = 1;
parameter GPIO_PORT_NUM = 1;
parameter RAM_EN_ARRAY = "Def:1";
parameter NOC_EN_ARRAY = "Def:1";
parameter GPIO_EN_ARRAY = "Def:1";
parameter EXT_INT_EN_ARRAY = "IP0_0:1;Def:0";
parameter TIMER_EN_ARRAY = "IP0_0:1;Def:0";
parameter INT_CTRL_EN_ARRAY = "IP0_0:1;Def:0";
//gpio parameters
parameter IO_EN_ARRAY = "Def:0";
parameter I_EN_ARRAY = "Def:0";
parameter O_EN_ARRAY = "IP0_1:0;Def:1";
parameter EXT_INT_NUM_ARRAY = "IP0_0:3;Def:0";//max 32
parameter IO_PORT_WIDTH_ARRAY = "Def:1";
parameter I_PORT_WIDTH_ARRAY = "Def:0";
parameter O_PORT_WIDTH_ARRAY = "IP0_0:7,7,7,7,7,7,7,7;IP0_1:0;Def:1";
localparam X_NODE_NUM_WIDTH = log2(X_NODE_NUM);
localparam Y_NODE_NUM_WIDTH = log2(Y_NODE_NUM);
localparam PORT_NUM_BCD_WIDTH = log2(PORT_NUM);
//generate the base addresses
`define ADD_BUS_LOCALPARAM 1
localparam RAM_EN = 1;
localparam NOC_EN = 1;
localparam GPIO_EN = 1;
localparam EXT_INT_EN = 1;
localparam TIMER_EN = 1;
localparam INT_CTRL_EN = 1;
`include "parameter.v"
`define ADD_FUNCTION 1
`include "my_functions.v"
`LOG2
 
reg reset ,clk;
wire[TOTAL_ROUTERS_NUM-1 :0] led;
localparam TOTAL_EXT_INT_NUM = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,EXT_INT_NUM_ARRAY)+1;
localparam TOTAL_IO_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,IO_PORT_WIDTH_ARRAY)+1;
localparam TOTAL_I_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,I_PORT_WIDTH_ARRAY)+1;
localparam TOTAL_O_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,O_PORT_WIDTH_ARRAY)+1;
reg reset ,clk;
reg [TOTAL_EXT_INT_NUM-1 :0] ext_int_i;
wire [TOTAL_IO_WIDTH-1 :0] gpio_io;
reg [TOTAL_I_WIDTH-1 :0] gpio_i;
wire [TOTAL_O_WIDTH-1 :0] gpio_o;
 
 
wire [CPU_ADDR_ARRAY_WIDTH-1 :0] cpu_adr_i_array;
111,7 → 144,7
end
endgenerate
 
wire [12 :0] sdram_addr; // sdram_wire.addr
wire [12 :0] sdram_addr; // sdram_wire.addr
wire [1 :0] sdram_ba; // .ba
wire sdram_cas_n; // .cas_n
wire sdram_cke; // .cke
155,18 → 188,30
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
.AEMB_DWB (AEMB_DWB),
.SDRAM_EN (SDRAM_EN),
.RAM_EN (RAM_EN),
.NOC_EN (NOC_EN),
.GPIO_EN (GPIO_EN),
.GPIO_PORT_WIDTH (GPIO_PORT_WIDTH),
.GPIO_PORT_NUM (GPIO_PORT_NUM)
.RAM_EN_ARRAY (RAM_EN_ARRAY),
.NOC_EN_ARRAY (NOC_EN_ARRAY),
.GPIO_EN_ARRAY (GPIO_EN_ARRAY),
.EXT_INT_EN_ARRAY (EXT_INT_EN_ARRAY),
.TIMER_EN_ARRAY (TIMER_EN_ARRAY),
.INT_CTRL_EN_ARRAY (INT_CTRL_EN_ARRAY),
.IO_EN_ARRAY (IO_EN_ARRAY),
.I_EN_ARRAY (I_EN_ARRAY),
.O_EN_ARRAY (O_EN_ARRAY),
.EXT_INT_NUM_ARRAY (EXT_INT_NUM_ARRAY),
.IO_PORT_WIDTH_ARRAY (IO_PORT_WIDTH_ARRAY),
.I_PORT_WIDTH_ARRAY (I_PORT_WIDTH_ARRAY),
.O_PORT_WIDTH_ARRAY (O_PORT_WIDTH_ARRAY)
)
aeMB_mpsoc_inst
(
.reset (reset) , // reg
.clk (clk) , // reg
.led (led), // wire
.reset (reset), // reg
.clk (clk), // reg
.ext_int_i (ext_int_i),
.gpio_io (gpio_io),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.sdram_addr (sdram_addr) , // wire [12:0] sdram_addr
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/SoC_IP_top.v
0,0 → 1,139
/*********************************************************************
File: SoC_IP_top.v
Copyright (C) 2014 Alireza Monemi
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Purpose:
The top module for SoC with one aeMB processor, wishbone bus, gpio
and timer
 
Info: monemi@fkegraduate.utm.my
 
****************************************************************/
 
 
module SoC_IP_top (
input CLOCK_50,
input [3 : 0] KEY,
output [3 : 0] LEDG,
output [6 : 0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7
 
 
);
 
 
parameter SEVEN_SEG_NUM = 8;
parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF;
parameter RAM_EN = 1;
parameter GPIO_EN = 1;
parameter EXT_INT_EN = 1;
parameter TIMER_EN = 1;
parameter INT_CTRL_EN = 1;
//gpio parameters
parameter IO_EN = 0;
parameter I_EN = 0;
parameter O_EN = 1;
parameter IO_PORT_WIDTH = "0";
parameter I_PORT_WIDTH = "0";
parameter O_PORT_WIDTH = "7,7,7,7,7,7,7,7";
//external int parameters
parameter EXT_INT_NUM = 3;//max 32
 
 
wire [(SEVEN_SEG_NUM *7)-1 :0] seven_segment;
wire [2 :0] ext_int_i;
wire reset,reset_in,sys_en,sys_en_n;
wire clk;
assign sys_en = ~ sys_en_n;
assign clk = CLOCK_50;
assign LEDG[0] = reset;
assign LEDG[3:1]= ext_int_i;
assign {HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0} = seven_segment;
assign reset_in = ~KEY[0];
assign ext_int_i = ~KEY[3:1];
signal_holder #(
.DELAY_COUNT(1000)
)
hold_reset
(
.reset_in (reset_in),
.clk (clk),
.reset_out (reset)
);
signal_holder #(
.DELAY_COUNT(100)
)
hold_en
(
.reset_in (reset),
.clk (clk),
.reset_out (sys_en_n)
);
aeMB_IP #(
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD ),
.RAM_EN (RAM_EN),
.NOC_EN (0),
.GPIO_EN (GPIO_EN),
.EXT_INT_EN (EXT_INT_EN),
.TIMER_EN (TIMER_EN),
.INT_CTRL_EN (INT_CTRL_EN),
.IO_EN (IO_EN),
.I_EN (I_EN),
.O_EN (O_EN),
.IO_PORT_WIDTH (IO_PORT_WIDTH),
.I_PORT_WIDTH (I_PORT_WIDTH),
.O_PORT_WIDTH (O_PORT_WIDTH),
.EXT_INT_NUM (EXT_INT_NUM),
.SW_X_ADDR(0),
.SW_Y_ADDR(0)
)IP
(
.clk (clk),
.reset_in(reset),
.sys_ena_i(sys_en),
.ext_int_i(ext_int_i),
.gpio_io(),
.gpio_i(),
.gpio_o(seven_segment)
);
 
 
 
 
 
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/parameter.v
31,30 → 31,43
 
 
`ifdef ADD_BUS_LOCALPARAM
 
localparam MASTER_NUM = 2+NOC_EN; //number of master port
localparam SLAVE_NUM = RAM_EN + GPIO_EN + NOC_EN ; //number of slave port
localparam ADDR_PERFIX = 8;
localparam ADDR_PERFIX = 8;
// Total number of master port in wishbone bus. The aeMB has two master port. To add new device
// update its as : MASTER_NUM = 2+NOC_EN + (NEW_DEV_EN * number of master port the new device has)
localparam MASTER_NUM = 2+NOC_EN; //number of master port
//Total number of slave port.
// To add new device, update its as : SLAVE_NUM = old_value + (NEW_DEV_EN * number of slave port the new device has)
localparam SLAVE_NUM = RAM_EN + GPIO_EN + NOC_EN + EXT_INT_EN + TIMER_EN + INT_CTRL_EN;
 
// addrees range definition
localparam RAM_ADDR_START = 8'H00; // 32'H00000000 to 32'H3FFFFFFF
localparam RAM_BK_NUM = 8'H3F;
 
localparam RAM_ADDR_START = 8'H00; // 32'H00000000 to 32'H3FFFFFFF
localparam RAM_BK_NUM = 8'H3F;
 
localparam NOC_ADDR_START = 8'H40 ; // 32'H40000000 to 32'H40FFFFFF
localparam NOC_BK_NUM = 8'H01;
localparam NOC_ADDR_START = 8'H40; // 32'H40000000 to 32'H40FFFFFF
localparam NOC_BK_NUM = 8'H01;
localparam GPIO_ADDR_START= 8'H41; // 32'H41000000 to 32'H41FFFFFF
localparam GPIO_BK_NUM = 8'H01 ;
localparam GPIO_ADDR_START = 8'H41; // 32'H41000000 to 32'H41FFFFFF
localparam GPIO_BK_NUM = 8'H01;
localparam EXT_INT_ADDR_START = 8'H42; // 32'H42000000 to 32'H42FFFFFF
localparam EXT_INT_BK_NUM = 8'H01;
 
localparam TIMER_ADDR_START = 8'H43; // 32'H43000000 to 32'H43FFFFFF
localparam TIMER_BK_NUM = 8'H01;
 
localparam INT_CTRL_ADDR_START = 8'H44; // 32'H44000000 to 32'H44FFFFFF
localparam INT_CTRL_BK_NUM = 8'H01;
//add new device addr range here
// salve and master conection port definition
 
// salve and master coonection port definition
 
 
localparam RAM_ID = 0;
localparam RAM_ID_E = 0;
63,9 → 76,19
localparam GPIO_ID = ( GPIO_EN ) ? NOC_S_ID_E + 1 : 255;
localparam GPIO_ID_E = NOC_S_ID_E + GPIO_EN ;
localparam EXT_INT_ID = (EXT_INT_EN) ? GPIO_ID_E +1 : 255;
localparam EXT_INT_ID_E = GPIO_ID_E + EXT_INT_EN;
localparam TIMER_ID = (TIMER_EN) ? EXT_INT_ID_E +1 : 255;
localparam TIMER_ID_E = EXT_INT_ID_E + TIMER_EN;
localparam INT_CTRL_ID = (INT_CTRL_EN) ? TIMER_ID_E +1 : 255;
localparam INT_CTRL_ID_E = TIMER_ID_E + INT_CTRL_EN;
//localparam NEW_ID = (NEW_EN) ? LAST_ID_E +1 : 255;
//localparam NEW_ID_E = LAST_ID_E + NEW_EN;
//master device number
localparam IWB_ID = 0;
localparam IWB_ERR_EN = 0;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/testbench_mpsoc.v
0,0 → 1,238
/*********************************************************************
File: testbench.v
Copyright (C) 2014 Alireza Monemi
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Purpose:
A testbench for top-level design. This testbench can be used to simulate
a real life application. running the ./run file in sw folder
will copy the generated mif files in simulation folder which will be read
by modelsim. However, due to simulating the aemb processors it is slow
Info: monemi@fkegraduate.utm.my
*********************************************************************/
 
 
 
 
 
`timescale 1ns/1ps
`include "define.v"
 
module testbench_mpsoc ();
parameter NI_CTRL_SIMULATION = "aeMB";
/*"aeMB" or "testbench".
Definig it as " aeMB" will generate the same MPSoC for both simulation and
implementation.
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.v file */
parameter TOPOLOGY = `TOPOLOGY_DEF;
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF;
parameter X_NODE_NUM = `X_NODE_NUM_DEF;
parameter Y_NODE_NUM = `Y_NODE_NUM_DEF;
parameter PORT_NUM = 5;
parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF;
parameter TOTAL_ROUTERS_NUM = X_NODE_NUM * Y_NODE_NUM;
parameter AEMB_DWB = `AEMB_DWB_DEF;
parameter SDRAM_EN = `SDRAM_EN_DEF;// 0 : disabled 1: enabled
parameter CPU_ADR_WIDTH = AEMB_DWB-2;
parameter CPU_ADDR_ARRAY_WIDTH = CPU_ADR_WIDTH * TOTAL_ROUTERS_NUM;
parameter CPU_DATA_ARRAY_WIDTH = 32 * TOTAL_ROUTERS_NUM;
 
parameter RAM_EN_ARRAY = `RAM_EN_ARRAY_DEF;
parameter NOC_EN_ARRAY = `NOC_EN_ARRAY_DEF;
parameter GPIO_EN_ARRAY = `GPIO_EN_ARRAY_DEF;
parameter EXT_INT_EN_ARRAY = `EXT_INT_EN_ARRAY_DEF;
parameter TIMER_EN_ARRAY = `TIMER_EN_ARRAY_DEF;
parameter INT_CTRL_EN_ARRAY = `INT_CTRL_EN_ARRAY_DEF;
//gpio parameters
parameter IO_EN_ARRAY = `IO_EN_ARRAY_DEF;
parameter I_EN_ARRAY = `I_EN_ARRAY_DEF;
parameter O_EN_ARRAY = `O_EN_ARRAY_DEF;
parameter EXT_INT_NUM_ARRAY = `EXT_INT_NUM_ARRAY_DEF;
parameter IO_PORT_WIDTH_ARRAY = `IO_PORT_WIDTH_ARRAY_DEF;
parameter I_PORT_WIDTH_ARRAY = `I_PORT_WIDTH_ARRAY_DEF;
parameter O_PORT_WIDTH_ARRAY = `O_PORT_WIDTH_ARRAY_DEF;
localparam X_NODE_NUM_WIDTH = log2(X_NODE_NUM);
localparam Y_NODE_NUM_WIDTH = log2(Y_NODE_NUM);
localparam PORT_NUM_BCD_WIDTH = log2(PORT_NUM);
//`define ADD_BUS_LOCALPARAM 1
//`include "parameter.v"
`define ADD_FUNCTION 1
`include "my_functions.v"
`LOG2
 
localparam TOTAL_EXT_INT_NUM = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,EXT_INT_NUM_ARRAY)+1;
localparam TOTAL_IO_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,IO_PORT_WIDTH_ARRAY)+1;
localparam TOTAL_I_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,I_PORT_WIDTH_ARRAY)+1;
localparam TOTAL_O_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,O_PORT_WIDTH_ARRAY)+1;
reg reset ,clk;
reg [TOTAL_EXT_INT_NUM-1 :0] ext_int_i;
wire [TOTAL_IO_WIDTH-1 :0] gpio_io;
reg [TOTAL_I_WIDTH-1 :0] gpio_i;
wire [TOTAL_O_WIDTH-1 :0] gpio_o;
 
 
 
 
 
wire [12 :0] sdram_addr; // sdram_wire.addr
wire [1 :0] sdram_ba; // .ba
wire sdram_cas_n; // .cas_n
wire sdram_cke; // .cke
wire sdram_cs_n; // .cs_n
wire [31 :0] sdram_dq; // .dq
wire [3 :0] sdram_dqm; // .dqm
wire sdram_ras_n; // .ras_n
wire sdram_we_n; // .we_n
wire sdram_clk; // sdram_clk.clk
 
generate
if (SDRAM_EN) begin
sdram_sdram_controller_test_component sdram_test_component(
// regs:
.clk (clk),
.zs_addr (sdram_addr),
.zs_ba (sdram_ba),
.zs_cas_n (sdram_cas_n),
.zs_cke (sdram_cke),
.zs_cs_n (sdram_cs_n),
.zs_dqm (sdram_dqm),
.zs_ras_n (sdram_ras_n),
.zs_we_n (sdram_we_n),
// wires:
.zs_dq (sdram_dq)
);
end
endgenerate
 
aeMB_mpsoc #(
.NI_CTRL_SIMULATION (NI_CTRL_SIMULATION),
.TOPOLOGY (TOPOLOGY),
.ROUTE_ALGRMT (ROUTE_ALGRMT),
.X_NODE_NUM (X_NODE_NUM),
.Y_NODE_NUM (Y_NODE_NUM),
.AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD),
.AEMB_DWB (AEMB_DWB),
.SDRAM_EN (SDRAM_EN),
.RAM_EN_ARRAY (RAM_EN_ARRAY),
.NOC_EN_ARRAY (NOC_EN_ARRAY),
.GPIO_EN_ARRAY (GPIO_EN_ARRAY),
.EXT_INT_EN_ARRAY (EXT_INT_EN_ARRAY),
.TIMER_EN_ARRAY (TIMER_EN_ARRAY),
.INT_CTRL_EN_ARRAY (INT_CTRL_EN_ARRAY),
.IO_EN_ARRAY (IO_EN_ARRAY),
.I_EN_ARRAY (I_EN_ARRAY),
.O_EN_ARRAY (O_EN_ARRAY),
.EXT_INT_NUM_ARRAY (EXT_INT_NUM_ARRAY),
.IO_PORT_WIDTH_ARRAY (IO_PORT_WIDTH_ARRAY),
.I_PORT_WIDTH_ARRAY (I_PORT_WIDTH_ARRAY),
.O_PORT_WIDTH_ARRAY (O_PORT_WIDTH_ARRAY)
)
aeMB_mpsoc_inst
(
.reset (reset) , // reg
.clk (clk) , // reg
.ext_int_i (ext_int_i),
.gpio_io (gpio_io),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.sdram_addr (sdram_addr) , // wire [12:0] sdram_addr
.sdram_ba (sdram_ba) , // wire [1:0] sdram_ba
.sdram_cas_n (sdram_cas_n) , // wire sdram_cas_n
.sdram_cke (sdram_cke) , // wire sdram_cke
.sdram_cs_n (sdram_cs_n) , // wire sdram_cs_n
.sdram_dq (sdram_dq) , // inout [31:0] sdram_dq
.sdram_dqm (sdram_dqm) , // wire [3:0] sdram_dqm
.sdram_ras_n (sdram_ras_n) , // wire sdram_ras_n
.sdram_we_n (sdram_we_n) , // wire sdram_we_n
.sdram_clk (sdram_clk) // ou
//synthesis translate_off
//In case we want to handle NI interface using testbench not aeMB
,
.cpu_adr_i_array (),
.cpu_cyc_i (),
.cpu_dat_i_array (),
.cpu_sel_i_array (),
.cpu_stb_i (),
.cpu_wre_i (),
.cpu_ack_o (),
.cpu_dat_o_array ()
//synthesis translate_on
);
 
 
 
 
 
 
 
initial begin
clk = 1'b0;
forever clk = #10 ~clk;
end
 
initial begin
reset=1;
ext_int_i=0;
#50
reset=0;
end
 
 
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/MPSoC_top.v
0,0 → 1,158
/*********************************************************************
File: MPSoC_top.v
Copyright (C) 2014 Alireza Monemi
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Purpose:
The NoC based MPSoC top module for DE2-115 Altra board. The global
parameters for NoC are defined in "define.v" file.
 
Info: monemi@fkegraduate.utm.my
 
****************************************************************/
 
 
 
`include "define.v"
module MPSoC_top #(
parameter NI_CTRL_SIMULATION = "aeMB",
/*"aeMB" or "testbench".
Definig it as " aeMB" will generate the same MPSoC for both simulation and
implementation.
Defining it as "testbench" will remove the processors
in simulation. Hence, the simulation time will be decreased. The tasks to control
NI pins are written in tasks.V file */
//noc parameter
parameter TOPOLOGY = `TOPOLOGY_DEF,
parameter ROUTE_ALGRMT = `ROUTE_ALGRMT_DEF, //"XY" or "MINIMAL"
parameter VC_NUM_PER_PORT = `VC_NUM_PER_PORT_DEF ,
parameter PYLD_WIDTH = `PYLD_WIDTH_DEF,
parameter BUFFER_NUM_PER_VC = `BUFFER_NUM_PER_VC_DEF,
parameter X_NODE_NUM = `X_NODE_NUM_DEF,
parameter Y_NODE_NUM = `Y_NODE_NUM_DEF,
parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF,
parameter NOC_S_ADDR_WIDTH = `NOC_S_ADDR_WIDTH_DEF,
parameter SW_OUTPUT_REGISTERED = 0,// 1: registered , 0 not registered
// external sdram parameter
parameter SDRAM_EN = `SDRAM_EN_DEF,// 0 : disabled 1: enabled
parameter SDRAM_SW_X_ADDR = `SDRAM_SW_X_ADDR_DEF,
parameter SDRAM_SW_Y_ADDR = `SDRAM_SW_Y_ADDR_DEF,
parameter SDRAM_NI_CONNECT_PORT = `SDRAM_NI_CONNECT_PORT_DEF,
parameter SDRAM_ADDR_WIDTH = `SDRAM_ADDR_WIDTH_DEF,
parameter CAND_VC_SEL_MODE = 0,
// processors parameter
//parameter DEV_EN_ARRAY ="IPn:[the specefic value for nth IP];Def:[default value for the rest of IPs]"
parameter RAM_EN_ARRAY = `RAM_EN_ARRAY_DEF,
parameter NOC_EN_ARRAY = `NOC_EN_ARRAY_DEF,
parameter GPIO_EN_ARRAY = `GPIO_EN_ARRAY_DEF,
parameter EXT_INT_EN_ARRAY = `EXT_INT_EN_ARRAY_DEF,
parameter TIMER_EN_ARRAY = `TIMER_EN_ARRAY_DEF,
parameter INT_CTRL_EN_ARRAY = `INT_CTRL_EN_ARRAY_DEF,
//gpio parameters
parameter IO_EN_ARRAY = `IO_EN_ARRAY_DEF,
parameter I_EN_ARRAY = `I_EN_ARRAY_DEF,
parameter O_EN_ARRAY = `O_EN_ARRAY_DEF,
parameter EXT_INT_NUM_ARRAY = `EXT_INT_NUM_ARRAY_DEF,
parameter IO_PORT_WIDTH_ARRAY = `IO_PORT_WIDTH_ARRAY_DEF,
parameter I_PORT_WIDTH_ARRAY = `I_PORT_WIDTH_ARRAY_DEF,
parameter O_PORT_WIDTH_ARRAY = `O_PORT_WIDTH_ARRAY_DEF,
parameter TOTAL_EXT_INT_NUM = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,EXT_INT_NUM_ARRAY)+1,
parameter TOTAL_IO_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,IO_PORT_WIDTH_ARRAY)+1,
parameter TOTAL_I_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,I_PORT_WIDTH_ARRAY)+1,
parameter TOTAL_O_WIDTH = end_loc_in_array(X_NODE_NUM-1,Y_NODE_NUM-1,X_NODE_NUM,O_PORT_WIDTH_ARRAY)+1,
parameter TOTAL_ROUTERS_NUM = X_NODE_NUM * Y_NODE_NUM
)
(
 
 
input CLOCK_50,
input [3 : 0] KEY,
output [1 : 0] LEDG,
output [TOTAL_ROUTERS_NUM-2 : 0] LEDR,
output [6 : 0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,
// DRAM interface
output [12 : 0] DRAM_ADDR,
output [1 : 0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31 : 0] DRAM_DQ,
output [3 : 0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N
);
`define ADD_FUNCTION 1
`include "my_functions.v"
 
 
wire reset;
wire clk;
wire [TOTAL_ROUTERS_NUM-2 :0] led;
wire [3 :0] ext_int_i;
wire jtag_reset;
 
assign clk = CLOCK_50;
assign LEDR = led;
assign LEDG[0] = reset;
assign LEDG[1] = jtag_reset;
assign reset = ~KEY[0];
assign ext_int_i= ~KEY[3:1];
aeMB_mpsoc the_mpsoc
(
.reset (reset | jtag_reset),
.clk (clk),
.ext_int_i (ext_int_i),
.gpio_io ( ),
.gpio_i ( ),
.gpio_o ({led,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0} ),
.sdram_addr (DRAM_ADDR), // sdram_wire.addr
.sdram_ba (DRAM_BA), // .ba
.sdram_cas_n (DRAM_CAS_N), // .cas_n
.sdram_cke (DRAM_CKE), // .cke
.sdram_cs_n (DRAM_CS_N), // .cs_n
.sdram_dq (DRAM_DQ), // .dq
.sdram_dqm (DRAM_DQM), // .dqm
.sdram_ras_n (DRAM_RAS_N), // .ras_n
.sdram_we_n (DRAM_WE_N), // .we_n
.sdram_clk (DRAM_CLK) // sdram_clk.clk
);
 
 
reset_jtag the_reset(
.probe(),
.source(jtag_reset)
);
 
 
 
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/testbench_soc.v
0,0 → 1,81
/*********************************************************************
File: testbench_soc.v
Copyright (C) 2014 Alireza Monemi
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Purpose:
A testbench for top-level design. This testbench can be used to simulate
a real life application. running the ./soc_run file in sw folder
will copy the generated mif file in simulation folder which will be read
by modelsim.
Info: monemi@fkegraduate.utm.my
*********************************************************************/
 
`timescale 1ns/1ps
 
 
module testbench_soc ();
reg clk,reset;
wire [3 : 0] KEY;
wire [3 : 0] LEDG;
wire [6 : 0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
reg [2: 0] ext_int;
 
SoC_IP_top IP(
.CLOCK_50 (clk),
.KEY (KEY),
.LEDG (LEDG),
.HEX0 (HEX0),
.HEX1 (HEX1),
.HEX2 (HEX2),
.HEX3 (HEX3),
.HEX4 (HEX4),
.HEX5 (HEX5),
.HEX6 (HEX6),
.HEX7 (HEX7)
);
 
assign KEY= {ext_int,~reset};
 
 
initial begin
clk = 1'b0;
forever clk = #10 ~clk;
end
 
initial begin
ext_int=0;
reset=1;
#50
reset=0;
#300000
ext_int = 1;
#50
ext_int = 0;
end
 
 
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/mpsoc.qsf
38,7 → 38,7
 
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY top_de115
set_global_assignment -name TOP_LEVEL_ENTITY MPSoC_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:41:22 DECEMBER 25, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 13.0
1107,20 → 1107,25
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_soc -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_soc
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_soc -section_id testbench_soc
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_mpsoc -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_mpsoc
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_mpsoc -section_id testbench_mpsoc
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_noc -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_noc
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_noc -section_id testbench_noc
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench.v -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench_noc
set_global_assignment -name VERILOG_FILE src/IP_core/reset_jtag.v
set_global_assignment -name VERILOG_FILE src/MPSoC_top.v
set_global_assignment -name VERILOG_FILE src/IP_core/int_ctrl.v
set_global_assignment -name VERILOG_FILE src/IP_core/ext_int.v
set_global_assignment -name VERILOG_FILE src/IP_core/timer.v
set_global_assignment -name VERILOG_FILE src/SoC_IP_top.v
set_global_assignment -name VERILOG_FILE src/NoC/route_compute.v
set_global_assignment -name VERILOG_FILE src/top_de115.v
set_global_assignment -name VERILOG_FILE src/NoC/ext_ram_nic.v
set_global_assignment -name VERILOG_FILE src/NoC/sdram_core.v
set_global_assignment -name VERILOG_FILE src/IP_core/sdram/synthesis/submodules/sdram_up_clocks_0.v
1184,4 → 1189,8
set_global_assignment -name VERILOG_FILE src/IP_core/aeMB_mpsoc.v
set_global_assignment -name VERILOG_FILE src/IP_core/bus_addr_cmp.v
set_global_assignment -name SDC_FILE clk50.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench_soc
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_soc.v -section_id testbench_soc
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_mpsoc.v -section_id testbench_mpsoc
set_global_assignment -name EDA_TEST_BENCH_FILE src/testbench_noc.v -section_id testbench_noc
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/do File deleted
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/do Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_00.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_00.c (nonexistent) @@ -1,66 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - -unsigned int buffer [BUFFER_SIZE]; - -#define DES_X 2 -#define DES_Y 1 -#define DES_ADDR core_addr(DES_X, DES_Y) - -void delay(unsigned int); - - -int main() -{ -unsigned int status=0; - int i; - *led_ptr = 0x0001; - while(1){ - - - *led_ptr = *led_ptr +1; - // delay ( 10); - - for (i=1;i<15;i++) { - buffer [i] = i*2; - } - - - - - buffer [0]= DES_ADDR ; - *nic_wr_ptr = (unsigned int) (&buffer[0]) + (BUFFER_SIZE<<19); - while (!(status & NIC_WR_DONE_LOC)) status = *nic_st_ptr ; - - // usleep(1000000); - // *led_ptr = 0x0000; -//delay ( 10); - //usleep(1000000); - - - } - - - - - - - return 0; -} - - - - -void delay ( unsigned int num ){ - - while (num>0){ - num--; - asm volatile ("nop"); - } - return; - -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_00.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_00.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_01.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_01.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_00.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_00.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_01.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_01.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_02.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_02.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_01.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_01.c (nonexistent) @@ -1,37 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - -unsigned int buffer [BUFFER_SIZE]; - -int main(void){ - - - unsigned int status=0; - int i; - - while(1){ - while (!(status & NIC_HAS_PCK_LOC)) status = *nic_st_ptr ; - *led_ptr = 0xFFFF; - *nic_rd_ptr= (unsigned int) (&buffer[0]) + (BUFFER_SIZE<<19); - - } - return 0; -} - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_02.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_02.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_03.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu00_03.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_00.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_00.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/send.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/send.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/send.c (nonexistent) @@ -1,66 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" -//#include "aemb/core.hh" - - -unsigned int buffer [BUFFER_SIZE]; - -#define DES_X 3 -#define DES_Y 1 -#define DES_ADDR core_addr(DES_X, DES_Y) - -void delay(unsigned int); - - -int main() -{ -unsigned int status=0; - int i; - *led_ptr = 0x0001; - while(1){ - - - *led_ptr = *led_ptr +1; - // delay ( 10); - - for (i=1;i<15;i++) { - buffer [i] = i*2; - } - - - - - buffer [0]= DES_ADDR ; - *nic_wr_ptr = (unsigned int) (&buffer[0]) + (BUFFER_SIZE<<19); - while (!(status & NIC_WR_DONE_LOC)) status = *nic_st_ptr ; - - // usleep(1000000); - // *led_ptr = 0x0000; -//delay ( 10); - //usleep(1000000); - - - } - - - - - - - return 0; -} - - - - -void delay ( unsigned int num ){ - - while (num>0){ - num--; - asm volatile ("nop"); - } - return; - -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_01.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_01.c (nonexistent) @@ -1,37 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - -unsigned int buffer [BUFFER_SIZE]; - -int main(void){ - - - unsigned int status=0; - int i; - - while(1){ - while (!(status & NIC_HAS_PCK_LOC)) status = *nic_st_ptr ; - *led_ptr = 0xFFFF; - *nic_rd_ptr= (unsigned int) (&buffer[0]) + (BUFFER_SIZE<<19); - - } - return 0; -} - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_02.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_02.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_03.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu01_03.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_02.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_02.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_03.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu02_03.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_03.c (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/code/cpu03_03.c (nonexistent) @@ -1,28 +0,0 @@ -#include "orsocdef.h" -#include -#include "addr_map.h" - - - - - - -void delay ( unsigned int ); - - -int main(void){ - *led_ptr = *led_ptr +1; - delay ( 10); - return 0; -} - - - -void delay ( unsigned int num ){ - while (num>0){ - num--; - asm volatile ("nop"); - } - return; -} - Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/run =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/run (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/run (nonexistent) @@ -1,15 +0,0 @@ -#!/bin/sh - - rm -Rf ram/*.mif - rm -Rf ../simulation/modelsim/sw/ram/*.mif - cd code -for i in $(ls *.c); do - echo item: $i - cp $i ../compile/code.c - cd ../compile - ./gccrom code.c - cp out/ram0.mif ../ram/${i%.*}.mif - cp out/ram0.mif ../../simulation/modelsim/sw/ram/${i%.*}.mif - rm code.c - cd ../code -done
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/run Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_00.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_00.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_00.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B808017C; + 00000002 : B8080320; 00000003 : 00000000; - 00000004 : B808018C; + 00000004 : B8080190; [00000005..00000007] : 00000000; - 00000008 : B8080184; + 00000008 : B8080328; [00000009..00000013] : 00000000; - 00000014 : 31A004C0; - 00000015 : 304003B8; - 00000016 : 30200D30; + 00000014 : 31A00688; + 00000015 : 30400590; + 00000016 : 30200E80; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F40140; + 00000019 : B9F402DC; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C004C0; - 0000001F : 20E004C0; + 0000001E : 20C00688; + 0000001F : 20E00688; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C004C0; - 00000027 : 20E0053C; + 00000026 : 20C00688; + 00000027 : 20E0068C; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,204 +40,318 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400E4; + 0000002E : B9F40280; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; - 00000032 : B9F40024; + 00000032 : B9F401A8; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F400C0; + 00000035 : B9F4025C; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; 00000039 : B60F0008; 0000003A : 20210014; - 0000003B : E8A003B8; - 0000003C : E8E003C0; - 0000003D : E94003C4; - 0000003E : B00000F8; - 0000003F : 312004C0; - 00000040 : B0001200; - 00000041 : 31000000; - 00000042 : 30600001; - 00000043 : F8650000; - 00000044 : 10C00000; - 00000045 : E8650000; - 00000046 : 30800002; - 00000047 : 30630001; - 00000048 : F8650000; - 00000049 : 10642000; - 0000004A : F88304C0; - 0000004B : 30840002; - 0000004C : AA44001E; - 0000004D : BE32FFF4; - 0000004E : 10642000; - 0000004F : F90004C0; - 00000050 : F9270000; - 00000051 : BC26FFD0; - 00000052 : E86A0000; - 00000053 : A4C30001; - 00000054 : BC26FFC4; - 00000055 : E86A0000; - 00000056 : A4C30001; - 00000057 : BC26FFB8; - 00000058 : B800FFE8; - 00000059 : B8000008; - 0000005A : 80000000; - 0000005B : BE25FFFC; - 0000005C : 30A5FFFF; - 0000005D : B60F0008; - 0000005E : 80000000; - 0000005F : B6110000; - 00000060 : 80000000; - 00000061 : B6910000; - 00000062 : 80000000; - 00000063 : B62E0000; - 00000064 : 80000000; - 00000065 : B60F0008; - 00000066 : 80000000; - 00000067 : B60F0008; - 00000068 : 80000000; - 00000069 : 3021FFE0; - 0000006A : 10C00000; - 0000006B : FA61001C; - 0000006C : F9E10000; - 0000006D : B9F40024; - 0000006E : 12650000; - 0000006F : E8A003AC; - 00000070 : E8650028; - 00000071 : BC03000C; - 00000072 : 99FC1800; - 00000073 : 80000000; - 00000074 : B9F4FE9C; - 00000075 : 10B30000; - 00000076 : E86003AC; - 00000077 : 3021FFC8; - 00000078 : FB410030; - 00000079 : FB610034; - 0000007A : F9E10000; - 0000007B : FA61001C; - 0000007C : FAC10020; - 0000007D : FAE10024; - 0000007E : FB010028; - 0000007F : FB21002C; - 00000080 : EB030048; - 00000081 : 13650000; - 00000082 : BE180050; - 00000083 : 13460000; - 00000084 : E8780004; - 00000085 : EB380088; - 00000086 : 3263FFFF; - 00000087 : BC53003C; - 00000088 : 64930402; - 00000089 : 30640008; - 0000008A : 12D81800; - 0000008B : BE060074; - 0000008C : 12F92000; - 0000008D : BC1900C0; - 0000008E : E8770080; - 0000008F : 1643D000; - 00000090 : BC1200EC; - 00000091 : 3273FFFF; - 00000092 : 32F7FFFC; - 00000093 : AA53FFFF; - 00000094 : BE32FFE8; - 00000095 : 32D6FFFC; - 00000096 : E9E10000; - 00000097 : EA61001C; - 00000098 : EAC10020; - 00000099 : EAE10024; - 0000009A : EB010028; - 0000009B : EB21002C; - 0000009C : EB410030; - 0000009D : EB610034; - 0000009E : B60F0008; - 0000009F : 30210038; - 000000A0 : E8B70000; - 000000A1 : 99FC3800; - 000000A2 : 80000000; - 000000A3 : 3273FFFF; - 000000A4 : 32F7FFFC; - 000000A5 : AA53FFFF; - 000000A6 : BE12FFC0; - 000000A7 : 32D6FFFC; - 000000A8 : E8780004; - 000000A9 : E8F60000; - 000000AA : 3063FFFF; - 000000AB : 16439800; - 000000AC : BC120074; - 000000AD : F8160000; - 000000AE : BC07FFD4; - 000000AF : BE190058; - 000000B0 : 30800001; - 000000B1 : E8790100; - 000000B2 : 44849C00; - 000000B3 : 84641800; - 000000B4 : BC030044; - 000000B5 : E8790104; - 000000B6 : 84641800; - 000000B7 : BC23FFA4; - 000000B8 : E8D70000; - 000000B9 : 99FC3800; - 000000BA : 10BB0000; - 000000BB : B810FFA4; - 000000BC : 3273FFFF; - 000000BD : 3273FFFF; - 000000BE : AA53FFFF; - 000000BF : BE12FF5C; - 000000C0 : 3273FFFF; - 000000C1 : AA53FFFF; - 000000C2 : BE32FFF0; - 000000C3 : 3273FFFF; - 000000C4 : B800FF48; - 000000C5 : 99FC3800; - 000000C6 : 3273FFFF; - 000000C7 : B810FF78; - 000000C8 : 32F7FFFC; - 000000C9 : FA780004; - 000000CA : B800FF90; - 000000CB : E8780004; - 000000CC : E8F60000; - 000000CD : 3063FFFF; - 000000CE : 16439800; - 000000CF : BC120054; - 000000D0 : F8160000; - 000000D1 : BC07FF00; - 000000D2 : BC190038; - 000000D3 : 30800001; - 000000D4 : E8790100; - 000000D5 : 44849C00; - 000000D6 : 84641800; - 000000D7 : BC030024; - 000000D8 : E8790104; - 000000D9 : 84641800; - 000000DA : BC230030; - 000000DB : E8D70000; - 000000DC : 99FC3800; - 000000DD : 10BB0000; - 000000DE : B810FED0; - 000000DF : 3273FFFF; - 000000E0 : 99FC3800; - 000000E1 : 3273FFFF; - 000000E2 : B810FEC4; - 000000E3 : 32F7FFFC; - 000000E4 : FA780004; - 000000E5 : B800FFB0; - 000000E6 : E8B70000; - 000000E7 : 99FC3800; - 000000E8 : 3273FFFF; - 000000E9 : B810FEA8; - 000000EA : 32F7FFFC; - 000000EB : 000003CC; - 000000EC : 43000000; - 000000ED : 00000000; - 000000EE : 41000000; - 000000EF : 40000000; - 000000F0 : 40000004; - 000000F1 : 40000008; - 000000F2 : 000003CC; - [000000F3..000000FA] : 00000000; - 000000FB : 000003B0; - [000000FC..00000FFF] : 00000000; + 0000003B : 94608001; + 0000003C : A0630002; + 0000003D : 9403C001; + 0000003E : B60F0008; + 0000003F : 80000000; + 00000040 : B0004300; + 00000041 : 30600000; + 00000042 : E8800688; + 00000043 : E8A30000; + 00000044 : 30840001; + 00000045 : F8800688; + 00000046 : F8A30000; + 00000047 : B60F0008; + 00000048 : 80000000; + 00000049 : B0004400; + 0000004A : E860000C; + 0000004B : A4630001; + 0000004C : BC030010; + 0000004D : B000DEAD; + 0000004E : 3060BEAF; + 0000004F : F8600688; + 00000050 : B0004400; + 00000051 : E860000C; + 00000052 : A4630002; + 00000053 : BC030010; + 00000054 : B0001234; + 00000055 : 30605678; + 00000056 : F8600688; + 00000057 : B0004400; + 00000058 : E860000C; + 00000059 : A4630004; + 0000005A : BC030010; + 0000005B : B000AAAA; + 0000005C : 3060AAAA; + 0000005D : F8600688; + 0000005E : B0004200; + 0000005F : E860000C; + 00000060 : B0004200; + 00000061 : F860000C; + 00000062 : B60F0008; + 00000063 : 80000000; + 00000064 : 3021FFB0; + 00000065 : F9E10000; + 00000066 : F8610020; + 00000067 : F8810024; + 00000068 : F8A10028; + 00000069 : F8C1002C; + 0000006A : F8E10030; + 0000006B : F9010034; + 0000006C : F9210038; + 0000006D : F941003C; + 0000006E : F9610040; + 0000006F : F9810044; + 00000070 : FA210048; + 00000071 : 95608001; + 00000072 : FA41004C; + 00000073 : F961001C; + 00000074 : B0004400; + 00000075 : E860000C; + 00000076 : A4630008; + 00000077 : BC230070; + 00000078 : B0004400; + 00000079 : E860000C; + 0000007A : A4630007; + 0000007B : BC03000C; + 0000007C : B9F4FF34; + 0000007D : 80000000; + 0000007E : B0004400; + 0000007F : E860000C; + 00000080 : B0004400; + 00000081 : F8600008; + 00000082 : E9E10000; + 00000083 : E961001C; + 00000084 : E8610020; + 00000085 : E8810024; + 00000086 : 940BC001; + 00000087 : E8A10028; + 00000088 : E8C1002C; + 00000089 : E8E10030; + 0000008A : E9010034; + 0000008B : E9210038; + 0000008C : E941003C; + 0000008D : E9610040; + 0000008E : E9810044; + 0000008F : EA210048; + 00000090 : EA41004C; + 00000091 : B62E0000; + 00000092 : 30210050; + 00000093 : B9F4FEB4; + 00000094 : 80000000; + 00000095 : B800FF8C; + 00000096 : B8000008; + 00000097 : 80000000; + 00000098 : BE25FFFC; + 00000099 : 30A5FFFF; + 0000009A : B60F0008; + 0000009B : 30A50001; + 0000009C : 3021FFE4; + 0000009D : F9E10000; + 0000009E : 30800007; + 0000009F : B00002FA; + 000000A0 : 3060F080; + 000000A1 : B0004200; + 000000A2 : F8800004; + 000000A3 : 30A00003; + 000000A4 : B0004200; + 000000A5 : F8A00000; + 000000A6 : B0004300; + 000000A7 : F8600008; + 000000A8 : B0004300; + 000000A9 : F8800000; + 000000AA : 3060000F; + 000000AB : B0004400; + 000000AC : F8600004; + 000000AD : B0004400; + 000000AE : F8A00000; + 000000AF : F8000688; + 000000B0 : B9F4FE2C; + 000000B1 : 80000000; + 000000B2 : 10E00000; + 000000B3 : 10C70000; + 000000B4 : B0004100; + 000000B5 : 30A02004; + 000000B6 : E8600688; + 000000B7 : 30E70001; + 000000B8 : 44633000; + 000000B9 : A463000F; + 000000BA : 64630402; + 000000BB : E8830548; + 000000BC : 30C60004; + 000000BD : A884FFFF; + 000000BE : F8850000; + 000000BF : AA470008; + 000000C0 : BE32FFD8; + 000000C1 : 30A50080; + 000000C2 : B0000000; + 000000C3 : 30A0C350; + 000000C4 : B9F4FF48; + 000000C5 : 80000000; + 000000C6 : B810FFB4; + 000000C7 : 10E00000; + 000000C8 : B6110000; + 000000C9 : 80000000; + 000000CA : B6910000; + 000000CB : 80000000; + 000000CC : B60F0008; + 000000CD : 80000000; + 000000CE : B60F0008; + 000000CF : 80000000; + 000000D0 : 3021FFE0; + 000000D1 : 10C00000; + 000000D2 : FA61001C; + 000000D3 : F9E10000; + 000000D4 : B9F40024; + 000000D5 : 12650000; + 000000D6 : E8A00588; + 000000D7 : E8650028; + 000000D8 : BC03000C; + 000000D9 : 99FC1800; + 000000DA : 80000000; + 000000DB : B9F4FD00; + 000000DC : 10B30000; + 000000DD : E8600588; + 000000DE : 3021FFC8; + 000000DF : FB410030; + 000000E0 : FB610034; + 000000E1 : F9E10000; + 000000E2 : FA61001C; + 000000E3 : FAC10020; + 000000E4 : FAE10024; + 000000E5 : FB010028; + 000000E6 : FB21002C; + 000000E7 : EB030048; + 000000E8 : 13650000; + 000000E9 : BE180050; + 000000EA : 13460000; + 000000EB : E8780004; + 000000EC : EB380088; + 000000ED : 3263FFFF; + 000000EE : BC53003C; + 000000EF : 64930402; + 000000F0 : 30640008; + 000000F1 : 12D81800; + 000000F2 : BE060074; + 000000F3 : 12F92000; + 000000F4 : BC1900C0; + 000000F5 : E8770080; + 000000F6 : 1643D000; + 000000F7 : BC1200EC; + 000000F8 : 3273FFFF; + 000000F9 : 32F7FFFC; + 000000FA : AA53FFFF; + 000000FB : BE32FFE8; + 000000FC : 32D6FFFC; + 000000FD : E9E10000; + 000000FE : EA61001C; + 000000FF : EAC10020; + 00000100 : EAE10024; + 00000101 : EB010028; + 00000102 : EB21002C; + 00000103 : EB410030; + 00000104 : EB610034; + 00000105 : B60F0008; + 00000106 : 30210038; + 00000107 : E8B70000; + 00000108 : 99FC3800; + 00000109 : 80000000; + 0000010A : 3273FFFF; + 0000010B : 32F7FFFC; + 0000010C : AA53FFFF; + 0000010D : BE12FFC0; + 0000010E : 32D6FFFC; + 0000010F : E8780004; + 00000110 : E8F60000; + 00000111 : 3063FFFF; + 00000112 : 16439800; + 00000113 : BC120074; + 00000114 : F8160000; + 00000115 : BC07FFD4; + 00000116 : BE190058; + 00000117 : 30800001; + 00000118 : E8790100; + 00000119 : 44849C00; + 0000011A : 84641800; + 0000011B : BC030044; + 0000011C : E8790104; + 0000011D : 84641800; + 0000011E : BC23FFA4; + 0000011F : E8D70000; + 00000120 : 99FC3800; + 00000121 : 10BB0000; + 00000122 : B810FFA4; + 00000123 : 3273FFFF; + 00000124 : 3273FFFF; + 00000125 : AA53FFFF; + 00000126 : BE12FF5C; + 00000127 : 3273FFFF; + 00000128 : AA53FFFF; + 00000129 : BE32FFF0; + 0000012A : 3273FFFF; + 0000012B : B800FF48; + 0000012C : 99FC3800; + 0000012D : 3273FFFF; + 0000012E : B810FF78; + 0000012F : 32F7FFFC; + 00000130 : FA780004; + 00000131 : B800FF90; + 00000132 : E8780004; + 00000133 : E8F60000; + 00000134 : 3063FFFF; + 00000135 : 16439800; + 00000136 : BC120054; + 00000137 : F8160000; + 00000138 : BC07FF00; + 00000139 : BC190038; + 0000013A : 30800001; + 0000013B : E8790100; + 0000013C : 44849C00; + 0000013D : 84641800; + 0000013E : BC030024; + 0000013F : E8790104; + 00000140 : 84641800; + 00000141 : BC230030; + 00000142 : E8D70000; + 00000143 : 99FC3800; + 00000144 : 10BB0000; + 00000145 : B810FED0; + 00000146 : 3273FFFF; + 00000147 : 99FC3800; + 00000148 : 3273FFFF; + 00000149 : B810FEC4; + 0000014A : 32F7FFFC; + 0000014B : FA780004; + 0000014C : B800FFB0; + 0000014D : E8B70000; + 0000014E : 99FC3800; + 0000014F : 3273FFFF; + 00000150 : B810FEA8; + 00000151 : 32F7FFFC; + 00000152 : 0000003F; + 00000153 : 00000006; + 00000154 : 0000005B; + 00000155 : 0000004F; + 00000156 : 00000066; + 00000157 : 0000006D; + 00000158 : 0000007D; + 00000159 : 00000007; + 0000015A : 0000007F; + 0000015B : 0000006F; + 0000015C : 00000077; + 0000015D : 0000007C; + 0000015E : 00000039; + 0000015F : 0000005E; + 00000160 : 00000079; + 00000161 : 00000071; + 00000162 : 00000594; + 00000163 : 43000000; + 00000164 : 00000594; + [00000165..0000016C] : 00000000; + 0000016D : 0000058C; + [0000016E..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_01.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_01.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_01.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B8080158; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B8080168; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080160; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00488; + 00000015 : 30400390; + 00000016 : 30200CF8; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F4011C; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00488; + 0000001F : 20E00488; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00488; + 00000027 : 20E00504; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,186 +40,190 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400C0; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; - 00000032 : B9F4003C; + 00000032 : B9F40024; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F4009C; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; 00000039 : B60F0008; 0000003A : 20210014; - 0000003B : B8000008; - 0000003C : 80000000; - 0000003D : BE25FFFC; - 0000003E : 30A5FFFF; - 0000003F : B60F0008; - 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 0000003B : B00000F8; + 0000003C : 30C00488; + 0000003D : B0000420; + 0000003E : 30A00000; + 0000003F : 30600001; + 00000040 : 10800000; + 00000041 : F864048C; + 00000042 : 30630001; + 00000043 : AA43001F; + 00000044 : BE32FFF4; + 00000045 : 30840004; + 00000046 : F8A00488; + 00000047 : B0004000; + 00000048 : F8C00004; + 00000049 : B0004000; + 0000004A : E8600008; + 0000004B : A4630001; + 0000004C : BE03FFF4; + 0000004D : 30600001; + 0000004E : B810FFCC; + 0000004F : 10800000; + 00000050 : B8000008; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; + 00000052 : BE25FFFC; + 00000053 : 30A5FFFF; 00000054 : B60F0008; 00000055 : 80000000; - 00000056 : B60F0008; + 00000056 : B6110000; 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000058 : B6910000; + 00000059 : 80000000; + 0000005A : B62E0000; + 0000005B : 80000000; + 0000005C : B60F0008; + 0000005D : 80000000; + 0000005E : B60F0008; + 0000005F : 80000000; + 00000060 : 3021FFE0; + 00000061 : 10C00000; + 00000062 : FA61001C; + 00000063 : F9E10000; + 00000064 : B9F40024; + 00000065 : 12650000; + 00000066 : E8A00388; + 00000067 : E8650028; + 00000068 : BC03000C; + 00000069 : 99FC1800; + 0000006A : 80000000; + 0000006B : B9F4FEC0; + 0000006C : 10B30000; + 0000006D : E8600388; + 0000006E : 3021FFC8; + 0000006F : FB410030; + 00000070 : FB610034; + 00000071 : F9E10000; + 00000072 : FA61001C; + 00000073 : FAC10020; + 00000074 : FAE10024; + 00000075 : FB010028; + 00000076 : FB21002C; + 00000077 : EB030048; + 00000078 : 13650000; + 00000079 : BE180050; + 0000007A : 13460000; + 0000007B : E8780004; + 0000007C : EB380088; + 0000007D : 3263FFFF; + 0000007E : BC53003C; + 0000007F : 64930402; + 00000080 : 30640008; + 00000081 : 12D81800; + 00000082 : BE060074; + 00000083 : 12F92000; + 00000084 : BC1900C0; + 00000085 : E8770080; + 00000086 : 1643D000; + 00000087 : BC1200EC; + 00000088 : 3273FFFF; + 00000089 : 32F7FFFC; + 0000008A : AA53FFFF; + 0000008B : BE32FFE8; + 0000008C : 32D6FFFC; + 0000008D : E9E10000; + 0000008E : EA61001C; + 0000008F : EAC10020; + 00000090 : EAE10024; + 00000091 : EB010028; + 00000092 : EB21002C; + 00000093 : EB410030; + 00000094 : EB610034; + 00000095 : B60F0008; + 00000096 : 30210038; + 00000097 : E8B70000; + 00000098 : 99FC3800; + 00000099 : 80000000; + 0000009A : 3273FFFF; + 0000009B : 32F7FFFC; + 0000009C : AA53FFFF; + 0000009D : BE12FFC0; + 0000009E : 32D6FFFC; + 0000009F : E8780004; + 000000A0 : E8F60000; + 000000A1 : 3063FFFF; + 000000A2 : 16439800; + 000000A3 : BC120074; + 000000A4 : F8160000; + 000000A5 : BC07FFD4; + 000000A6 : BE190058; + 000000A7 : 30800001; + 000000A8 : E8790100; + 000000A9 : 44849C00; + 000000AA : 84641800; + 000000AB : BC030044; + 000000AC : E8790104; + 000000AD : 84641800; + 000000AE : BC23FFA4; + 000000AF : E8D70000; + 000000B0 : 99FC3800; + 000000B1 : 10BB0000; + 000000B2 : B810FFA4; + 000000B3 : 3273FFFF; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE12FF5C; + 000000B7 : 3273FFFF; + 000000B8 : AA53FFFF; + 000000B9 : BE32FFF0; + 000000BA : 3273FFFF; + 000000BB : B800FF48; + 000000BC : 99FC3800; + 000000BD : 3273FFFF; + 000000BE : B810FF78; + 000000BF : 32F7FFFC; + 000000C0 : FA780004; + 000000C1 : B800FF90; + 000000C2 : E8780004; + 000000C3 : E8F60000; + 000000C4 : 3063FFFF; + 000000C5 : 16439800; + 000000C6 : BC120054; + 000000C7 : F8160000; + 000000C8 : BC07FF00; + 000000C9 : BC190038; + 000000CA : 30800001; + 000000CB : E8790100; + 000000CC : 44849C00; + 000000CD : 84641800; + 000000CE : BC030024; + 000000CF : E8790104; + 000000D0 : 84641800; + 000000D1 : BC230030; + 000000D2 : E8D70000; + 000000D3 : 99FC3800; + 000000D4 : 10BB0000; + 000000D5 : B810FED0; + 000000D6 : 3273FFFF; + 000000D7 : 99FC3800; + 000000D8 : 3273FFFF; + 000000D9 : B810FEC4; + 000000DA : 32F7FFFC; + 000000DB : FA780004; + 000000DC : B800FFB0; + 000000DD : E8B70000; + 000000DE : 99FC3800; + 000000DF : 3273FFFF; + 000000E0 : B810FEA8; + 000000E1 : 32F7FFFC; + 000000E2 : 00000394; + 000000E3 : 43000000; + 000000E4 : 00000394; + [000000E5..000000EC] : 00000000; + 000000ED : 0000038C; + [000000EE..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_00.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_00.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_00.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_02.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_02.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_02.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B000000F; + 00000049 : 30A04240; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B000000F; + 0000004E : 30A04240; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_01.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_01.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_01.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B000004C; + 00000049 : 30A04B40; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B000004C; + 0000004E : 30A04B40; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_00.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_00.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_00.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000003; + 00000049 : 30A00D40; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000003; + 0000004E : 30A00D40; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_03.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_03.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu00_03.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_02.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_02.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_02.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B000002D; + 00000049 : 30A0C6C0; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B000002D; + 0000004E : 30A0C6C0; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_01.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_01.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_01.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080140; + 00000002 : B8080128; 00000003 : 00000000; - 00000004 : B8080150; + 00000004 : B8080138; [00000005..00000007] : 00000000; - 00000008 : B8080148; + 00000008 : B8080130; [00000009..00000013] : 00000000; - 00000014 : 31A00480; - 00000015 : 30400378; - 00000016 : 30200CF0; + 00000014 : 31A00458; + 00000015 : 30400360; + 00000016 : 30200CC8; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F40104; + 00000019 : B9F400EC; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00480; - 0000001F : 20E00480; + 0000001E : 20C00458; + 0000001F : 20E00458; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00480; - 00000027 : 20E004FC; + 00000026 : 20C00458; + 00000027 : 20E004D4; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A8; + 0000002E : B9F40090; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,181 +47,171 @@ 00000032 : B9F40024; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F40084; + 00000035 : B9F4006C; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; 00000039 : B60F0008; 0000003A : 20210014; - 0000003B : E8C00378; - 0000003C : E8A0037C; - 0000003D : E8800384; - 0000003E : B00000F8; - 0000003F : 31000480; - 00000040 : B0000000; - 00000041 : 30E0FFFF; - 00000042 : 10600000; - 00000043 : BC030010; - 00000044 : F8E60000; - 00000045 : F9050000; - 00000046 : BC23FFF8; - 00000047 : E8640000; - 00000048 : B810FFEC; - 00000049 : A4630010; - 0000004A : B8000008; + 0000003B : B00000F8; + 0000003C : 30800458; + 0000003D : B0004000; + 0000003E : E8600008; + 0000003F : A4630010; + 00000040 : BC03FFF4; + 00000041 : B0004000; + 00000042 : F8800000; + 00000043 : B800FFE8; + 00000044 : B8000008; + 00000045 : 80000000; + 00000046 : BE25FFFC; + 00000047 : 30A5FFFF; + 00000048 : B60F0008; + 00000049 : 80000000; + 0000004A : B6110000; 0000004B : 80000000; - 0000004C : BE25FFFC; - 0000004D : 30A5FFFF; - 0000004E : B60F0008; + 0000004C : B6910000; + 0000004D : 80000000; + 0000004E : B62E0000; 0000004F : 80000000; - 00000050 : B6110000; + 00000050 : B60F0008; 00000051 : 80000000; - 00000052 : B6910000; + 00000052 : B60F0008; 00000053 : 80000000; - 00000054 : B62E0000; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : B60F0008; - 00000059 : 80000000; - 0000005A : 3021FFE0; - 0000005B : 10C00000; - 0000005C : FA61001C; - 0000005D : F9E10000; - 0000005E : B9F40024; - 0000005F : 12650000; - 00000060 : E8A00370; - 00000061 : E8650028; - 00000062 : BC03000C; - 00000063 : 99FC1800; - 00000064 : 80000000; - 00000065 : B9F4FED8; - 00000066 : 10B30000; - 00000067 : E8600370; - 00000068 : 3021FFC8; - 00000069 : FB410030; - 0000006A : FB610034; - 0000006B : F9E10000; - 0000006C : FA61001C; - 0000006D : FAC10020; - 0000006E : FAE10024; - 0000006F : FB010028; - 00000070 : FB21002C; - 00000071 : EB030048; - 00000072 : 13650000; - 00000073 : BE180050; - 00000074 : 13460000; - 00000075 : E8780004; - 00000076 : EB380088; - 00000077 : 3263FFFF; - 00000078 : BC53003C; - 00000079 : 64930402; - 0000007A : 30640008; - 0000007B : 12D81800; - 0000007C : BE060074; - 0000007D : 12F92000; - 0000007E : BC1900C0; - 0000007F : E8770080; - 00000080 : 1643D000; - 00000081 : BC1200EC; - 00000082 : 3273FFFF; - 00000083 : 32F7FFFC; - 00000084 : AA53FFFF; - 00000085 : BE32FFE8; - 00000086 : 32D6FFFC; - 00000087 : E9E10000; - 00000088 : EA61001C; - 00000089 : EAC10020; - 0000008A : EAE10024; - 0000008B : EB010028; - 0000008C : EB21002C; - 0000008D : EB410030; - 0000008E : EB610034; - 0000008F : B60F0008; - 00000090 : 30210038; - 00000091 : E8B70000; - 00000092 : 99FC3800; - 00000093 : 80000000; - 00000094 : 3273FFFF; - 00000095 : 32F7FFFC; - 00000096 : AA53FFFF; - 00000097 : BE12FFC0; - 00000098 : 32D6FFFC; - 00000099 : E8780004; - 0000009A : E8F60000; - 0000009B : 3063FFFF; - 0000009C : 16439800; - 0000009D : BC120074; - 0000009E : F8160000; - 0000009F : BC07FFD4; - 000000A0 : BE190058; - 000000A1 : 30800001; - 000000A2 : E8790100; - 000000A3 : 44849C00; - 000000A4 : 84641800; - 000000A5 : BC030044; - 000000A6 : E8790104; - 000000A7 : 84641800; - 000000A8 : BC23FFA4; - 000000A9 : E8D70000; - 000000AA : 99FC3800; - 000000AB : 10BB0000; - 000000AC : B810FFA4; - 000000AD : 3273FFFF; + 00000054 : 3021FFE0; + 00000055 : 10C00000; + 00000056 : FA61001C; + 00000057 : F9E10000; + 00000058 : B9F40024; + 00000059 : 12650000; + 0000005A : E8A00358; + 0000005B : E8650028; + 0000005C : BC03000C; + 0000005D : 99FC1800; + 0000005E : 80000000; + 0000005F : B9F4FEF0; + 00000060 : 10B30000; + 00000061 : E8600358; + 00000062 : 3021FFC8; + 00000063 : FB410030; + 00000064 : FB610034; + 00000065 : F9E10000; + 00000066 : FA61001C; + 00000067 : FAC10020; + 00000068 : FAE10024; + 00000069 : FB010028; + 0000006A : FB21002C; + 0000006B : EB030048; + 0000006C : 13650000; + 0000006D : BE180050; + 0000006E : 13460000; + 0000006F : E8780004; + 00000070 : EB380088; + 00000071 : 3263FFFF; + 00000072 : BC53003C; + 00000073 : 64930402; + 00000074 : 30640008; + 00000075 : 12D81800; + 00000076 : BE060074; + 00000077 : 12F92000; + 00000078 : BC1900C0; + 00000079 : E8770080; + 0000007A : 1643D000; + 0000007B : BC1200EC; + 0000007C : 3273FFFF; + 0000007D : 32F7FFFC; + 0000007E : AA53FFFF; + 0000007F : BE32FFE8; + 00000080 : 32D6FFFC; + 00000081 : E9E10000; + 00000082 : EA61001C; + 00000083 : EAC10020; + 00000084 : EAE10024; + 00000085 : EB010028; + 00000086 : EB21002C; + 00000087 : EB410030; + 00000088 : EB610034; + 00000089 : B60F0008; + 0000008A : 30210038; + 0000008B : E8B70000; + 0000008C : 99FC3800; + 0000008D : 80000000; + 0000008E : 3273FFFF; + 0000008F : 32F7FFFC; + 00000090 : AA53FFFF; + 00000091 : BE12FFC0; + 00000092 : 32D6FFFC; + 00000093 : E8780004; + 00000094 : E8F60000; + 00000095 : 3063FFFF; + 00000096 : 16439800; + 00000097 : BC120074; + 00000098 : F8160000; + 00000099 : BC07FFD4; + 0000009A : BE190058; + 0000009B : 30800001; + 0000009C : E8790100; + 0000009D : 44849C00; + 0000009E : 84641800; + 0000009F : BC030044; + 000000A0 : E8790104; + 000000A1 : 84641800; + 000000A2 : BC23FFA4; + 000000A3 : E8D70000; + 000000A4 : 99FC3800; + 000000A5 : 10BB0000; + 000000A6 : B810FFA4; + 000000A7 : 3273FFFF; + 000000A8 : 3273FFFF; + 000000A9 : AA53FFFF; + 000000AA : BE12FF5C; + 000000AB : 3273FFFF; + 000000AC : AA53FFFF; + 000000AD : BE32FFF0; 000000AE : 3273FFFF; - 000000AF : AA53FFFF; - 000000B0 : BE12FF5C; + 000000AF : B800FF48; + 000000B0 : 99FC3800; 000000B1 : 3273FFFF; - 000000B2 : AA53FFFF; - 000000B3 : BE32FFF0; - 000000B4 : 3273FFFF; - 000000B5 : B800FF48; - 000000B6 : 99FC3800; - 000000B7 : 3273FFFF; - 000000B8 : B810FF78; - 000000B9 : 32F7FFFC; - 000000BA : FA780004; - 000000BB : B800FF90; - 000000BC : E8780004; - 000000BD : E8F60000; - 000000BE : 3063FFFF; - 000000BF : 16439800; - 000000C0 : BC120054; - 000000C1 : F8160000; - 000000C2 : BC07FF00; - 000000C3 : BC190038; - 000000C4 : 30800001; - 000000C5 : E8790100; - 000000C6 : 44849C00; - 000000C7 : 84641800; - 000000C8 : BC030024; - 000000C9 : E8790104; - 000000CA : 84641800; - 000000CB : BC230030; - 000000CC : E8D70000; - 000000CD : 99FC3800; - 000000CE : 10BB0000; - 000000CF : B810FED0; - 000000D0 : 3273FFFF; - 000000D1 : 99FC3800; - 000000D2 : 3273FFFF; - 000000D3 : B810FEC4; - 000000D4 : 32F7FFFC; - 000000D5 : FA780004; - 000000D6 : B800FFB0; - 000000D7 : E8B70000; - 000000D8 : 99FC3800; - 000000D9 : 3273FFFF; - 000000DA : B810FEA8; - 000000DB : 32F7FFFC; - 000000DC : 0000038C; - 000000DD : 43000000; - 000000DE : 41000000; - 000000DF : 40000000; - 000000E0 : 40000004; - 000000E1 : 40000008; - 000000E2 : 0000038C; - [000000E3..000000EA] : 00000000; - 000000EB : 00000374; - [000000EC..00000FFF] : 00000000; + 000000B2 : B810FF78; + 000000B3 : 32F7FFFC; + 000000B4 : FA780004; + 000000B5 : B800FF90; + 000000B6 : E8780004; + 000000B7 : E8F60000; + 000000B8 : 3063FFFF; + 000000B9 : 16439800; + 000000BA : BC120054; + 000000BB : F8160000; + 000000BC : BC07FF00; + 000000BD : BC190038; + 000000BE : 30800001; + 000000BF : E8790100; + 000000C0 : 44849C00; + 000000C1 : 84641800; + 000000C2 : BC030024; + 000000C3 : E8790104; + 000000C4 : 84641800; + 000000C5 : BC230030; + 000000C6 : E8D70000; + 000000C7 : 99FC3800; + 000000C8 : 10BB0000; + 000000C9 : B810FED0; + 000000CA : 3273FFFF; + 000000CB : 99FC3800; + 000000CC : 3273FFFF; + 000000CD : B810FEC4; + 000000CE : 32F7FFFC; + 000000CF : FA780004; + 000000D0 : B800FFB0; + 000000D1 : E8B70000; + 000000D2 : 99FC3800; + 000000D3 : 3273FFFF; + 000000D4 : B810FEA8; + 000000D5 : 32F7FFFC; + 000000D6 : 00000364; + 000000D7 : 43000000; + 000000D8 : 00000364; + [000000D9..000000E0] : 00000000; + 000000E1 : 0000035C; + [000000E2..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_00.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_00.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_00.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_03.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_03.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu01_03.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_02.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_02.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_02.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_01.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_01.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_01.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080140; + 00000002 : B8080128; 00000003 : 00000000; - 00000004 : B8080150; + 00000004 : B8080138; [00000005..00000007] : 00000000; - 00000008 : B8080148; + 00000008 : B8080130; [00000009..00000013] : 00000000; - 00000014 : 31A00480; - 00000015 : 30400378; - 00000016 : 30200CF0; + 00000014 : 31A00458; + 00000015 : 30400360; + 00000016 : 30200CC8; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F40104; + 00000019 : B9F400EC; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00480; - 0000001F : 20E00480; + 0000001E : 20C00458; + 0000001F : 20E00458; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00480; - 00000027 : 20E004FC; + 00000026 : 20C00458; + 00000027 : 20E004D4; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A8; + 0000002E : B9F40090; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,181 +47,171 @@ 00000032 : B9F40024; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F40084; + 00000035 : B9F4006C; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; 00000039 : B60F0008; 0000003A : 20210014; - 0000003B : E8C00378; - 0000003C : E8A0037C; - 0000003D : E8800384; - 0000003E : B00000F8; - 0000003F : 31000480; - 00000040 : B0000000; - 00000041 : 30E0FFFF; - 00000042 : 10600000; - 00000043 : BC030010; - 00000044 : F8E60000; - 00000045 : F9050000; - 00000046 : BC23FFF8; - 00000047 : E8640000; - 00000048 : B810FFEC; - 00000049 : A4630010; - 0000004A : B8000008; + 0000003B : B00000F8; + 0000003C : 30800458; + 0000003D : B0004000; + 0000003E : E8600008; + 0000003F : A4630010; + 00000040 : BC03FFF4; + 00000041 : B0004000; + 00000042 : F8800000; + 00000043 : B800FFE8; + 00000044 : B8000008; + 00000045 : 80000000; + 00000046 : BE25FFFC; + 00000047 : 30A5FFFF; + 00000048 : B60F0008; + 00000049 : 80000000; + 0000004A : B6110000; 0000004B : 80000000; - 0000004C : BE25FFFC; - 0000004D : 30A5FFFF; - 0000004E : B60F0008; + 0000004C : B6910000; + 0000004D : 80000000; + 0000004E : B62E0000; 0000004F : 80000000; - 00000050 : B6110000; + 00000050 : B60F0008; 00000051 : 80000000; - 00000052 : B6910000; + 00000052 : B60F0008; 00000053 : 80000000; - 00000054 : B62E0000; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : B60F0008; - 00000059 : 80000000; - 0000005A : 3021FFE0; - 0000005B : 10C00000; - 0000005C : FA61001C; - 0000005D : F9E10000; - 0000005E : B9F40024; - 0000005F : 12650000; - 00000060 : E8A00370; - 00000061 : E8650028; - 00000062 : BC03000C; - 00000063 : 99FC1800; - 00000064 : 80000000; - 00000065 : B9F4FED8; - 00000066 : 10B30000; - 00000067 : E8600370; - 00000068 : 3021FFC8; - 00000069 : FB410030; - 0000006A : FB610034; - 0000006B : F9E10000; - 0000006C : FA61001C; - 0000006D : FAC10020; - 0000006E : FAE10024; - 0000006F : FB010028; - 00000070 : FB21002C; - 00000071 : EB030048; - 00000072 : 13650000; - 00000073 : BE180050; - 00000074 : 13460000; - 00000075 : E8780004; - 00000076 : EB380088; - 00000077 : 3263FFFF; - 00000078 : BC53003C; - 00000079 : 64930402; - 0000007A : 30640008; - 0000007B : 12D81800; - 0000007C : BE060074; - 0000007D : 12F92000; - 0000007E : BC1900C0; - 0000007F : E8770080; - 00000080 : 1643D000; - 00000081 : BC1200EC; - 00000082 : 3273FFFF; - 00000083 : 32F7FFFC; - 00000084 : AA53FFFF; - 00000085 : BE32FFE8; - 00000086 : 32D6FFFC; - 00000087 : E9E10000; - 00000088 : EA61001C; - 00000089 : EAC10020; - 0000008A : EAE10024; - 0000008B : EB010028; - 0000008C : EB21002C; - 0000008D : EB410030; - 0000008E : EB610034; - 0000008F : B60F0008; - 00000090 : 30210038; - 00000091 : E8B70000; - 00000092 : 99FC3800; - 00000093 : 80000000; - 00000094 : 3273FFFF; - 00000095 : 32F7FFFC; - 00000096 : AA53FFFF; - 00000097 : BE12FFC0; - 00000098 : 32D6FFFC; - 00000099 : E8780004; - 0000009A : E8F60000; - 0000009B : 3063FFFF; - 0000009C : 16439800; - 0000009D : BC120074; - 0000009E : F8160000; - 0000009F : BC07FFD4; - 000000A0 : BE190058; - 000000A1 : 30800001; - 000000A2 : E8790100; - 000000A3 : 44849C00; - 000000A4 : 84641800; - 000000A5 : BC030044; - 000000A6 : E8790104; - 000000A7 : 84641800; - 000000A8 : BC23FFA4; - 000000A9 : E8D70000; - 000000AA : 99FC3800; - 000000AB : 10BB0000; - 000000AC : B810FFA4; - 000000AD : 3273FFFF; + 00000054 : 3021FFE0; + 00000055 : 10C00000; + 00000056 : FA61001C; + 00000057 : F9E10000; + 00000058 : B9F40024; + 00000059 : 12650000; + 0000005A : E8A00358; + 0000005B : E8650028; + 0000005C : BC03000C; + 0000005D : 99FC1800; + 0000005E : 80000000; + 0000005F : B9F4FEF0; + 00000060 : 10B30000; + 00000061 : E8600358; + 00000062 : 3021FFC8; + 00000063 : FB410030; + 00000064 : FB610034; + 00000065 : F9E10000; + 00000066 : FA61001C; + 00000067 : FAC10020; + 00000068 : FAE10024; + 00000069 : FB010028; + 0000006A : FB21002C; + 0000006B : EB030048; + 0000006C : 13650000; + 0000006D : BE180050; + 0000006E : 13460000; + 0000006F : E8780004; + 00000070 : EB380088; + 00000071 : 3263FFFF; + 00000072 : BC53003C; + 00000073 : 64930402; + 00000074 : 30640008; + 00000075 : 12D81800; + 00000076 : BE060074; + 00000077 : 12F92000; + 00000078 : BC1900C0; + 00000079 : E8770080; + 0000007A : 1643D000; + 0000007B : BC1200EC; + 0000007C : 3273FFFF; + 0000007D : 32F7FFFC; + 0000007E : AA53FFFF; + 0000007F : BE32FFE8; + 00000080 : 32D6FFFC; + 00000081 : E9E10000; + 00000082 : EA61001C; + 00000083 : EAC10020; + 00000084 : EAE10024; + 00000085 : EB010028; + 00000086 : EB21002C; + 00000087 : EB410030; + 00000088 : EB610034; + 00000089 : B60F0008; + 0000008A : 30210038; + 0000008B : E8B70000; + 0000008C : 99FC3800; + 0000008D : 80000000; + 0000008E : 3273FFFF; + 0000008F : 32F7FFFC; + 00000090 : AA53FFFF; + 00000091 : BE12FFC0; + 00000092 : 32D6FFFC; + 00000093 : E8780004; + 00000094 : E8F60000; + 00000095 : 3063FFFF; + 00000096 : 16439800; + 00000097 : BC120074; + 00000098 : F8160000; + 00000099 : BC07FFD4; + 0000009A : BE190058; + 0000009B : 30800001; + 0000009C : E8790100; + 0000009D : 44849C00; + 0000009E : 84641800; + 0000009F : BC030044; + 000000A0 : E8790104; + 000000A1 : 84641800; + 000000A2 : BC23FFA4; + 000000A3 : E8D70000; + 000000A4 : 99FC3800; + 000000A5 : 10BB0000; + 000000A6 : B810FFA4; + 000000A7 : 3273FFFF; + 000000A8 : 3273FFFF; + 000000A9 : AA53FFFF; + 000000AA : BE12FF5C; + 000000AB : 3273FFFF; + 000000AC : AA53FFFF; + 000000AD : BE32FFF0; 000000AE : 3273FFFF; - 000000AF : AA53FFFF; - 000000B0 : BE12FF5C; + 000000AF : B800FF48; + 000000B0 : 99FC3800; 000000B1 : 3273FFFF; - 000000B2 : AA53FFFF; - 000000B3 : BE32FFF0; - 000000B4 : 3273FFFF; - 000000B5 : B800FF48; - 000000B6 : 99FC3800; - 000000B7 : 3273FFFF; - 000000B8 : B810FF78; - 000000B9 : 32F7FFFC; - 000000BA : FA780004; - 000000BB : B800FF90; - 000000BC : E8780004; - 000000BD : E8F60000; - 000000BE : 3063FFFF; - 000000BF : 16439800; - 000000C0 : BC120054; - 000000C1 : F8160000; - 000000C2 : BC07FF00; - 000000C3 : BC190038; - 000000C4 : 30800001; - 000000C5 : E8790100; - 000000C6 : 44849C00; - 000000C7 : 84641800; - 000000C8 : BC030024; - 000000C9 : E8790104; - 000000CA : 84641800; - 000000CB : BC230030; - 000000CC : E8D70000; - 000000CD : 99FC3800; - 000000CE : 10BB0000; - 000000CF : B810FED0; - 000000D0 : 3273FFFF; - 000000D1 : 99FC3800; - 000000D2 : 3273FFFF; - 000000D3 : B810FEC4; - 000000D4 : 32F7FFFC; - 000000D5 : FA780004; - 000000D6 : B800FFB0; - 000000D7 : E8B70000; - 000000D8 : 99FC3800; - 000000D9 : 3273FFFF; - 000000DA : B810FEA8; - 000000DB : 32F7FFFC; - 000000DC : 0000038C; - 000000DD : 43000000; - 000000DE : 41000000; - 000000DF : 40000000; - 000000E0 : 40000004; - 000000E1 : 40000008; - 000000E2 : 0000038C; - [000000E3..000000EA] : 00000000; - 000000EB : 00000374; - [000000EC..00000FFF] : 00000000; + 000000B2 : B810FF78; + 000000B3 : 32F7FFFC; + 000000B4 : FA780004; + 000000B5 : B800FF90; + 000000B6 : E8780004; + 000000B7 : E8F60000; + 000000B8 : 3063FFFF; + 000000B9 : 16439800; + 000000BA : BC120054; + 000000BB : F8160000; + 000000BC : BC07FF00; + 000000BD : BC190038; + 000000BE : 30800001; + 000000BF : E8790100; + 000000C0 : 44849C00; + 000000C1 : 84641800; + 000000C2 : BC030024; + 000000C3 : E8790104; + 000000C4 : 84641800; + 000000C5 : BC230030; + 000000C6 : E8D70000; + 000000C7 : 99FC3800; + 000000C8 : 10BB0000; + 000000C9 : B810FED0; + 000000CA : 3273FFFF; + 000000CB : 99FC3800; + 000000CC : 3273FFFF; + 000000CD : B810FEC4; + 000000CE : 32F7FFFC; + 000000CF : FA780004; + 000000D0 : B800FFB0; + 000000D1 : E8B70000; + 000000D2 : 99FC3800; + 000000D3 : 3273FFFF; + 000000D4 : B810FEA8; + 000000D5 : 32F7FFFC; + 000000D6 : 00000364; + 000000D7 : 43000000; + 000000D8 : 00000364; + [000000D9..000000E0] : 00000000; + 000000E1 : 0000035C; + [000000E2..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_03.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_03.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu02_03.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_02.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_02.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_02.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_03.mif =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_03.mif (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/ram/cpu03_03.mif (revision 7) @@ -8,24 +8,24 @@ CONTENT BEGIN 00000000 : B8080050; 00000001 : 00000000; - 00000002 : B8080138; + 00000002 : B808014C; 00000003 : 00000000; - 00000004 : B8080148; + 00000004 : B808015C; [00000005..00000007] : 00000000; - 00000008 : B8080140; + 00000008 : B8080154; [00000009..00000013] : 00000000; - 00000014 : 31A00478; - 00000015 : 30400370; - 00000016 : 30200C68; + 00000014 : 31A00480; + 00000015 : 30400388; + 00000016 : 30200C70; 00000017 : B9F40014; 00000018 : 80000000; - 00000019 : B9F400FC; + 00000019 : B9F40110; 0000001A : 30A30000; 0000001B : B8000000; 0000001C : 2021FFEC; 0000001D : F9E10000; - 0000001E : 20C00478; - 0000001F : 20E00478; + 0000001E : 20C00480; + 0000001F : 20E00480; 00000020 : 06463800; 00000021 : BC720014; 00000022 : F8060000; @@ -32,8 +32,8 @@ 00000023 : 20C60004; 00000024 : 06463800; 00000025 : BC92FFF4; - 00000026 : 20C00478; - 00000027 : 20E00478; + 00000026 : 20C00480; + 00000027 : 20E00480; 00000028 : 06463800; 00000029 : BC720014; 0000002A : F8060000; @@ -40,7 +40,7 @@ 0000002B : 20C60004; 0000002C : 06463800; 0000002D : BC92FFF4; - 0000002E : B9F400A0; + 0000002E : B9F400B4; 0000002F : 80000000; 00000030 : 20C00000; 00000031 : 20E00000; @@ -47,7 +47,7 @@ 00000032 : B9F4003C; 00000033 : 20A00000; 00000034 : 32630000; - 00000035 : B9F4007C; + 00000035 : B9F40090; 00000036 : 80000000; 00000037 : C9E10000; 00000038 : 30730000; @@ -59,167 +59,169 @@ 0000003E : 30A5FFFF; 0000003F : B60F0008; 00000040 : 80000000; - 00000041 : E8800370; - 00000042 : 3021FFE4; - 00000043 : F9E10000; - 00000044 : E8640000; - 00000045 : 30A0000A; - 00000046 : 30630001; - 00000047 : F8640000; - 00000048 : B9F4FFCC; - 00000049 : 80000000; - 0000004A : E9E10000; - 0000004B : 10600000; - 0000004C : B60F0008; - 0000004D : 3021001C; - 0000004E : B6110000; - 0000004F : 80000000; - 00000050 : B6910000; + 00000041 : 3021FFDC; + 00000042 : FA61001C; + 00000043 : B0004100; + 00000044 : 32602004; + 00000045 : FAC10020; + 00000046 : F9E10000; + 00000047 : 32C00001; + 00000048 : B0000000; + 00000049 : 30A0C350; + 0000004A : FAD30000; + 0000004B : B9F4FFC0; + 0000004C : 80000000; + 0000004D : B0000000; + 0000004E : 30A0C350; + 0000004F : F8130000; + 00000050 : B9F4FFAC; 00000051 : 80000000; - 00000052 : B62E0000; - 00000053 : 80000000; - 00000054 : B60F0008; - 00000055 : 80000000; - 00000056 : B60F0008; - 00000057 : 80000000; - 00000058 : 3021FFE0; - 00000059 : 10C00000; - 0000005A : FA61001C; - 0000005B : F9E10000; - 0000005C : B9F40024; - 0000005D : 12650000; - 0000005E : E8A00368; - 0000005F : E8650028; - 00000060 : BC03000C; - 00000061 : 99FC1800; - 00000062 : 80000000; - 00000063 : B9F4FEE0; - 00000064 : 10B30000; - 00000065 : E8600368; - 00000066 : 3021FFC8; - 00000067 : FB410030; - 00000068 : FB610034; - 00000069 : F9E10000; - 0000006A : FA61001C; - 0000006B : FAC10020; - 0000006C : FAE10024; - 0000006D : FB010028; - 0000006E : FB21002C; - 0000006F : EB030048; - 00000070 : 13650000; - 00000071 : BE180050; - 00000072 : 13460000; - 00000073 : E8780004; - 00000074 : EB380088; - 00000075 : 3263FFFF; - 00000076 : BC53003C; - 00000077 : 64930402; - 00000078 : 30640008; - 00000079 : 12D81800; - 0000007A : BE060074; - 0000007B : 12F92000; - 0000007C : BC1900C0; - 0000007D : E8770080; - 0000007E : 1643D000; - 0000007F : BC1200EC; - 00000080 : 3273FFFF; - 00000081 : 32F7FFFC; - 00000082 : AA53FFFF; - 00000083 : BE32FFE8; - 00000084 : 32D6FFFC; - 00000085 : E9E10000; - 00000086 : EA61001C; - 00000087 : EAC10020; - 00000088 : EAE10024; - 00000089 : EB010028; - 0000008A : EB21002C; - 0000008B : EB410030; - 0000008C : EB610034; - 0000008D : B60F0008; - 0000008E : 30210038; - 0000008F : E8B70000; - 00000090 : 99FC3800; - 00000091 : 80000000; - 00000092 : 3273FFFF; - 00000093 : 32F7FFFC; - 00000094 : AA53FFFF; - 00000095 : BE12FFC0; - 00000096 : 32D6FFFC; - 00000097 : E8780004; - 00000098 : E8F60000; - 00000099 : 3063FFFF; - 0000009A : 16439800; - 0000009B : BC120074; - 0000009C : F8160000; - 0000009D : BC07FFD4; - 0000009E : BE190058; - 0000009F : 30800001; - 000000A0 : E8790100; - 000000A1 : 44849C00; - 000000A2 : 84641800; - 000000A3 : BC030044; - 000000A4 : E8790104; - 000000A5 : 84641800; - 000000A6 : BC23FFA4; - 000000A7 : E8D70000; - 000000A8 : 99FC3800; - 000000A9 : 10BB0000; - 000000AA : B810FFA4; - 000000AB : 3273FFFF; - 000000AC : 3273FFFF; - 000000AD : AA53FFFF; - 000000AE : BE12FF5C; - 000000AF : 3273FFFF; - 000000B0 : AA53FFFF; - 000000B1 : BE32FFF0; - 000000B2 : 3273FFFF; - 000000B3 : B800FF48; - 000000B4 : 99FC3800; - 000000B5 : 3273FFFF; - 000000B6 : B810FF78; - 000000B7 : 32F7FFFC; - 000000B8 : FA780004; - 000000B9 : B800FF90; - 000000BA : E8780004; - 000000BB : E8F60000; - 000000BC : 3063FFFF; - 000000BD : 16439800; - 000000BE : BC120054; - 000000BF : F8160000; - 000000C0 : BC07FF00; - 000000C1 : BC190038; - 000000C2 : 30800001; - 000000C3 : E8790100; - 000000C4 : 44849C00; - 000000C5 : 84641800; - 000000C6 : BC030024; - 000000C7 : E8790104; - 000000C8 : 84641800; - 000000C9 : BC230030; - 000000CA : E8D70000; - 000000CB : 99FC3800; - 000000CC : 10BB0000; - 000000CD : B810FED0; - 000000CE : 3273FFFF; - 000000CF : 99FC3800; - 000000D0 : 3273FFFF; - 000000D1 : B810FEC4; - 000000D2 : 32F7FFFC; - 000000D3 : FA780004; - 000000D4 : B800FFB0; - 000000D5 : E8B70000; - 000000D6 : 99FC3800; - 000000D7 : 3273FFFF; - 000000D8 : B810FEA8; - 000000D9 : 32F7FFFC; - 000000DA : 00000384; - 000000DB : 43000000; - 000000DC : 41000000; - 000000DD : 40000000; - 000000DE : 40000004; - 000000DF : 40000008; - 000000E0 : 00000384; - [000000E1..000000E8] : 00000000; - 000000E9 : 0000036C; - [000000EA..00000FFF] : 00000000; + 00000052 : B800FFD8; + 00000053 : B6110000; + 00000054 : 80000000; + 00000055 : B6910000; + 00000056 : 80000000; + 00000057 : B62E0000; + 00000058 : 80000000; + 00000059 : B60F0008; + 0000005A : 80000000; + 0000005B : B60F0008; + 0000005C : 80000000; + 0000005D : 3021FFE0; + 0000005E : 10C00000; + 0000005F : FA61001C; + 00000060 : F9E10000; + 00000061 : B9F40024; + 00000062 : 12650000; + 00000063 : E8A0037C; + 00000064 : E8650028; + 00000065 : BC03000C; + 00000066 : 99FC1800; + 00000067 : 80000000; + 00000068 : B9F4FECC; + 00000069 : 10B30000; + 0000006A : E860037C; + 0000006B : 3021FFC8; + 0000006C : FB410030; + 0000006D : FB610034; + 0000006E : F9E10000; + 0000006F : FA61001C; + 00000070 : FAC10020; + 00000071 : FAE10024; + 00000072 : FB010028; + 00000073 : FB21002C; + 00000074 : EB030048; + 00000075 : 13650000; + 00000076 : BE180050; + 00000077 : 13460000; + 00000078 : E8780004; + 00000079 : EB380088; + 0000007A : 3263FFFF; + 0000007B : BC53003C; + 0000007C : 64930402; + 0000007D : 30640008; + 0000007E : 12D81800; + 0000007F : BE060074; + 00000080 : 12F92000; + 00000081 : BC1900C0; + 00000082 : E8770080; + 00000083 : 1643D000; + 00000084 : BC1200EC; + 00000085 : 3273FFFF; + 00000086 : 32F7FFFC; + 00000087 : AA53FFFF; + 00000088 : BE32FFE8; + 00000089 : 32D6FFFC; + 0000008A : E9E10000; + 0000008B : EA61001C; + 0000008C : EAC10020; + 0000008D : EAE10024; + 0000008E : EB010028; + 0000008F : EB21002C; + 00000090 : EB410030; + 00000091 : EB610034; + 00000092 : B60F0008; + 00000093 : 30210038; + 00000094 : E8B70000; + 00000095 : 99FC3800; + 00000096 : 80000000; + 00000097 : 3273FFFF; + 00000098 : 32F7FFFC; + 00000099 : AA53FFFF; + 0000009A : BE12FFC0; + 0000009B : 32D6FFFC; + 0000009C : E8780004; + 0000009D : E8F60000; + 0000009E : 3063FFFF; + 0000009F : 16439800; + 000000A0 : BC120074; + 000000A1 : F8160000; + 000000A2 : BC07FFD4; + 000000A3 : BE190058; + 000000A4 : 30800001; + 000000A5 : E8790100; + 000000A6 : 44849C00; + 000000A7 : 84641800; + 000000A8 : BC030044; + 000000A9 : E8790104; + 000000AA : 84641800; + 000000AB : BC23FFA4; + 000000AC : E8D70000; + 000000AD : 99FC3800; + 000000AE : 10BB0000; + 000000AF : B810FFA4; + 000000B0 : 3273FFFF; + 000000B1 : 3273FFFF; + 000000B2 : AA53FFFF; + 000000B3 : BE12FF5C; + 000000B4 : 3273FFFF; + 000000B5 : AA53FFFF; + 000000B6 : BE32FFF0; + 000000B7 : 3273FFFF; + 000000B8 : B800FF48; + 000000B9 : 99FC3800; + 000000BA : 3273FFFF; + 000000BB : B810FF78; + 000000BC : 32F7FFFC; + 000000BD : FA780004; + 000000BE : B800FF90; + 000000BF : E8780004; + 000000C0 : E8F60000; + 000000C1 : 3063FFFF; + 000000C2 : 16439800; + 000000C3 : BC120054; + 000000C4 : F8160000; + 000000C5 : BC07FF00; + 000000C6 : BC190038; + 000000C7 : 30800001; + 000000C8 : E8790100; + 000000C9 : 44849C00; + 000000CA : 84641800; + 000000CB : BC030024; + 000000CC : E8790104; + 000000CD : 84641800; + 000000CE : BC230030; + 000000CF : E8D70000; + 000000D0 : 99FC3800; + 000000D1 : 10BB0000; + 000000D2 : B810FED0; + 000000D3 : 3273FFFF; + 000000D4 : 99FC3800; + 000000D5 : 3273FFFF; + 000000D6 : B810FEC4; + 000000D7 : 32F7FFFC; + 000000D8 : FA780004; + 000000D9 : B800FFB0; + 000000DA : E8B70000; + 000000DB : 99FC3800; + 000000DC : 3273FFFF; + 000000DD : B810FEA8; + 000000DE : 32F7FFFC; + 000000DF : 0000038C; + 000000E0 : 43000000; + 000000E1 : 00000000; + 000000E2 : 0000038C; + [000000E3..000000EA] : 00000000; + 000000EB : 00000380; + [000000EC..00000FFF] : 00000000; END; \ No newline at end of file Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/tcl/prog.tcl =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/tcl/prog.tcl (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/tcl/prog.tcl (revision 7) @@ -0,0 +1,78 @@ +#/usr/bin/tclsh + +proc hold_reset {} { + global device_name usb + start_insystem_source_probe -device_name $device_name -hardware_name $usb + write_source_data -instance_index 127 -value 0x1 -value_in_hex + end_insystem_source_probe +} + +proc release_reset {} { + global device_name usb + start_insystem_source_probe -device_name $device_name -hardware_name $usb + write_source_data -instance_index 127 -value 0x0 -value_in_hex + end_insystem_source_probe +} + +## Setup USB hardware - assumes only USB Blaster is installed and +## an FPGA is the only device in the JTAG chain +set usb [lindex [get_hardware_names] 0] +set device_name [lindex [get_device_names -hardware_name $usb] 0] + +puts $usb +puts $device_name + +#reset all processors +hold_reset + + +# Initiate a editing sequence +begin_memory_edit -hardware_name $usb -device_name $device_name + +foreach instance \ + [get_editable_mem_instances -hardware_name $usb -device_name $device_name] { + set inst_name [lindex $instance 5] + set inst_index [lindex $instance 0] + #puts $inst_name + #puts $inst_index + set xx [string range $inst_name 0 1] + set yy [string range $inst_name 2 end] + #puts $xx + #puts $yy + set ram_file_name ../ram/cpu${xx}_${yy}.mif + +#update prog memory + if {[file exists $ram_file_name] == 1} { + puts "memory ${inst_name} is programed with $ram_file_name" + update_content_to_memory_from_file -instance_index $inst_index -mem_file_path $ram_file_name -mem_file_type mif + } + +} + + + + +#set xx 0 +#set yy 0 +# for {set yy 0} {$yy<$Y_NODE_NUM} {incr yy} { +# for {set xx 0} {$xx<$X_NODE_NUM} {incr xx} { +# set ram_file_name [format "ram/cpu%02d_%02d.mif" $xx $yy] +# set mem_index [format "%02d%02d" $xx $yy] + +#update prog memory +# update_content_to_memory_from_file -instance_index $mem_index -mem_file_path $ram_file_name -mem_file_type mif + +#puts $ram_file_name\n +#puts $mem_index\n + +# }} + + + + + +#End the editing sequence +end_memory_edit + +#release reset +release_reset
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/tcl/prog.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/prog_memories =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/prog_memories (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/prog_memories (revision 7) @@ -0,0 +1,4 @@ +#!/bin/sh + cd tcl + quartus_stp -t prog.tcl + cd ..
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/prog_memories Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/addr_map.h =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/addr_map.h (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/addr_map.h (nonexistent) @@ -1,32 +0,0 @@ -#ifndef ADDR_MAP_H - #define ADDR_MAP_H - - #define RAM_BASE 0x00000000 - #define NOC_BASE 0x40000000 - #define GPIO_BASE 0x41000000 - - - - //NOC - #define NIC_WR_DONE_LOC 1<<0 - #define NIC_RD_DONE_LOC 1<<1 - #define NIC_RD_OVR_ERR_LOC 1<<2 - #define NIC_RD_NPCK_ERR_LOC 1<<3 - #define NIC_HAS_PCK_LOC 1<<4 - #define X_NODE_NUM_WIDTH 2 - #define Y_NODE_NUM_WIDTH 2 - #define BUFFER_SIZE 31 - - volatile unsigned int *led_ptr = (unsigned int*) (GPIO_BASE); - volatile unsigned int *nic_rd_ptr = (unsigned int*) (NOC_BASE); - volatile unsigned int *nic_wr_ptr = (unsigned int*) (NOC_BASE+4); - volatile unsigned int *nic_st_ptr = (unsigned int*) (NOC_BASE+8); - - #define core_addr(DES_X, DES_Y) ((DES_X << Y_NODE_NUM_WIDTH) + DES_Y)<<(32-3-Y_NODE_NUM_WIDTH-X_NODE_NUM_WIDTH) - - - - - - -#endif Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/gccrom =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/gccrom (revision 6) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/gccrom (revision 7) @@ -13,25 +13,25 @@ INPUT="custom_crt/crt0.s custom_crt/crtinit.s" mb-g++ $XILFLAGS $CXXFLAGS $LNKFLAGS $LIBFLAGS $INCFLAGS -specs=aemb.specs $INPUT $@ -o $ELFFILE && \ -echo "xgcc=$?" && \ +#echo "xgcc=$?" && \ # Create a text listing of the compiled code mb-objdump -dDSCz $ELFFILE > $ELFFILE.dump && \ -echo "dump=$?" && \ +#echo "dump=$?" && \ # Convert the ELF file to an SREC file mb-objcopy -O srec $ELFFILE $ELFFILE.srec && \ -echo "copy=$?" && \ +#echo "copy=$?" && \ # Generate a Verilog VMEM file from the SREC file srec_cat $ELFFILE.srec -fill 0xFF -within $ELFFILE.srec --range-pad 4 -o out/dump.vmem -vmem 32 && \ -echo "srec=$?" && \ +#echo "srec=$?" && \ # Convert the ELF file to an IHEX file mb-objcopy -O ihex $ELFFILE $ELFFILE.ihex && \ -echo "copy2ihex=$?" && \ +#echo "copy2ihex=$?" && \ # Generate a MIF file from the IHEX file ihex/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o out/ram0.mif && \
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/system.h
0,0 → 1,116
#ifndef SYSTEM_H
#define SYSTEM_H
//define base addresses
#define RAM_BASE 0x00000000
#define NOC_BASE 0x40000000
#define GPIO_BASE 0x41000000
#define EXT_INT_BASE 0x42000000
#define TIMER_BASE 0x43000000
#define INT_CTRL_BASE 0x44000000
//GPIO
#define GPIO_ADDR_TYPE_START 5
#define GPIO_ADDR_PORT_WIDTH 5
#define GPIO_ADDR_REG_WIDTH 5
 
 
#define GPIO_IO_TYPE_NUM 0
#define GPIO_I_TYPE_NUM 4
#define GPIO_O_TYPE_NUM 8
 
#define GPIO_DIR_REG 0
#define GPIO_WRITE_REG 4
#define GPIO_READ_REG 8
 
#define GPIO_TYPE_LOC_START (GPIO_ADDR_REG_WIDTH + GPIO_ADDR_PORT_WIDTH)
#define GPIO_PORT_LOC_START (GPIO_ADDR_REG_WIDTH+2)
 
#define GPIO_IO_BASE (GPIO_BASE + (GPIO_IO_TYPE_NUM << GPIO_TYPE_LOC_START))
#define GPIO_I_BASE (GPIO_BASE + (GPIO_I_TYPE_NUM << GPIO_TYPE_LOC_START))
#define GPIO_O_BASE (GPIO_BASE + (GPIO_O_TYPE_NUM << GPIO_TYPE_LOC_START))
 
#define gpio_io_dir_reg(port_num) (*((volatile unsigned int *) (GPIO_IO_BASE+(port_num << GPIO_PORT_LOC_START)+GPIO_DIR_REG)))
#define gpio_io_wr_reg(port_num) (*((volatile unsigned int *) (GPIO_IO_BASE+(port_num << GPIO_PORT_LOC_START)+GPIO_WRITE_REG)))
#define gpio_io_rd_reg(port_num) (*((volatile unsigned int *) (GPIO_IO_BASE+(port_num << GPIO_PORT_LOC_START)+GPIO_READ_REG)))
#define gpio_o_wr_reg(port_num) (*((volatile unsigned int *) (GPIO_O_BASE+(port_num << GPIO_PORT_LOC_START)+GPIO_WRITE_REG)))
#define gpio_i_rd_reg(port_num) (*((volatile unsigned int *) (GPIO_I_BASE+(port_num << GPIO_PORT_LOC_START)+GPIO_READ_REG)))
 
#define gpio_io_dir(port_num,val) gpio_io_dir_reg(port_num)=val
#define gpio_io_wr(port_num,val) gpio_io_wr_reg(port_num)=val
#define gpio_o_wr(port_num,val) gpio_o_wr_reg(port_num)=val
 
//EXT_INT
#define EXT_INT_GER (*((volatile unsigned int *) (EXT_INT_BASE )))
#define EXT_INT_IER_RISE (*((volatile unsigned int *) (EXT_INT_BASE+4 )))
#define EXT_INT_IER_FALL (*((volatile unsigned int *) (EXT_INT_BASE+8 )))
#define EXT_INT_ISR (*((volatile unsigned int *) (EXT_INT_BASE+12 )))
#define EXT_INT_RD (*((volatile unsigned int *) (EXT_INT_BASE+16 )))
 
//TIMER
#define TCSR0 (*((volatile unsigned int *) (TIMER_BASE )))
/*
//timer control register
TCSR0
bit
6-3 : clk_dev_ctrl
3 : timer_isr
2 : rst_on_cmp_value
1 : int_enble_on_cmp_value
0 : timer enable
*/
#define TLR0 (*((volatile unsigned int *) (TIMER_BASE+4 )))
#define TCMP0 (*((volatile unsigned int *) (TIMER_BASE+8 )))
#define TIMER_EN 1
#define TIMER_INT_EN 2
#define TIMER_RST_ON_CMP 4
 
//INT CONTROLLER
 
#define INTC_MER (*((volatile unsigned int *) (INT_CTRL_BASE )))
#define INTC_IER (*((volatile unsigned int *) (INT_CTRL_BASE+4 )))
#define INTC_IAR (*((volatile unsigned int *) (INT_CTRL_BASE+8 )))
#define INTC_IPR (*((volatile unsigned int *) (INT_CTRL_BASE+12 )))
 
 
 
//NOC
#define X_Y_ADDR_WIDTH_IN_HDR 4
#define NI_PTR_WIDTH 19
#define NI_PCK_SIZE_WIDTH 13
#define NIC_WR_DONE_LOC 1<<0
#define NIC_RD_DONE_LOC 1<<1
#define NIC_RD_OVR_ERR_LOC 1<<2
#define NIC_RD_NPCK_ERR_LOC 1<<3
#define NIC_HAS_PCK_LOC 1<<4
 
#define NIC_RD (*((volatile unsigned int *) (NOC_BASE )))
#define NIC_WR (*((volatile unsigned int *) (NOC_BASE+4)))
#define NIC_ST (*((volatile unsigned int *) (NOC_BASE+8)))
 
 
#define core_addr(DES_X, DES_Y) ((DES_X << X_Y_ADDR_WIDTH_IN_HDR) + DES_Y)<<(32-3-(2*X_Y_ADDR_WIDTH_IN_HDR))
inline void send_pck (unsigned int * pck_buffer, unsigned int pck_size){
NIC_WR = (unsigned int) (& pck_buffer [0]) + (pck_size<<NI_PTR_WIDTH);
}
inline void save_pck (unsigned int * pck_buffer, unsigned int pck_size){
NIC_RD = (unsigned int) (& pck_buffer [0]) + (pck_size<<NI_PTR_WIDTH);
}
#define wait_for_sending_pck() while (!(NIC_ST & NIC_WR_DONE_LOC))
#define wait_for_getting_pck() while (!(NIC_ST & NIC_HAS_PCK_LOC))
 
 
 
#endif
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_mpsoc
0,0 → 1,15
#!/bin/sh
 
rm -Rf ram/*.mif
rm -Rf ../simulation/modelsim/sw/ram/*.mif
cd mpsoc_code
for i in $(ls *.c); do
echo item: $i
cp $i ../compile/code.c
cd ../compile
./gccrom code.c
cp out/ram0.mif ../ram/${i%.*}.mif
cp out/ram0.mif ../../simulation/modelsim/sw/ram/${i%.*}.mif
rm code.c
cd ../mpsoc_code
done
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_mpsoc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/do =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/do (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/do (revision 7) @@ -0,0 +1,14 @@ +#!/bin/sh +for x in 0 1 2 3 ; do + for y in 0 1 2 3; do + echo "cpu0${x}_0$y.c" + rm cpu0$x_$y.c + cp cpu.c "cpu0${x}_0$y.c" + done +done + + # echo item: cpu0$x$y.c + #cp cpu00_001.c cpu0$x_$y.c + #done + +
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_00.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_00.c (revision 7) @@ -0,0 +1,122 @@ +#include "orsocdef.h" +#include + +#include "system.h" + + +#define EXT_INT_EN 1 +#define TIMER_EN 1 +#define EXT_INT_NUM 3 + +#define TIMER_INT (1<<(EXT_INT_NUM*EXT_INT_EN)) +#define EXT_INT_1 (1<<0) +#define EXT_INT_2 (1<<1) +#define EXT_INT_3 (1<<2) + +#define EXT_INT_ALL (EXT_INT_1 | EXT_INT_2 | EXT_INT_3) // ((1<>(j*4))&0xF; + gpio_o_wr(j,~seven_seg_tab[hex_val]); + } + + delay(50000); + }//while + return 0; + + + +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_00.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_00.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_01.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_01.c (revision 7) @@ -0,0 +1,49 @@ +#include "orsocdef.h" +#include +#include "system.h" + +#define BUFFER_SIZE 31 + +unsigned int buffer [BUFFER_SIZE]; + +#define DES_X 2 +#define DES_Y 1 +#define DES_ADDR core_addr(DES_X, DES_Y) + +void delay(unsigned int); + + + + + + +int main() +{ + unsigned int status=0; + int i; + + while(1){ + for (i=1;i0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_01.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_01.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(5000000); + gpio_o_wr(0,0); + delay(5000000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_02.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_02.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(1000000); + gpio_o_wr(0,0); + delay(1000000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_00.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_00.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(200000); + gpio_o_wr(0,0); + delay(200000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_02.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_02.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(3000000); + gpio_o_wr(0,0); + delay(3000000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_00.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_00.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_00.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_03.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_03.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_01.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_01.c (revision 7) @@ -0,0 +1,40 @@ +#include "orsocdef.h" +#include +#include "system.h" + +#define BUFFER_SIZE 31 + +void delay(unsigned int); + +unsigned int buffer [BUFFER_SIZE]; + + + + +int main(void){ + + + unsigned int status=0; + + + while(1){ + wait_for_getting_pck(); + save_pck (buffer,BUFFER_SIZE); + + } + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_03.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_03.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_01.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_01.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_01.c (revision 7) @@ -0,0 +1,46 @@ +#include "orsocdef.h" +#include +#include "system.h" + +#define BUFFER_SIZE 31 +void delay(unsigned int); + +unsigned int buffer [BUFFER_SIZE]; + + + + + + + + + + +int main(void){ + + + unsigned int status=0; + + + while(1){ + wait_for_getting_pck(); + save_pck (buffer,BUFFER_SIZE); + + } + return 0; +} + + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_02.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_02.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_03.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu02_03.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_02.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_02.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_02.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_03.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_03.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu03_03.c (revision 7) @@ -0,0 +1,34 @@ +#include "orsocdef.h" +#include +#include "system.h" + + +void delay(unsigned int); + + +int main() +{ + + while(1) + { + gpio_o_wr(0,1); + delay(50000); + gpio_o_wr(0,0); + delay(50000); + }//while + return 0; +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_soc =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_soc (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_soc (revision 7) @@ -0,0 +1,13 @@ +#!/bin/sh + + rm -Rf ram/*.mif + rm -Rf ../simulation/modelsim/sw/ram/*.mif + cd soc_code + cp soc.c ../compile/code.c + cd ../compile + ./gccrom code.c + cp out/ram0.mif ../ram/cpu00_00.mif + cp out/ram0.mif ../../simulation/modelsim/sw/ram/cpu00_00.mif + rm code.c + cd ../soc_code +
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile_soc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/soc_code/soc.c =================================================================== --- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/soc_code/soc.c (nonexistent) +++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/soc_code/soc.c (revision 7) @@ -0,0 +1,122 @@ +#include "orsocdef.h" +#include + +#include "system.h" + + +#define EXT_INT_EN 1 +#define TIMER_EN 1 +#define EXT_INT_NUM 3 + +#define TIMER_INT (1<<(EXT_INT_NUM*EXT_INT_EN)) +#define EXT_INT_1 (1<<0) +#define EXT_INT_2 (1<<1) +#define EXT_INT_3 (1<<2) + +#define EXT_INT_ALL (EXT_INT_1 | EXT_INT_2 | EXT_INT_3) // ((1<>(j*4))&0xF; + gpio_o_wr(j,~seven_seg_tab[hex_val]); + } + + delay(50000); + }//while + return 0; + + + +} + + + + +void delay ( unsigned int num ){ + + while (num>0){ + num--; + asm volatile ("nop"); + } + return; + +} + Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/mpsoc.qws =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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