OpenCores
URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/hf-risc/trunk/ucore/control.vhd
12,12 → 12,12
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
mem_write: out std_logic;
br_link: out std_logic;
reg_to_mem: out std_logic;
mem_to_reg: out std_logic;
signed_imm: out std_logic;
mem_we: out std_logic_vector(3 downto 0);
mem_rd_byte: out std_logic;
mem_rd_half: out std_logic;
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
signed_rd: out std_logic;
shift: out std_logic
);
37,12 → 37,12
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000010" => -- SRL
52,12 → 52,12
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000011" => -- SRA
67,12 → 67,12
alu_op <= "1011";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000100" => -- SLLV
82,12 → 82,12
alu_op <= "1100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000110" => -- SRLV
97,12 → 97,12
alu_op <= "1101";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000111" => -- SRAV
112,12 → 112,12
alu_op <= "1110";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "001000" => -- JR
127,12 → 127,12
alu_op <= "0100";
jump <= "10";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001001" => -- JALR
142,12 → 142,12
alu_op <= "0100";
jump <= "10";
branch <= "000";
mem_write <= '0';
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001100" => -- SYSCALL
168,12 → 168,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "100010" => -- SUB
184,12 → 184,12
alu_op <= "0101";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100100" => -- AND
199,12 → 199,12
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100101" => -- OR
214,12 → 214,12
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100110" => -- XOR
229,12 → 229,12
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100111" => -- NOR
244,12 → 244,12
alu_op <= "0011";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101010" => -- SLT
259,12 → 259,12
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101011" => -- SLTU
274,12 → 274,12
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- all other R type instructions, generate a NOP
289,12 → 289,12
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
307,12 → 307,12
alu_op <= "0101";
jump <= "00";
branch <= "101";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "00001" => -- BGEZ
322,12 → 322,12
alu_op <= "0101";
jump <= "00";
branch <= "110";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10000" => -- BLTZAL
337,12 → 337,12
alu_op <= "0101";
jump <= "00";
branch <= "101";
mem_write <= '0';
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10001" => -- BGEZAL
352,12 → 352,12
alu_op <= "0101";
jump <= "00";
branch <= "110";
mem_write <= '0';
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- invalid instruction, generate a NOP
367,12 → 367,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
383,12 → 383,12
alu_op <= "0100";
jump <= "01";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000011" => -- JAL
398,12 → 398,12
alu_op <= "0100";
jump <= "01";
branch <= "000";
mem_write <= '0';
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000100" => -- BEQ
413,12 → 413,12
alu_op <= "0101";
jump <= "00";
branch <= "001";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000101" => -- BNE
428,12 → 428,12
alu_op <= "0101";
jump <= "00";
branch <= "010";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000110" => -- BLEZ
443,12 → 443,12
alu_op <= "0101";
jump <= "00";
branch <= "011";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000111" => -- BGTZ
458,12 → 458,12
alu_op <= "0101";
jump <= "00";
branch <= "100";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001000" => -- ADDI
474,12 → 474,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001010" => -- SLTI
489,12 → 489,12
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001011" => -- SLTIU
504,12 → 504,12
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001100" => -- ANDI
519,12 → 519,12
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001101" => -- ORI
534,12 → 534,12
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001110" => -- XORI
549,12 → 549,12
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001111" => -- LUI
564,12 → 564,12
alu_op <= "0110";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "010000" => -- COP0
583,12 → 583,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '1';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '1';
shift <= '0';
when "100001" => -- LH
598,12 → 598,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '1';
shift <= '0';
-- when "100010" => -- LWL
614,12 → 614,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "11";
signed_rd <= '0';
shift <= '0';
when "100100" => -- LBU
629,12 → 629,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '1';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '0';
shift <= '0';
when "100101" => -- LHU
644,12 → 644,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '0';
shift <= '0';
-- when "100110" => -- LWR
660,12 → 660,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '1';
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0001";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "01";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101001" => -- SH
675,12 → 675,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '1';
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "0011";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "10";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101010" => -- SWL
691,12 → 691,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '1';
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_we <= "1111";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "11";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101110" => -- SWR
715,12 → 715,12
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= '0';
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_we <= "0000";
mem_rd_byte <= '0';
mem_rd_half <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
/hf-risc/trunk/ucore/peripherals_busmux.vhd
1,4 → 1,4
-- HF-RISC v3.2
-- HF-RISC v3.3
-- Sergio Johann Filho, 2013 - 2016
--
-- *This is a quick and dirty organization of a 3-stage pipelined MIPS microprocessor. All registers / memory
64,12 → 64,14
--
-- Memory map:
--
-- ROM / Flash Address Space 0x00000000 - 0x3fffffff (1GB)
-- RAM Address Space 0x40000000 - 0x7fffffff (1GB)
-- Reserved 0x80000000 - 0xefffffff (1.75GB)
-- Peripherals 0xf0000000 - 0xffffffff (256MB)
-- Core Peripherals 0xf0000000 - 0xf7fffffc (128MB)
-- External Peripherals 0xf8000000 - 0xfffffffc (128MB)
-- ROM 0x00000000 - 0x1fffffff (512MB)
-- System 0x20000000 - 0x3fffffff (512MB)
-- SRAM 0x40000000 - 0x5fffffff (512MB)
-- External RAM / device 0x60000000 - 0x9fffffff (1GB)
-- External RAM / device 0xa0000000 - 0xdfffffff (1GB) (uncached)
-- External Peripheral 0xe0000000 - 0xefffffff (256MB) (uncached)
-- Peripheral (core) 0xf0000000 - 0xf7ffffff (128MB) (uncached)
-- Peripheral (extended) 0xf8000000 - 0xffffffff (128MB) (uncached)
--
-- IRQ_VECTOR 0xf0000000
-- IRQ_CAUSE 0xf0000010
/hf-risc/trunk/ucore/datapath.vhd
32,20 → 32,20
signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm: std_logic_vector(15 downto 0);
signal wreg, zero, less_than, branch_and_link, branch_taken, branch_taken_dly, jump_taken, jump_taken_dly, stall_reg: std_logic;
signal wreg, zero, less_than, br_link_ctl, branch_taken, branch_taken_dly, jump_taken, jump_taken_dly, stall_reg: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
 
-- control signals
signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, mem_write_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, mem_rd_byte_ctl, mem_rd_half_ctl, signed_rd_ctl, shift_ctl: std_logic;
signal jump_ctl, mem_rd_ctl: std_logic_vector(1 downto 0);
signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
signal branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl, mem_we_ctl: std_logic_vector(3 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
 
 
signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, mem_write_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, mem_rd_byte_ctl_r, mem_rd_half_ctl_r, signed_rd_ctl_r, shift_ctl_r, branch_and_link_r: std_logic;
signal jump_ctl_r: std_logic_vector(1 downto 0);
signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, reg_to_mem_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, signed_rd_ctl_r, shift_ctl_r, br_link_ctl_r: std_logic;
signal jump_ctl_r, mem_read_ctl_r, mem_write_ctl_r: std_logic_vector(1 downto 0);
signal branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r, mem_we_ctl_r: std_logic_vector(3 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
signal rs_r, rt_r, rd_r: std_logic_vector(4 downto 0);
signal imm_r: std_logic_vector(15 downto 0);
begin
56,7 → 56,7
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
 
-- program counter logic
process(clock, reset, mem_write_ctl_r, mem_to_reg_ctl_r, busy, stall)
process(clock, reset, reg_to_mem_ctl_r, mem_to_reg_ctl_r, busy, stall)
begin
if reset = '1' then
pc <= (others => '0');
67,7 → 67,7
pc <= pc_next;
pc_last <= pc;
else
if (mem_write_ctl_r = '1' or mem_to_reg_ctl_r = '1') and branch_taken_dly = '0' and jump_taken_dly = '0' then
if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and branch_taken_dly = '0' and jump_taken_dly = '0' then
pc <= pc_last;
end if;
end if;
85,7 → 85,7
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
mem_write_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
 
irq_ack <= irq_ack_s_dly;
 
125,12 → 125,10
opcode <= inst_in(31 downto 26);
rs <= inst_in(25 downto 21);
rt <= inst_in(20 downto 16);
rd <= "11111" when branch_and_link = '1' else inst_in(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
rd <= "11111" when br_link_ctl = '1' else inst_in(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
funct <= inst_in(5 downto 0);
imm <= inst_in(15 downto 0);
 
branch_and_link <= '1' when branch_ctl /= "000" or jump_ctl /= "00" else '0';
 
-- control unit
control_hellfire: entity work.control
port map( opcode => opcode,
142,17 → 140,17
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
mem_write => mem_write_ctl,
br_link => br_link_ctl,
reg_to_mem => reg_to_mem_ctl,
mem_to_reg => mem_to_reg_ctl,
signed_imm => signed_imm_ctl,
mem_we => mem_we_ctl,
mem_rd_byte => mem_rd_byte_ctl,
mem_rd_half => mem_rd_half_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
signed_rd => signed_rd_ctl,
shift => shift_ctl
);
 
process(clock, reset, irq_ack_s, bds, busy, stall)
process(clock, reset, busy, stall)
begin
if reset = '1' then
rs_r <= (others => '0');
165,15 → 163,14
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= '0';
br_link_ctl_r <= '0';
reg_to_mem_ctl_r <= '0';
mem_to_reg_ctl_r <= '0';
signed_imm_ctl_r <= '0';
mem_we_ctl_r <= (others => '0');
mem_rd_byte_ctl_r <= '0';
mem_rd_half_ctl_r <= '0';
mem_write_ctl_r <= "00";
mem_read_ctl_r <= "00";
signed_rd_ctl_r <= '0';
shift_ctl_r <= '0';
branch_and_link_r <= '0';
elsif clock'event and clock = '1' then
if stall = '0' then
if irq_ack_s = '1' then
187,18 → 184,17
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= '0';
br_link_ctl_r <= '0';
reg_to_mem_ctl_r <= '0';
mem_to_reg_ctl_r <= '0';
signed_imm_ctl_r <= '0';
mem_we_ctl_r <= (others => '0');
mem_rd_byte_ctl_r <= '0';
mem_rd_half_ctl_r <= '0';
mem_write_ctl_r <= "00";
mem_read_ctl_r <= "00";
signed_rd_ctl_r <= '0';
shift_ctl_r <= '0';
branch_and_link_r <= '0';
else
if busy = '0' then
if mem_write_ctl_r = '1' or mem_to_reg_ctl_r = '1' or branch_taken_dly = '1' or jump_taken_dly = '1' then
if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or branch_taken_dly = '1' or jump_taken_dly = '1' then
rs_r <= (others => '0');
rt_r <= (others => '0');
rd_r <= (others => '0');
209,15 → 205,14
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= '0';
br_link_ctl_r <= '0';
reg_to_mem_ctl_r <= '0';
mem_to_reg_ctl_r <= '0';
signed_imm_ctl_r <= '0';
mem_we_ctl_r <= (others => '0');
mem_rd_byte_ctl_r <= '0';
mem_rd_half_ctl_r <= '0';
mem_write_ctl_r <= "00";
mem_read_ctl_r <= "00";
signed_rd_ctl_r <= '0';
shift_ctl_r <= '0';
branch_and_link_r <= '0';
else
rs_r <= rs;
rt_r <= rt;
229,15 → 224,14
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
mem_write_ctl_r <= mem_write_ctl;
br_link_ctl_r <= br_link_ctl;
reg_to_mem_ctl_r <= reg_to_mem_ctl;
mem_to_reg_ctl_r <= mem_to_reg_ctl;
signed_imm_ctl_r <= signed_imm_ctl;
mem_we_ctl_r <= mem_we_ctl;
mem_rd_byte_ctl_r <= mem_rd_byte_ctl;
mem_rd_half_ctl_r <= mem_rd_half_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
signed_rd_ctl_r <= signed_rd_ctl;
shift_ctl_r <= shift_ctl;
branch_and_link_r <= branch_and_link;
end if;
end if;
end if;
296,19 → 290,19
jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR
 
inst_addr <= pc;
data_addr <= result(31 downto 2) & "00";
data_access <= '1' when mem_write_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
data_addr <= result; --result(31 downto 2) & "00";
data_access <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
 
 
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_we_ctl_r, result, read_data2)
process(mem_write_ctl_r, result, read_data2)
begin
case mem_we_ctl_r is
when "1111" => -- store word
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2;
data_w <= "1111";
when "0001" => -- store byte
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
316,7 → 310,7
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "0011" => -- store half word
when "10" => -- store half word
data_out <= read_data2(15 downto 0) & read_data2(15 downto 0);
case result(1) is
when '1' => data_w <= "0011";
329,11 → 323,9
end process;
 
-- memory access, load operations
mem_rd_ctl <= mem_rd_half_ctl_r & mem_rd_byte_ctl_r;
 
process(mem_rd_ctl, result, data_in)
process(mem_read_ctl_r, result, data_in)
begin
case mem_rd_ctl is
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
356,10 → 348,10
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or signed_rd_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or signed_rd_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
 
write_data <= data_in_s when mem_to_reg_ctl_r = '1' and (mem_rd_byte_ctl_r = '0' and mem_rd_half_ctl_r = '0') else
ext32b when mem_to_reg_ctl_r = '1' and mem_rd_byte_ctl_r = '1' else
ext32h when mem_to_reg_ctl_r = '1' and mem_rd_half_ctl_r = '1' else
pc when branch_and_link_r = '1' else result;
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc when br_link_ctl_r = '1' else result;
 
end arch_datapath;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.